345 lines
9.1 KiB
C
345 lines
9.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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*/
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#ifndef _MT_DIP_H
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#define _MT_DIP_H
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#include <linux/ioctl.h>
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#ifndef CONFIG_OF
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extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
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extern void mt_irq_set_polarity
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(unsigned int irq, unsigned int polarity);
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#endif
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/**
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* enforce kernel log enable
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*/
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#define KERNEL_LOG
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#define ISR_LOG_ON
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#define SIG_ERESTARTSYS 512
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/**************************************************************
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*
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**************************************************************/
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#define DIP_DEV_MAJOR_NUMBER 251
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#define DIP_MAGIC 'D'
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/*Chip Dependent Constanct*/
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#define DIP_IMGSYS_BASE_HW 0x15020000
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#define DIP_A_BASE_HW 0x15022000
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/*PAGE_SIZE*6 = 4096*6 <=dependent on device tree setting */
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#define DIP_REG_RANGE (0x6000)
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#define MAX_TILE_TOT_NO (256)
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#define MAX_ISP_DUMP_HEX_PER_TILE (256)
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#define MAX_ISP_TILE_TDR_HEX_NO (MAX_TILE_TOT_NO*MAX_ISP_DUMP_HEX_PER_TILE)
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#define MAX_DIP_CMDQ_BUFFER_SIZE (0x1000)
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/* 0xffff0000 chip dependent, sizeof = 256x256 = 0x10000 */
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#define DIP_TDRI_ADDR_MASK (0xffff0000)
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#define DIP_IMBI_BASEADDR_OFFSET (0x500>>2)
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#define DIP_DUMP_ADDR_MASK (0xffffffff)
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/*0x15022214 -0x15022208 */
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/* DIP_A_CQ_THR1_BASEADDR-DIP_A_CQ_THR0_BASEADDR */
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#define DIP_CMDQ_BASEADDR_OFFSET (12)
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/* In order with the suquence of device nodes defined in dtsi */
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enum DIP_DEV_NODE_ENUM {
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DIP_IMGSYS_CONFIG_IDX = 0,
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DIP_DIP_A_IDX, /* Remider: Add this device node manually in .dtsi */
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DIP_DEV_NODE_NUM
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};
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/**
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* interrupt clear type
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*/
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enum DIP_IRQ_CLEAR_ENUM {
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DIP_IRQ_CLEAR_NONE, /* non-clear wait, clear after wait */
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DIP_IRQ_CLEAR_WAIT, /* clear wait, clear before and after wait */
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DIP_IRQ_CLEAR_STATUS, /* clear specific status only */
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DIP_IRQ_CLEAR_ALL /* clear all status */
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};
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/**
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum DIP_IRQ_TYPE_ENUM {
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DIP_IRQ_TYPE_INT_DIP_A_ST,
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DIP_IRQ_TYPE_AMOUNT
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};
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struct DIP_WAIT_IRQ_ST {
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enum DIP_IRQ_CLEAR_ENUM Clear;
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unsigned int Status;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Timeout;
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};
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struct DIP_WAIT_IRQ_STRUCT {
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enum DIP_IRQ_TYPE_ENUM Type;
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unsigned int bDumpReg;
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struct DIP_WAIT_IRQ_ST EventInfo;
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};
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struct DIP_REGISTER_USERKEY_STRUCT {
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int userKey;
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/* this size must the same as the icamiopipe api - registerIrq(...) */
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char userName[32];
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};
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struct DIP_CLEAR_IRQ_ST {
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status;
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};
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struct DIP_CLEAR_IRQ_STRUCT {
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enum DIP_IRQ_TYPE_ENUM Type;
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struct DIP_CLEAR_IRQ_ST EventInfo;
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};
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struct DIP_REG_STRUCT {
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unsigned int module; /*plz refer to DIP_DEV_NODE_ENUM */
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct DIP_REG_IO_STRUCT {
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struct DIP_REG_STRUCT *pData; /* pointer to DIP_REG_STRUCT */
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unsigned int Count; /* count */
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};
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#ifdef CONFIG_COMPAT
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struct compat_DIP_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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#endif
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enum DIP_DUMP_CMD {
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DIP_DUMP_TPIPEBUF_CMD = 0,
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DIP_DUMP_TUNINGBUF_CMD,
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DIP_DUMP_DIPVIRBUF_CMD,
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DIP_DUMP_CMDQVIRBUF_CMD
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};
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struct DIP_DUMP_BUFFER_STRUCT {
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unsigned int DumpCmd;
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unsigned int *pBuffer;
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unsigned int BytesofBufferSize;
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};
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struct DIP_GET_DUMP_INFO_STRUCT {
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unsigned int extracmd;
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unsigned int imgi_baseaddr;
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unsigned int tdri_baseaddr;
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unsigned int dmgi_baseaddr;
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unsigned int cmdq_baseaddr;
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};
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enum DIP_MEMORY_INFO_CMD {
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DIP_MEMORY_INFO_TPIPE_CMD = 1,
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DIP_MEMORY_INFO_CMDQ_CMD
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};
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struct DIP_MEM_INFO_STRUCT {
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unsigned int MemInfoCmd;
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unsigned int MemPa;
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unsigned int *MemVa;
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unsigned int MemSizeDiff;
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};
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#ifdef CONFIG_COMPAT
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struct compat_DIP_DUMP_BUFFER_STRUCT {
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unsigned int DumpCmd;
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compat_uptr_t pBuffer;
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unsigned int BytesofBufferSize;
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};
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struct compat_DIP_MEM_INFO_STRUCT {
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unsigned int MemInfoCmd;
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unsigned int MemPa;
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compat_uptr_t MemVa;
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unsigned int MemSizeDiff;
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};
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#endif
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/* struct for enqueue/dequeue control in ihalpipe wrapper */
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/* 0,signal that a specific buffer is enqueued */
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/* 1,a dequeue thread is waiting to do dequeue */
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/* 2,signal that a buffer is dequeued (success) */
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/* 3,signal that a buffer is dequeued (fail) */
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/* 4,wait for a specific buffer */
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/* 5,wake all slept users to check buffer is dequeued or not */
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/* 6,free all recored dequeued buffer */
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enum DIP_P2_BUFQUE_CTRL_ENUM {
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DIP_P2_BUFQUE_CTRL_ENQUE_FRAME = 0,
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DIP_P2_BUFQUE_CTRL_WAIT_DEQUE,
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DIP_P2_BUFQUE_CTRL_DEQUE_SUCCESS,
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DIP_P2_BUFQUE_CTRL_DEQUE_FAIL,
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DIP_P2_BUFQUE_CTRL_WAIT_FRAME,
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DIP_P2_BUFQUE_CTRL_WAKE_WAITFRAME,
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DIP_P2_BUFQUE_CTRL_CLAER_ALL,
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DIP_P2_BUFQUE_CTRL_MAX
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};
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enum DIP_GCE_EVENT_ENUM {
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DIP_GCE_EVENT_NONE,
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DIP_GCE_EVENT_DPE,
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DIP_GCE_EVENT_RSC,
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DIP_GCE_EVENT_WPE,
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DIP_GCE_EVENT_MFB,
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DIP_GCE_EVENT_FDVT,
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DIP_GCE_EVENT_DIP,
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DIP_GCE_EVENT_MDP,
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DIP_GCE_EVENT_DISP,
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DIP_GCE_EVENT_JPGE,
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DIP_GCE_EVENT_VENC,
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DIP_GCE_EVENT_CMDQ,
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DIP_GCE_EVENT_THEOTHERS
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};
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enum DIP_P2_BUFQUE_PROPERTY {
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DIP_P2_BUFQUE_PROPERTY_DIP = 0,
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DIP_P2_BUFQUE_PROPERTY_NUM = 1,
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DIP_P2_BUFQUE_PROPERTY_WARP
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};
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struct DIP_P2_BUFQUE_STRUCT {
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enum DIP_P2_BUFQUE_CTRL_ENUM ctrl;
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enum DIP_P2_BUFQUE_PROPERTY property;
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unsigned int processID; /* judge multi-process */
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/* judge multi-thread and different buffer type */
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unsigned int callerID;
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int frameNum; /* total frame number in the enque request */
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int cQIdx; /* cq index */
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int dupCQIdx; /* dup cq index */
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int burstQIdx; /* burst queue index */
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unsigned int timeoutIns; /* timeout for wait buffer */
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};
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enum DIP_P2_BUF_STATE_ENUM {
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DIP_P2_BUF_STATE_NONE = -1,
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DIP_P2_BUF_STATE_ENQUE = 0,
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DIP_P2_BUF_STATE_RUNNING,
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DIP_P2_BUF_STATE_WAIT_DEQUE_FAIL,
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DIP_P2_BUF_STATE_DEQUE_SUCCESS,
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DIP_P2_BUF_STATE_DEQUE_FAIL
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};
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enum DIP_P2_BUFQUE_LIST_TAG {
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DIP_P2_BUFQUE_LIST_TAG_PACKAGE = 0, DIP_P2_BUFQUE_LIST_TAG_UNIT
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};
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enum DIP_P2_BUFQUE_MATCH_TYPE {
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DIP_P2_BUFQUE_MATCH_TYPE_WAITDQ = 0, /* waiting for deque */
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DIP_P2_BUFQUE_MATCH_TYPE_WAITFM, /* wait frame from user */
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DIP_P2_BUFQUE_MATCH_TYPE_FRAMEOP, /* frame operaetion */
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DIP_P2_BUFQUE_MATCH_TYPE_WAITFMEQD /* wait frame enqueued for deque */
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};
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/**************************************************************
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*
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**************************************************************/
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enum DIP_CMD_ENUM {
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DIP_CMD_RESET_BY_HWMODULE,
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DIP_CMD_READ_REG, /* Read register from driver */
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DIP_CMD_WRITE_REG, /* Write register to driver */
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DIP_CMD_WAIT_IRQ, /* Wait IRQ */
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DIP_CMD_CLEAR_IRQ, /* Clear IRQ */
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DIP_CMD_DEBUG_FLAG, /* Dump message level */
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DIP_CMD_P2_BUFQUE_CTRL,
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DIP_CMD_WAKELOCK_CTRL,
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DIP_CMD_FLUSH_IRQ_REQUEST, /* flush signal */
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DIP_CMD_ION_IMPORT, /* get ion handle */
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DIP_CMD_ION_FREE, /* free ion handle */
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DIP_CMD_ION_FREE_BY_HWMODULE, /* free all ion handle */
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DIP_CMD_DUMP_BUFFER,
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DIP_CMD_GET_DUMP_INFO,
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DIP_CMD_SET_MEM_INFO,
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DIP_CMD_GET_GCE_FIRST_ERR
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};
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#define DIP_RESET_BY_HWMODULE \
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_IOW(DIP_MAGIC, DIP_CMD_RESET_BY_HWMODULE, unsigned long)
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/* read phy reg */
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#define DIP_READ_REGISTER \
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_IOWR(DIP_MAGIC, DIP_CMD_READ_REG, struct DIP_REG_IO_STRUCT)
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/* write phy reg */
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#define DIP_WRITE_REGISTER \
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_IOWR(DIP_MAGIC, DIP_CMD_WRITE_REG, struct DIP_REG_IO_STRUCT)
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#define DIP_WAIT_IRQ \
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_IOW(DIP_MAGIC, DIP_CMD_WAIT_IRQ, struct DIP_WAIT_IRQ_STRUCT)
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#define DIP_CLEAR_IRQ \
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_IOW(DIP_MAGIC, DIP_CMD_CLEAR_IRQ, struct DIP_CLEAR_IRQ_STRUCT)
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#define DIP_FLUSH_IRQ_REQUEST \
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_IOW(DIP_MAGIC, DIP_CMD_FLUSH_IRQ_REQUEST, struct DIP_WAIT_IRQ_STRUCT)
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#define DIP_DEBUG_FLAG \
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_IOW(DIP_MAGIC, DIP_CMD_DEBUG_FLAG, unsigned char*)
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#define DIP_P2_BUFQUE_CTRL \
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_IOWR(DIP_MAGIC, DIP_CMD_P2_BUFQUE_CTRL, struct DIP_P2_BUFQUE_STRUCT)
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#define DIP_WAKELOCK_CTRL \
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_IOWR(DIP_MAGIC, DIP_CMD_WAKELOCK_CTRL, unsigned long)
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#define DIP_DUMP_BUFFER \
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_IOWR(DIP_MAGIC, DIP_CMD_DUMP_BUFFER, struct DIP_DUMP_BUFFER_STRUCT)
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#define DIP_GET_DUMP_INFO \
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_IOWR(DIP_MAGIC, DIP_CMD_GET_DUMP_INFO, \
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struct DIP_GET_DUMP_INFO_STRUCT)
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#define DIP_SET_MEM_INFO \
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_IOWR(DIP_MAGIC, DIP_CMD_SET_MEM_INFO, struct DIP_MEM_INFO_STRUCT)
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#define DIP_GET_GCE_FIRST_ERR \
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_IOWR(DIP_MAGIC, DIP_CMD_GET_GCE_FIRST_ERR, unsigned int)
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#ifdef CONFIG_COMPAT
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#define COMPAT_DIP_RESET_BY_HWMODULE \
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_IOW(DIP_MAGIC, DIP_CMD_RESET_BY_HWMODULE, compat_uptr_t)
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#define COMPAT_DIP_READ_REGISTER \
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_IOWR(DIP_MAGIC, DIP_CMD_READ_REG, struct compat_DIP_REG_IO_STRUCT)
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#define COMPAT_DIP_WRITE_REGISTER \
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_IOWR(DIP_MAGIC, DIP_CMD_WRITE_REG, struct compat_DIP_REG_IO_STRUCT)
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#define COMPAT_DIP_DEBUG_FLAG \
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_IOW(DIP_MAGIC, DIP_CMD_DEBUG_FLAG, compat_uptr_t)
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#define COMPAT_DIP_WAKELOCK_CTRL \
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_IOWR(DIP_MAGIC, DIP_CMD_WAKELOCK_CTRL, compat_uptr_t)
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#define COMPAT_DIP_DUMP_BUFFER \
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_IOWR(DIP_MAGIC, DIP_CMD_DUMP_BUFFER, \
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struct compat_DIP_DUMP_BUFFER_STRUCT)
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#define COMPAT_DIP_SET_MEM_INFO \
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_IOWR(DIP_MAGIC, DIP_CMD_SET_MEM_INFO, \
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struct compat_DIP_MEM_INFO_STRUCT)
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#endif
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int32_t DIP_MDPClockOnCallback(uint64_t engineFlag);
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int32_t DIP_MDPDumpCallback(uint64_t engineFlag, int level);
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int32_t DIP_MDPResetCallback(uint64_t engineFlag);
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int32_t DIP_MDPClockOffCallback(uint64_t engineFlag);
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int32_t DIP_BeginGCECallback
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(uint32_t taskID, uint32_t *regCount, uint32_t **regAddress);
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int32_t DIP_EndGCECallback
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(uint32_t taskID, uint32_t regCount, uint32_t *regValues);
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#endif
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