336 lines
9.4 KiB
C
336 lines
9.4 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/pm_runtime.h>
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#include <linux/ratelimit.h>
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#include<linux/ktime.h>
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#include <linux/irq.h>
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#include "../inc/mt6360_pmu.h"
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#ifdef CONFIG_MT6360_PMU_DEBUG
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static unsigned long long duration_index[8], pmu_irq_duration;
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static int count_index[8];
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#endif
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static irqreturn_t mt6360_pmu_irq_handler(int irq, void *data)
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{
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struct mt6360_pmu_info *mpi = data;
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u8 irq_events[MT6360_PMU_IRQ_REGNUM] = {0};
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u8 irq_masks[MT6360_PMU_IRQ_REGNUM] = {0};
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int i, j, ret;
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#ifdef CONFIG_MT6360_PMU_DEBUG
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int k;
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unsigned long long duration = 0;
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ktime_t calltime, delta, rettime;
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#endif
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mt_dbg(mpi->dev, "%s ++\n", __func__);
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pm_runtime_get_sync(mpi->dev);
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ret = mt6360_pmu_reg_block_read(mpi, MT6360_PMU_CHG_IRQ1,
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MT6360_PMU_IRQ_REGNUM, irq_events);
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if (ret < 0) {
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dev_err(mpi->dev, "fail to read irq events\n");
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goto out_irq_handler;
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}
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memcpy(irq_masks, mpi->cache_irq_masks, MT6360_PMU_IRQ_REGNUM);
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/* make faultb reg, it's not irq mask, 0xfb[7:0] & 0xfc[7] */
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irq_masks[11] = 0xff;
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irq_masks[12] |= 0x80;
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for (i = 0; i < MT6360_PMU_IRQ_REGNUM; i++) {
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irq_events[i] &= ~irq_masks[i];
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for (j = 0; j < 8; j++) {
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if (!(irq_events[i] & (1 << j)))
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continue;
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ret = irq_find_mapping(mpi->irq_domain, i * 8 + j);
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if (ret) {
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#ifdef CONFIG_MT6360_PMU_DEBUG
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calltime = ktime_get();
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#endif
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/* bypass adc donei & mivr irq */
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if ((i == 5 && j == 4) || (i == 0 && j == 6))
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mt_dbg(mpi->dev,
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"handle_irq [%d,%d]\n", i, j);
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else
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dev_dbg(mpi->dev,
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"handle_irq [%d,%d]\n", i, j);
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handle_nested_irq(ret);
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#ifdef CONFIG_MT6360_PMU_DEBUG
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rettime = ktime_get();
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delta = ktime_sub(rettime, calltime);
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duration = (unsigned long long)
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ktime_to_ns(delta) >> 10;
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pmu_irq_duration += duration;
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duration_index[i] += duration;
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count_index[i]++;
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#endif
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} else
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dev_err(mpi->dev, "unmapped [%d,%d]\n", i, j);
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}
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}
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ret = mt6360_pmu_reg_block_write(mpi, MT6360_PMU_CHG_IRQ1,
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MT6360_PMU_IRQ_REGNUM, irq_events);
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if (ret < 0) {
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dev_err(mpi->dev, "fail to write clear irq events\n");
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goto out_irq_handler;
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}
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ret = mt6360_pmu_reg_set_bits(mpi,
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MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG);
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if (ret < 0)
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dev_err(mpi->dev, "fail to retrig interrupt\n");
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#ifdef CONFIG_MT6360_PMU_DEBUG
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dev_info_ratelimited(mpi->dev, "%s: pmu_irq_duration: %lld\n",
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__func__, pmu_irq_duration);
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for (k = 0; k < 8; k++) {
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if (k != 2)
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dev_info_ratelimited(mpi->dev,
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"%d index_count: %d, index_duration: %lld\n", k,
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count_index[k], duration_index[k]);
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}
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#endif
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out_irq_handler:
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pm_runtime_put(mpi->dev);
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mt_dbg(mpi->dev, "%s --\n", __func__);
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return IRQ_HANDLED;
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}
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static void mt6360_pmu_irq_bus_lock(struct irq_data *data)
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{
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struct mt6360_pmu_info *mpi = data->chip_data;
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int ret;
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/* mask all irq indicator mask */
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ret = mt6360_pmu_reg_write(mpi, MT6360_PMU_IRQ_MASK, 0xff);
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if (ret < 0)
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dev_err(mpi->dev, "%s: fail to write irq ind_mask\n", __func__);
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}
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static void mt6360_pmu_irq_bus_sync_unlock(struct irq_data *data)
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{
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struct mt6360_pmu_info *mpi = data->chip_data;
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int ret;
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unsigned long offset = data->hwirq;
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u8 clr_curr_irq_evt = 1 << (offset % 8);
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/* force clear current irq event */
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ret = mt6360_pmu_reg_block_write(mpi, MT6360_PMU_CHG_IRQ1 + offset / 8,
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1, &clr_curr_irq_evt);
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if (ret < 0)
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dev_err(mpi->dev, "%s: fail to write clr irq\n", __func__);
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/* unmask current irq */
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ret = mt6360_pmu_reg_write(mpi, MT6360_PMU_CHG_MASK1 + offset / 8,
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mpi->cache_irq_masks[offset / 8]);
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if (ret < 0)
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dev_err(mpi->dev, "%s: fail to write irq mask\n", __func__);
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/* unmask all irq indicator mask */
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ret = mt6360_pmu_reg_write(mpi, MT6360_PMU_IRQ_MASK, 0);
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if (ret < 0)
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dev_err(mpi->dev, "%s: fail to write irq ind_mask\n", __func__);
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}
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static void mt6360_pmu_irq_enable(struct irq_data *data)
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{
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struct mt6360_pmu_info *mpi = data->chip_data;
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mt_dbg(mpi->dev, "%s: hwirq[%d]\n", __func__, (int)data->hwirq);
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mpi->cache_irq_masks[data->hwirq / 8] &= ~(1 << (data->hwirq % 8));
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}
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static void mt6360_pmu_irq_disable(struct irq_data *data)
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{
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struct mt6360_pmu_info *mpi = data->chip_data;
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mt_dbg(mpi->dev, "%s: hwirq[%d]\n", __func__, (int)data->hwirq);
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mpi->cache_irq_masks[data->hwirq / 8] |= (1 << (data->hwirq % 8));
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}
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static struct irq_chip mt6360_pmu_irq_chip = {
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.name = "mt6360_pmu_irqs",
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.irq_bus_lock = mt6360_pmu_irq_bus_lock,
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.irq_bus_sync_unlock = mt6360_pmu_irq_bus_sync_unlock,
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.irq_enable = mt6360_pmu_irq_enable,
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.irq_disable = mt6360_pmu_irq_disable,
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};
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static int mt6360_pmu_irq_domain_map(struct irq_domain *d,
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unsigned int virq, irq_hw_number_t hw)
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{
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struct mt6360_pmu_info *mpi = d->host_data;
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if (hw >= MT6360_PMU_IRQEVT_MAX)
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return -EINVAL;
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irq_set_chip_data(virq, mpi);
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irq_set_chip_and_handler(virq, &mt6360_pmu_irq_chip, handle_simple_irq);
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irq_set_nested_thread(virq, true);
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irq_set_parent(virq, mpi->irq);
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irq_set_noprobe(virq);
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return 0;
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}
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static void mt6360_pmu_irq_domain_unmap(struct irq_domain *d, unsigned int virq)
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{
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irq_set_chip_and_handler(virq, NULL, NULL);
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irq_set_chip_data(virq, NULL);
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}
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static const struct irq_domain_ops mt6360_pmu_irq_domain_ops = {
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.map = mt6360_pmu_irq_domain_map,
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.unmap = mt6360_pmu_irq_domain_unmap,
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.xlate = irq_domain_xlate_onetwocell,
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};
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static int mt6360_pmu_gpio_irq_init(struct mt6360_pmu_info *mpi)
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{
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struct mt6360_pmu_platform_data *pdata = dev_get_platdata(mpi->dev);
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int ret;
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#ifdef CONFIG_MT6360_PMU_DEBUG
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int i;
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#endif
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ret = devm_gpio_request_one(mpi->dev, pdata->irq_gpio, GPIOF_IN,
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devm_kasprintf(mpi->dev, GFP_KERNEL,
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"%s.irq", dev_name(mpi->dev)));
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if (ret < 0) {
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dev_err(mpi->dev, "gpio reqeuest [%d] fail\n", pdata->irq_gpio);
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return ret;
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}
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mpi->irq = gpio_to_irq(pdata->irq_gpio);
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if (mpi->irq < 0) {
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dev_err(mpi->dev, "irq number [%d] fail\n", mpi->irq);
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return mpi->irq;
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}
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ret = devm_request_threaded_irq(mpi->dev, mpi->irq, NULL,
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mt6360_pmu_irq_handler,
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IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
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dev_name(mpi->dev), mpi);
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if (ret < 0) {
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dev_err(mpi->dev, "request irq [%d] fail\n", mpi->irq);
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return ret;
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}
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device_init_wakeup(mpi->dev, true);
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mpi->irq_domain = irq_domain_add_linear(mpi->dev->of_node,
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MT6360_PMU_IRQEVT_MAX,
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&mt6360_pmu_irq_domain_ops,
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mpi);
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if (!mpi->irq_domain) {
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dev_err(mpi->dev, "irq domain add fail\n");
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return -EINVAL;
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}
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#ifdef CONFIG_MT6360_PMU_DEBUG
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pmu_irq_duration = 0;
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for (i = 0; i < 8; i++) {
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duration_index[i] = 0;
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count_index[i] = 0;
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}
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#endif
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return 0;
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}
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static int mt6360_pmu_irq_maskall(struct mt6360_pmu_info *mpi)
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{
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u8 irq_events[MT6360_PMU_IRQ_REGNUM] = {0}, faultb_mask[2] = {0};
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int i, ret;
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/* init cache irq events*/
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memset(mpi->cache_irq_masks, 0xff, MT6360_PMU_IRQ_REGNUM);
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/* mask all indicator */
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ret = mt6360_pmu_reg_write(mpi, MT6360_PMU_IRQ_MASK, 0xff);
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if (ret < 0) {
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dev_err(mpi->dev, "write irq ind mask fail\n");
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return ret;
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}
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/* read faultb_mask */
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ret = mt6360_pmu_reg_block_read(mpi,
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MT6360_PMU_FAULTB_MASK, 2, faultb_mask);
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if (ret < 0) {
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dev_err(mpi->dev, "read faultb mask fail\n");
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return ret;
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}
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/* keep faultb default value */
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mpi->cache_irq_masks[11] = faultb_mask[0];
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mpi->cache_irq_masks[12] &= ~0x80;
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mpi->cache_irq_masks[12] |= (faultb_mask[1] & 0x80);
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ret = mt6360_pmu_reg_block_write(mpi, MT6360_PMU_CHG_MASK1,
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MT6360_PMU_IRQ_REGNUM,
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mpi->cache_irq_masks);
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if (ret < 0) {
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dev_err(mpi->dev, "write irq mask all to 0xff fail\n");
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return ret;
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}
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/* read booton status */
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ret = mt6360_pmu_reg_block_read(mpi, MT6360_PMU_CHG_IRQ1,
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MT6360_PMU_IRQ_REGNUM, irq_events);
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if (ret < 0) {
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dev_err(mpi->dev, "read booton irq status fail\n");
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return ret;
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}
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dev_info(mpi->dev, "booton irq status ++\n");
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for (i = 0; i < MT6360_PMU_IRQ_REGNUM; i++)
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dev_info(mpi->dev, "irq[%02x], %02x\n", i, irq_events[i]);
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dev_info(mpi->dev, "booton irq status --\n");
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/* write clear for booton events */
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ret = mt6360_pmu_reg_block_write(mpi, MT6360_PMU_CHG_IRQ1,
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MT6360_PMU_IRQ_REGNUM, irq_events);
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if (ret < 0) {
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dev_err(mpi->dev, "write already irq events to clear fail\n");
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return ret;
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}
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/* config all indicator to unmask, but all channel events are masked */
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ret = mt6360_pmu_reg_write(mpi, MT6360_PMU_IRQ_MASK, 0x00);
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if (ret < 0) {
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dev_err(mpi->dev, "write irq ind mask fail\n");
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return ret;
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}
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return 0;
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}
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int mt6360_pmu_irq_suspend(struct mt6360_pmu_info *mpi)
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{
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if (device_may_wakeup(mpi->dev))
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enable_irq_wake(mpi->irq);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt6360_pmu_irq_suspend);
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int mt6360_pmu_irq_resume(struct mt6360_pmu_info *mpi)
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{
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if (device_may_wakeup(mpi->dev))
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disable_irq_wake(mpi->irq);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt6360_pmu_irq_resume);
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int mt6360_pmu_irq_register(struct mt6360_pmu_info *mpi)
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{
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int ret;
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dev_dbg(mpi->dev, "%s ++\n", __func__);
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ret = mt6360_pmu_irq_maskall(mpi);
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if (ret < 0) {
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dev_err(mpi->dev, "irq mask all fail\n");
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return ret;
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}
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ret = mt6360_pmu_gpio_irq_init(mpi);
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if (ret < 0) {
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dev_err(mpi->dev, "gpio_irq_init fail\n");
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return ret;
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}
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dev_dbg(mpi->dev, "%s --\n", __func__);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mt6360_pmu_irq_register);
|
||
|
|
|
||
|
|
void mt6360_pmu_irq_unregister(struct mt6360_pmu_info *mpi)
|
||
|
|
{
|
||
|
|
irq_domain_remove(mpi->irq_domain);
|
||
|
|
device_init_wakeup(mpi->dev, false);
|
||
|
|
mt6360_pmu_irq_maskall(mpi);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(mt6360_pmu_irq_unregister);
|