5020 lines
359 KiB
C
5020 lines
359 KiB
C
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/*************************************************************************/ /*!
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@Title Hardware definition file rgxpmdefs.h
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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/* **** Autogenerated C -- do not edit **** */
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/*
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* rogue_pm.def: #13
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*/
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#ifndef RGXPMDEFS_H
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#define RGXPMDEFS_H
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#include "img_types.h"
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#include "img_defs.h"
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#define RGXPMDEFS_REVISION 13
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/*
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The mini PB size on a per-RT basis
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*/
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typedef struct PM_DATA_MINI_PB_TAG {
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IMG_UINT32 u32_0;
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} PM_DATA_MINI_PB;
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/*
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*/
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#define PM_DATA_MINI_PB_SIZE_WOFF (0U)
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#define PM_DATA_MINI_PB_SIZE_SHIFT (0U)
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#define PM_DATA_MINI_PB_SIZE_CLRMSK (0xFFFFFC00U)
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#define PM_DATA_MINI_PB_SET_SIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_MINI_PB_SIZE_CLRMSK ) | (((_x_) & (0x000003ffU)) << (PM_DATA_MINI_PB_SIZE_SHIFT))))
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#define PM_DATA_MINI_PB_GET_SIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_MINI_PB_SIZE_SHIFT)) & 0x000003ffU)
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/*
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The minimum PB size for the WDDM driver only. It is consistent with the OPENGL/OPENGLES. However, it is breaking down as two parts: the pagable memory and non pagable memory.
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*/
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typedef struct PM_DATA_WDDM_MINI_PB_TAG {
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IMG_UINT32 u32_0;
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} PM_DATA_WDDM_MINI_PB;
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/*
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*/
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#define PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_WOFF (0U)
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#define PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_SHIFT (10U)
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#define PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_CLRMSK (0xFFF003FFU)
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#define PM_DATA_WDDM_MINI_PB_SET_NON_PAGABLE_SIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_CLRMSK ) | (((_x_) & (0x000003ffU)) << (PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_SHIFT))))
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#define PM_DATA_WDDM_MINI_PB_GET_NON_PAGABLE_SIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_WDDM_MINI_PB_NON_PAGABLE_SIZE_SHIFT)) & 0x000003ffU)
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/*
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*/
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#define PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_WOFF (0U)
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#define PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_SHIFT (0U)
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#define PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_CLRMSK (0xFFFFFC00U)
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#define PM_DATA_WDDM_MINI_PB_SET_PAGABLE_SIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_CLRMSK ) | (((_x_) & (0x000003ffU)) << (PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_SHIFT))))
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#define PM_DATA_WDDM_MINI_PB_GET_PAGABLE_SIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_WDDM_MINI_PB_PAGABLE_SIZE_SHIFT)) & 0x000003ffU)
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/*
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the mini number of the reserve pages when only the local free list is used */
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#define PM_DATA_PM_RESERVE_PAGES_MIN_SIZE (0x00000007U)
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/*
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the mini number of the reserve pages when unified free list is present */
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#define PM_DATA_PM_RESERVE_PAGES_MIN_UNIFIED_SIZE (0x0000000bU)
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/*
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This defines the format of entries in the FSTACK, UFSTACK and MMUSTACK
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*/
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typedef struct PM_DATA_FSTACK_ENTRY_TAG {
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IMG_UINT32 u32_0;
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} PM_DATA_FSTACK_ENTRY;
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/*
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Reserved for future use
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*/
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#define PM_DATA_FSTACK_ENTRY_RSV_WOFF (0U)
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#define PM_DATA_FSTACK_ENTRY_RSV_SHIFT (28U)
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#define PM_DATA_FSTACK_ENTRY_RSV_CLRMSK (0x0FFFFFFFU)
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#define PM_DATA_FSTACK_ENTRY_SET_RSV(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_FSTACK_ENTRY_RSV_CLRMSK ) | (((_x_) & (0x0000000fU)) << (PM_DATA_FSTACK_ENTRY_RSV_SHIFT))))
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#define PM_DATA_FSTACK_ENTRY_GET_RSV(_ft_) (((_ft_).u32_0 >> (PM_DATA_FSTACK_ENTRY_RSV_SHIFT)) & 0x0000000fU)
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/*
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Address of 4 kB physical page
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*/
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#define PM_DATA_FSTACK_ENTRY_PPAGE_WOFF (0U)
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#define PM_DATA_FSTACK_ENTRY_PPAGE_SHIFT (0U)
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#define PM_DATA_FSTACK_ENTRY_PPAGE_CLRMSK (0xF0000000U)
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#define PM_DATA_FSTACK_ENTRY_SET_PPAGE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_FSTACK_ENTRY_PPAGE_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_FSTACK_ENTRY_PPAGE_SHIFT))))
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#define PM_DATA_FSTACK_ENTRY_GET_PPAGE(_ft_) (((_ft_).u32_0 >> (PM_DATA_FSTACK_ENTRY_PPAGE_SHIFT)) & 0x0fffffffU)
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/*
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This defines the format of an ALIST (Allocation List) entry
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*/
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typedef struct PM_DATA_ALIST_ENTRY_TAG {
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IMG_UINT32 u32_0;
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IMG_UINT32 u32_1;
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} PM_DATA_ALIST_ENTRY;
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/*
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Valid bit. Indicates whether this ALIST entry is valid.
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*/
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#define PM_DATA_ALIST_ENTRY_VAL_WOFF (1U)
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#define PM_DATA_ALIST_ENTRY_VAL_SHIFT (31U)
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#define PM_DATA_ALIST_ENTRY_VAL_CLRMSK (0x7FFFFFFFU)
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#define PM_DATA_ALIST_ENTRY_SET_VAL(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_ALIST_ENTRY_VAL_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_ALIST_ENTRY_VAL_SHIFT))))
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#define PM_DATA_ALIST_ENTRY_GET_VAL(_ft_) (((_ft_).u32_1 >> (PM_DATA_ALIST_ENTRY_VAL_SHIFT)) & 0x00000001U)
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/*
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The "data master" of the virtual page. 0=VCE, 1=TE, 2,3=reserved.
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*/
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#define PM_DATA_ALIST_ENTRY_DM_INDEX_WOFF (1U)
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#define PM_DATA_ALIST_ENTRY_DM_INDEX_SHIFT (26U)
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#define PM_DATA_ALIST_ENTRY_DM_INDEX_CLRMSK (0xF3FFFFFFU)
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#define PM_DATA_ALIST_ENTRY_SET_DM_INDEX(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_ALIST_ENTRY_DM_INDEX_CLRMSK ) | (((_x_) & (0x00000003U)) << (PM_DATA_ALIST_ENTRY_DM_INDEX_SHIFT))))
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#define PM_DATA_ALIST_ENTRY_GET_DM_INDEX(_ft_) (((_ft_).u32_1 >> (PM_DATA_ALIST_ENTRY_DM_INDEX_SHIFT)) & 0x00000003U)
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/*
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Render Target Array index. Up to 2 k Render Target Arrays are supported.
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*/
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#define PM_DATA_ALIST_ENTRY_RTA_INDEX_WOFF (1U)
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#define PM_DATA_ALIST_ENTRY_RTA_INDEX_SHIFT (14U)
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#define PM_DATA_ALIST_ENTRY_RTA_INDEX_CLRMSK (0xFE003FFFU)
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#define PM_DATA_ALIST_ENTRY_SET_RTA_INDEX(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_ALIST_ENTRY_RTA_INDEX_CLRMSK ) | (((_x_) & (0x000007ffU)) << (PM_DATA_ALIST_ENTRY_RTA_INDEX_SHIFT))))
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#define PM_DATA_ALIST_ENTRY_GET_RTA_INDEX(_ft_) (((_ft_).u32_1 >> (PM_DATA_ALIST_ENTRY_RTA_INDEX_SHIFT)) & 0x000007ffU)
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/*
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The virtual page number (16 kB virtual page).
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*/
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W0_WOFF (0U)
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W1_WOFF (1U)
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W0_SHIFT (16U)
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W1_SHIFT (0U)
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W0_CLRMSK (0x0000FFFFU)
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#define PM_DATA_ALIST_ENTRY_VRP_PPAGE_W1_CLRMSK (0xFFFFFFF0U)
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#define PM_DATA_ALIST_ENTRY_SET_VRP_PPAGE(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_ALIST_ENTRY_VRP_PPAGE_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000ffff))) << 16))); \
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((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_ALIST_ENTRY_VRP_PPAGE_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000f0000))) >> 16))); }
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#define PM_DATA_ALIST_ENTRY_GET_VRP_PPAGE(_ft_) (((_ft_).u32_0 >> (16)) | ((IMG_UINT64)((_ft_).u32_1 & 0x0000000fU ) << (16)))
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/*
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The 16-bit macrotile mask. Indicates which macrotile(s) are using this 16 kB page
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*/
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#define PM_DATA_ALIST_ENTRY_MTILE_MASK_WOFF (0U)
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#define PM_DATA_ALIST_ENTRY_MTILE_MASK_SHIFT (0U)
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#define PM_DATA_ALIST_ENTRY_MTILE_MASK_CLRMSK (0xFFFF0000U)
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#define PM_DATA_ALIST_ENTRY_SET_MTILE_MASK(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_ALIST_ENTRY_MTILE_MASK_CLRMSK ) | (((_x_) & (0x0000ffffU)) << (PM_DATA_ALIST_ENTRY_MTILE_MASK_SHIFT))))
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#define PM_DATA_ALIST_ENTRY_GET_MTILE_MASK(_ft_) (((_ft_).u32_0 >> (PM_DATA_ALIST_ENTRY_MTILE_MASK_SHIFT)) & 0x0000ffffU)
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/*
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This defines the format of entries in the MLIST
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*/
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typedef struct PM_DATA_MLIST_ENTRY_TAG {
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IMG_UINT32 u32_0;
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} PM_DATA_MLIST_ENTRY;
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/*
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Original source of the MMU page:
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0=Page was allocated from the FSTACK,
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1=Page was allocated from the UFSTACK.
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This bit is ignored when RGX_CR_PM_MMU_STACK_POLICY=1
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*/
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#define PM_DATA_MLIST_ENTRY_SRC_WOFF (0U)
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#define PM_DATA_MLIST_ENTRY_SRC_SHIFT (31U)
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#define PM_DATA_MLIST_ENTRY_SRC_CLRMSK (0x7FFFFFFFU)
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#define PM_DATA_MLIST_ENTRY_SET_SRC(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_MLIST_ENTRY_SRC_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_MLIST_ENTRY_SRC_SHIFT))))
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#define PM_DATA_MLIST_ENTRY_GET_SRC(_ft_) (((_ft_).u32_0 >> (PM_DATA_MLIST_ENTRY_SRC_SHIFT)) & 0x00000001U)
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/*
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Address of Physical Page allocated to MMU
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*/
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#define PM_DATA_MLIST_ENTRY_PPAGE_WOFF (0U)
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#define PM_DATA_MLIST_ENTRY_PPAGE_SHIFT (0U)
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#define PM_DATA_MLIST_ENTRY_PPAGE_CLRMSK (0xF0000000U)
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#define PM_DATA_MLIST_ENTRY_SET_PPAGE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_MLIST_ENTRY_PPAGE_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_MLIST_ENTRY_PPAGE_SHIFT))))
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#define PM_DATA_MLIST_ENTRY_GET_PPAGE(_ft_) (((_ft_).u32_0 >> (PM_DATA_MLIST_ENTRY_PPAGE_SHIFT)) & 0x0fffffffU)
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/*
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This defines the format of entries in the VFP Table
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*/
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typedef struct PM_DATA_VFP_TABLE_ENTRY_TAG {
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IMG_UINT32 u32_0;
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IMG_UINT32 u32_1;
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} PM_DATA_VFP_TABLE_ENTRY;
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/*
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Valid bit. 0=VFP is unmapped, 1=VFP is mapped.
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*/
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#define PM_DATA_VFP_TABLE_ENTRY_VALID_WOFF (1U)
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#define PM_DATA_VFP_TABLE_ENTRY_VALID_SHIFT (31U)
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#define PM_DATA_VFP_TABLE_ENTRY_VALID_CLRMSK (0x7FFFFFFFU)
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#define PM_DATA_VFP_TABLE_ENTRY_SET_VALID(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_VFP_TABLE_ENTRY_VALID_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VFP_TABLE_ENTRY_VALID_SHIFT))))
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#define PM_DATA_VFP_TABLE_ENTRY_GET_VALID(_ft_) (((_ft_).u32_1 >> (PM_DATA_VFP_TABLE_ENTRY_VALID_SHIFT)) & 0x00000001U)
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/*
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Address of MMU Page Table Entry. 8 Byte Granular.
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*/
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#define PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_WOFF (1U)
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#define PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_SHIFT (0U)
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#define PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_CLRMSK (0x80000000U)
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#define PM_DATA_VFP_TABLE_ENTRY_SET_PTE_PTR(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_SHIFT))))
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#define PM_DATA_VFP_TABLE_ENTRY_GET_PTE_PTR(_ft_) (((_ft_).u32_1 >> (PM_DATA_VFP_TABLE_ENTRY_PTE_PTR_SHIFT)) & 0x7fffffffU)
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/*
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Reserved for future use.
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*/
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#define PM_DATA_VFP_TABLE_ENTRY_RSV_WOFF (0U)
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#define PM_DATA_VFP_TABLE_ENTRY_RSV_SHIFT (28U)
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#define PM_DATA_VFP_TABLE_ENTRY_RSV_CLRMSK (0x0FFFFFFFU)
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#define PM_DATA_VFP_TABLE_ENTRY_SET_RSV(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_VFP_TABLE_ENTRY_RSV_CLRMSK ) | (((_x_) & (0x0000000fU)) << (PM_DATA_VFP_TABLE_ENTRY_RSV_SHIFT))))
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#define PM_DATA_VFP_TABLE_ENTRY_GET_RSV(_ft_) (((_ft_).u32_0 >> (PM_DATA_VFP_TABLE_ENTRY_RSV_SHIFT)) & 0x0000000fU)
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/*
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Address of 1 kB Physical Page. 1 TB addressable.
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*/
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#define PM_DATA_VFP_TABLE_ENTRY_PPAGE_WOFF (0U)
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#define PM_DATA_VFP_TABLE_ENTRY_PPAGE_SHIFT (0U)
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|
|
#define PM_DATA_VFP_TABLE_ENTRY_PPAGE_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VFP_TABLE_ENTRY_SET_PPAGE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_VFP_TABLE_ENTRY_PPAGE_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VFP_TABLE_ENTRY_PPAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VFP_TABLE_ENTRY_GET_PPAGE(_ft_) (((_ft_).u32_0 >> (PM_DATA_VFP_TABLE_ENTRY_PPAGE_SHIFT)) & 0x0fffffffU)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
PerPipe Segment SIZE, it has a fixed mapping as follows:
|
||
|
|
PIPE Number - Segment Size
|
||
|
|
1 16G
|
||
|
|
2 8G
|
||
|
|
4 4G
|
||
|
|
8 2G
|
||
|
|
*/
|
||
|
|
typedef struct PM_DATA_PERPIPE_SEGSIZE_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
} PM_DATA_PERPIPE_SEGSIZE;
|
||
|
|
|
||
|
|
/*
|
||
|
|
PerSegment Size 2G
|
||
|
|
*/
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_WOFF (0U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_SHIFT (3U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_CLRMSK (0xFFFFFFF7U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_SET_PIPE8_SEGSZIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_SHIFT))))
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_GET_PIPE8_SEGSZIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_PERPIPE_SEGSIZE_PIPE8_SEGSZIZE_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
PerSegment Size 4G
|
||
|
|
*/
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_WOFF (0U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_SHIFT (2U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_CLRMSK (0xFFFFFFFBU)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_SET_PIPE4_SEGSZIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_SHIFT))))
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_GET_PIPE4_SEGSZIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_PERPIPE_SEGSIZE_PIPE4_SEGSZIZE_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
PerSegment Size 8G
|
||
|
|
*/
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_WOFF (0U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_SHIFT (1U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_CLRMSK (0xFFFFFFFDU)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_SET_PIPE2_SEGSZIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_SHIFT))))
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_GET_PIPE2_SEGSZIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_PERPIPE_SEGSIZE_PIPE2_SEGSZIZE_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
PerSegment Size 16G
|
||
|
|
*/
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_WOFF (0U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_SHIFT (0U)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_CLRMSK (0xFFFFFFFEU)
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_SET_PIPE1_SEGSZIZE(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_SHIFT))))
|
||
|
|
#define PM_DATA_PERPIPE_SEGSIZE_GET_PIPE1_SEGSZIZE(_ft_) (((_ft_).u32_0 >> (PM_DATA_PERPIPE_SEGSIZE_PIPE1_SEGSZIZE_SHIFT)) & 0x00000001U)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
PM Virtual Heap Buffer Offset. This buffer contains all the meta-data associated with each render target.
|
||
|
|
size is 11904/8 = 1488 Bytes.
|
||
|
|
|
||
|
|
Natively the buffer supports up to 8-VCEs and 8-TEs scaling without changing HW.
|
||
|
|
|
||
|
|
In case relevant PIPE N is not present, the corresponding space is just reserved.
|
||
|
|
*/
|
||
|
|
typedef struct PM_DATA_VHEAP_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
IMG_UINT32 u32_8;
|
||
|
|
IMG_UINT32 u32_9;
|
||
|
|
IMG_UINT32 u32_10;
|
||
|
|
IMG_UINT32 u32_11;
|
||
|
|
IMG_UINT32 u32_12;
|
||
|
|
IMG_UINT32 u32_13;
|
||
|
|
IMG_UINT32 u32_14;
|
||
|
|
IMG_UINT32 u32_15;
|
||
|
|
IMG_UINT32 u32_16;
|
||
|
|
IMG_UINT32 u32_17;
|
||
|
|
IMG_UINT32 u32_18;
|
||
|
|
IMG_UINT32 u32_19;
|
||
|
|
IMG_UINT32 u32_20;
|
||
|
|
IMG_UINT32 u32_21;
|
||
|
|
IMG_UINT32 u32_22;
|
||
|
|
IMG_UINT32 u32_23;
|
||
|
|
IMG_UINT32 u32_24;
|
||
|
|
IMG_UINT32 u32_25;
|
||
|
|
IMG_UINT32 u32_26;
|
||
|
|
IMG_UINT32 u32_27;
|
||
|
|
IMG_UINT32 u32_28;
|
||
|
|
IMG_UINT32 u32_29;
|
||
|
|
IMG_UINT32 u32_30;
|
||
|
|
IMG_UINT32 u32_31;
|
||
|
|
IMG_UINT32 u32_32;
|
||
|
|
IMG_UINT32 u32_33;
|
||
|
|
IMG_UINT32 u32_34;
|
||
|
|
IMG_UINT32 u32_35;
|
||
|
|
IMG_UINT32 u32_36;
|
||
|
|
IMG_UINT32 u32_37;
|
||
|
|
IMG_UINT32 u32_38;
|
||
|
|
IMG_UINT32 u32_39;
|
||
|
|
IMG_UINT32 u32_40;
|
||
|
|
IMG_UINT32 u32_41;
|
||
|
|
IMG_UINT32 u32_42;
|
||
|
|
IMG_UINT32 u32_43;
|
||
|
|
IMG_UINT32 u32_44;
|
||
|
|
IMG_UINT32 u32_45;
|
||
|
|
IMG_UINT32 u32_46;
|
||
|
|
IMG_UINT32 u32_47;
|
||
|
|
IMG_UINT32 u32_48;
|
||
|
|
IMG_UINT32 u32_49;
|
||
|
|
IMG_UINT32 u32_50;
|
||
|
|
IMG_UINT32 u32_51;
|
||
|
|
IMG_UINT32 u32_52;
|
||
|
|
IMG_UINT32 u32_53;
|
||
|
|
IMG_UINT32 u32_54;
|
||
|
|
IMG_UINT32 u32_55;
|
||
|
|
IMG_UINT32 u32_56;
|
||
|
|
IMG_UINT32 u32_57;
|
||
|
|
IMG_UINT32 u32_58;
|
||
|
|
IMG_UINT32 u32_59;
|
||
|
|
IMG_UINT32 u32_60;
|
||
|
|
IMG_UINT32 u32_61;
|
||
|
|
IMG_UINT32 u32_62;
|
||
|
|
IMG_UINT32 u32_63;
|
||
|
|
IMG_UINT32 u32_64;
|
||
|
|
IMG_UINT32 u32_65;
|
||
|
|
IMG_UINT32 u32_66;
|
||
|
|
IMG_UINT32 u32_67;
|
||
|
|
IMG_UINT32 u32_68;
|
||
|
|
IMG_UINT32 u32_69;
|
||
|
|
IMG_UINT32 u32_70;
|
||
|
|
IMG_UINT32 u32_71;
|
||
|
|
IMG_UINT32 u32_72;
|
||
|
|
IMG_UINT32 u32_73;
|
||
|
|
IMG_UINT32 u32_74;
|
||
|
|
IMG_UINT32 u32_75;
|
||
|
|
IMG_UINT32 u32_76;
|
||
|
|
IMG_UINT32 u32_77;
|
||
|
|
IMG_UINT32 u32_78;
|
||
|
|
IMG_UINT32 u32_79;
|
||
|
|
IMG_UINT32 u32_80;
|
||
|
|
IMG_UINT32 u32_81;
|
||
|
|
IMG_UINT32 u32_82;
|
||
|
|
IMG_UINT32 u32_83;
|
||
|
|
IMG_UINT32 u32_84;
|
||
|
|
IMG_UINT32 u32_85;
|
||
|
|
IMG_UINT32 u32_86;
|
||
|
|
IMG_UINT32 u32_87;
|
||
|
|
IMG_UINT32 u32_88;
|
||
|
|
IMG_UINT32 u32_89;
|
||
|
|
IMG_UINT32 u32_90;
|
||
|
|
IMG_UINT32 u32_91;
|
||
|
|
IMG_UINT32 u32_92;
|
||
|
|
IMG_UINT32 u32_93;
|
||
|
|
IMG_UINT32 u32_94;
|
||
|
|
IMG_UINT32 u32_95;
|
||
|
|
IMG_UINT32 u32_96;
|
||
|
|
IMG_UINT32 u32_97;
|
||
|
|
IMG_UINT32 u32_98;
|
||
|
|
IMG_UINT32 u32_99;
|
||
|
|
IMG_UINT32 u32_100;
|
||
|
|
IMG_UINT32 u32_101;
|
||
|
|
IMG_UINT32 u32_102;
|
||
|
|
IMG_UINT32 u32_103;
|
||
|
|
IMG_UINT32 u32_104;
|
||
|
|
IMG_UINT32 u32_105;
|
||
|
|
IMG_UINT32 u32_106;
|
||
|
|
IMG_UINT32 u32_107;
|
||
|
|
IMG_UINT32 u32_108;
|
||
|
|
IMG_UINT32 u32_109;
|
||
|
|
IMG_UINT32 u32_110;
|
||
|
|
IMG_UINT32 u32_111;
|
||
|
|
IMG_UINT32 u32_112;
|
||
|
|
IMG_UINT32 u32_113;
|
||
|
|
IMG_UINT32 u32_114;
|
||
|
|
IMG_UINT32 u32_115;
|
||
|
|
IMG_UINT32 u32_116;
|
||
|
|
IMG_UINT32 u32_117;
|
||
|
|
IMG_UINT32 u32_118;
|
||
|
|
IMG_UINT32 u32_119;
|
||
|
|
IMG_UINT32 u32_120;
|
||
|
|
IMG_UINT32 u32_121;
|
||
|
|
IMG_UINT32 u32_122;
|
||
|
|
IMG_UINT32 u32_123;
|
||
|
|
IMG_UINT32 u32_124;
|
||
|
|
IMG_UINT32 u32_125;
|
||
|
|
IMG_UINT32 u32_126;
|
||
|
|
IMG_UINT32 u32_127;
|
||
|
|
IMG_UINT32 u32_128;
|
||
|
|
IMG_UINT32 u32_129;
|
||
|
|
IMG_UINT32 u32_130;
|
||
|
|
IMG_UINT32 u32_131;
|
||
|
|
IMG_UINT32 u32_132;
|
||
|
|
IMG_UINT32 u32_133;
|
||
|
|
IMG_UINT32 u32_134;
|
||
|
|
IMG_UINT32 u32_135;
|
||
|
|
IMG_UINT32 u32_136;
|
||
|
|
IMG_UINT32 u32_137;
|
||
|
|
IMG_UINT32 u32_138;
|
||
|
|
IMG_UINT32 u32_139;
|
||
|
|
IMG_UINT32 u32_140;
|
||
|
|
IMG_UINT32 u32_141;
|
||
|
|
IMG_UINT32 u32_142;
|
||
|
|
IMG_UINT32 u32_143;
|
||
|
|
IMG_UINT32 u32_144;
|
||
|
|
IMG_UINT32 u32_145;
|
||
|
|
IMG_UINT32 u32_146;
|
||
|
|
IMG_UINT32 u32_147;
|
||
|
|
IMG_UINT32 u32_148;
|
||
|
|
IMG_UINT32 u32_149;
|
||
|
|
IMG_UINT32 u32_150;
|
||
|
|
IMG_UINT32 u32_151;
|
||
|
|
IMG_UINT32 u32_152;
|
||
|
|
IMG_UINT32 u32_153;
|
||
|
|
IMG_UINT32 u32_154;
|
||
|
|
IMG_UINT32 u32_155;
|
||
|
|
IMG_UINT32 u32_156;
|
||
|
|
IMG_UINT32 u32_157;
|
||
|
|
IMG_UINT32 u32_158;
|
||
|
|
IMG_UINT32 u32_159;
|
||
|
|
IMG_UINT32 u32_160;
|
||
|
|
IMG_UINT32 u32_161;
|
||
|
|
IMG_UINT32 u32_162;
|
||
|
|
IMG_UINT32 u32_163;
|
||
|
|
IMG_UINT32 u32_164;
|
||
|
|
IMG_UINT32 u32_165;
|
||
|
|
IMG_UINT32 u32_166;
|
||
|
|
IMG_UINT32 u32_167;
|
||
|
|
IMG_UINT32 u32_168;
|
||
|
|
IMG_UINT32 u32_169;
|
||
|
|
IMG_UINT32 u32_170;
|
||
|
|
IMG_UINT32 u32_171;
|
||
|
|
IMG_UINT32 u32_172;
|
||
|
|
IMG_UINT32 u32_173;
|
||
|
|
IMG_UINT32 u32_174;
|
||
|
|
IMG_UINT32 u32_175;
|
||
|
|
IMG_UINT32 u32_176;
|
||
|
|
IMG_UINT32 u32_177;
|
||
|
|
IMG_UINT32 u32_178;
|
||
|
|
IMG_UINT32 u32_179;
|
||
|
|
IMG_UINT32 u32_180;
|
||
|
|
IMG_UINT32 u32_181;
|
||
|
|
IMG_UINT32 u32_182;
|
||
|
|
IMG_UINT32 u32_183;
|
||
|
|
IMG_UINT32 u32_184;
|
||
|
|
IMG_UINT32 u32_185;
|
||
|
|
IMG_UINT32 u32_186;
|
||
|
|
IMG_UINT32 u32_187;
|
||
|
|
IMG_UINT32 u32_188;
|
||
|
|
IMG_UINT32 u32_189;
|
||
|
|
IMG_UINT32 u32_190;
|
||
|
|
IMG_UINT32 u32_191;
|
||
|
|
IMG_UINT32 u32_192;
|
||
|
|
IMG_UINT32 u32_193;
|
||
|
|
IMG_UINT32 u32_194;
|
||
|
|
IMG_UINT32 u32_195;
|
||
|
|
IMG_UINT32 u32_196;
|
||
|
|
IMG_UINT32 u32_197;
|
||
|
|
IMG_UINT32 u32_198;
|
||
|
|
IMG_UINT32 u32_199;
|
||
|
|
IMG_UINT32 u32_200;
|
||
|
|
IMG_UINT32 u32_201;
|
||
|
|
IMG_UINT32 u32_202;
|
||
|
|
IMG_UINT32 u32_203;
|
||
|
|
IMG_UINT32 u32_204;
|
||
|
|
IMG_UINT32 u32_205;
|
||
|
|
IMG_UINT32 u32_206;
|
||
|
|
IMG_UINT32 u32_207;
|
||
|
|
IMG_UINT32 u32_208;
|
||
|
|
IMG_UINT32 u32_209;
|
||
|
|
IMG_UINT32 u32_210;
|
||
|
|
IMG_UINT32 u32_211;
|
||
|
|
IMG_UINT32 u32_212;
|
||
|
|
IMG_UINT32 u32_213;
|
||
|
|
IMG_UINT32 u32_214;
|
||
|
|
IMG_UINT32 u32_215;
|
||
|
|
IMG_UINT32 u32_216;
|
||
|
|
IMG_UINT32 u32_217;
|
||
|
|
IMG_UINT32 u32_218;
|
||
|
|
IMG_UINT32 u32_219;
|
||
|
|
IMG_UINT32 u32_220;
|
||
|
|
IMG_UINT32 u32_221;
|
||
|
|
IMG_UINT32 u32_222;
|
||
|
|
IMG_UINT32 u32_223;
|
||
|
|
IMG_UINT32 u32_224;
|
||
|
|
IMG_UINT32 u32_225;
|
||
|
|
IMG_UINT32 u32_226;
|
||
|
|
IMG_UINT32 u32_227;
|
||
|
|
IMG_UINT32 u32_228;
|
||
|
|
IMG_UINT32 u32_229;
|
||
|
|
IMG_UINT32 u32_230;
|
||
|
|
IMG_UINT32 u32_231;
|
||
|
|
IMG_UINT32 u32_232;
|
||
|
|
IMG_UINT32 u32_233;
|
||
|
|
IMG_UINT32 u32_234;
|
||
|
|
IMG_UINT32 u32_235;
|
||
|
|
IMG_UINT32 u32_236;
|
||
|
|
IMG_UINT32 u32_237;
|
||
|
|
IMG_UINT32 u32_238;
|
||
|
|
IMG_UINT32 u32_239;
|
||
|
|
IMG_UINT32 u32_240;
|
||
|
|
IMG_UINT32 u32_241;
|
||
|
|
IMG_UINT32 u32_242;
|
||
|
|
IMG_UINT32 u32_243;
|
||
|
|
IMG_UINT32 u32_244;
|
||
|
|
IMG_UINT32 u32_245;
|
||
|
|
IMG_UINT32 u32_246;
|
||
|
|
IMG_UINT32 u32_247;
|
||
|
|
IMG_UINT32 u32_248;
|
||
|
|
IMG_UINT32 u32_249;
|
||
|
|
IMG_UINT32 u32_250;
|
||
|
|
IMG_UINT32 u32_251;
|
||
|
|
IMG_UINT32 u32_252;
|
||
|
|
IMG_UINT32 u32_253;
|
||
|
|
IMG_UINT32 u32_254;
|
||
|
|
IMG_UINT32 u32_255;
|
||
|
|
IMG_UINT32 u32_256;
|
||
|
|
IMG_UINT32 u32_257;
|
||
|
|
IMG_UINT32 u32_258;
|
||
|
|
IMG_UINT32 u32_259;
|
||
|
|
IMG_UINT32 u32_260;
|
||
|
|
IMG_UINT32 u32_261;
|
||
|
|
IMG_UINT32 u32_262;
|
||
|
|
IMG_UINT32 u32_263;
|
||
|
|
IMG_UINT32 u32_264;
|
||
|
|
IMG_UINT32 u32_265;
|
||
|
|
IMG_UINT32 u32_266;
|
||
|
|
IMG_UINT32 u32_267;
|
||
|
|
IMG_UINT32 u32_268;
|
||
|
|
IMG_UINT32 u32_269;
|
||
|
|
IMG_UINT32 u32_270;
|
||
|
|
IMG_UINT32 u32_271;
|
||
|
|
IMG_UINT32 u32_272;
|
||
|
|
IMG_UINT32 u32_273;
|
||
|
|
IMG_UINT32 u32_274;
|
||
|
|
IMG_UINT32 u32_275;
|
||
|
|
IMG_UINT32 u32_276;
|
||
|
|
IMG_UINT32 u32_277;
|
||
|
|
IMG_UINT32 u32_278;
|
||
|
|
IMG_UINT32 u32_279;
|
||
|
|
IMG_UINT32 u32_280;
|
||
|
|
IMG_UINT32 u32_281;
|
||
|
|
IMG_UINT32 u32_282;
|
||
|
|
IMG_UINT32 u32_283;
|
||
|
|
IMG_UINT32 u32_284;
|
||
|
|
IMG_UINT32 u32_285;
|
||
|
|
IMG_UINT32 u32_286;
|
||
|
|
IMG_UINT32 u32_287;
|
||
|
|
IMG_UINT32 u32_288;
|
||
|
|
IMG_UINT32 u32_289;
|
||
|
|
IMG_UINT32 u32_290;
|
||
|
|
IMG_UINT32 u32_291;
|
||
|
|
IMG_UINT32 u32_292;
|
||
|
|
IMG_UINT32 u32_293;
|
||
|
|
IMG_UINT32 u32_294;
|
||
|
|
IMG_UINT32 u32_295;
|
||
|
|
IMG_UINT32 u32_296;
|
||
|
|
IMG_UINT32 u32_297;
|
||
|
|
IMG_UINT32 u32_298;
|
||
|
|
IMG_UINT32 u32_299;
|
||
|
|
IMG_UINT32 u32_300;
|
||
|
|
IMG_UINT32 u32_301;
|
||
|
|
IMG_UINT32 u32_302;
|
||
|
|
IMG_UINT32 u32_303;
|
||
|
|
IMG_UINT32 u32_304;
|
||
|
|
IMG_UINT32 u32_305;
|
||
|
|
IMG_UINT32 u32_306;
|
||
|
|
IMG_UINT32 u32_307;
|
||
|
|
IMG_UINT32 u32_308;
|
||
|
|
IMG_UINT32 u32_309;
|
||
|
|
IMG_UINT32 u32_310;
|
||
|
|
IMG_UINT32 u32_311;
|
||
|
|
IMG_UINT32 u32_312;
|
||
|
|
IMG_UINT32 u32_313;
|
||
|
|
IMG_UINT32 u32_314;
|
||
|
|
IMG_UINT32 u32_315;
|
||
|
|
IMG_UINT32 u32_316;
|
||
|
|
IMG_UINT32 u32_317;
|
||
|
|
IMG_UINT32 u32_318;
|
||
|
|
IMG_UINT32 u32_319;
|
||
|
|
IMG_UINT32 u32_320;
|
||
|
|
IMG_UINT32 u32_321;
|
||
|
|
IMG_UINT32 u32_322;
|
||
|
|
IMG_UINT32 u32_323;
|
||
|
|
IMG_UINT32 u32_324;
|
||
|
|
IMG_UINT32 u32_325;
|
||
|
|
IMG_UINT32 u32_326;
|
||
|
|
IMG_UINT32 u32_327;
|
||
|
|
IMG_UINT32 u32_328;
|
||
|
|
IMG_UINT32 u32_329;
|
||
|
|
IMG_UINT32 u32_330;
|
||
|
|
IMG_UINT32 u32_331;
|
||
|
|
IMG_UINT32 u32_332;
|
||
|
|
IMG_UINT32 u32_333;
|
||
|
|
IMG_UINT32 u32_334;
|
||
|
|
IMG_UINT32 u32_335;
|
||
|
|
IMG_UINT32 u32_336;
|
||
|
|
IMG_UINT32 u32_337;
|
||
|
|
IMG_UINT32 u32_338;
|
||
|
|
IMG_UINT32 u32_339;
|
||
|
|
IMG_UINT32 u32_340;
|
||
|
|
IMG_UINT32 u32_341;
|
||
|
|
IMG_UINT32 u32_342;
|
||
|
|
IMG_UINT32 u32_343;
|
||
|
|
IMG_UINT32 u32_344;
|
||
|
|
IMG_UINT32 u32_345;
|
||
|
|
IMG_UINT32 u32_346;
|
||
|
|
IMG_UINT32 u32_347;
|
||
|
|
IMG_UINT32 u32_348;
|
||
|
|
IMG_UINT32 u32_349;
|
||
|
|
IMG_UINT32 u32_350;
|
||
|
|
IMG_UINT32 u32_351;
|
||
|
|
IMG_UINT32 u32_352;
|
||
|
|
IMG_UINT32 u32_353;
|
||
|
|
IMG_UINT32 u32_354;
|
||
|
|
IMG_UINT32 u32_355;
|
||
|
|
IMG_UINT32 u32_356;
|
||
|
|
IMG_UINT32 u32_357;
|
||
|
|
IMG_UINT32 u32_358;
|
||
|
|
IMG_UINT32 u32_359;
|
||
|
|
IMG_UINT32 u32_360;
|
||
|
|
IMG_UINT32 u32_361;
|
||
|
|
IMG_UINT32 u32_362;
|
||
|
|
IMG_UINT32 u32_363;
|
||
|
|
IMG_UINT32 u32_364;
|
||
|
|
IMG_UINT32 u32_365;
|
||
|
|
IMG_UINT32 u32_366;
|
||
|
|
IMG_UINT32 u32_367;
|
||
|
|
IMG_UINT32 u32_368;
|
||
|
|
IMG_UINT32 u32_369;
|
||
|
|
IMG_UINT32 u32_370;
|
||
|
|
IMG_UINT32 u32_371;
|
||
|
|
} PM_DATA_VHEAP_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_WOFF (371U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_371 = (((_ft_).u32_371 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_371 >> (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W0_WOFF (370U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W1_WOFF (371U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_370 = (((_ft_).u32_370 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_371 = (((_ft_).u32_371 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_370 >> (20)) | ((IMG_UINT64)((_ft_).u32_371 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W0_WOFF (369U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W1_WOFF (370U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_369 = (((_ft_).u32_369 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_370 = (((_ft_).u32_370 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_369 >> (24)) | ((IMG_UINT64)((_ft_).u32_370 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W0_WOFF (368U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W1_WOFF (369U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_368 = (((_ft_).u32_368 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_369 = (((_ft_).u32_369 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_368 >> (28)) | ((IMG_UINT64)((_ft_).u32_369 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_WOFF (368U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_368 = (((_ft_).u32_368 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_368 >> (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE7 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_WOFF (364U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_364 = (((_ft_).u32_364 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_364 >> (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_WOFF (363U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_363 = (((_ft_).u32_363 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_363 >> (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W0_WOFF (362U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W1_WOFF (363U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_362 = (((_ft_).u32_362 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_363 = (((_ft_).u32_363 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_362 >> (20)) | ((IMG_UINT64)((_ft_).u32_363 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W0_WOFF (361U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W1_WOFF (362U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_361 = (((_ft_).u32_361 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_362 = (((_ft_).u32_362 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_361 >> (24)) | ((IMG_UINT64)((_ft_).u32_362 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W0_WOFF (360U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W1_WOFF (361U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_360 = (((_ft_).u32_360 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_361 = (((_ft_).u32_361 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_360 >> (28)) | ((IMG_UINT64)((_ft_).u32_361 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_WOFF (360U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_360 = (((_ft_).u32_360 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_360 >> (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE6 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_WOFF (356U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_356 = (((_ft_).u32_356 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_356 >> (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_WOFF (355U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_355 = (((_ft_).u32_355 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_355 >> (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W0_WOFF (354U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W1_WOFF (355U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_354 = (((_ft_).u32_354 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_355 = (((_ft_).u32_355 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_354 >> (20)) | ((IMG_UINT64)((_ft_).u32_355 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W0_WOFF (353U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W1_WOFF (354U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_353 = (((_ft_).u32_353 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_354 = (((_ft_).u32_354 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_353 >> (24)) | ((IMG_UINT64)((_ft_).u32_354 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W0_WOFF (352U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W1_WOFF (353U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_352 = (((_ft_).u32_352 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_353 = (((_ft_).u32_353 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_352 >> (28)) | ((IMG_UINT64)((_ft_).u32_353 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_WOFF (352U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_352 = (((_ft_).u32_352 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_352 >> (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE5 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_WOFF (348U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_348 = (((_ft_).u32_348 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_348 >> (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_WOFF (347U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_347 = (((_ft_).u32_347 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_347 >> (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W0_WOFF (346U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W1_WOFF (347U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_346 = (((_ft_).u32_346 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_347 = (((_ft_).u32_347 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_346 >> (20)) | ((IMG_UINT64)((_ft_).u32_347 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W0_WOFF (345U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W1_WOFF (346U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_345 = (((_ft_).u32_345 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_346 = (((_ft_).u32_346 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_345 >> (24)) | ((IMG_UINT64)((_ft_).u32_346 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W0_WOFF (344U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W1_WOFF (345U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_344 = (((_ft_).u32_344 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_345 = (((_ft_).u32_345 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_344 >> (28)) | ((IMG_UINT64)((_ft_).u32_345 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_WOFF (344U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_344 = (((_ft_).u32_344 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_344 >> (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE4 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_WOFF (340U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_340 = (((_ft_).u32_340 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_340 >> (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_WOFF (339U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_339 = (((_ft_).u32_339 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_339 >> (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W0_WOFF (338U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W1_WOFF (339U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_338 = (((_ft_).u32_338 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_339 = (((_ft_).u32_339 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_338 >> (20)) | ((IMG_UINT64)((_ft_).u32_339 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W0_WOFF (337U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W1_WOFF (338U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_337 = (((_ft_).u32_337 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_338 = (((_ft_).u32_338 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_337 >> (24)) | ((IMG_UINT64)((_ft_).u32_338 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W0_WOFF (336U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W1_WOFF (337U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_336 = (((_ft_).u32_336 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_337 = (((_ft_).u32_337 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_336 >> (28)) | ((IMG_UINT64)((_ft_).u32_337 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_WOFF (336U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_336 = (((_ft_).u32_336 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_336 >> (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE3 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_WOFF (332U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_332 = (((_ft_).u32_332 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_332 >> (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_WOFF (331U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_331 = (((_ft_).u32_331 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_331 >> (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W0_WOFF (330U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W1_WOFF (331U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_330 = (((_ft_).u32_330 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_331 = (((_ft_).u32_331 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_330 >> (20)) | ((IMG_UINT64)((_ft_).u32_331 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W0_WOFF (329U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W1_WOFF (330U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_329 = (((_ft_).u32_329 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_330 = (((_ft_).u32_330 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_329 >> (24)) | ((IMG_UINT64)((_ft_).u32_330 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W0_WOFF (328U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W1_WOFF (329U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_328 = (((_ft_).u32_328 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_329 = (((_ft_).u32_329 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_328 >> (28)) | ((IMG_UINT64)((_ft_).u32_329 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_WOFF (328U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_328 = (((_ft_).u32_328 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_328 >> (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE2 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_WOFF (324U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_324 = (((_ft_).u32_324 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_324 >> (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_WOFF (323U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_323 = (((_ft_).u32_323 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_323 >> (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W0_WOFF (322U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W1_WOFF (323U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_322 = (((_ft_).u32_322 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_323 = (((_ft_).u32_323 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_322 >> (20)) | ((IMG_UINT64)((_ft_).u32_323 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W0_WOFF (321U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W1_WOFF (322U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_321 = (((_ft_).u32_321 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_322 = (((_ft_).u32_322 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_321 >> (24)) | ((IMG_UINT64)((_ft_).u32_322 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W0_WOFF (320U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W1_WOFF (321U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_320 = (((_ft_).u32_320 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_321 = (((_ft_).u32_321 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_320 >> (28)) | ((IMG_UINT64)((_ft_).u32_321 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_WOFF (320U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_320 = (((_ft_).u32_320 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_320 >> (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE1 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_WOFF (316U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_316 = (((_ft_).u32_316 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_316 >> (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_WOFF (315U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_315 = (((_ft_).u32_315 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_315 >> (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W0_WOFF (314U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W1_WOFF (315U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_314 = (((_ft_).u32_314 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_315 = (((_ft_).u32_315 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_314 >> (20)) | ((IMG_UINT64)((_ft_).u32_315 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W0_WOFF (313U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W1_WOFF (314U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_313 = (((_ft_).u32_313 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_314 = (((_ft_).u32_314 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_313 >> (24)) | ((IMG_UINT64)((_ft_).u32_314 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W0_WOFF (312U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W1_WOFF (313U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_312 = (((_ft_).u32_312 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_313 = (((_ft_).u32_313 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_312 >> (28)) | ((IMG_UINT64)((_ft_).u32_313 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_WOFF (312U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_312 = (((_ft_).u32_312 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_312 >> (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
TE0 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_WOFF (308U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_308 = (((_ft_).u32_308 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_308 >> (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_WOFF (307U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_307 = (((_ft_).u32_307 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_307 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W0_WOFF (306U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W1_WOFF (307U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_306 = (((_ft_).u32_306 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_307 = (((_ft_).u32_307 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_306 >> (20)) | ((IMG_UINT64)((_ft_).u32_307 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W0_WOFF (305U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W1_WOFF (306U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_305 = (((_ft_).u32_305 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_306 = (((_ft_).u32_306 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_305 >> (24)) | ((IMG_UINT64)((_ft_).u32_306 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W0_WOFF (304U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W1_WOFF (305U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_304 = (((_ft_).u32_304 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_305 = (((_ft_).u32_305 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_304 >> (28)) | ((IMG_UINT64)((_ft_).u32_305 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_WOFF (304U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_304 = (((_ft_).u32_304 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_304 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_WOFF (300U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_300 = (((_ft_).u32_300 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_300 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_WOFF (299U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_299 = (((_ft_).u32_299 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_299 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W0_WOFF (298U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W1_WOFF (299U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_298 = (((_ft_).u32_298 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_299 = (((_ft_).u32_299 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_298 >> (20)) | ((IMG_UINT64)((_ft_).u32_299 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W0_WOFF (297U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W1_WOFF (298U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_297 = (((_ft_).u32_297 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_298 = (((_ft_).u32_298 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_297 >> (24)) | ((IMG_UINT64)((_ft_).u32_298 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W0_WOFF (296U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W1_WOFF (297U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_296 = (((_ft_).u32_296 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_297 = (((_ft_).u32_297 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_296 >> (28)) | ((IMG_UINT64)((_ft_).u32_297 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_WOFF (296U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_296 = (((_ft_).u32_296 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_296 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_WOFF (292U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_292 = (((_ft_).u32_292 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_292 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_WOFF (291U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_291 = (((_ft_).u32_291 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_291 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W0_WOFF (290U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W1_WOFF (291U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_290 = (((_ft_).u32_290 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_291 = (((_ft_).u32_291 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_290 >> (20)) | ((IMG_UINT64)((_ft_).u32_291 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W0_WOFF (289U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W1_WOFF (290U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_289 = (((_ft_).u32_289 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_290 = (((_ft_).u32_290 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_289 >> (24)) | ((IMG_UINT64)((_ft_).u32_290 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W0_WOFF (288U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W1_WOFF (289U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_288 = (((_ft_).u32_288 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_289 = (((_ft_).u32_289 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_288 >> (28)) | ((IMG_UINT64)((_ft_).u32_289 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_WOFF (288U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_288 = (((_ft_).u32_288 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_288 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_WOFF (284U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_284 = (((_ft_).u32_284 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_284 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_WOFF (283U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_283 = (((_ft_).u32_283 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_283 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W0_WOFF (282U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W1_WOFF (283U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_282 = (((_ft_).u32_282 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_283 = (((_ft_).u32_283 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_282 >> (20)) | ((IMG_UINT64)((_ft_).u32_283 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W0_WOFF (281U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W1_WOFF (282U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_281 = (((_ft_).u32_281 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_282 = (((_ft_).u32_282 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_281 >> (24)) | ((IMG_UINT64)((_ft_).u32_282 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W0_WOFF (280U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W1_WOFF (281U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_280 = (((_ft_).u32_280 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_281 = (((_ft_).u32_281 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_280 >> (28)) | ((IMG_UINT64)((_ft_).u32_281 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_WOFF (280U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_280 = (((_ft_).u32_280 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_280 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE7 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_WOFF (276U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_276 = (((_ft_).u32_276 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_276 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_WOFF (259U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_259 = (((_ft_).u32_259 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_259 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W0_WOFF (258U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W1_WOFF (259U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_258 = (((_ft_).u32_258 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_259 = (((_ft_).u32_259 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_258 >> (20)) | ((IMG_UINT64)((_ft_).u32_259 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W0_WOFF (257U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W1_WOFF (258U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_257 = (((_ft_).u32_257 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_258 = (((_ft_).u32_258 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_257 >> (24)) | ((IMG_UINT64)((_ft_).u32_258 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W0_WOFF (256U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W1_WOFF (257U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_256 = (((_ft_).u32_256 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_257 = (((_ft_).u32_257 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_256 >> (28)) | ((IMG_UINT64)((_ft_).u32_257 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_WOFF (256U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_256 = (((_ft_).u32_256 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_256 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE6 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_WOFF (252U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_252 = (((_ft_).u32_252 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_252 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_WOFF (251U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_251 = (((_ft_).u32_251 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_251 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W0_WOFF (250U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W1_WOFF (251U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_250 = (((_ft_).u32_250 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_251 = (((_ft_).u32_251 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_250 >> (20)) | ((IMG_UINT64)((_ft_).u32_251 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W0_WOFF (249U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W1_WOFF (250U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_249 = (((_ft_).u32_249 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_250 = (((_ft_).u32_250 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_249 >> (24)) | ((IMG_UINT64)((_ft_).u32_250 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W0_WOFF (248U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W1_WOFF (249U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_248 = (((_ft_).u32_248 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_249 = (((_ft_).u32_249 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_248 >> (28)) | ((IMG_UINT64)((_ft_).u32_249 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_WOFF (248U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_248 = (((_ft_).u32_248 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_248 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE6 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_WOFF (244U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_244 = (((_ft_).u32_244 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_244 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_WOFF (243U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_243 = (((_ft_).u32_243 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_243 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W0_WOFF (242U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W1_WOFF (243U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_242 = (((_ft_).u32_242 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_243 = (((_ft_).u32_243 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_242 >> (20)) | ((IMG_UINT64)((_ft_).u32_243 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W0_WOFF (241U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W1_WOFF (242U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_241 = (((_ft_).u32_241 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_242 = (((_ft_).u32_242 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_241 >> (24)) | ((IMG_UINT64)((_ft_).u32_242 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W0_WOFF (240U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W1_WOFF (241U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_240 = (((_ft_).u32_240 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_241 = (((_ft_).u32_241 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_240 >> (28)) | ((IMG_UINT64)((_ft_).u32_241 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_WOFF (240U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_240 = (((_ft_).u32_240 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_240 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_WOFF (236U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_236 = (((_ft_).u32_236 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_236 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_WOFF (235U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_235 = (((_ft_).u32_235 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_235 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W0_WOFF (234U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W1_WOFF (235U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_234 = (((_ft_).u32_234 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_235 = (((_ft_).u32_235 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_234 >> (20)) | ((IMG_UINT64)((_ft_).u32_235 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W0_WOFF (233U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W1_WOFF (234U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_233 = (((_ft_).u32_233 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_234 = (((_ft_).u32_234 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_233 >> (24)) | ((IMG_UINT64)((_ft_).u32_234 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W0_WOFF (232U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W1_WOFF (233U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_232 = (((_ft_).u32_232 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_233 = (((_ft_).u32_233 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_232 >> (28)) | ((IMG_UINT64)((_ft_).u32_233 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_WOFF (232U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_232 = (((_ft_).u32_232 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_232 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_WOFF (228U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_228 = (((_ft_).u32_228 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_228 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_WOFF (227U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_227 = (((_ft_).u32_227 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_227 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W0_WOFF (226U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W1_WOFF (227U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_226 = (((_ft_).u32_226 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_227 = (((_ft_).u32_227 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_226 >> (20)) | ((IMG_UINT64)((_ft_).u32_227 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W0_WOFF (225U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W1_WOFF (226U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_225 = (((_ft_).u32_225 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_226 = (((_ft_).u32_226 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_225 >> (24)) | ((IMG_UINT64)((_ft_).u32_226 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W0_WOFF (224U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W1_WOFF (225U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_224 = (((_ft_).u32_224 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_225 = (((_ft_).u32_225 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_224 >> (28)) | ((IMG_UINT64)((_ft_).u32_225 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_WOFF (224U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_224 = (((_ft_).u32_224 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_224 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_WOFF (220U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_220 = (((_ft_).u32_220 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_220 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_WOFF (219U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_219 = (((_ft_).u32_219 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_219 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W0_WOFF (218U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W1_WOFF (219U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_218 = (((_ft_).u32_218 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_219 = (((_ft_).u32_219 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_218 >> (20)) | ((IMG_UINT64)((_ft_).u32_219 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W0_WOFF (217U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W1_WOFF (218U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_217 = (((_ft_).u32_217 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_218 = (((_ft_).u32_218 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_217 >> (24)) | ((IMG_UINT64)((_ft_).u32_218 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W0_WOFF (216U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W1_WOFF (217U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_216 = (((_ft_).u32_216 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_217 = (((_ft_).u32_217 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_216 >> (28)) | ((IMG_UINT64)((_ft_).u32_217 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_WOFF (216U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_216 = (((_ft_).u32_216 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_216 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE5 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_WOFF (212U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_212 = (((_ft_).u32_212 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_212 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_WOFF (211U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_211 = (((_ft_).u32_211 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_211 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W0_WOFF (210U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W1_WOFF (211U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_210 = (((_ft_).u32_210 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_211 = (((_ft_).u32_211 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_210 >> (20)) | ((IMG_UINT64)((_ft_).u32_211 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W0_WOFF (209U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W1_WOFF (210U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_209 = (((_ft_).u32_209 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_210 = (((_ft_).u32_210 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_209 >> (24)) | ((IMG_UINT64)((_ft_).u32_210 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W0_WOFF (208U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W1_WOFF (209U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_208 = (((_ft_).u32_208 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_209 = (((_ft_).u32_209 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_208 >> (28)) | ((IMG_UINT64)((_ft_).u32_209 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_WOFF (208U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_208 = (((_ft_).u32_208 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_208 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_WOFF (204U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_204 = (((_ft_).u32_204 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_204 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_WOFF (203U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_203 = (((_ft_).u32_203 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_203 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W0_WOFF (202U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W1_WOFF (203U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_202 = (((_ft_).u32_202 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_203 = (((_ft_).u32_203 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_202 >> (20)) | ((IMG_UINT64)((_ft_).u32_203 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W0_WOFF (201U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W1_WOFF (202U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_201 = (((_ft_).u32_201 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_202 = (((_ft_).u32_202 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_201 >> (24)) | ((IMG_UINT64)((_ft_).u32_202 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W0_WOFF (200U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W1_WOFF (201U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_200 = (((_ft_).u32_200 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_201 = (((_ft_).u32_201 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_200 >> (28)) | ((IMG_UINT64)((_ft_).u32_201 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_WOFF (200U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_200 = (((_ft_).u32_200 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_200 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_WOFF (196U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_196 = (((_ft_).u32_196 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_196 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_WOFF (195U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_195 = (((_ft_).u32_195 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_195 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W0_WOFF (194U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W1_WOFF (195U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_194 = (((_ft_).u32_194 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_195 = (((_ft_).u32_195 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_194 >> (20)) | ((IMG_UINT64)((_ft_).u32_195 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W0_WOFF (193U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W1_WOFF (194U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_193 = (((_ft_).u32_193 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_194 = (((_ft_).u32_194 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_193 >> (24)) | ((IMG_UINT64)((_ft_).u32_194 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W0_WOFF (192U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W1_WOFF (193U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_192 = (((_ft_).u32_192 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_193 = (((_ft_).u32_193 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_192 >> (28)) | ((IMG_UINT64)((_ft_).u32_193 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_WOFF (192U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_192 = (((_ft_).u32_192 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_192 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_WOFF (188U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_188 = (((_ft_).u32_188 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_188 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_WOFF (187U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_187 = (((_ft_).u32_187 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_187 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W0_WOFF (186U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W1_WOFF (187U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_186 = (((_ft_).u32_186 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_187 = (((_ft_).u32_187 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_186 >> (20)) | ((IMG_UINT64)((_ft_).u32_187 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W0_WOFF (185U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W1_WOFF (186U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_185 = (((_ft_).u32_185 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_186 = (((_ft_).u32_186 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_185 >> (24)) | ((IMG_UINT64)((_ft_).u32_186 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W0_WOFF (184U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W1_WOFF (185U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_184 = (((_ft_).u32_184 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_185 = (((_ft_).u32_185 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_184 >> (28)) | ((IMG_UINT64)((_ft_).u32_185 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_WOFF (184U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_184 = (((_ft_).u32_184 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_184 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE4 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_WOFF (180U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_180 = (((_ft_).u32_180 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_180 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_WOFF (179U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_179 = (((_ft_).u32_179 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_179 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W0_WOFF (178U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W1_WOFF (179U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_178 = (((_ft_).u32_178 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_179 = (((_ft_).u32_179 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_178 >> (20)) | ((IMG_UINT64)((_ft_).u32_179 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W0_WOFF (177U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W1_WOFF (178U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_177 = (((_ft_).u32_177 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_178 = (((_ft_).u32_178 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_177 >> (24)) | ((IMG_UINT64)((_ft_).u32_178 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W0_WOFF (176U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W1_WOFF (177U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_176 = (((_ft_).u32_176 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_177 = (((_ft_).u32_177 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_176 >> (28)) | ((IMG_UINT64)((_ft_).u32_177 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_WOFF (176U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_176 = (((_ft_).u32_176 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_176 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_WOFF (172U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_172 = (((_ft_).u32_172 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_172 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_WOFF (171U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_171 = (((_ft_).u32_171 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_171 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W0_WOFF (170U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W1_WOFF (171U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_170 = (((_ft_).u32_170 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_171 = (((_ft_).u32_171 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_170 >> (20)) | ((IMG_UINT64)((_ft_).u32_171 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W0_WOFF (169U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W1_WOFF (170U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_169 = (((_ft_).u32_169 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_170 = (((_ft_).u32_170 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_169 >> (24)) | ((IMG_UINT64)((_ft_).u32_170 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W0_WOFF (168U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W1_WOFF (169U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_168 = (((_ft_).u32_168 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_169 = (((_ft_).u32_169 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_168 >> (28)) | ((IMG_UINT64)((_ft_).u32_169 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_WOFF (168U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_168 = (((_ft_).u32_168 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_168 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_WOFF (164U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_164 = (((_ft_).u32_164 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_164 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_WOFF (163U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_163 = (((_ft_).u32_163 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_163 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W0_WOFF (162U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W1_WOFF (163U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_162 = (((_ft_).u32_162 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_163 = (((_ft_).u32_163 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_162 >> (20)) | ((IMG_UINT64)((_ft_).u32_163 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W0_WOFF (161U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W1_WOFF (162U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_161 = (((_ft_).u32_161 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_162 = (((_ft_).u32_162 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_161 >> (24)) | ((IMG_UINT64)((_ft_).u32_162 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W0_WOFF (160U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W1_WOFF (161U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_160 = (((_ft_).u32_160 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_161 = (((_ft_).u32_161 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_160 >> (28)) | ((IMG_UINT64)((_ft_).u32_161 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_WOFF (160U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_160 = (((_ft_).u32_160 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_160 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_WOFF (156U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_156 = (((_ft_).u32_156 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_156 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_WOFF (155U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_155 = (((_ft_).u32_155 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_155 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W0_WOFF (154U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W1_WOFF (155U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_154 = (((_ft_).u32_154 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_155 = (((_ft_).u32_155 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_154 >> (20)) | ((IMG_UINT64)((_ft_).u32_155 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W0_WOFF (153U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W1_WOFF (154U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_153 = (((_ft_).u32_153 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_154 = (((_ft_).u32_154 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_153 >> (24)) | ((IMG_UINT64)((_ft_).u32_154 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W0_WOFF (152U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W1_WOFF (153U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_152 = (((_ft_).u32_152 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_153 = (((_ft_).u32_153 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_152 >> (28)) | ((IMG_UINT64)((_ft_).u32_153 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_WOFF (152U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_152 = (((_ft_).u32_152 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_152 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE3 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_WOFF (148U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_148 = (((_ft_).u32_148 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_148 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_WOFF (147U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_147 = (((_ft_).u32_147 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_147 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W0_WOFF (146U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W1_WOFF (147U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_146 = (((_ft_).u32_146 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_147 = (((_ft_).u32_147 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_146 >> (20)) | ((IMG_UINT64)((_ft_).u32_147 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W0_WOFF (145U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W1_WOFF (146U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_145 = (((_ft_).u32_145 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_146 = (((_ft_).u32_146 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_145 >> (24)) | ((IMG_UINT64)((_ft_).u32_146 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W0_WOFF (144U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W1_WOFF (145U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_144 = (((_ft_).u32_144 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_145 = (((_ft_).u32_145 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_144 >> (28)) | ((IMG_UINT64)((_ft_).u32_145 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_WOFF (144U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_144 = (((_ft_).u32_144 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_144 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_WOFF (140U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_140 = (((_ft_).u32_140 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_140 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_WOFF (139U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_139 = (((_ft_).u32_139 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_139 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W0_WOFF (138U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W1_WOFF (139U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_138 = (((_ft_).u32_138 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_139 = (((_ft_).u32_139 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_138 >> (20)) | ((IMG_UINT64)((_ft_).u32_139 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W0_WOFF (137U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W1_WOFF (138U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_137 = (((_ft_).u32_137 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_138 = (((_ft_).u32_138 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_137 >> (24)) | ((IMG_UINT64)((_ft_).u32_138 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W0_WOFF (136U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W1_WOFF (137U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_136 = (((_ft_).u32_136 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_137 = (((_ft_).u32_137 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_136 >> (28)) | ((IMG_UINT64)((_ft_).u32_137 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_WOFF (136U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_136 = (((_ft_).u32_136 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_136 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_WOFF (132U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_132 = (((_ft_).u32_132 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_132 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_WOFF (131U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_131 = (((_ft_).u32_131 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_131 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W0_WOFF (130U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W1_WOFF (131U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_130 = (((_ft_).u32_130 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_131 = (((_ft_).u32_131 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_130 >> (20)) | ((IMG_UINT64)((_ft_).u32_131 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W0_WOFF (129U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W1_WOFF (130U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_129 = (((_ft_).u32_129 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_130 = (((_ft_).u32_130 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_129 >> (24)) | ((IMG_UINT64)((_ft_).u32_130 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W0_WOFF (128U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W1_WOFF (129U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_128 = (((_ft_).u32_128 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_129 = (((_ft_).u32_129 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_128 >> (28)) | ((IMG_UINT64)((_ft_).u32_129 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_WOFF (128U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_128 = (((_ft_).u32_128 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_128 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_WOFF (124U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_124 = (((_ft_).u32_124 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_124 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_WOFF (123U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_123 = (((_ft_).u32_123 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_123 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W0_WOFF (122U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W1_WOFF (123U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_122 = (((_ft_).u32_122 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_123 = (((_ft_).u32_123 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_122 >> (20)) | ((IMG_UINT64)((_ft_).u32_123 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W0_WOFF (121U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W1_WOFF (122U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_121 = (((_ft_).u32_121 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_122 = (((_ft_).u32_122 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_121 >> (24)) | ((IMG_UINT64)((_ft_).u32_122 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W0_WOFF (120U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W1_WOFF (121U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_120 = (((_ft_).u32_120 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_121 = (((_ft_).u32_121 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_120 >> (28)) | ((IMG_UINT64)((_ft_).u32_121 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_WOFF (120U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_120 = (((_ft_).u32_120 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_120 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE2 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_WOFF (116U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_116 = (((_ft_).u32_116 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_116 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_WOFF (115U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_115 = (((_ft_).u32_115 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_115 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W0_WOFF (114U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W1_WOFF (115U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_114 = (((_ft_).u32_114 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_115 = (((_ft_).u32_115 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_114 >> (20)) | ((IMG_UINT64)((_ft_).u32_115 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W0_WOFF (113U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W1_WOFF (114U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_113 = (((_ft_).u32_113 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_114 = (((_ft_).u32_114 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_113 >> (24)) | ((IMG_UINT64)((_ft_).u32_114 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W0_WOFF (112U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W1_WOFF (113U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_112 = (((_ft_).u32_112 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_113 = (((_ft_).u32_113 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_112 >> (28)) | ((IMG_UINT64)((_ft_).u32_113 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_WOFF (112U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_112 = (((_ft_).u32_112 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_112 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_WOFF (108U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_108 = (((_ft_).u32_108 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_108 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_WOFF (107U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_107 = (((_ft_).u32_107 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_107 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W0_WOFF (106U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W1_WOFF (107U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_106 = (((_ft_).u32_106 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_107 = (((_ft_).u32_107 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_106 >> (20)) | ((IMG_UINT64)((_ft_).u32_107 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W0_WOFF (105U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W1_WOFF (106U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_105 = (((_ft_).u32_105 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_106 = (((_ft_).u32_106 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_105 >> (24)) | ((IMG_UINT64)((_ft_).u32_106 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W0_WOFF (104U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W1_WOFF (105U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_104 = (((_ft_).u32_104 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_105 = (((_ft_).u32_105 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_104 >> (28)) | ((IMG_UINT64)((_ft_).u32_105 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_WOFF (104U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_104 = (((_ft_).u32_104 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_104 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_WOFF (100U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_100 = (((_ft_).u32_100 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_100 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_WOFF (99U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_99 = (((_ft_).u32_99 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_99 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W0_WOFF (98U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W1_WOFF (99U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_98 = (((_ft_).u32_98 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_99 = (((_ft_).u32_99 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_98 >> (20)) | ((IMG_UINT64)((_ft_).u32_99 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W0_WOFF (97U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W1_WOFF (98U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_97 = (((_ft_).u32_97 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_98 = (((_ft_).u32_98 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_97 >> (24)) | ((IMG_UINT64)((_ft_).u32_98 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W0_WOFF (96U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W1_WOFF (97U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_96 = (((_ft_).u32_96 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_97 = (((_ft_).u32_97 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_96 >> (28)) | ((IMG_UINT64)((_ft_).u32_97 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_WOFF (96U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_96 = (((_ft_).u32_96 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_96 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_WOFF (92U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_92 = (((_ft_).u32_92 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_92 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_WOFF (91U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_91 = (((_ft_).u32_91 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_91 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W0_WOFF (90U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W1_WOFF (91U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_90 = (((_ft_).u32_90 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_91 = (((_ft_).u32_91 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_90 >> (20)) | ((IMG_UINT64)((_ft_).u32_91 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W0_WOFF (89U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W1_WOFF (90U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_89 = (((_ft_).u32_89 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_90 = (((_ft_).u32_90 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_89 >> (24)) | ((IMG_UINT64)((_ft_).u32_90 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W0_WOFF (88U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W1_WOFF (89U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_88 = (((_ft_).u32_88 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_89 = (((_ft_).u32_89 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_88 >> (28)) | ((IMG_UINT64)((_ft_).u32_89 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_WOFF (88U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_88 = (((_ft_).u32_88 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_88 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE1 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_WOFF (84U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_84 = (((_ft_).u32_84 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_84 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_WOFF (83U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_UFSTACK(_ft_,_x_) ((_ft_).u32_83 = (((_ft_).u32_83 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_UFSTACK(_ft_) (((_ft_).u32_83 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W0_WOFF (82U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W1_WOFF (83U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_PPAGE3(_ft_,_x_) { ((_ft_).u32_82 = (((_ft_).u32_82 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_83 = (((_ft_).u32_83 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_PPAGE3(_ft_) (((_ft_).u32_82 >> (20)) | ((IMG_UINT64)((_ft_).u32_83 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W0_WOFF (81U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W1_WOFF (82U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_PPAGE2(_ft_,_x_) { ((_ft_).u32_81 = (((_ft_).u32_81 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_82 = (((_ft_).u32_82 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_PPAGE2(_ft_) (((_ft_).u32_81 >> (24)) | ((IMG_UINT64)((_ft_).u32_82 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W0_WOFF (80U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W1_WOFF (81U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_PPAGE1(_ft_,_x_) { ((_ft_).u32_80 = (((_ft_).u32_80 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_81 = (((_ft_).u32_81 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_PPAGE1(_ft_) (((_ft_).u32_80 >> (28)) | ((IMG_UINT64)((_ft_).u32_81 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_WOFF (80U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_PPAGE0(_ft_,_x_) ((_ft_).u32_80 = (((_ft_).u32_80 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_PPAGE0(_ft_) (((_ft_).u32_80 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page3 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_WOFF (76U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT3_PAGE(_ft_,_x_) ((_ft_).u32_76 = (((_ft_).u32_76 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT3_PAGE(_ft_) (((_ft_).u32_76 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT3_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_WOFF (75U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_UFSTACK(_ft_,_x_) ((_ft_).u32_75 = (((_ft_).u32_75 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_UFSTACK(_ft_) (((_ft_).u32_75 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W0_WOFF (74U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W1_WOFF (75U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_PPAGE3(_ft_,_x_) { ((_ft_).u32_74 = (((_ft_).u32_74 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_75 = (((_ft_).u32_75 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_PPAGE3(_ft_) (((_ft_).u32_74 >> (20)) | ((IMG_UINT64)((_ft_).u32_75 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W0_WOFF (73U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W1_WOFF (74U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_PPAGE2(_ft_,_x_) { ((_ft_).u32_73 = (((_ft_).u32_73 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_74 = (((_ft_).u32_74 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_PPAGE2(_ft_) (((_ft_).u32_73 >> (24)) | ((IMG_UINT64)((_ft_).u32_74 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W0_WOFF (72U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W1_WOFF (73U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_PPAGE1(_ft_,_x_) { ((_ft_).u32_72 = (((_ft_).u32_72 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_73 = (((_ft_).u32_73 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_PPAGE1(_ft_) (((_ft_).u32_72 >> (28)) | ((IMG_UINT64)((_ft_).u32_73 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_WOFF (72U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_PPAGE0(_ft_,_x_) ((_ft_).u32_72 = (((_ft_).u32_72 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_PPAGE0(_ft_) (((_ft_).u32_72 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page2 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_WOFF (68U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT2_PAGE(_ft_,_x_) ((_ft_).u32_68 = (((_ft_).u32_68 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT2_PAGE(_ft_) (((_ft_).u32_68 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT2_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_WOFF (67U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_UFSTACK(_ft_,_x_) ((_ft_).u32_67 = (((_ft_).u32_67 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_UFSTACK(_ft_) (((_ft_).u32_67 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W0_WOFF (66U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W1_WOFF (67U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_PPAGE3(_ft_,_x_) { ((_ft_).u32_66 = (((_ft_).u32_66 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_67 = (((_ft_).u32_67 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_PPAGE3(_ft_) (((_ft_).u32_66 >> (20)) | ((IMG_UINT64)((_ft_).u32_67 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W0_WOFF (65U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W1_WOFF (66U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_PPAGE2(_ft_,_x_) { ((_ft_).u32_65 = (((_ft_).u32_65 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_66 = (((_ft_).u32_66 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_PPAGE2(_ft_) (((_ft_).u32_65 >> (24)) | ((IMG_UINT64)((_ft_).u32_66 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W0_WOFF (64U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W1_WOFF (65U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_PPAGE1(_ft_,_x_) { ((_ft_).u32_64 = (((_ft_).u32_64 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_65 = (((_ft_).u32_65 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_PPAGE1(_ft_) (((_ft_).u32_64 >> (28)) | ((IMG_UINT64)((_ft_).u32_65 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_WOFF (64U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_PPAGE0(_ft_,_x_) ((_ft_).u32_64 = (((_ft_).u32_64 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_PPAGE0(_ft_) (((_ft_).u32_64 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page1 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_WOFF (60U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT1_PAGE(_ft_,_x_) ((_ft_).u32_60 = (((_ft_).u32_60 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT1_PAGE(_ft_) (((_ft_).u32_60 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT1_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: unified stack bit
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_WOFF (59U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_CLRMSK (0xFFFEFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_UFSTACK(_ft_,_x_) ((_ft_).u32_59 = (((_ft_).u32_59 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_UFSTACK(_ft_) (((_ft_).u32_59 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_UFSTACK_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: physical page 3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W0_WOFF (58U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W1_WOFF (59U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W0_SHIFT (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W0_CLRMSK (0x000FFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W1_CLRMSK (0xFFFF0000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_PPAGE3(_ft_,_x_) { ((_ft_).u32_58 = (((_ft_).u32_58 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000000000fff))) << 20))); \
|
||
|
|
((_ft_).u32_59 = (((_ft_).u32_59 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE3_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffff000))) >> 12))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_PPAGE3(_ft_) (((_ft_).u32_58 >> (20)) | ((IMG_UINT64)((_ft_).u32_59 & 0x0000ffffU ) << (12)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: physical page 2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W0_WOFF (57U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W1_WOFF (58U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W0_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W0_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_PPAGE2(_ft_,_x_) { ((_ft_).u32_57 = (((_ft_).u32_57 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000000000ff))) << 24))); \
|
||
|
|
((_ft_).u32_58 = (((_ft_).u32_58 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE2_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffff00))) >> 8))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_PPAGE2(_ft_) (((_ft_).u32_57 >> (24)) | ((IMG_UINT64)((_ft_).u32_58 & 0x000fffffU ) << (8)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: physical page 1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W0_WOFF (56U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W1_WOFF (57U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W0_SHIFT (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W0_CLRMSK (0x0FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W1_CLRMSK (0xFF000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_PPAGE1(_ft_,_x_) { ((_ft_).u32_56 = (((_ft_).u32_56 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000000000f))) << 28))); \
|
||
|
|
((_ft_).u32_57 = (((_ft_).u32_57 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE1_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000ffffff0))) >> 4))); }
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_PPAGE1(_ft_) (((_ft_).u32_56 >> (28)) | ((IMG_UINT64)((_ft_).u32_57 & 0x00ffffffU ) << (4)))
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: physical page 0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_WOFF (56U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_CLRMSK (0xF0000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_PPAGE0(_ft_,_x_) ((_ft_).u32_56 = (((_ft_).u32_56 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_PPAGE0(_ft_) (((_ft_).u32_56 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PPAGE0_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
VCE0 opened page0 struct: virtual page number
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_WOFF (52U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT0_PAGE(_ft_,_x_) ((_ft_).u32_52 = (((_ft_).u32_52 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT0_PAGE(_ft_) (((_ft_).u32_52 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT0_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Rsv2 area
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W0_WOFF (42U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W1_WOFF (43U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W2_WOFF (44U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W2_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W3_WOFF (45U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W3_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W4_WOFF (46U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W4_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W5_WOFF (47U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W5_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W6_WOFF (48U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W6_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W7_WOFF (49U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W7_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W8_WOFF (50U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W8_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W9_WOFF (51U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W9_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W0_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W1_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W2_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W3_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W4_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W5_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W6_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W7_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W8_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV2_W9_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W0(_ft_,_x_) ((_ft_).u32_42 = (((_ft_).u32_42 & PM_DATA_VHEAP_BUFFER_RESV2_W0_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W0_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W0(_ft_) (((_ft_).u32_42 >> (PM_DATA_VHEAP_BUFFER_RESV2_W0_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W1(_ft_,_x_) ((_ft_).u32_43 = (((_ft_).u32_43 & PM_DATA_VHEAP_BUFFER_RESV2_W1_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W1_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W1(_ft_) (((_ft_).u32_43 >> (PM_DATA_VHEAP_BUFFER_RESV2_W1_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W2(_ft_,_x_) ((_ft_).u32_44 = (((_ft_).u32_44 & PM_DATA_VHEAP_BUFFER_RESV2_W2_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W2_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W2(_ft_) (((_ft_).u32_44 >> (PM_DATA_VHEAP_BUFFER_RESV2_W2_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W3(_ft_,_x_) ((_ft_).u32_45 = (((_ft_).u32_45 & PM_DATA_VHEAP_BUFFER_RESV2_W3_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W3_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W3(_ft_) (((_ft_).u32_45 >> (PM_DATA_VHEAP_BUFFER_RESV2_W3_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W4(_ft_,_x_) ((_ft_).u32_46 = (((_ft_).u32_46 & PM_DATA_VHEAP_BUFFER_RESV2_W4_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W4_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W4(_ft_) (((_ft_).u32_46 >> (PM_DATA_VHEAP_BUFFER_RESV2_W4_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W5(_ft_,_x_) ((_ft_).u32_47 = (((_ft_).u32_47 & PM_DATA_VHEAP_BUFFER_RESV2_W5_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W5_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W5(_ft_) (((_ft_).u32_47 >> (PM_DATA_VHEAP_BUFFER_RESV2_W5_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W6(_ft_,_x_) ((_ft_).u32_48 = (((_ft_).u32_48 & PM_DATA_VHEAP_BUFFER_RESV2_W6_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W6_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W6(_ft_) (((_ft_).u32_48 >> (PM_DATA_VHEAP_BUFFER_RESV2_W6_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W7(_ft_,_x_) ((_ft_).u32_49 = (((_ft_).u32_49 & PM_DATA_VHEAP_BUFFER_RESV2_W7_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W7_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W7(_ft_) (((_ft_).u32_49 >> (PM_DATA_VHEAP_BUFFER_RESV2_W7_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W8(_ft_,_x_) ((_ft_).u32_50 = (((_ft_).u32_50 & PM_DATA_VHEAP_BUFFER_RESV2_W8_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W8_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W8(_ft_) (((_ft_).u32_50 >> (PM_DATA_VHEAP_BUFFER_RESV2_W8_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV2_W9(_ft_,_x_) ((_ft_).u32_51 = (((_ft_).u32_51 & PM_DATA_VHEAP_BUFFER_RESV2_W9_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV2_W9_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV2_W9(_ft_) (((_ft_).u32_51 >> (PM_DATA_VHEAP_BUFFER_RESV2_W9_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE7 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_WOFF (41U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE7_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_41 = (((_ft_).u32_41 & PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE7_INFLIGHT_CNT(_ft_) (((_ft_).u32_41 >> (PM_DATA_VHEAP_BUFFER_TE7_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE6 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_WOFF (41U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_CLRMSK (0xFF00FFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE6_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_41 = (((_ft_).u32_41 & PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE6_INFLIGHT_CNT(_ft_) (((_ft_).u32_41 >> (PM_DATA_VHEAP_BUFFER_TE6_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE5 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_WOFF (41U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_SHIFT (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_CLRMSK (0xFFFF00FFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE5_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_41 = (((_ft_).u32_41 & PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE5_INFLIGHT_CNT(_ft_) (((_ft_).u32_41 >> (PM_DATA_VHEAP_BUFFER_TE5_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE4 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_WOFF (41U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_CLRMSK (0xFFFFFF00U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE4_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_41 = (((_ft_).u32_41 & PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE4_INFLIGHT_CNT(_ft_) (((_ft_).u32_41 >> (PM_DATA_VHEAP_BUFFER_TE4_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE3 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_WOFF (40U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE3_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE3_INFLIGHT_CNT(_ft_) (((_ft_).u32_40 >> (PM_DATA_VHEAP_BUFFER_TE3_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE2 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_WOFF (40U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_CLRMSK (0xFF00FFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE2_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE2_INFLIGHT_CNT(_ft_) (((_ft_).u32_40 >> (PM_DATA_VHEAP_BUFFER_TE2_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE1 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_WOFF (40U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_SHIFT (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_CLRMSK (0xFFFF00FFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE1_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE1_INFLIGHT_CNT(_ft_) (((_ft_).u32_40 >> (PM_DATA_VHEAP_BUFFER_TE1_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to TE0 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_WOFF (40U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_CLRMSK (0xFFFFFF00U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_TE0_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_TE0_INFLIGHT_CNT(_ft_) (((_ft_).u32_40 >> (PM_DATA_VHEAP_BUFFER_TE0_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE7 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_WOFF (39U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE7_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_39 = (((_ft_).u32_39 & PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE7_INFLIGHT_CNT(_ft_) (((_ft_).u32_39 >> (PM_DATA_VHEAP_BUFFER_VCE7_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE6 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_WOFF (39U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_CLRMSK (0xFF00FFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE6_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_39 = (((_ft_).u32_39 & PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE6_INFLIGHT_CNT(_ft_) (((_ft_).u32_39 >> (PM_DATA_VHEAP_BUFFER_VCE6_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE5 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_WOFF (39U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_SHIFT (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_CLRMSK (0xFFFF00FFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE5_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_39 = (((_ft_).u32_39 & PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE5_INFLIGHT_CNT(_ft_) (((_ft_).u32_39 >> (PM_DATA_VHEAP_BUFFER_VCE5_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE4 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_WOFF (39U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_CLRMSK (0xFFFFFF00U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE4_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_39 = (((_ft_).u32_39 & PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE4_INFLIGHT_CNT(_ft_) (((_ft_).u32_39 >> (PM_DATA_VHEAP_BUFFER_VCE4_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE3 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_WOFF (38U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_SHIFT (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_CLRMSK (0x00FFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE3_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_38 = (((_ft_).u32_38 & PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE3_INFLIGHT_CNT(_ft_) (((_ft_).u32_38 >> (PM_DATA_VHEAP_BUFFER_VCE3_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE2 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_WOFF (38U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_SHIFT (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_CLRMSK (0xFF00FFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE2_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_38 = (((_ft_).u32_38 & PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE2_INFLIGHT_CNT(_ft_) (((_ft_).u32_38 >> (PM_DATA_VHEAP_BUFFER_VCE2_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE1 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_WOFF (38U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_SHIFT (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_CLRMSK (0xFFFF00FFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE1_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_38 = (((_ft_).u32_38 & PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE1_INFLIGHT_CNT(_ft_) (((_ft_).u32_38 >> (PM_DATA_VHEAP_BUFFER_VCE1_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
Number of pages allocated to VCE0 but not yet closed
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_WOFF (38U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_CLRMSK (0xFFFFFF00U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VCE0_INFLIGHT_CNT(_ft_,_x_) ((_ft_).u32_38 = (((_ft_).u32_38 & PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_CLRMSK ) | (((_x_) & (0x000000ffU)) << (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VCE0_INFLIGHT_CNT(_ft_) (((_ft_).u32_38 >> (PM_DATA_VHEAP_BUFFER_VCE0_INFLIGHT_CNT_SHIFT)) & 0x000000ffU)
|
||
|
|
/*
|
||
|
|
1=The PM ran out of memory during processing
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_WOFF (37U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_PM_OUTOFMEM_R(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_PM_OUTOFMEM_R(_ft_) (((_ft_).u32_37 >> (PM_DATA_VHEAP_BUFFER_PM_OUTOFMEM_R_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
A copy of rgx_cr_pm_outofmem_abortall (at the point the VHEAP buffer was written)
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_WOFF (37U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_SHIFT (30U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_CLRMSK (0xBFFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_OUTOFMEM_ABORT(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_OUTOFMEM_ABORT(_ft_) (((_ft_).u32_37 >> (PM_DATA_VHEAP_BUFFER_OUTOFMEM_ABORT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
When running out of memory, indicates which of the free stacks have run out of memory.
|
||
|
|
If bit 2 is set, MMUSTACK has run out of memory.
|
||
|
|
Bit 2 is reserved.
|
||
|
|
If bit 1 is set, UFSTACK has run out of memory.
|
||
|
|
If bit 0 is set, FSTACK has run out of memory.
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_WOFF (37U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_SHIFT (2U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_CLRMSK (0xFFFFFFE3U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_OUTOFMEM_SRC(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_CLRMSK ) | (((_x_) & (0x00000007U)) << (PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_OUTOFMEM_SRC(_ft_) (((_ft_).u32_37 >> (PM_DATA_VHEAP_BUFFER_OUTOFMEM_SRC_SHIFT)) & 0x00000007U)
|
||
|
|
/*
|
||
|
|
When running out of memory, indicates the source of the request that caused the OOM event
|
||
|
|
If bit 1 is set, TE caused the OOM.
|
||
|
|
If bit 0 is set, VCE caused the OOM.
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_REQ_SRC_WOFF (37U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_REQ_SRC_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_REQ_SRC_CLRMSK (0xFFFFFFFCU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_REQ_SRC(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & PM_DATA_VHEAP_BUFFER_REQ_SRC_CLRMSK ) | (((_x_) & (0x00000003U)) << (PM_DATA_VHEAP_BUFFER_REQ_SRC_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_REQ_SRC(_ft_) (((_ft_).u32_37 >> (PM_DATA_VHEAP_BUFFER_REQ_SRC_SHIFT)) & 0x00000003U)
|
||
|
|
/*
|
||
|
|
MAX RTA index dword in TA stream
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_MAX_RTA_WOFF (36U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_MAX_RTA_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_MAX_RTA_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_MAX_RTA(_ft_,_x_) ((_ft_).u32_36 = (((_ft_).u32_36 & PM_DATA_VHEAP_BUFFER_MAX_RTA_CLRMSK ) | (((_x_) & (0xffffffffU)) << (PM_DATA_VHEAP_BUFFER_MAX_RTA_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_MAX_RTA(_ft_) (((_ft_).u32_36 >> (PM_DATA_VHEAP_BUFFER_MAX_RTA_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Rsv1 area
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W0_WOFF (20U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W1_WOFF (21U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W2_WOFF (22U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W2_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W3_WOFF (23U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W3_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W4_WOFF (24U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W4_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W5_WOFF (25U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W5_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W6_WOFF (26U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W6_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W7_WOFF (27U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W7_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W8_WOFF (28U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W8_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W9_WOFF (29U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W9_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W10_WOFF (30U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W10_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W11_WOFF (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W11_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W12_WOFF (32U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W12_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W13_WOFF (33U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W13_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W14_WOFF (34U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W14_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W15_WOFF (35U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W15_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W0_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W1_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W2_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W3_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W4_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W5_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W6_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W7_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W8_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W9_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W10_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W11_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W12_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W13_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W14_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV1_W15_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W0(_ft_,_x_) ((_ft_).u32_20 = (((_ft_).u32_20 & PM_DATA_VHEAP_BUFFER_RESV1_W0_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W0_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W0(_ft_) (((_ft_).u32_20 >> (PM_DATA_VHEAP_BUFFER_RESV1_W0_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W1(_ft_,_x_) ((_ft_).u32_21 = (((_ft_).u32_21 & PM_DATA_VHEAP_BUFFER_RESV1_W1_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W1_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W1(_ft_) (((_ft_).u32_21 >> (PM_DATA_VHEAP_BUFFER_RESV1_W1_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W2(_ft_,_x_) ((_ft_).u32_22 = (((_ft_).u32_22 & PM_DATA_VHEAP_BUFFER_RESV1_W2_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W2_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W2(_ft_) (((_ft_).u32_22 >> (PM_DATA_VHEAP_BUFFER_RESV1_W2_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W3(_ft_,_x_) ((_ft_).u32_23 = (((_ft_).u32_23 & PM_DATA_VHEAP_BUFFER_RESV1_W3_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W3_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W3(_ft_) (((_ft_).u32_23 >> (PM_DATA_VHEAP_BUFFER_RESV1_W3_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W4(_ft_,_x_) ((_ft_).u32_24 = (((_ft_).u32_24 & PM_DATA_VHEAP_BUFFER_RESV1_W4_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W4_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W4(_ft_) (((_ft_).u32_24 >> (PM_DATA_VHEAP_BUFFER_RESV1_W4_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W5(_ft_,_x_) ((_ft_).u32_25 = (((_ft_).u32_25 & PM_DATA_VHEAP_BUFFER_RESV1_W5_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W5_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W5(_ft_) (((_ft_).u32_25 >> (PM_DATA_VHEAP_BUFFER_RESV1_W5_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W6(_ft_,_x_) ((_ft_).u32_26 = (((_ft_).u32_26 & PM_DATA_VHEAP_BUFFER_RESV1_W6_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W6_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W6(_ft_) (((_ft_).u32_26 >> (PM_DATA_VHEAP_BUFFER_RESV1_W6_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W7(_ft_,_x_) ((_ft_).u32_27 = (((_ft_).u32_27 & PM_DATA_VHEAP_BUFFER_RESV1_W7_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W7_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W7(_ft_) (((_ft_).u32_27 >> (PM_DATA_VHEAP_BUFFER_RESV1_W7_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W8(_ft_,_x_) ((_ft_).u32_28 = (((_ft_).u32_28 & PM_DATA_VHEAP_BUFFER_RESV1_W8_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W8_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W8(_ft_) (((_ft_).u32_28 >> (PM_DATA_VHEAP_BUFFER_RESV1_W8_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W9(_ft_,_x_) ((_ft_).u32_29 = (((_ft_).u32_29 & PM_DATA_VHEAP_BUFFER_RESV1_W9_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W9_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W9(_ft_) (((_ft_).u32_29 >> (PM_DATA_VHEAP_BUFFER_RESV1_W9_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W10(_ft_,_x_) ((_ft_).u32_30 = (((_ft_).u32_30 & PM_DATA_VHEAP_BUFFER_RESV1_W10_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W10_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W10(_ft_) (((_ft_).u32_30 >> (PM_DATA_VHEAP_BUFFER_RESV1_W10_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W11(_ft_,_x_) ((_ft_).u32_31 = (((_ft_).u32_31 & PM_DATA_VHEAP_BUFFER_RESV1_W11_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W11_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W11(_ft_) (((_ft_).u32_31 >> (PM_DATA_VHEAP_BUFFER_RESV1_W11_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W12(_ft_,_x_) ((_ft_).u32_32 = (((_ft_).u32_32 & PM_DATA_VHEAP_BUFFER_RESV1_W12_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W12_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W12(_ft_) (((_ft_).u32_32 >> (PM_DATA_VHEAP_BUFFER_RESV1_W12_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W13(_ft_,_x_) ((_ft_).u32_33 = (((_ft_).u32_33 & PM_DATA_VHEAP_BUFFER_RESV1_W13_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W13_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W13(_ft_) (((_ft_).u32_33 >> (PM_DATA_VHEAP_BUFFER_RESV1_W13_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W14(_ft_,_x_) ((_ft_).u32_34 = (((_ft_).u32_34 & PM_DATA_VHEAP_BUFFER_RESV1_W14_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W14_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W14(_ft_) (((_ft_).u32_34 >> (PM_DATA_VHEAP_BUFFER_RESV1_W14_SHIFT)) & 0xffffffffU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV1_W15(_ft_,_x_) ((_ft_).u32_35 = (((_ft_).u32_35 & PM_DATA_VHEAP_BUFFER_RESV1_W15_CLRMSK ) | (((_x_) & (0xffffffffU)) << PM_DATA_VHEAP_BUFFER_RESV1_W15_SHIFT)))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV1_W15(_ft_) (((_ft_).u32_35 >> (PM_DATA_VHEAP_BUFFER_RESV1_W15_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Rsv0 area
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV0_WOFF (19U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_RESV0_CLRMSK (0x00000000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_RESV0(_ft_,_x_) ((_ft_).u32_19 = (((_ft_).u32_19 & PM_DATA_VHEAP_BUFFER_RESV0_CLRMSK ) | (((_x_) & (0xffffffffU)) << (PM_DATA_VHEAP_BUFFER_RESV0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_RESV0(_ft_) (((_ft_).u32_19 >> (PM_DATA_VHEAP_BUFFER_RESV0_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE7
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_WOFF (18U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE7_INIT(_ft_,_x_) ((_ft_).u32_18 = (((_ft_).u32_18 & PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE7_INIT(_ft_) (((_ft_).u32_18 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE7_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE7
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_WOFF (18U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE7_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE7(_ft_,_x_) ((_ft_).u32_18 = (((_ft_).u32_18 & PM_DATA_VHEAP_BUFFER_VPTR_TE7_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE7_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE7(_ft_) (((_ft_).u32_18 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE7_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE7
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_WOFF (17U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE7_INIT(_ft_,_x_) ((_ft_).u32_17 = (((_ft_).u32_17 & PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE7_INIT(_ft_) (((_ft_).u32_17 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE7_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE7
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_WOFF (17U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE7_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE7(_ft_,_x_) ((_ft_).u32_17 = (((_ft_).u32_17 & PM_DATA_VHEAP_BUFFER_VPTR_VCE7_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE7_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE7(_ft_) (((_ft_).u32_17 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE7_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE6
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_WOFF (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE6_INIT(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE6_INIT(_ft_) (((_ft_).u32_16 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE6_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE6
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_WOFF (16U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE6_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE6(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & PM_DATA_VHEAP_BUFFER_VPTR_TE6_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE6_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE6(_ft_) (((_ft_).u32_16 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE6_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE6
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_WOFF (15U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE6_INIT(_ft_,_x_) ((_ft_).u32_15 = (((_ft_).u32_15 & PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE6_INIT(_ft_) (((_ft_).u32_15 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE6_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE6
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_WOFF (15U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE6_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE6(_ft_,_x_) ((_ft_).u32_15 = (((_ft_).u32_15 & PM_DATA_VHEAP_BUFFER_VPTR_VCE6_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE6_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE6(_ft_) (((_ft_).u32_15 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE6_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE5
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_WOFF (14U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE5_INIT(_ft_,_x_) ((_ft_).u32_14 = (((_ft_).u32_14 & PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE5_INIT(_ft_) (((_ft_).u32_14 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE5_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE5
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_WOFF (14U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE5_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE5(_ft_,_x_) ((_ft_).u32_14 = (((_ft_).u32_14 & PM_DATA_VHEAP_BUFFER_VPTR_TE5_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE5_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE5(_ft_) (((_ft_).u32_14 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE5_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE5
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_WOFF (13U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE5_INIT(_ft_,_x_) ((_ft_).u32_13 = (((_ft_).u32_13 & PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE5_INIT(_ft_) (((_ft_).u32_13 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE5_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE5
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_WOFF (13U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE5_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE5(_ft_,_x_) ((_ft_).u32_13 = (((_ft_).u32_13 & PM_DATA_VHEAP_BUFFER_VPTR_VCE5_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE5_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE5(_ft_) (((_ft_).u32_13 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE5_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE4
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_WOFF (12U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE4_INIT(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE4_INIT(_ft_) (((_ft_).u32_12 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE4_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE4
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_WOFF (12U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE4_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE4(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & PM_DATA_VHEAP_BUFFER_VPTR_TE4_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE4_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE4(_ft_) (((_ft_).u32_12 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE4_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE4
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_WOFF (11U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE4_INIT(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE4_INIT(_ft_) (((_ft_).u32_11 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE4_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE4
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_WOFF (11U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE4_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE4(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & PM_DATA_VHEAP_BUFFER_VPTR_VCE4_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE4_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE4(_ft_) (((_ft_).u32_11 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE4_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_WOFF (10U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE3_INIT(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE3_INIT(_ft_) (((_ft_).u32_10 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE3_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_WOFF (10U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE3_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE3(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & PM_DATA_VHEAP_BUFFER_VPTR_TE3_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE3_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE3(_ft_) (((_ft_).u32_10 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE3_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_WOFF (9U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE3_INIT(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE3_INIT(_ft_) (((_ft_).u32_9 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE3_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE3
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_WOFF (9U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE3_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE3(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & PM_DATA_VHEAP_BUFFER_VPTR_VCE3_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE3_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE3(_ft_) (((_ft_).u32_9 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE3_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_WOFF (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE2_INIT(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE2_INIT(_ft_) (((_ft_).u32_8 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE2_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_WOFF (8U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE2_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE2(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & PM_DATA_VHEAP_BUFFER_VPTR_TE2_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE2_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE2(_ft_) (((_ft_).u32_8 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE2_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_WOFF (7U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE2_INIT(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE2_INIT(_ft_) (((_ft_).u32_7 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE2_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE2
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_WOFF (7U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE2_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE2(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & PM_DATA_VHEAP_BUFFER_VPTR_VCE2_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE2_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE2(_ft_) (((_ft_).u32_7 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE2_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_WOFF (6U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE1_INIT(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE1_INIT(_ft_) (((_ft_).u32_6 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE1_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_WOFF (6U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE1(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & PM_DATA_VHEAP_BUFFER_VPTR_TE1_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE1_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE1(_ft_) (((_ft_).u32_6 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE1_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_WOFF (5U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE1_INIT(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE1_INIT(_ft_) (((_ft_).u32_5 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE1_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE1
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_WOFF (5U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE1_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE1(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & PM_DATA_VHEAP_BUFFER_VPTR_VCE1_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE1_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE1(_ft_) (((_ft_).u32_5 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE1_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
4KB aligned top pointer for MMU
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_MMU_WOFF (4U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_MMU_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_MMU_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_MMU(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & PM_DATA_VHEAP_BUFFER_VPTR_MMU_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_MMU_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_MMU(_ft_) (((_ft_).u32_4 >> (PM_DATA_VHEAP_BUFFER_VPTR_MMU_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for ALIST
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_WOFF (3U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_ALIST_INIT(_ft_,_x_) ((_ft_).u32_3 = (((_ft_).u32_3 & PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_ALIST_INIT(_ft_) (((_ft_).u32_3 >> (PM_DATA_VHEAP_BUFFER_VPTR_ALIST_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for ALIST
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_WOFF (3U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_ALIST_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_ALIST(_ft_,_x_) ((_ft_).u32_3 = (((_ft_).u32_3 & PM_DATA_VHEAP_BUFFER_VPTR_ALIST_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_ALIST_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_ALIST(_ft_) (((_ft_).u32_3 >> (PM_DATA_VHEAP_BUFFER_VPTR_ALIST_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_WOFF (1U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE0_INIT(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE0_INIT(_ft_) (((_ft_).u32_1 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_WOFF (1U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_TE0_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_TE0(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & PM_DATA_VHEAP_BUFFER_VPTR_TE0_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_TE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_TE0(_ft_) (((_ft_).u32_1 >> (PM_DATA_VHEAP_BUFFER_VPTR_TE0_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_WOFF (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_SHIFT (31U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE0_INIT(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE0_INIT(_ft_) (((_ft_).u32_0 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE0
|
||
|
|
*/
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_WOFF (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_SHIFT (0U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_VPTR_VCE0_CLRMSK (0xFFF00000U)
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_SET_VPTR_VCE0(_ft_,_x_) ((_ft_).u32_0 = (((_ft_).u32_0 & PM_DATA_VHEAP_BUFFER_VPTR_VCE0_CLRMSK ) | (((_x_) & (0x000fffffU)) << (PM_DATA_VHEAP_BUFFER_VPTR_VCE0_SHIFT))))
|
||
|
|
#define PM_DATA_VHEAP_BUFFER_GET_VPTR_VCE0(_ft_) (((_ft_).u32_0 >> (PM_DATA_VHEAP_BUFFER_VPTR_VCE0_SHIFT)) & 0x000fffffU)
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
The PM FreeListState Buffer Layout - this will apply to 3 resources - FSTACK, UFSTACK and MMUSTACK
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_FREELISTSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
} RGX_PM_FREELISTSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
Reserved field word 2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_WOFF (7U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_2(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_2(_ft_) (((_ft_).u32_7 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved field word 1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_WOFF (6U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_1(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_1(_ft_) (((_ft_).u32_6 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved field word 0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_WOFF (5U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_0(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_0(_ft_) (((_ft_).u32_5 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of pages consumed for the MMU Page Table. Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_WOFF (4U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_MMUPAGE_STATUS(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_MMUPAGE_STATUS(_ft_) (((_ft_).u32_4 >> (RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The total number of pages consumed from the free stack. Must be initialised to zero. This field is unused in the MMUSTACK.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_WOFF (3U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_PAGE_STATUS(_ft_,_x_) ((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_PAGE_STATUS(_ft_) (((_ft_).u32_3 >> (RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Stack pointer for the free stack - the location of the next free page relative to the BaseAddr, in number of DWORDs. Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_WOFF (2U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_STACK_PTR(_ft_,_x_) ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_STACK_PTR(_ft_) (((_ft_).u32_2 >> (RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Base address of the free stack - points to the bottom of the stack.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_SHIFT (5U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_SHIFT (5U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_CLRMSK (0x0000001FU)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000007ffffff))) << 5))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x07fffffff8000000))) >> 27))); }
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_BASE_ADDR(_ft_) (((_ft_).u32_0 >> (5)) | ((IMG_UINT64)((_ft_).u32_1 & 0xffffffffU ) << (27)))
|
||
|
|
#endif /* RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES */
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
The PM FreeListState Buffer Layout - this will apply to 3 resources - FSTACK, UFSTACK and MMUSTACK
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_FREELISTSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
} RGX_PM_FREELISTSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
Reserved field word 2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_WOFF (7U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_2(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_2(_ft_) (((_ft_).u32_7 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_2_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved field word 1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_WOFF (6U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_1(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_1(_ft_) (((_ft_).u32_6 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_1_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved field word 0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_WOFF (5U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_RSV_STUFF32_0(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_RSV_STUFF32_0(_ft_) (((_ft_).u32_5 >> (RGX_PM_FREELISTSTATE_BUFFER_RSV_STUFF32_0_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of pages consumed for the MMU Page Table. Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_WOFF (4U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_MMUPAGE_STATUS(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_MMUPAGE_STATUS(_ft_) (((_ft_).u32_4 >> (RGX_PM_FREELISTSTATE_BUFFER_MMUPAGE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The total number of pages consumed from the free stack. Must be initialised to zero. This field is unused in the MMUSTACK.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_WOFF (3U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_PAGE_STATUS(_ft_,_x_) ((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_PAGE_STATUS(_ft_) (((_ft_).u32_3 >> (RGX_PM_FREELISTSTATE_BUFFER_PAGE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Stack pointer for the free stack - the location of the next free page relative to the BaseAddr, in number of DWORDs. Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_WOFF (2U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_STACK_PTR(_ft_,_x_) ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT))))
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_STACK_PTR(_ft_) (((_ft_).u32_2 >> (RGX_PM_FREELISTSTATE_BUFFER_STACK_PTR_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Base address of the free stack - points to the bottom of the stack.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_SET_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_FREELISTSTATE_BUFFER_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_FREELISTSTATE_BUFFER_GET_BASE_ADDR(_ft_) (((_ft_).u32_0 >> (0)) | ((IMG_UINT64)((_ft_).u32_1 & 0xffffffffU ) << (32)))
|
||
|
|
#endif /* !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES) */
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
256-bit granular, lower bits ignored.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_ALIGNSHIFT (5U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_ALIGNSIZE (32U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES */
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit aligned.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
The 40-bit, 16-byte-aligned address is packed into bits 35:0 of the two DWORDs.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_BASE_ADDR_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES) */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Maximum range supported by hardware is 23 bits.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_STACK_PTR_STACK_PTR (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_STACK_PTR_STACK_PTR_LOWER (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_STACK_PTR_STACK_PTR_UPPER (16777215U)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Maximum range supported by hardware is 23 bits.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_PAGE_STATUS_PAGE_STATUS (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_PAGE_STATUS_PAGE_STATUS_LOWER (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_PAGE_STATUS_PAGE_STATUS_UPPER (16777215U)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Maximum range supported by hardware is 23 bits.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_FREELISTSTATE_MMUPAGE_STATUS_MMUPAGE_STATUS (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_MMUPAGE_STATUS_MMUPAGE_STATUS_LOWER (0U)
|
||
|
|
#define RGX_PM_FREELISTSTATE_MMUPAGE_STATUS_MMUPAGE_STATUS_UPPER (16777215U)
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)
|
||
|
|
/*
|
||
|
|
The PM Render Context Buffer Layout
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_RENDERSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
IMG_UINT32 u32_8;
|
||
|
|
IMG_UINT32 u32_9;
|
||
|
|
IMG_UINT32 u32_10;
|
||
|
|
IMG_UINT32 u32_11;
|
||
|
|
IMG_UINT32 u32_12;
|
||
|
|
IMG_UINT32 u32_13;
|
||
|
|
IMG_UINT32 u32_14;
|
||
|
|
IMG_UINT32 u32_15;
|
||
|
|
IMG_UINT32 u32_16;
|
||
|
|
IMG_UINT32 u32_17;
|
||
|
|
IMG_UINT32 u32_18;
|
||
|
|
IMG_UINT32 u32_19;
|
||
|
|
IMG_UINT32 u32_20;
|
||
|
|
IMG_UINT32 u32_21;
|
||
|
|
IMG_UINT32 u32_22;
|
||
|
|
IMG_UINT32 u32_23;
|
||
|
|
IMG_UINT32 u32_24;
|
||
|
|
IMG_UINT32 u32_25;
|
||
|
|
IMG_UINT32 u32_26;
|
||
|
|
IMG_UINT32 u32_27;
|
||
|
|
IMG_UINT32 u32_28;
|
||
|
|
IMG_UINT32 u32_29;
|
||
|
|
IMG_UINT32 u32_30;
|
||
|
|
IMG_UINT32 u32_31;
|
||
|
|
IMG_UINT32 u32_32;
|
||
|
|
IMG_UINT32 u32_33;
|
||
|
|
IMG_UINT32 u32_34;
|
||
|
|
IMG_UINT32 u32_35;
|
||
|
|
IMG_UINT32 u32_36;
|
||
|
|
IMG_UINT32 u32_37;
|
||
|
|
IMG_UINT32 u32_38;
|
||
|
|
IMG_UINT32 u32_39;
|
||
|
|
IMG_UINT32 u32_40;
|
||
|
|
IMG_UINT32 u32_41;
|
||
|
|
IMG_UINT32 u32_42;
|
||
|
|
IMG_UINT32 u32_43;
|
||
|
|
IMG_UINT32 u32_44;
|
||
|
|
IMG_UINT32 u32_45;
|
||
|
|
} RGX_PM_RENDERSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
The base address of the Virtual-Physical Page Translation Table.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_SHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_SHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_CLRMSK (0x0000000FU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VFP_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffffff))) << 4))); \
|
||
|
|
((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0ffffffff0000000))) >> 28))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VFP_BASE_ADDR(_ft_) (((_ft_).u32_10 >> (4)) | ((IMG_UINT64)((_ft_).u32_11 & 0xffffffffU ) << (28)))
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the ISP.
|
||
|
|
A '1' in a bit position indicates that the ISP has signalled that the corresponding macrotile can be freed.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MTILEFREE_STATUS(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MTILEFREE_STATUS(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the PM.
|
||
|
|
A '1' in a bit position indicates that the corresponding macrotile has been freed, and its pages released back to the appropriate free stack.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_DEALLOC_MASK_STATUS(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_DEALLOC_MASK_STATUS(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the VHEAP buffer.
|
||
|
|
Must be initialised to point to the location of the VHEAP buffer in memory.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_WOFF (6U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_SHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_WOFF (7U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_SHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_CLRMSK (0x0000000FU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VHEAP_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x000000000fffffff))) << 4))); \
|
||
|
|
((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0ffffffff0000000))) >> 28))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VHEAP_BASE_ADDR(_ft_) (((_ft_).u32_6 >> (4)) | ((IMG_UINT64)((_ft_).u32_7 & 0xffffffffU ) << (28)))
|
||
|
|
/*
|
||
|
|
Reserved bits, un-used.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_WOFF (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_RSV_STUFF32(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_RSV_STUFF32(_ft_) (((_ft_).u32_5 >> (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of entries on the MLIST. Must be initialised to zero, meaning no pages allocated.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_WOFF (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_TAIL(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_TAIL(_ft_) (((_ft_).u32_4 >> (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the MLIST.
|
||
|
|
Must be initialised to point to a block of memory where the PM can write the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_WOFF (2U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_WOFF (3U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK (0x0000001FU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000007ffffff))) << 5))); \
|
||
|
|
((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x07fffffff8000000))) >> 27))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_BASE_ADDR(_ft_) (((_ft_).u32_2 >> (5)) | ((IMG_UINT64)((_ft_).u32_3 & 0xffffffffU ) << (27)))
|
||
|
|
/*
|
||
|
|
The number of entries on the ALIST. Must be initialised to zero, meaning no pages allocated.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_TAIL(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_TAIL(_ft_) (((_ft_).u32_0 >> (0)) | ((IMG_UINT64)((_ft_).u32_1 & 0xffffffffU ) << (32)))
|
||
|
|
#endif /* RGX_FEATURE_PM_REGISTER_CONFIG_MODE&&PM_BYTE_ALIGNED_BASE_ADDRESSES&&!SINGLE_TE_VSPACE */
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&!defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)
|
||
|
|
/*
|
||
|
|
The PM Render Context Buffer Layout
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_RENDERSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
IMG_UINT32 u32_8;
|
||
|
|
IMG_UINT32 u32_9;
|
||
|
|
IMG_UINT32 u32_10;
|
||
|
|
IMG_UINT32 u32_11;
|
||
|
|
} RGX_PM_RENDERSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
The base address of the Virtual-Physical Page Translation Table.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VFP_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VFP_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VFP_BASE_ADDR(_ft_) (((_ft_).u32_10 >> (0)) | ((IMG_UINT64)((_ft_).u32_11 & 0xffffffffU ) << (32)))
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the ISP.
|
||
|
|
A '1' in a bit position indicates that the ISP has signalled that the corresponding macrotile can be freed.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MTILEFREE_STATUS(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MTILEFREE_STATUS(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the PM.
|
||
|
|
A '1' in a bit position indicates that the corresponding macrotile has been freed, and its pages released back to the appropriate free stack.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
Must be initialised to zero.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_DEALLOC_MASK_STATUS(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_DEALLOC_MASK_STATUS(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the VHEAP buffer.
|
||
|
|
Must be initialised to point to the location of the VHEAP buffer in memory.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_WOFF (6U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_WOFF (7U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VHEAP_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_RENDERSTATE_BUFFER_VHEAP_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VHEAP_BASE_ADDR(_ft_) (((_ft_).u32_6 >> (0)) | ((IMG_UINT64)((_ft_).u32_7 & 0xffffffffU ) << (32)))
|
||
|
|
/*
|
||
|
|
Reserved bits, un-used.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_WOFF (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_RSV_STUFF32(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_RSV_STUFF32(_ft_) (((_ft_).u32_5 >> (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of entries on the MLIST. Must be initialised to zero, meaning no pages allocated.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_WOFF (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_TAIL(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_TAIL(_ft_) (((_ft_).u32_4 >> (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the MLIST.
|
||
|
|
Must be initialised to point to a block of memory where the PM can write the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_WOFF (2U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_WOFF (3U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_BASE_ADDR(_ft_) (((_ft_).u32_2 >> (0)) | ((IMG_UINT64)((_ft_).u32_3 & 0xffffffffU ) << (32)))
|
||
|
|
/*
|
||
|
|
The number of entries on the ALIST. Must be initialised to zero, meaning no pages allocated.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_TAIL(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0xffffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_TAIL(_ft_) (((_ft_).u32_0 >> (0)) | ((IMG_UINT64)((_ft_).u32_1 & 0xffffffffU ) << (32)))
|
||
|
|
#endif /* RGX_FEATURE_PM_REGISTER_CONFIG_MODE&&!PM_BYTE_ALIGNED_BASE_ADDRESSES&&!SINGLE_TE_VSPACE */
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_SINGLE_TE_VSPACE)
|
||
|
|
/*
|
||
|
|
The PM Render Context Buffer Layout
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_RENDERSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
IMG_UINT32 u32_8;
|
||
|
|
IMG_UINT32 u32_9;
|
||
|
|
IMG_UINT32 u32_10;
|
||
|
|
IMG_UINT32 u32_11;
|
||
|
|
IMG_UINT32 u32_12;
|
||
|
|
IMG_UINT32 u32_13;
|
||
|
|
IMG_UINT32 u32_14;
|
||
|
|
IMG_UINT32 u32_15;
|
||
|
|
IMG_UINT32 u32_16;
|
||
|
|
IMG_UINT32 u32_17;
|
||
|
|
IMG_UINT32 u32_18;
|
||
|
|
IMG_UINT32 u32_19;
|
||
|
|
IMG_UINT32 u32_20;
|
||
|
|
IMG_UINT32 u32_21;
|
||
|
|
IMG_UINT32 u32_22;
|
||
|
|
IMG_UINT32 u32_23;
|
||
|
|
IMG_UINT32 u32_24;
|
||
|
|
IMG_UINT32 u32_25;
|
||
|
|
IMG_UINT32 u32_26;
|
||
|
|
IMG_UINT32 u32_27;
|
||
|
|
IMG_UINT32 u32_28;
|
||
|
|
IMG_UINT32 u32_29;
|
||
|
|
IMG_UINT32 u32_30;
|
||
|
|
IMG_UINT32 u32_31;
|
||
|
|
IMG_UINT32 u32_32;
|
||
|
|
IMG_UINT32 u32_33;
|
||
|
|
IMG_UINT32 u32_34;
|
||
|
|
IMG_UINT32 u32_35;
|
||
|
|
IMG_UINT32 u32_36;
|
||
|
|
IMG_UINT32 u32_37;
|
||
|
|
IMG_UINT32 u32_38;
|
||
|
|
IMG_UINT32 u32_39;
|
||
|
|
IMG_UINT32 u32_40;
|
||
|
|
IMG_UINT32 u32_41;
|
||
|
|
IMG_UINT32 u32_42;
|
||
|
|
IMG_UINT32 u32_43;
|
||
|
|
IMG_UINT32 u32_44;
|
||
|
|
IMG_UINT32 u32_45;
|
||
|
|
} RGX_PM_RENDERSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_WOFF (37U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE(_ft_) (((_ft_).u32_37 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_WOFF (36U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_MAPPED(_ft_,_x_) ((_ft_).u32_36 = (((_ft_).u32_36 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_MAPPED(_ft_) (((_ft_).u32_36 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_WOFF (36U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE(_ft_,_x_) ((_ft_).u32_36 = (((_ft_).u32_36 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE(_ft_) (((_ft_).u32_36 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_WOFF (35U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE(_ft_,_x_) ((_ft_).u32_35 = (((_ft_).u32_35 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE(_ft_) (((_ft_).u32_35 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_WOFF (34U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_MAPPED(_ft_,_x_) ((_ft_).u32_34 = (((_ft_).u32_34 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_MAPPED(_ft_) (((_ft_).u32_34 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_WOFF (34U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE(_ft_,_x_) ((_ft_).u32_34 = (((_ft_).u32_34 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE(_ft_) (((_ft_).u32_34 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_WOFF (33U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE(_ft_,_x_) ((_ft_).u32_33 = (((_ft_).u32_33 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE(_ft_) (((_ft_).u32_33 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_WOFF (32U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_MAPPED(_ft_,_x_) ((_ft_).u32_32 = (((_ft_).u32_32 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_MAPPED(_ft_) (((_ft_).u32_32 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_WOFF (32U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE(_ft_,_x_) ((_ft_).u32_32 = (((_ft_).u32_32 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE(_ft_) (((_ft_).u32_32 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_WOFF (30U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE(_ft_,_x_) ((_ft_).u32_30 = (((_ft_).u32_30 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE(_ft_) (((_ft_).u32_30 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_WOFF (29U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_ADDR(_ft_,_x_) ((_ft_).u32_29 = (((_ft_).u32_29 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_ADDR(_ft_) (((_ft_).u32_29 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_WOFF (28U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_MAPPED(_ft_,_x_) ((_ft_).u32_28 = (((_ft_).u32_28 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_MAPPED(_ft_) (((_ft_).u32_28 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_WOFF (28U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE(_ft_,_x_) ((_ft_).u32_28 = (((_ft_).u32_28 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE(_ft_) (((_ft_).u32_28 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_WOFF (26U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE(_ft_,_x_) ((_ft_).u32_26 = (((_ft_).u32_26 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE(_ft_) (((_ft_).u32_26 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_WOFF (25U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_ADDR(_ft_,_x_) ((_ft_).u32_25 = (((_ft_).u32_25 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_ADDR(_ft_) (((_ft_).u32_25 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_WOFF (24U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_MAPPED(_ft_,_x_) ((_ft_).u32_24 = (((_ft_).u32_24 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_MAPPED(_ft_) (((_ft_).u32_24 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_WOFF (24U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE(_ft_,_x_) ((_ft_).u32_24 = (((_ft_).u32_24 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE(_ft_) (((_ft_).u32_24 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_WOFF (18U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_LAST_PAGE(_ft_,_x_) ((_ft_).u32_18 = (((_ft_).u32_18 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_LAST_PAGE(_ft_) (((_ft_).u32_18 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_WOFF (17U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_ADDR(_ft_,_x_) ((_ft_).u32_17 = (((_ft_).u32_17 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_ADDR(_ft_) (((_ft_).u32_17 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_WOFF (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_MAPPED(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_MAPPED(_ft_) (((_ft_).u32_16 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_WOFF (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_INIT_PAGE(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_INIT_PAGE(_ft_) (((_ft_).u32_16 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_WOFF (12U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE0_INIT(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE0_INIT(_ft_) (((_ft_).u32_12 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_WOFF (12U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE0(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE0(_ft_) (((_ft_).u32_12 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE3_INIT(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE3_INIT(_ft_) (((_ft_).u32_11 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE3(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE3(_ft_) (((_ft_).u32_11 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE2_INIT(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE2_INIT(_ft_) (((_ft_).u32_10 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE2(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE2(_ft_) (((_ft_).u32_10 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE1_INIT(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE1_INIT(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE1(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE1(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE0_INIT(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE0_INIT(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE0(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE0(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the ISP.
|
||
|
|
A '1' in a bit position indicates that the ISP has signalled that the corresponding macrotile can be freed.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_WOFF (7U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MTILEFREE_STATUS(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MTILEFREE_STATUS(_ft_) (((_ft_).u32_7 >> (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the PM.
|
||
|
|
A '1' in a bit position indicates that the corresponding macrotile has been freed, and its pages released back to the appropriate free stack.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_WOFF (6U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_DEALLOC_MASK_STATUS(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_DEALLOC_MASK_STATUS(_ft_) (((_ft_).u32_6 >> (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved bits, un-used.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_WOFF (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_RSV_STUFF32(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_RSV_STUFF32(_ft_) (((_ft_).u32_5 >> (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of entries on the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_WOFF (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_TAIL(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_TAIL(_ft_) (((_ft_).u32_4 >> (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the MLIST.
|
||
|
|
Must be initialised to point to a block of memory where the PM can write the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_WOFF (2U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_WOFF (3U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK (0x0000001FU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000007ffffff))) << 5))); \
|
||
|
|
((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x07fffffff8000000))) >> 27))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_BASE_ADDR(_ft_) (((_ft_).u32_2 >> (5)) | ((IMG_UINT64)((_ft_).u32_3 & 0xffffffffU ) << (27)))
|
||
|
|
/*
|
||
|
|
Init bit sent flag for ALIST
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_INIT(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_INIT(_ft_) (((_ft_).u32_1 >> (RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
The number of entries on the ALIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_TAIL(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x7fffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_TAIL(_ft_) (((_ft_).u32_0 >> (0)) | ((IMG_UINT64)((_ft_).u32_1 & 0x7fffffffU ) << (32)))
|
||
|
|
#endif /* RGX_FEATURE_SINGLE_TE_VSPACE */
|
||
|
|
|
||
|
|
|
||
|
|
#if !(defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)) && !(defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&!defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)) && !(defined(RGX_FEATURE_SINGLE_TE_VSPACE))
|
||
|
|
/*
|
||
|
|
The PM Render Context Buffer Layout
|
||
|
|
*/
|
||
|
|
typedef struct RGX_PM_RENDERSTATE_BUFFER_TAG {
|
||
|
|
IMG_UINT32 u32_0;
|
||
|
|
IMG_UINT32 u32_1;
|
||
|
|
IMG_UINT32 u32_2;
|
||
|
|
IMG_UINT32 u32_3;
|
||
|
|
IMG_UINT32 u32_4;
|
||
|
|
IMG_UINT32 u32_5;
|
||
|
|
IMG_UINT32 u32_6;
|
||
|
|
IMG_UINT32 u32_7;
|
||
|
|
IMG_UINT32 u32_8;
|
||
|
|
IMG_UINT32 u32_9;
|
||
|
|
IMG_UINT32 u32_10;
|
||
|
|
IMG_UINT32 u32_11;
|
||
|
|
IMG_UINT32 u32_12;
|
||
|
|
IMG_UINT32 u32_13;
|
||
|
|
IMG_UINT32 u32_14;
|
||
|
|
IMG_UINT32 u32_15;
|
||
|
|
IMG_UINT32 u32_16;
|
||
|
|
IMG_UINT32 u32_17;
|
||
|
|
IMG_UINT32 u32_18;
|
||
|
|
IMG_UINT32 u32_19;
|
||
|
|
IMG_UINT32 u32_20;
|
||
|
|
IMG_UINT32 u32_21;
|
||
|
|
IMG_UINT32 u32_22;
|
||
|
|
IMG_UINT32 u32_23;
|
||
|
|
IMG_UINT32 u32_24;
|
||
|
|
IMG_UINT32 u32_25;
|
||
|
|
IMG_UINT32 u32_26;
|
||
|
|
IMG_UINT32 u32_27;
|
||
|
|
IMG_UINT32 u32_28;
|
||
|
|
IMG_UINT32 u32_29;
|
||
|
|
IMG_UINT32 u32_30;
|
||
|
|
IMG_UINT32 u32_31;
|
||
|
|
IMG_UINT32 u32_32;
|
||
|
|
IMG_UINT32 u32_33;
|
||
|
|
IMG_UINT32 u32_34;
|
||
|
|
IMG_UINT32 u32_35;
|
||
|
|
IMG_UINT32 u32_36;
|
||
|
|
IMG_UINT32 u32_37;
|
||
|
|
IMG_UINT32 u32_38;
|
||
|
|
IMG_UINT32 u32_39;
|
||
|
|
IMG_UINT32 u32_40;
|
||
|
|
IMG_UINT32 u32_41;
|
||
|
|
IMG_UINT32 u32_42;
|
||
|
|
IMG_UINT32 u32_43;
|
||
|
|
IMG_UINT32 u32_44;
|
||
|
|
IMG_UINT32 u32_45;
|
||
|
|
} RGX_PM_RENDERSTATE_BUFFER;
|
||
|
|
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_WOFF (45U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE(_ft_,_x_) ((_ft_).u32_45 = (((_ft_).u32_45 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE(_ft_) (((_ft_).u32_45 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_WOFF (44U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_MAPPED(_ft_,_x_) ((_ft_).u32_44 = (((_ft_).u32_44 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_MAPPED(_ft_) (((_ft_).u32_44 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 3 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_WOFF (44U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE(_ft_,_x_) ((_ft_).u32_44 = (((_ft_).u32_44 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE(_ft_) (((_ft_).u32_44 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE3_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_WOFF (43U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE(_ft_,_x_) ((_ft_).u32_43 = (((_ft_).u32_43 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE(_ft_) (((_ft_).u32_43 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_WOFF (42U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_MAPPED(_ft_,_x_) ((_ft_).u32_42 = (((_ft_).u32_42 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_MAPPED(_ft_) (((_ft_).u32_42 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 2 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_WOFF (42U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE(_ft_,_x_) ((_ft_).u32_42 = (((_ft_).u32_42 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE(_ft_) (((_ft_).u32_42 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE2_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_WOFF (41U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE(_ft_,_x_) ((_ft_).u32_41 = (((_ft_).u32_41 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE(_ft_) (((_ft_).u32_41 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_WOFF (40U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_MAPPED(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_MAPPED(_ft_) (((_ft_).u32_40 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 1 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_WOFF (40U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE(_ft_,_x_) ((_ft_).u32_40 = (((_ft_).u32_40 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE(_ft_) (((_ft_).u32_40 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE1_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 3 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_WOFF (37U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE(_ft_,_x_) ((_ft_).u32_37 = (((_ft_).u32_37 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE(_ft_) (((_ft_).u32_37 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 3 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_WOFF (36U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE3_MAPPED(_ft_,_x_) ((_ft_).u32_36 = (((_ft_).u32_36 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE3_MAPPED(_ft_) (((_ft_).u32_36 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 3 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_WOFF (36U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE(_ft_,_x_) ((_ft_).u32_36 = (((_ft_).u32_36 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE(_ft_) (((_ft_).u32_36 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE3_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 2 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_WOFF (35U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE(_ft_,_x_) ((_ft_).u32_35 = (((_ft_).u32_35 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE(_ft_) (((_ft_).u32_35 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 2 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_WOFF (34U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE2_MAPPED(_ft_,_x_) ((_ft_).u32_34 = (((_ft_).u32_34 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE2_MAPPED(_ft_) (((_ft_).u32_34 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 2 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_WOFF (34U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE(_ft_,_x_) ((_ft_).u32_34 = (((_ft_).u32_34 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE(_ft_) (((_ft_).u32_34 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE2_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 1 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_WOFF (33U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE(_ft_,_x_) ((_ft_).u32_33 = (((_ft_).u32_33 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE(_ft_) (((_ft_).u32_33 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 1 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_WOFF (32U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE1_MAPPED(_ft_,_x_) ((_ft_).u32_32 = (((_ft_).u32_32 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE1_MAPPED(_ft_) (((_ft_).u32_32 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 1 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_WOFF (32U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE(_ft_,_x_) ((_ft_).u32_32 = (((_ft_).u32_32 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE(_ft_) (((_ft_).u32_32 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE1_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_WOFF (30U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE(_ft_,_x_) ((_ft_).u32_30 = (((_ft_).u32_30 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE(_ft_) (((_ft_).u32_30 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_WOFF (29U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_ADDR(_ft_,_x_) ((_ft_).u32_29 = (((_ft_).u32_29 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_ADDR(_ft_) (((_ft_).u32_29 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_WOFF (28U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_MAPPED(_ft_,_x_) ((_ft_).u32_28 = (((_ft_).u32_28 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_MAPPED(_ft_) (((_ft_).u32_28 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for VCE pipe 0 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_WOFF (28U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE(_ft_,_x_) ((_ft_).u32_28 = (((_ft_).u32_28 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE(_ft_) (((_ft_).u32_28 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_VCE_PIPE0_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 0 LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_WOFF (26U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE(_ft_,_x_) ((_ft_).u32_26 = (((_ft_).u32_26 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE(_ft_) (((_ft_).u32_26 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 0 ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_WOFF (25U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_ADDR(_ft_,_x_) ((_ft_).u32_25 = (((_ft_).u32_25 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_ADDR(_ft_) (((_ft_).u32_25 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 0 MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_WOFF (24U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_MAPPED(_ft_,_x_) ((_ft_).u32_24 = (((_ft_).u32_24 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_MAPPED(_ft_) (((_ft_).u32_24 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for TE pipe 0 INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_WOFF (24U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE(_ft_,_x_) ((_ft_).u32_24 = (((_ft_).u32_24 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE(_ft_) (((_ft_).u32_24 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_TE_PIPE0_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST LAST_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_WOFF (18U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_LAST_PAGE(_ft_,_x_) ((_ft_).u32_18 = (((_ft_).u32_18 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_LAST_PAGE(_ft_) (((_ft_).u32_18 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_LAST_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST ADDR
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_WOFF (17U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_CLRMSK (0xF0000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_ADDR(_ft_,_x_) ((_ft_).u32_17 = (((_ft_).u32_17 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_CLRMSK ) | (((_x_) & (0x0fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_ADDR(_ft_) (((_ft_).u32_17 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_ADDR_SHIFT)) & 0x0fffffffU)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST MAPPED
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_WOFF (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_MAPPED(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_MAPPED(_ft_) (((_ft_).u32_16 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_MAPPED_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
MMU catalogue base address for ALIST INIT_PAGE
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_WOFF (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_CLRMSK (0xFFF00000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MMU_CAT_BASE_ALIST_INIT_PAGE(_ft_,_x_) ((_ft_).u32_16 = (((_ft_).u32_16 & RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_CLRMSK ) | (((_x_) & (0x000fffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MMU_CAT_BASE_ALIST_INIT_PAGE(_ft_) (((_ft_).u32_16 >> (RGX_PM_RENDERSTATE_BUFFER_MMU_CAT_BASE_ALIST_INIT_PAGE_SHIFT)) & 0x000fffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_WOFF (15U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE3_INIT(_ft_,_x_) ((_ft_).u32_15 = (((_ft_).u32_15 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE3_INIT(_ft_) (((_ft_).u32_15 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_WOFF (15U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE3(_ft_,_x_) ((_ft_).u32_15 = (((_ft_).u32_15 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE3(_ft_) (((_ft_).u32_15 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE3_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_WOFF (14U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE3_INIT(_ft_,_x_) ((_ft_).u32_14 = (((_ft_).u32_14 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE3_INIT(_ft_) (((_ft_).u32_14 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE3
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_WOFF (14U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE3(_ft_,_x_) ((_ft_).u32_14 = (((_ft_).u32_14 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE3(_ft_) (((_ft_).u32_14 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE3_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_WOFF (13U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE2_INIT(_ft_,_x_) ((_ft_).u32_13 = (((_ft_).u32_13 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE2_INIT(_ft_) (((_ft_).u32_13 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_WOFF (13U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE2(_ft_,_x_) ((_ft_).u32_13 = (((_ft_).u32_13 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE2(_ft_) (((_ft_).u32_13 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE2_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_WOFF (12U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE2_INIT(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE2_INIT(_ft_) (((_ft_).u32_12 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE2
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_WOFF (12U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE2(_ft_,_x_) ((_ft_).u32_12 = (((_ft_).u32_12 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE2(_ft_) (((_ft_).u32_12 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE2_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE1_INIT(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE1_INIT(_ft_) (((_ft_).u32_11 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_WOFF (11U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE1(_ft_,_x_) ((_ft_).u32_11 = (((_ft_).u32_11 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE1(_ft_) (((_ft_).u32_11 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE1_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE1_INIT(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE1_INIT(_ft_) (((_ft_).u32_10 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE1
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_WOFF (10U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE1(_ft_,_x_) ((_ft_).u32_10 = (((_ft_).u32_10 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE1(_ft_) (((_ft_).u32_10 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE1_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for TE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE0_INIT(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE0_INIT(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for TE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_WOFF (9U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_TE0(_ft_,_x_) ((_ft_).u32_9 = (((_ft_).u32_9 & RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_TE0(_ft_) (((_ft_).u32_9 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_TE0_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
Init Bit Sent Flag for VCE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE0_INIT(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE0_INIT(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
16KB aligned virtual top pointer for VCE0
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_WOFF (8U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_VPTR_VCE0(_ft_,_x_) ((_ft_).u32_8 = (((_ft_).u32_8 & RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_CLRMSK ) | (((_x_) & (0x7fffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_VPTR_VCE0(_ft_) (((_ft_).u32_8 >> (RGX_PM_RENDERSTATE_BUFFER_VPTR_VCE0_SHIFT)) & 0x7fffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the ISP.
|
||
|
|
A '1' in a bit position indicates that the ISP has signalled that the corresponding macrotile can be freed.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_WOFF (7U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MTILEFREE_STATUS(_ft_,_x_) ((_ft_).u32_7 = (((_ft_).u32_7 & RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MTILEFREE_STATUS(_ft_) (((_ft_).u32_7 >> (RGX_PM_RENDERSTATE_BUFFER_MTILEFREE_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
A 16-bit macrotile mask indicating which macrotiles have been freed by the PM.
|
||
|
|
A '1' in a bit position indicates that the corresponding macrotile has been freed, and its pages released back to the appropriate free stack.
|
||
|
|
Only the least-significant 16 bits are valid.
|
||
|
|
Only used in the 3D phase.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_WOFF (6U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_DEALLOC_MASK_STATUS(_ft_,_x_) ((_ft_).u32_6 = (((_ft_).u32_6 & RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_DEALLOC_MASK_STATUS(_ft_) (((_ft_).u32_6 >> (RGX_PM_RENDERSTATE_BUFFER_DEALLOC_MASK_STATUS_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
Reserved bits, un-used.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_WOFF (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_RSV_STUFF32(_ft_,_x_) ((_ft_).u32_5 = (((_ft_).u32_5 & RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_RSV_STUFF32(_ft_) (((_ft_).u32_5 >> (RGX_PM_RENDERSTATE_BUFFER_RSV_STUFF32_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The number of entries on the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_WOFF (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_TAIL(_ft_,_x_) ((_ft_).u32_4 = (((_ft_).u32_4 & RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_CLRMSK ) | (((_x_) & (0xffffffffU)) << (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_TAIL(_ft_) (((_ft_).u32_4 >> (RGX_PM_RENDERSTATE_BUFFER_MLIST_TAIL_SHIFT)) & 0xffffffffU)
|
||
|
|
/*
|
||
|
|
The base address of the MLIST.
|
||
|
|
Must be initialised to point to a block of memory where the PM can write the MLIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_WOFF (2U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_WOFF (3U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_SHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK (0x0000001FU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_MLIST_BASE_ADDR(_ft_,_x_) { ((_ft_).u32_2 = (((_ft_).u32_2 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x0000000007ffffff))) << 5))); \
|
||
|
|
((_ft_).u32_3 = (((_ft_).u32_3 & RGX_PM_RENDERSTATE_BUFFER_MLIST_BASE_ADDR_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x07fffffff8000000))) >> 27))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_MLIST_BASE_ADDR(_ft_) (((_ft_).u32_2 >> (5)) | ((IMG_UINT64)((_ft_).u32_3 & 0xffffffffU ) << (27)))
|
||
|
|
/*
|
||
|
|
Init bit sent flag for ALIST
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT (31U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_CLRMSK (0x7FFFFFFFU)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_INIT(_ft_,_x_) ((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_CLRMSK ) | (((_x_) & (0x00000001U)) << (RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT))))
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_INIT(_ft_) (((_ft_).u32_1 >> (RGX_PM_RENDERSTATE_BUFFER_ALIST_INIT_SHIFT)) & 0x00000001U)
|
||
|
|
/*
|
||
|
|
The number of entries on the ALIST.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_WOFF (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_WOFF (1U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_SHIFT (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK (0x00000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK (0x80000000U)
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_SET_ALIST_TAIL(_ft_,_x_) { ((_ft_).u32_0 = (((_ft_).u32_0 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W0_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x00000000ffffffff))) << 0))); \
|
||
|
|
((_ft_).u32_1 = (((_ft_).u32_1 & RGX_PM_RENDERSTATE_BUFFER_ALIST_TAIL_W1_CLRMSK ) | (((_x_) & (IMG_UINT64_C(0x7fffffff00000000))) >> 32))); }
|
||
|
|
#define RGX_PM_RENDERSTATE_BUFFER_GET_ALIST_TAIL(_ft_) (((_ft_).u32_0 >> (0)) | ((IMG_UINT64)((_ft_).u32_1 & 0x7fffffffU ) << (32)))
|
||
|
|
#endif /* !(defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)) && !(defined(RGX_FEATURE_PM_REGISTER_CONFIG_MODE)&&!defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)&&!defined(RGX_FEATURE_SINGLE_TE_VSPACE)) && !(defined(RGX_FEATURE_SINGLE_TE_VSPACE)) */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Maximum range supported by hardware is 33 bits.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_ALIST_TAIL_ALIST_TAIL (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_ALIST_TAIL_ALIST_TAIL_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_ALIST_TAIL_ALIST_TAIL_UPPER (8589934591ULL)
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
256-bit granular, lower bits ignored.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_ALIGNSHIFT (5U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_ALIGNSIZE (32U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES */
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit aligned.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
The 40-bit, 16-byte-aligned address is packed into bits 35:0 of the two DWORDs.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_BASE_ADDR_MLIST_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES) */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Maximum range supported by hardware is 33 bits.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_TAIL_MLIST_TAIL (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_TAIL_MLIST_TAIL_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MLIST_TAIL_MLIST_TAIL_UPPER (8589934591ULL)
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit granular, lower bits ignored.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES */
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit aligned.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
The 40-bit, 16-byte-aligned address is packed into bits 35:0 of the two DWORDs.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VHEAP_BASE_ADDR_VHEAP_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES) */
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Only the 16 least-significant bits are used
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_DEALLOC_MASK_STATUS_DEALLOC_MASK_STATUS (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_DEALLOC_MASK_STATUS_DEALLOC_MASK_STATUS_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_DEALLOC_MASK_STATUS_DEALLOC_MASK_STATUS_UPPER (65535U)
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
Only the 16 least-significant bits are used
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_MTILEFREE_STATUS_MTILEFREE_STATUS (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MTILEFREE_STATUS_MTILEFREE_STATUS_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_MTILEFREE_STATUS_MTILEFREE_STATUS_UPPER (65535U)
|
||
|
|
|
||
|
|
|
||
|
|
#if defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit granular, lower bits ignored.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES */
|
||
|
|
|
||
|
|
|
||
|
|
#if !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES)
|
||
|
|
/*
|
||
|
|
128-bit aligned.
|
||
|
|
Maximum addressable range supported by hardware is 1 TB.
|
||
|
|
The 40-bit, 16-byte-aligned address is packed into bits 35:0 of the two DWORDs.
|
||
|
|
*/
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_ALIGNSHIFT (4U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_ALIGNSIZE (16U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR_LOWER (0U)
|
||
|
|
#define RGX_PM_RENDERSTATE_VFP_BASE_ADDR_VFP_BASE_ADDR_UPPER (68719476735ULL)
|
||
|
|
#endif /* !defined(RGX_FEATURE_PM_BYTE_ALIGNED_BASE_ADDRESSES) */
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* RGXPMDEFS_H */
|
||
|
|
/*****************************************************************************
|
||
|
|
End of file (rgxpmdefs.h)
|
||
|
|
*****************************************************************************/
|