208 lines
7.4 KiB
C
208 lines
7.4 KiB
C
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/*
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* Copyright (C) 2010 - 2017 Novatek, Inc.
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*
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* $Revision: 19587 $
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* $Date: 2017-11-28 21:00:30 +0800 (周二, 28 十一月 2017) $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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struct nvt_ts_mem_map {
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uint32_t EVENT_BUF_ADDR;
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uint32_t RAW_PIPE0_ADDR;
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uint32_t RAW_PIPE0_Q_ADDR;
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uint32_t RAW_PIPE1_ADDR;
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uint32_t RAW_PIPE1_Q_ADDR;
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uint32_t BASELINE_ADDR;
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uint32_t BASELINE_Q_ADDR;
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uint32_t BASELINE_BTN_ADDR;
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uint32_t BASELINE_BTN_Q_ADDR;
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uint32_t DIFF_PIPE0_ADDR;
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uint32_t DIFF_PIPE0_Q_ADDR;
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uint32_t DIFF_PIPE1_ADDR;
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uint32_t DIFF_PIPE1_Q_ADDR;
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uint32_t RAW_BTN_PIPE0_ADDR;
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uint32_t RAW_BTN_PIPE0_Q_ADDR;
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uint32_t RAW_BTN_PIPE1_ADDR;
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uint32_t RAW_BTN_PIPE1_Q_ADDR;
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uint32_t DIFF_BTN_PIPE0_ADDR;
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uint32_t DIFF_BTN_PIPE0_Q_ADDR;
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uint32_t DIFF_BTN_PIPE1_ADDR;
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uint32_t DIFF_BTN_PIPE1_Q_ADDR;
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uint32_t READ_FLASH_CHECKSUM_ADDR;
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uint32_t RW_FLASH_DATA_ADDR;
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};
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static const struct nvt_ts_mem_map NT36672A_memory_map = {
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.EVENT_BUF_ADDR = 0x21C00,
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.RAW_PIPE0_ADDR = 0x20000,
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.RAW_PIPE0_Q_ADDR = 0,
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.RAW_PIPE1_ADDR = 0x23000,
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.RAW_PIPE1_Q_ADDR = 0,
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.BASELINE_ADDR = 0x20BFC,
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.BASELINE_Q_ADDR = 0,
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.BASELINE_BTN_ADDR = 0x23BFC,
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.BASELINE_BTN_Q_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x206DC,
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.DIFF_PIPE0_Q_ADDR = 0,
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.DIFF_PIPE1_ADDR = 0x236DC,
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.DIFF_PIPE1_Q_ADDR = 0,
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.RAW_BTN_PIPE0_ADDR = 0x20510,
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.RAW_BTN_PIPE0_Q_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0x23510,
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.RAW_BTN_PIPE1_Q_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0x20BF0,
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.DIFF_BTN_PIPE0_Q_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0x23BF0,
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.DIFF_BTN_PIPE1_Q_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x24000,
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.RW_FLASH_DATA_ADDR = 0x24002,
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};
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static const struct nvt_ts_mem_map NT36772_memory_map = {
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.EVENT_BUF_ADDR = 0x11E00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE0_Q_ADDR = 0,
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.RAW_PIPE1_ADDR = 0x12000,
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.RAW_PIPE1_Q_ADDR = 0,
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.BASELINE_ADDR = 0x10E70,
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.BASELINE_Q_ADDR = 0,
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.BASELINE_BTN_ADDR = 0x12E70,
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.BASELINE_BTN_Q_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x10830,
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.DIFF_PIPE0_Q_ADDR = 0,
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.DIFF_PIPE1_ADDR = 0x12830,
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.DIFF_PIPE1_Q_ADDR = 0,
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.RAW_BTN_PIPE0_ADDR = 0x10E60,
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.RAW_BTN_PIPE0_Q_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0x12E60,
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.RAW_BTN_PIPE1_Q_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0x10E68,
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.DIFF_BTN_PIPE0_Q_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0x12E68,
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.DIFF_BTN_PIPE1_Q_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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};
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static const struct nvt_ts_mem_map NT36525_memory_map = {
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.EVENT_BUF_ADDR = 0x11A00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE0_Q_ADDR = 0,
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.RAW_PIPE1_ADDR = 0x12000,
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.RAW_PIPE1_Q_ADDR = 0,
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.BASELINE_ADDR = 0x10B08,
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.BASELINE_Q_ADDR = 0,
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.BASELINE_BTN_ADDR = 0x12B08,
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.BASELINE_BTN_Q_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x1064C,
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.DIFF_PIPE0_Q_ADDR = 0,
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.DIFF_PIPE1_ADDR = 0x1264C,
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.DIFF_PIPE1_Q_ADDR = 0,
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.RAW_BTN_PIPE0_ADDR = 0x10634,
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.RAW_BTN_PIPE0_Q_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0x12634,
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.RAW_BTN_PIPE1_Q_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0x10AFC,
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.DIFF_BTN_PIPE0_Q_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0x12AFC,
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.DIFF_BTN_PIPE1_Q_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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};
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static const struct nvt_ts_mem_map NT36870_memory_map = {
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.EVENT_BUF_ADDR = 0x25000,
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.RAW_PIPE0_ADDR = 0x20000,
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.RAW_PIPE0_Q_ADDR = 0x204C8,
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.RAW_PIPE1_ADDR = 0x23000,
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.RAW_PIPE1_Q_ADDR = 0x234C8,
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.BASELINE_ADDR = 0x21350,
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.BASELINE_Q_ADDR = 0x21818,
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.BASELINE_BTN_ADDR = 0x24350,
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.BASELINE_BTN_Q_ADDR = 0x24358,
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.DIFF_PIPE0_ADDR = 0x209B0,
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.DIFF_PIPE0_Q_ADDR = 0x20E78,
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.DIFF_PIPE1_ADDR = 0x239B0,
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.DIFF_PIPE1_Q_ADDR = 0x23E78,
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.RAW_BTN_PIPE0_ADDR = 0x20990,
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.RAW_BTN_PIPE0_Q_ADDR = 0x20998,
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.RAW_BTN_PIPE1_ADDR = 0x23990,
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.RAW_BTN_PIPE1_Q_ADDR = 0x23998,
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.DIFF_BTN_PIPE0_ADDR = 0x21340,
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.DIFF_BTN_PIPE0_Q_ADDR = 0x21348,
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.DIFF_BTN_PIPE1_ADDR = 0x24340,
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.DIFF_BTN_PIPE1_Q_ADDR = 0x24348,
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.READ_FLASH_CHECKSUM_ADDR = 0x24000,
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.RW_FLASH_DATA_ADDR = 0x24002,
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};
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static const struct nvt_ts_mem_map NT36676F_memory_map = {
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.EVENT_BUF_ADDR = 0x11A00,
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.RAW_PIPE0_ADDR = 0x10000,
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.RAW_PIPE0_Q_ADDR = 0,
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.RAW_PIPE1_ADDR = 0x12000,
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.RAW_PIPE1_Q_ADDR = 0,
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.BASELINE_ADDR = 0x10B08,
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.BASELINE_Q_ADDR = 0,
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.BASELINE_BTN_ADDR = 0x12B08,
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.BASELINE_BTN_Q_ADDR = 0,
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.DIFF_PIPE0_ADDR = 0x1064C,
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.DIFF_PIPE0_Q_ADDR = 0,
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.DIFF_PIPE1_ADDR = 0x1264C,
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.DIFF_PIPE1_Q_ADDR = 0,
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.RAW_BTN_PIPE0_ADDR = 0x10634,
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.RAW_BTN_PIPE0_Q_ADDR = 0,
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.RAW_BTN_PIPE1_ADDR = 0x12634,
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.RAW_BTN_PIPE1_Q_ADDR = 0,
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.DIFF_BTN_PIPE0_ADDR = 0x10AFC,
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.DIFF_BTN_PIPE0_Q_ADDR = 0,
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.DIFF_BTN_PIPE1_ADDR = 0x12AFC,
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.DIFF_BTN_PIPE1_Q_ADDR = 0,
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.READ_FLASH_CHECKSUM_ADDR = 0x14000,
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.RW_FLASH_DATA_ADDR = 0x14002,
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};
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#define NVT_ID_BYTE_MAX 6
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struct nvt_ts_trim_id_table {
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uint8_t id[NVT_ID_BYTE_MAX];
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uint8_t mask[NVT_ID_BYTE_MAX];
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const struct nvt_ts_mem_map *mmap;
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uint8_t carrier_system;
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};
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static const struct nvt_ts_trim_id_table trim_id_table[] = {
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{.id = {0x0A, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {1, 0, 0, 1, 1, 1},
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.mmap = &NT36672A_memory_map, .carrier_system = 0},
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{.id = {0x55, 0x00, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0x55, 0x72, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xAA, 0x00, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xAA, 0x72, 0xFF, 0x00, 0x00, 0x00}, .mask = {1, 1, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x72, 0x67, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x70, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x70, 0x67, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x72, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36772_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x25, 0x65, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36525_memory_map, .carrier_system = 0},
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{.id = {0xFF, 0xFF, 0xFF, 0x70, 0x68, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36870_memory_map, .carrier_system = 1},
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{.id = {0xFF, 0xFF, 0xFF, 0x76, 0x66, 0x03}, .mask = {0, 0, 0, 1, 1, 1},
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.mmap = &NT36676F_memory_map, .carrier_system = 0}
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};
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