63 lines
1.9 KiB
C
63 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MTK_ADC_HW_H
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#define _MTK_ADC_HW_H
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extern void __iomem *auxadc_base;
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extern void __iomem *auxadc_apmix_base;
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extern void __iomem *auxadc_efuse_base;
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#undef AUXADC_BASE
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#undef APMIXED_BASE
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#undef EFUSEC_BASE
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#define AUXADC_BASE auxadc_base
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#define APMIXED_BASE auxadc_apmix_base
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#define EFUSEC_BASE auxadc_efuse_base
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/* For calibration */
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#define EFUSE_CALI
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#define AUXADC_INDEX 104
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#define ADC_GE_A_SHIFT 22
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#define ADC_GE_A_MASK (0x3ff << ADC_GE_A_SHIFT)
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#define ADC_OE_A_SHIFT 12
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#define ADC_OE_A_MASK (0x3ff << ADC_OE_A_SHIFT)
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#define ADC_CALI_EN_A_SHIFT 11
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#define ADC_CALI_EN_A_MASK (0x1 << ADC_CALI_EN_A_SHIFT)
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#define ADC_CALI_EN_A_REG (EFUSEC_BASE + 0x190)
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#define ADC_GE_A_REG (EFUSEC_BASE + 0x190)
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#define ADC_OE_A_REG (EFUSEC_BASE + 0x190)
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/************************/
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#define ADC_CHANNEL_MAX 16
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#define MT_PDN_PERI_AUXADC MT_CG_PERI_AUXADC
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#define AUXADC_NODE "mediatek,auxadc"
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#define AUXADC_APMIX_NODE "mediatek,apmixed"
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#define AUXADC_CON0 (AUXADC_BASE + 0x000)
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#define AUXADC_CON1 (AUXADC_BASE + 0x004)
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#define AUXADC_CON2 (AUXADC_BASE + 0x010)
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#define AUXADC_DAT0 (AUXADC_BASE + 0x014)
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#define AUXADC_TP_CMD (AUXADC_BASE + 0x005c)
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#define AUXADC_TP_ADDR (AUXADC_BASE + 0x0060)
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#define AUXADC_TP_CON0 (AUXADC_BASE + 0x0064)
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#define AUXADC_TP_DATA0 (AUXADC_BASE + 0x0074)
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#define AUXADC_DET_VOLT (AUXADC_BASE + 0x084)
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#define AUXADC_DET_SEL (AUXADC_BASE + 0x088)
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#define AUXADC_DET_PERIOD (AUXADC_BASE + 0x08C)
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#define AUXADC_DET_DEBT (AUXADC_BASE + 0x090)
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#define PAD_AUX_XP 13
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#define PAD_AUX_YM 15
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#define TP_CMD_ADDR_X 0x0005
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#define AUXADC_CON_RTP (APMIXED_BASE + 0x0404)
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#define AUXADC_CLOCK_BY_SPM
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#endif /*_MTK_ADC_HW_H*/
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