219 lines
11 KiB
C
219 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016 MediaTek Inc.
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*/
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#ifndef __pcm_def_h__
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#define __pcm_def_h__
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/*
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* Auto generated by DE, please DO NOT modify this file directly.
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*/
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/* --- R0 Define --- */
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#define R0_SC_26M_CK_OFF (1U << 0)
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#define R0_SC_MCUPM_MCUSYS_REQ (1U << 1)
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#define R0_SC_MEM_CK_OFF (1U << 2)
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#define R0_SC_AXI_CK_OFF (1U << 3)
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#define R0_SC_DR_GATE_RETRY_EN_PCM (1U << 4)
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#define R0_SC_MD26M_CK_OFF (1U << 5)
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#define R0_SC_DPY_MODE_SW_PCM (1U << 6)
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#define R0_SC_DMSUS_OFF_PCM (1U << 7)
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#define R0_SC_DPY_2ND_DLL_EN_PCM (1U << 8)
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#define R0_SC_SW_WDT_TIMER_RST (1U << 9)
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#define R0_SC_MPLLOUT_OFF (1U << 10)
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#define R0_SC_TX_TRACKING_DIS (1U << 11)
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#define R0_SC_DPY_DLL_EN_PCM (1U << 12)
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#define R0_SC_DPY_DLL_CK_EN_PCM (1U << 13)
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#define R0_SC_DPY_VREF_EN_PCM (1U << 14)
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#define R0_SC_PHYPLL_EN_PCM (1U << 15)
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#define R0_SC_DDRPHY_FB_CK_EN_PCM (1U << 16)
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#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
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#define R0_SC_MPLL_OFF (1U << 18)
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#define R0_SC_SHU_RESTORE (1U << 19)
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#define R0_SC_CKSQ0_OFF (1U << 20)
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#define R0_SC_CKSQ1_OFF (1U << 21)
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#define R0_SC_DR_SHU_EN_PCM (1U << 22)
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#define R0_SC_DPHY_PRECAL_UP (1U << 23)
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#define R0_SC_MPLL_S_OFF (1U << 24)
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#define R0_SC_DPHY_RXDLY_TRACK_EN (1U << 25)
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#define R0_SC_PHYPLL_SHU_EN_PCM (1U << 26)
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#define R0_SC_PHYPLL2_SHU_EN_PCM (1U << 27)
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#define R0_SC_PHYPLL_MODE_SW_PCM (1U << 28)
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#define R0_SC_PHYPLL2_MODE_SW_PCM (1U << 29)
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#define R0_SC_DR_SHU_LEVEL_PCM0 (1U << 30)
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#define R0_SC_DR_SHU_LEVEL_PCM1 (1U << 31)
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/* --- R7 Define --- */
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#define R7_PWRAP_SLEEP_REQ (1U << 0)
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#define R7_EMI_CLK_OFF_REQ (1U << 1)
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#define R7_TOP_MAS_PAU_REQ (1U << 2)
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#define R7_INTERNAL_CONN_DDREN_ACK (1U << 3)
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#define R7_PCM_CK_SEL0 (1U << 4)
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#define R7_PCM_CK_SEL1 (1U << 5)
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#define R7_SPM2RC_DVS_DONE (1U << 6)
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#define R7_FREQH_PAUSE_MPLL (1U << 7)
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#define R7_SC_26M_CK_SEL (1U << 8)
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#define R7_PCM_TIMER_SET (1U << 9)
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#define R7_PCM_TIMER_CLR (1U << 10)
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#define R7_SRCVOLTEN (1U << 11)
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#define R7_CSYSPWRUPACK (1U << 12)
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#define R7_IM_SLEEP_ENABLE (1U << 13)
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#define R7_SRCCLKENO_0 (1U << 14)
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#define R7_SYSRST (1U << 15)
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#define R7_MD_APSRC_ACK (1U << 16)
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#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
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#define R7_SC_AXI_DCM_DIS (1U << 18)
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#define R7_FREQH_PAUSE_MAIN (1U << 19)
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#define R7_FREQH_PAUSE_MEM (1U << 20)
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#define R7_SRCCLKENO_1 (1U << 21)
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#define R7_WDT_KICK_P (1U << 22)
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#define R7_INTERNAL_CONN_DDREN_2_ACK (1U << 23)
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#define R7_WAKEUP_EXT_W_SEL (1U << 24)
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#define R7_WAKEUP_EXT_R_SEL (1U << 25)
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#define R7_PMIC_IRQ_REQ_EN (1U << 26)
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#define R7_FORCE_26M_WAKE (1U << 27)
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#define R7_FORCE_APSRC_WAKE (1U << 28)
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#define R7_FORCE_INFRA_WAKE (1U << 29)
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#define R7_FORCE_VRF18_WAKE (1U << 30)
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#define R7_SC_DR_SHORT_QUEUE_PCM (1U << 31)
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/* --- R12 Define --- */
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#define R12_PCM_TIMER (1U << 0)
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#define R12_SSPM_WDT_EVENT_B (1U << 1)
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#define R12_KP_IRQ_B (1U << 2)
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#define R12_APWDT_EVENT_B (1U << 3)
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#define R12_APXGPT1_EVENT_B (1U << 4)
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#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
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#define R12_EINT_EVENT_B (1U << 6)
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#define R12_CONN_WDT_IRQ_B (1U << 7)
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#define R12_CCIF0_EVENT_B (1U << 8)
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#define R12_LOWBATTERY_IRQ_B (1U << 9)
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#define R12_SSPM_SPM_IRQ_B (1U << 10)
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#define R12_SCP_SPM_IRQ_B (1U << 11)
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#define R12_SCP_WDT_EVENT_B (1U << 12)
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#define R12_PCM_WDT_WAKEUP_B (1U << 13)
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#define R12_USB_CDSC_B (1U << 14)
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#define R12_USB_POWERDWN_B (1U << 15)
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#define R12_SYS_TIMER_EVENT_B (1U << 16)
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#define R12_EINT_EVENT_SECURE_B (1U << 17)
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#define R12_CCIF1_EVENT_B (1U << 18)
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#define R12_UART0_IRQ_B (1U << 19)
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#define R12_AFE_IRQ_MCU_B (1U << 20)
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#define R12_THERM_CTRL_EVENT_B (1U << 21)
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#define R12_SYS_CIRQ_IRQ_B (1U << 22)
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#define R12_MD2AP_PEER_EVENT_B (1U << 23)
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#define R12_CSYSPWREQ_B (1U << 24)
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#define R12_MD1_WDT_B (1U << 25)
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#define R12_CLDMA_EVENT_B (1U << 26)
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#define R12_SEJ_WDT_GPT_B (1U << 27)
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#define R12_ALL_SSPM_WAKEUP_B (1U << 28)
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#define R12_CPU_IRQ_B (1U << 29)
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#define R12_CPU_WFI_AND_B (1U << 30)
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#define R12_MCUSYS_IDLE_TO_EMI_ALL_B (1U << 31)
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/* --- R12ext Define --- */
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#define R12EXT_26M_WAKE (1U << 0)
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#define R12EXT_26M_SLEEP (1U << 1)
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#define R12EXT_INFRA_WAKE (1U << 2)
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#define R12EXT_INFRA_SLEEP (1U << 3)
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#define R12EXT_APSRC_WAKE (1U << 4)
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#define R12EXT_APSRC_SLEEP (1U << 5)
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#define R12EXT_VRF18_WAKE (1U << 6)
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#define R12EXT_VRF18_SLEEP (1U << 7)
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#define R12EXT_DVFS_ALL_STATE (1U << 8)
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#define R12EXT_DVFS_LEVEL_STATE0 (1U << 9)
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#define R12EXT_DVFS_LEVEL_STATE1 (1U << 10)
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#define R12EXT_DVFS_LEVEL_STATE2 (1U << 11)
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#define R12EXT_DDREN_WAKE (1U << 12)
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#define R12EXT_DDREN_SLEEP (1U << 13)
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#define R12EXT_NFC_CLK_BUF_WAKE (1U << 14)
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#define R12EXT_NFC_CLK_BUF_SLEEP (1U << 15)
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#define R12EXT_CONN_CLK_BUF_WAKE (1U << 16)
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#define R12EXT_CONN_CLK_BUF_SLEEP (1U << 17)
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#define R12EXT_MD_DVFS_ERROR_STATUS (1U << 18)
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#define R12EXT_DVFS_LEVEL_STATE3 (1U << 19)
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#define R12EXT_DVFS_LEVEL_STATE4 (1U << 20)
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#define R12EXT_DVFS_LEVEL_STATE5 (1U << 21)
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#define R12EXT_DVFS_LEVEL_STATE6 (1U << 22)
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#define R12EXT_DVFS_LEVEL_STATE7 (1U << 23)
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#define R12EXT_DVFS_LEVEL_STATE8 (1U << 24)
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#define R12EXT_DVFS_LEVEL_STATE9 (1U << 25)
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#define R12EXT_DVFS_LEVEL_STATE_G0 (1U << 26)
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#define R12EXT_DVFS_LEVEL_STATE_G1 (1U << 27)
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#define R12EXT_DVFS_LEVEL_STATE_G2 (1U << 28)
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#define R12EXT_DVFS_LEVEL_STATE_G3 (1U << 29)
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#define R12EXT_HYBRID_DDREN_SLEEP (1U << 30)
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#define R12EXT_HYBRID_DDREN_WAKE (1U << 31)
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/* --- R13 Define --- */
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#define R13_EXT_SRCCLKENI_0 (1U << 0)
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#define R13_EXT_SRCCLKENI_1 (1U << 1)
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#define R13_MD1_SRCCLKENA (1U << 2)
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#define R13_MD1_APSRC_REQ (1U << 3)
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#define R13_CONN_DDR_EN (1U << 4)
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#define R13_MD2_SRCCLKENA (1U << 5)
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#define R13_SSPM_SRCCLKENA (1U << 6)
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#define R13_SSPM_APSRC_REQ (1U << 7)
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#define R13_MD_STATE (1U << 8)
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#define R13_EMI_CLK_OFF_2_ACK (1U << 9)
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#define R13_MM_STATE (1U << 10)
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#define R13_SSPM_STATE (1U << 11)
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#define R13_MD_DDR_EN (1U << 12)
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#define R13_CONN_STATE (1U << 13)
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#define R13_CONN_SRCCLKENA (1U << 14)
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#define R13_CONN_APSRC_REQ (1U << 15)
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#define R13_SLEEP_EVENT_STA (1U << 16)
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#define R13_WAKE_EVENT_STA (1U << 17)
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#define R13_EMI_IDLE (1U << 18)
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#define R13_CSYSPWRUPREQ (1U << 19)
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#define R13_PWRAP_SLEEP_ACK (1U << 20)
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#define R13_EMI_CLK_OFF_ACK_ALL (1U << 21)
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#define R13_TOP_MAS_PAU_ACK (1U << 22)
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#define R13_SW_DMDRAMCSHU_ACK_ALL (1U << 23)
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#define R13_MCU_STATE (1U << 24)
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#define R13_DR_SHORT_QUEUE_ACK_ALL (1U << 25)
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#define R13_INFRA_AUX_IDLE (1U << 26)
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#define R13_DVFS_ALL_STATE (1U << 27)
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#define R13_RC2SPM_EVENT_ABORT_OR (1U << 28)
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#define R13_DRAMC_SPCMD_APSRC_REQ (1U << 29)
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#define R13_MD1_VRF18_REQ (1U << 30)
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#define R13_DDREN_STATE (1U << 31)
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enum SPM_WAKE_SRC_LIST {
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WAKE_SRC_R12_PCM_TIMER = (1U << 0),
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WAKE_SRC_R12_SSPM_WDT_EVENT_B = (1U << 1),
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WAKE_SRC_R12_KP_IRQ_B = (1U << 2),
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WAKE_SRC_R12_APWDT_EVENT_B = (1U << 3),
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WAKE_SRC_R12_APXGPT1_EVENT_B = (1U << 4),
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WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B = (1U << 5),
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WAKE_SRC_R12_EINT_EVENT_B = (1U << 6),
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WAKE_SRC_R12_CONN_WDT_IRQ_B = (1U << 7),
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WAKE_SRC_R12_CCIF0_EVENT_B = (1U << 8),
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WAKE_SRC_R12_LOWBATTERY_IRQ_B = (1U << 9),
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WAKE_SRC_R12_SSPM_SPM_IRQ_B = (1U << 10),
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WAKE_SRC_R12_SCP_SPM_IRQ_B = (1U << 11),
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WAKE_SRC_R12_SCP_WDT_EVENT_B = (1U << 12),
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WAKE_SRC_R12_PCM_WDT_WAKEUP_B = (1U << 13),
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WAKE_SRC_R12_USB_CDSC_B = (1U << 14),
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WAKE_SRC_R12_USB_POWERDWN_B = (1U << 15),
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WAKE_SRC_R12_SYS_TIMER_EVENT_B = (1U << 16),
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WAKE_SRC_R12_EINT_EVENT_SECURE_B = (1U << 17),
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WAKE_SRC_R12_CCIF1_EVENT_B = (1U << 18),
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WAKE_SRC_R12_UART0_IRQ_B = (1U << 19),
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WAKE_SRC_R12_AFE_IRQ_MCU_B = (1U << 20),
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WAKE_SRC_R12_THERM_CTRL_EVENT_B = (1U << 21),
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WAKE_SRC_R12_SYS_CIRQ_IRQ_B = (1U << 22),
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WAKE_SRC_R12_MD2AP_PEER_EVENT_B = (1U << 23),
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WAKE_SRC_R12_CSYSPWREQ_B = (1U << 24),
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WAKE_SRC_R12_MD1_WDT_B = (1U << 25),
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WAKE_SRC_R12_CLDMA_EVENT_B = (1U << 26),
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WAKE_SRC_R12_SEJ_WDT_GPT_B = (1U << 27),
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WAKE_SRC_R12_ALL_SSPM_WAKEUP_B = (1U << 28),
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WAKE_SRC_R12_CPU_IRQ_B = (1U << 29),
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WAKE_SRC_R12_CPU_WFI_AND_B = (1U << 30),
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WAKE_SRC_R12_MCUSYS_IDLE_TO_EMI_ALL_B = (1U << 31)
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};
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extern const char *wakesrc_str[32];
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/* define WAKE_SRC_CONN2AP for conn use */
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#define WAKE_SRC_CONN2AP WAKE_SRC_R12_CONN2AP_SPM_WAKEUP_B
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#endif /* __pcm_def_h__ */
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