282 lines
6.1 KiB
C
282 lines
6.1 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __PWR_CTRL_H__
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#define __PWR_CTRL_H__
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/* SPM_WAKEUP_MISC */
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#define WAKE_MISC_TWAM (1U << 18)
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#define WAKE_MISC_PCM_TIMER (1U << 19)
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#define WAKE_MISC_CPU_WAKE (1U << 20)
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struct pwr_ctrl {
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/* for SPM */
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u32 pcm_flags;
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u32 pcm_flags_cust;
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u32 pcm_flags_cust_set;
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u32 pcm_flags_cust_clr;
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u32 pcm_flags1;
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u32 pcm_flags1_cust;
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u32 pcm_flags1_cust_set;
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u32 pcm_flags1_cust_clr;
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u32 timer_val;
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u32 timer_val_cust;
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u32 timer_val_ramp_en;
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u32 timer_val_ramp_en_sec;
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u32 wake_src;
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u32 wake_src_cust;
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u32 wakelock_timer_val;
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u8 wdt_disable;
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/* Auto-gen Start */
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/* SPM_AP_STANDBY_CON */
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u8 wfi_op;
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u8 wfi_type;
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u8 mp0_cputop_idle_mask;
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u8 mp1_cputop_idle_mask;
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u8 mcusys_idle_mask;
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u8 mm_mask_b;
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u8 md_ddr_en_0_dbc_en;
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u8 md_ddr_en_1_dbc_en;
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u8 md_mask_b;
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u8 sspm_mask_b;
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u8 scp_mask_b;
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u8 srcclkeni_mask_b;
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u8 md_apsrc_1_sel;
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u8 md_apsrc_0_sel;
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u8 conn_ddr_en_dbc_en;
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u8 conn_mask_b;
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u8 conn_apsrc_sel;
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u8 conn_srcclkena_sel_mask;
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/* SPM_SRC_REQ */
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u8 spm_apsrc_req;
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u8 spm_f26m_req;
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u8 spm_infra_req;
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u8 spm_vrf18_req;
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u8 spm_ddren_req;
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u8 spm_rsv_src_req;
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u8 spm_ddren_2_req;
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u8 cpu_md_dvfs_sop_force_on;
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/* SPM_SRC_MASK */
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u8 csyspwreq_mask;
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u8 ccif0_md_event_mask_b;
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u8 ccif0_ap_event_mask_b;
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u8 ccif1_md_event_mask_b;
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u8 ccif1_ap_event_mask_b;
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u8 ccif2_md_event_mask_b;
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u8 ccif2_ap_event_mask_b;
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u8 ccif3_md_event_mask_b;
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u8 ccif3_ap_event_mask_b;
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u8 md_srcclkena_0_infra_mask_b;
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u8 md_srcclkena_1_infra_mask_b;
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u8 conn_srcclkena_infra_mask_b;
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u8 ufs_infra_req_mask_b;
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u8 srcclkeni_infra_mask_b;
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u8 md_apsrc_req_0_infra_mask_b;
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u8 md_apsrc_req_1_infra_mask_b;
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u8 conn_apsrcreq_infra_mask_b;
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u8 ufs_srcclkena_mask_b;
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u8 md_vrf18_req_0_mask_b;
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u8 md_vrf18_req_1_mask_b;
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u8 ufs_vrf18_req_mask_b;
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u8 gce_vrf18_req_mask_b;
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u8 conn_infra_req_mask_b;
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u8 gce_apsrc_req_mask_b;
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u8 disp0_apsrc_req_mask_b;
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u8 disp1_apsrc_req_mask_b;
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u8 mfg_req_mask_b;
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u8 vdec_req_mask_b;
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u8 mcu_apsrcreq_infra_mask_b;
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/* SPM_SRC2_MASK */
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u8 md_ddr_en_0_mask_b;
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u8 md_ddr_en_1_mask_b;
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u8 conn_ddr_en_mask_b;
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u8 ddren_sspm_apsrc_req_mask_b;
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u8 ddren_scp_apsrc_req_mask_b;
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u8 disp0_ddren_mask_b;
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u8 disp1_ddren_mask_b;
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u8 gce_ddren_mask_b;
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u8 ddren_emi_self_refresh_ch0_mask_b;
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u8 ddren_emi_self_refresh_ch1_mask_b;
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u8 mcu_apsrc_req_mask_b;
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u8 mcu_ddren_mask_b;
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/* SPM_WAKEUP_EVENT_MASK */
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u32 spm_wakeup_event_mask;
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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u32 spm_wakeup_event_ext_mask;
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/* SPM_SRC3_MASK */
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u8 md_ddr_en_2_0_mask_b;
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u8 md_ddr_en_2_1_mask_b;
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u8 conn_ddr_en_2_mask_b;
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u8 ddren2_sspm_apsrc_req_mask_b;
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u8 ddren2_scp_apsrc_req_mask_b;
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u8 disp0_ddren2_mask_b;
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u8 disp1_ddren2_mask_b;
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u8 gce_ddren2_mask_b;
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u8 ddren2_emi_self_refresh_ch0_mask_b;
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u8 ddren2_emi_self_refresh_ch1_mask_b;
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u8 mcu_ddren_2_mask_b;
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/* MP0_CPU0_WFI_EN */
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u8 mp0_cpu0_wfi_en;
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/* MP0_CPU1_WFI_EN */
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u8 mp0_cpu1_wfi_en;
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/* MP0_CPU2_WFI_EN */
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u8 mp0_cpu2_wfi_en;
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/* MP0_CPU3_WFI_EN */
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u8 mp0_cpu3_wfi_en;
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/* MP0_CPU4_WFI_EN */
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u8 mp0_cpu4_wfi_en;
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/* MP0_CPU5_WFI_EN */
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u8 mp0_cpu5_wfi_en;
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/* MP0_CPU6_WFI_EN */
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u8 mp0_cpu6_wfi_en;
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/* MP0_CPU7_WFI_EN */
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u8 mp0_cpu7_wfi_en;
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/* Auto-gen End */
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};
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/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
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enum pwr_ctrl_enum {
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PW_PCM_FLAGS,
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PW_PCM_FLAGS_CUST,
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PW_PCM_FLAGS_CUST_SET,
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PW_PCM_FLAGS_CUST_CLR,
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PW_PCM_FLAGS1,
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PW_PCM_FLAGS1_CUST,
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PW_PCM_FLAGS1_CUST_SET,
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PW_PCM_FLAGS1_CUST_CLR,
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PW_TIMER_VAL,
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PW_TIMER_VAL_CUST,
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PW_TIMER_VAL_RAMP_EN,
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PW_TIMER_VAL_RAMP_EN_SEC,
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PW_WAKE_SRC,
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PW_WAKE_SRC_CUST,
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PW_WAKELOCK_TIMER_VAL,
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PW_WDT_DISABLE,
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/* SPM_AP_STANDBY_CON */
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PW_WFI_OP,
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PW_WFI_TYPE,
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PW_MP0_CPUTOP_IDLE_MASK,
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PW_MP1_CPUTOP_IDLE_MASK,
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PW_MCUSYS_IDLE_MASK,
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PW_MM_MASK_B,
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PW_MD_DDR_EN_0_DBC_EN,
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PW_MD_DDR_EN_1_DBC_EN,
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PW_MD_MASK_B,
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PW_SSPM_MASK_B,
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PW_SCP_MASK_B,
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PW_SRCCLKENI_MASK_B,
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PW_MD_APSRC_1_SEL,
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PW_MD_APSRC_0_SEL,
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PW_CONN_DDR_EN_DBC_EN,
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PW_CONN_MASK_B,
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PW_CONN_APSRC_SEL,
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PW_CONN_SRCCLKENA_SEL_MASK,
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/* SPM_SRC_REQ */
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PW_SPM_APSRC_REQ,
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PW_SPM_F26M_REQ,
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PW_SPM_INFRA_REQ,
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PW_SPM_VRF18_REQ,
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PW_SPM_DDREN_REQ,
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PW_SPM_RSV_SRC_REQ,
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PW_SPM_DDREN_2_REQ,
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PW_CPU_MD_DVFS_SOP_FORCE_ON,
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/* SPM_SRC_MASK */
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PW_CSYSPWREQ_MASK,
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PW_CCIF0_MD_EVENT_MASK_B,
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PW_CCIF0_AP_EVENT_MASK_B,
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PW_CCIF1_MD_EVENT_MASK_B,
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PW_CCIF1_AP_EVENT_MASK_B,
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PW_CCIF2_MD_EVENT_MASK_B,
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PW_CCIF2_AP_EVENT_MASK_B,
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PW_CCIF3_MD_EVENT_MASK_B,
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PW_CCIF3_AP_EVENT_MASK_B,
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PW_MD_SRCCLKENA_0_INFRA_MASK_B,
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PW_MD_SRCCLKENA_1_INFRA_MASK_B,
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PW_CONN_SRCCLKENA_INFRA_MASK_B,
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PW_UFS_INFRA_REQ_MASK_B,
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PW_SRCCLKENI_INFRA_MASK_B,
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PW_MD_APSRC_REQ_0_INFRA_MASK_B,
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PW_MD_APSRC_REQ_1_INFRA_MASK_B,
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PW_CONN_APSRCREQ_INFRA_MASK_B,
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PW_UFS_SRCCLKENA_MASK_B,
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PW_MD_VRF18_REQ_0_MASK_B,
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PW_MD_VRF18_REQ_1_MASK_B,
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PW_UFS_VRF18_REQ_MASK_B,
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PW_GCE_VRF18_REQ_MASK_B,
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PW_CONN_INFRA_REQ_MASK_B,
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PW_GCE_APSRC_REQ_MASK_B,
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PW_DISP0_APSRC_REQ_MASK_B,
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PW_DISP1_APSRC_REQ_MASK_B,
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PW_MFG_REQ_MASK_B,
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PW_VDEC_REQ_MASK_B,
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PW_MCU_APSRCREQ_INFRA_MASK_B,
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/* SPM_SRC2_MASK */
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PW_MD_DDR_EN_0_MASK_B,
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PW_MD_DDR_EN_1_MASK_B,
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PW_CONN_DDR_EN_MASK_B,
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PW_DDREN_SSPM_APSRC_REQ_MASK_B,
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PW_DDREN_SCP_APSRC_REQ_MASK_B,
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PW_DISP0_DDREN_MASK_B,
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PW_DISP1_DDREN_MASK_B,
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PW_GCE_DDREN_MASK_B,
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PW_DDREN_EMI_SELF_REFRESH_CH0_MASK_B,
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PW_DDREN_EMI_SELF_REFRESH_CH1_MASK_B,
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PW_MCU_APSRC_REQ_MASK_B,
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PW_MCU_DDREN_MASK_B,
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/* SPM_WAKEUP_EVENT_MASK */
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PW_SPM_WAKEUP_EVENT_MASK,
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/* SPM_WAKEUP_EVENT_EXT_MASK */
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PW_SPM_WAKEUP_EVENT_EXT_MASK,
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/* SPM_SRC3_MASK */
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PW_MD_DDR_EN_2_0_MASK_B,
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PW_MD_DDR_EN_2_1_MASK_B,
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PW_CONN_DDR_EN_2_MASK_B,
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PW_DDREN2_SSPM_APSRC_REQ_MASK_B,
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PW_DDREN2_SCP_APSRC_REQ_MASK_B,
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PW_DISP0_DDREN2_MASK_B,
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PW_DISP1_DDREN2_MASK_B,
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PW_GCE_DDREN2_MASK_B,
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PW_DDREN2_EMI_SELF_REFRESH_CH0_MASK_B,
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PW_DDREN2_EMI_SELF_REFRESH_CH1_MASK_B,
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PW_MCU_DDREN_2_MASK_B,
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/* MP0_CPU0_WFI_EN */
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PW_MP0_CPU0_WFI_EN,
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/* MP0_CPU1_WFI_EN */
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PW_MP0_CPU1_WFI_EN,
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/* MP0_CPU2_WFI_EN */
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PW_MP0_CPU2_WFI_EN,
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/* MP0_CPU3_WFI_EN */
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PW_MP0_CPU3_WFI_EN,
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/* MP0_CPU4_WFI_EN */
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PW_MP0_CPU4_WFI_EN,
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/* MP0_CPU5_WFI_EN */
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PW_MP0_CPU5_WFI_EN,
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/* MP0_CPU6_WFI_EN */
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PW_MP0_CPU6_WFI_EN,
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/* MP0_CPU7_WFI_EN */
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PW_MP0_CPU7_WFI_EN,
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PW_MAX_COUNT,
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};
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#endif /* __PWR_CTRL_H__ */
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