384 lines
11 KiB
C
384 lines
11 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef _MT_DPE_H
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#define _MT_DPE_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/*
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* enforce kernel log enable
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*/
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_DPE_FRAME_REQUEST_ 6
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#define _SUPPORT_MAX_DPE_REQUEST_RING_SIZE_ 4
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/*
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*
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*/
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#define DPE_DEV_MAJOR_NUMBER 302
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#define DPE_MAGIC 'd'
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#define DPE_REG_RANGE (0x1000)
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#define DPE_BASE_HW 0x1B100000
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/*This macro is for setting irq status represnted
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* by a local variable,DPEInfo.IrqInfo.Status[DPE_IRQ_TYPE_INT_DPE_ST]
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*/
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#define DPE_INT_ST (1UL<<31)
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struct DPE_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct DPE_REG_IO_STRUCT {
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struct DPE_REG_STRUCT *pData; /* pointer to DPE_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/*
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* interrupt clear type
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*/
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enum DPE_IRQ_CLEAR_ENUM {
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DPE_IRQ_CLEAR_NONE, /* non-clear wait, clear after wait */
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DPE_IRQ_CLEAR_WAIT, /* clear wait, clear before and after wait */
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DPE_IRQ_WAIT_CLEAR,
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/* wait the signal and clear it, avoid hw executime is too s hort. */
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DPE_IRQ_CLEAR_STATUS, /* clear specific status only */
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DPE_IRQ_CLEAR_ALL /* clear all status */
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};
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/*
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum DPE_IRQ_TYPE_ENUM {
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DPE_IRQ_TYPE_INT_DVP_ST, /* DVP */
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DPE_IRQ_TYPE_INT_DVS_ST, /* DVS */
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DPE_IRQ_TYPE_AMOUNT
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};
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struct DPE_WAIT_IRQ_STRUCT {
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enum DPE_IRQ_CLEAR_ENUM Clear;
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enum DPE_IRQ_TYPE_ENUM Type;
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unsigned int Status; /*IRQ Status */
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unsigned int Timeout;
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int UserKey; /* user key for doing interrupt operation */
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int ProcessID; /* user ProcessID (will filled in kernel) */
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unsigned int bDumpReg; /* check dump register or not */
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};
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struct DPE_CLEAR_IRQ_STRUCT {
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enum DPE_IRQ_TYPE_ENUM Type;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status; /* Input */
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};
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struct DPE_Config {
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unsigned int DVS_CTRL00;
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unsigned int DVS_CTRL01;
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unsigned int DVS_CTRL02;
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unsigned int DVS_CTRL03;
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unsigned int DVS_CTRL04;
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unsigned int DVS_CTRL05;
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unsigned int DVS_CTRL06;
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unsigned int DVS_CTRL07;
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unsigned int DVS_OCC_PQ_0;
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unsigned int DVS_OCC_PQ_1;
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unsigned int DVS_OCC_ATPG;
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unsigned int DVS_IRQ_00;
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unsigned int DVS_CTRL_STATUS0;
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unsigned int DVS_CTRL_STATUS1;
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unsigned int DVS_CTRL_STATUS2;
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unsigned int DVS_IRQ_STATUS;
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unsigned int DVS_FRM_STATUS0;
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unsigned int DVS_FRM_STATUS1;
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unsigned int DVS_FRM_STATUS2;
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unsigned int DVS_FRM_STATUS3;
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unsigned int DVS_CUR_STATUS;
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unsigned int DVS_SRC_CTRL;
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unsigned int DVS_CRC_CTRL;
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unsigned int DVS_CRC_IN;
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unsigned int DVS_DRAM_STA0;
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unsigned int DVS_DRAM_STA1;
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unsigned int DVS_DRAM_ULT;
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unsigned int DVS_DRAM_PITCH;
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unsigned int DVS_SRC_00;
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unsigned int DVS_SRC_01;
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unsigned int DVS_SRC_02;
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unsigned int DVS_SRC_03;
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unsigned int DVS_SRC_04;
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unsigned int DVS_SRC_05_L_FRM0;
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unsigned int DVS_SRC_06_L_FRM1;
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unsigned int DVS_SRC_07_L_FRM2;
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unsigned int DVS_SRC_08_L_FRM3;
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unsigned int DVS_SRC_09_R_FRM0;
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unsigned int DVS_SRC_10_R_FRM1;
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unsigned int DVS_SRC_11_R_FRM2;
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unsigned int DVS_SRC_12_R_FRM3;
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unsigned int DVS_SRC_13_L_VMAP0;
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unsigned int DVS_SRC_14_L_VMAP1;
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unsigned int DVS_SRC_15_L_VMAP2;
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unsigned int DVS_SRC_16_L_VMAP3;
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unsigned int DVS_SRC_17_R_VMAP0;
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unsigned int DVS_SRC_18_R_VMAP1;
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unsigned int DVS_SRC_19_R_VMAP2;
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unsigned int DVS_SRC_20_R_VMAP3;
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unsigned int DVS_SRC_21_INTER_MEDV;
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unsigned int DVS_SRC_22_MEDV0;
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unsigned int DVS_SRC_23_MEDV1;
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unsigned int DVS_SRC_24_MEDV2;
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unsigned int DVS_SRC_25_MEDV3;
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unsigned int DVS_SRC_26_OCCDV0;
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unsigned int DVS_SRC_27_OCCDV1;
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unsigned int DVS_SRC_28_OCCDV2;
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unsigned int DVS_SRC_29_OCCDV3;
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unsigned int DVS_SRC_30_DCV_CONF0;
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unsigned int DVS_SRC_31_DCV_CONF1;
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unsigned int DVS_SRC_32_DCV_CONF2;
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unsigned int DVS_SRC_33_DCV_CONF3;
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unsigned int DVS_SRC_34_DCV_L_FRM0;
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unsigned int DVS_SRC_35_DCV_L_FRM1;
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unsigned int DVS_SRC_36_DCV_L_FRM2;
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unsigned int DVS_SRC_37_DCV_L_FRM3;
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unsigned int DVS_SRC_38_DCV_R_FRM0;
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unsigned int DVS_SRC_39_DCV_R_FRM1;
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unsigned int DVS_SRC_40_DCV_R_FRM2;
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unsigned int DVS_SRC_41_DCV_R_FRM3;
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unsigned int DVS_SRC_42_OCCDV_EXT0;
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unsigned int DVS_SRC_43_OCCDV_EXT1;
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unsigned int DVS_SRC_44_OCCDV_EXT2;
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unsigned int DVS_SRC_45_OCCDV_EXT3;
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unsigned int DVS_CRC_OUT_0;
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unsigned int DVS_CRC_OUT_1;
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unsigned int DVS_CRC_OUT_2;
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unsigned int DVS_CRC_OUT_3;
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unsigned int DVS_CTRL_RESERVED;
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unsigned int DVS_CTRL_ATPG;
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unsigned int DVS_ME_00;
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unsigned int DVS_ME_01;
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unsigned int DVS_ME_02;
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unsigned int DVS_ME_03;
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unsigned int DVS_ME_04;
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unsigned int DVS_ME_05;
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unsigned int DVS_ME_06;
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unsigned int DVS_ME_07;
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unsigned int DVS_ME_08;
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unsigned int DVS_ME_09;
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unsigned int DVS_ME_10;
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unsigned int DVS_ME_11;
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unsigned int DVS_ME_12;
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unsigned int DVS_ME_13;
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unsigned int DVS_ME_14;
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unsigned int DVS_ME_15;
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unsigned int DVS_ME_16;
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unsigned int DVS_ME_17;
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unsigned int DVS_ME_18;
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unsigned int DVS_ME_19;
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unsigned int DVS_ME_20;
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unsigned int DVS_ME_21;
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unsigned int DVS_ME_22;
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unsigned int DVS_ME_23;
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unsigned int DVS_ME_24;
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unsigned int DVS_ME_25;
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unsigned int DVS_ME_26;
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unsigned int DVS_ME_27;
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unsigned int DVS_ME_28;
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unsigned int DVS_ME_29;
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unsigned int DVS_ME_30;
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unsigned int DVS_ME_31;
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unsigned int DVS_ME_32;
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unsigned int DVS_ME_33;
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unsigned int DVS_ME_34;
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unsigned int DVS_ME_35;
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unsigned int DVS_ME_36;
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unsigned int DVS_STATUS_00;
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unsigned int DVS_STATUS_01;
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unsigned int DVS_STATUS_02;
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unsigned int DVS_STATUS_03;
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unsigned int DVS_DEBUG;
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unsigned int DVS_ME_RESERVED;
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unsigned int DVS_ME_ATPG;
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unsigned int DVP_CTRL00;
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unsigned int DVP_CTRL01;
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unsigned int DVP_CTRL02;
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unsigned int DVP_CTRL03;
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unsigned int DVP_CTRL04;
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unsigned int DVP_CTRL05;
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unsigned int DVP_CTRL06;
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unsigned int DVP_CTRL07;
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unsigned int DVP_IRQ_00;
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unsigned int DVP_CTRL_STATUS0;
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unsigned int DVP_CTRL_STATUS1;
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unsigned int DVP_CTRL_STATUS2;
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unsigned int DVP_IRQ_STATUS;
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unsigned int DVP_FRM_STATUS0;
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unsigned int DVP_FRM_STATUS1;
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unsigned int DVP_FRM_STATUS2;
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unsigned int DVP_FRM_STATUS3;
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unsigned int DVP_CUR_STATUS;
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unsigned int DVP_SRC_00;
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unsigned int DVP_SRC_01;
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unsigned int DVP_SRC_02;
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unsigned int DVP_SRC_03;
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unsigned int DVP_SRC_04;
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unsigned int DVP_SRC_05_Y_FRM0;
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unsigned int DVP_SRC_06_Y_FRM1;
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unsigned int DVP_SRC_07_Y_FRM2;
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unsigned int DVP_SRC_08_Y_FRM3;
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unsigned int DVP_SRC_09_C_FRM0;
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unsigned int DVP_SRC_10_C_FRM1;
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unsigned int DVP_SRC_11_C_FRM2;
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unsigned int DVP_SRC_12_C_FRM3;
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unsigned int DVP_SRC_13_OCCDV0;
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unsigned int DVP_SRC_14_OCCDV1;
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unsigned int DVP_SRC_15_OCCDV2;
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unsigned int DVP_SRC_16_OCCDV3;
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unsigned int DVP_SRC_17_CRM;
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unsigned int DVP_SRC_18_ASF_RMDV;
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unsigned int DVP_SRC_19_ASF_RDDV;
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unsigned int DVP_SRC_20_ASF_DV0;
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unsigned int DVP_SRC_21_ASF_DV1;
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unsigned int DVP_SRC_22_ASF_DV2;
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unsigned int DVP_SRC_23_ASF_DV3;
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unsigned int DVP_SRC_24_WMF_HFDV;
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unsigned int DVP_SRC_25_WMF_DV0;
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unsigned int DVP_SRC_26_WMF_DV1;
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unsigned int DVP_SRC_27_WMF_DV2;
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unsigned int DVP_SRC_28_WMF_DV3;
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unsigned int DVP_CORE_00;
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unsigned int DVP_CORE_01;
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unsigned int DVP_CORE_02;
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unsigned int DVP_CORE_03;
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unsigned int DVP_CORE_04;
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unsigned int DVP_CORE_05;
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unsigned int DVP_CORE_06;
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unsigned int DVP_CORE_07;
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unsigned int DVP_CORE_08;
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unsigned int DVP_CORE_09;
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unsigned int DVP_CORE_10;
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unsigned int DVP_CORE_11;
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unsigned int DVP_CORE_12;
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unsigned int DVP_CORE_13;
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unsigned int DVP_CORE_14;
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unsigned int DVP_CORE_15;
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unsigned int DVP_SRC_CTRL;
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unsigned int DVP_CTRL_RESERVED;
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unsigned int DVP_CTRL_ATPG;
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unsigned int DVP_CRC_OUT_0;
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unsigned int DVP_CRC_OUT_1;
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unsigned int DVP_CRC_OUT_2;
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unsigned int DVP_CRC_CTRL;
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unsigned int DVP_CRC_OUT;
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unsigned int DVP_CRC_IN;
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unsigned int DVP_DRAM_STA;
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unsigned int DVP_DRAM_ULT;
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unsigned int DVP_DRAM_PITCH;
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unsigned int DVP_CORE_CRC_IN;
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unsigned int DVP_EXT_SRC_13_OCCDV0;
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unsigned int DVP_EXT_SRC_14_OCCDV1;
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unsigned int DVP_EXT_SRC_15_OCCDV2;
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unsigned int DVP_EXT_SRC_16_OCCDV3;
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unsigned int DVP_EXT_SRC_18_ASF_RMDV;
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unsigned int DVP_EXT_SRC_19_ASF_RDDV;
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unsigned int DVP_EXT_SRC_20_ASF_DV0;
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unsigned int DVP_EXT_SRC_21_ASF_DV1;
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unsigned int DVP_EXT_SRC_22_ASF_DV2;
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unsigned int DVP_EXT_SRC_23_ASF_DV3;
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unsigned int USERDUMP_EN;
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unsigned int DPE_MODE;
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};
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/*
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*
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*/
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enum DPE_CMD_ENUM {
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DPE_CMD_RESET, /* Reset */
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DPE_CMD_DUMP_REG, /* Dump DPE Register */
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DPE_CMD_DUMP_ISR_LOG, /* Dump DPE ISR log */
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DPE_CMD_READ_REG, /* Read register from driver */
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DPE_CMD_WRITE_REG, /* Write register to driver */
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DPE_CMD_WAIT_IRQ, /* Wait IRQ */
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DPE_CMD_CLEAR_IRQ, /* Clear IRQ */
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DPE_CMD_ENQUE_NUM, /* DPE Enque Number */
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DPE_CMD_ENQUE, /* DPE Enque */
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DPE_CMD_ENQUE_REQ, /* DPE Enque Request */
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DPE_CMD_DEQUE_NUM, /* DPE Deque Number */
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DPE_CMD_DEQUE, /* DPE Deque */
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DPE_CMD_DEQUE_REQ, /* DPE Deque Request */
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DPE_CMD_TOTAL,
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};
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/* */
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struct DPE_Request {
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unsigned int m_ReqNum;
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struct DPE_Config *m_pDpeConfig;
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};
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#ifdef CONFIG_COMPAT
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||
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struct compat_DPE_REG_IO_STRUCT {
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||
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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struct compat_DPE_Request {
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unsigned int m_ReqNum;
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||
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compat_uptr_t m_pDpeConfig;
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||
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|
};
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||
|
|
|
||
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|
#endif
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||
|
|
|
||
|
|
#define DPE_RESET _IO(DPE_MAGIC, DPE_CMD_RESET)
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||
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|
#define DPE_DUMP_REG _IO(DPE_MAGIC, DPE_CMD_DUMP_REG)
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||
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#define DPE_DUMP_ISR_LOG _IO(DPE_MAGIC, DPE_CMD_DUMP_ISR_LOG)
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||
|
|
|
||
|
|
#define DPE_READ_REGISTER \
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||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_READ_REG, struct DPE_REG_IO_STRUCT)
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||
|
|
#define DPE_WRITE_REGISTER \
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||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_WRITE_REG, struct DPE_REG_IO_STRUCT)
|
||
|
|
#define DPE_WAIT_IRQ \
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||
|
|
_IOW(DPE_MAGIC, DPE_CMD_WAIT_IRQ, struct DPE_WAIT_IRQ_STRUCT)
|
||
|
|
#define DPE_CLEAR_IRQ \
|
||
|
|
_IOW(DPE_MAGIC, DPE_CMD_CLEAR_IRQ, struct DPE_CLEAR_IRQ_STRUCT)
|
||
|
|
|
||
|
|
#define DPE_ENQNUE_NUM _IOW(DPE_MAGIC, DPE_CMD_ENQUE_NUM, int)
|
||
|
|
#define DPE_ENQUE _IOWR(DPE_MAGIC, DPE_CMD_ENQUE, struct DPE_Config)
|
||
|
|
#define DPE_ENQUE_REQ _IOWR(DPE_MAGIC, DPE_CMD_ENQUE_REQ, struct DPE_Request)
|
||
|
|
|
||
|
|
#define DPE_DEQUE_NUM _IOR(DPE_MAGIC, DPE_CMD_DEQUE_NUM, int)
|
||
|
|
#define DPE_DEQUE _IOWR(DPE_MAGIC, DPE_CMD_DEQUE, struct DPE_Config)
|
||
|
|
#define DPE_DEQUE_REQ _IOWR(DPE_MAGIC, DPE_CMD_DEQUE_REQ, struct DPE_Request)
|
||
|
|
|
||
|
|
#ifdef CONFIG_COMPAT
|
||
|
|
#define COMPAT_DPE_WRITE_REGISTER \
|
||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_WRITE_REG, struct compat_DPE_REG_IO_STRUCT)
|
||
|
|
#define COMPAT_DPE_READ_REGISTER \
|
||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_READ_REG, struct compat_DPE_REG_IO_STRUCT)
|
||
|
|
|
||
|
|
#define COMPAT_DPE_ENQUE_REQ \
|
||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_ENQUE_REQ, struct compat_DPE_Request)
|
||
|
|
#define COMPAT_DPE_DEQUE_REQ \
|
||
|
|
_IOWR(DPE_MAGIC, DPE_CMD_DEQUE_REQ, struct compat_DPE_Request)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* */
|
||
|
|
#endif
|