389 lines
12 KiB
C
389 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef _MT_WPE_H
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#define _MT_WPE_H
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#include <linux/ioctl.h>
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/*
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* enforce kernel log enable
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*/
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_WPE_FRAME_REQUEST_ 32
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#define _SUPPORT_MAX_WPE_REQUEST_RING_SIZE_ 32
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/***********************************************************************
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*
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***********************************************************************/
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#define WPE_DEV_MAJOR_NUMBER 251
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/*TODO: r selected*/
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#define WPE_MAGIC 'w'
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#define WPE_REG_RANGE (0x1000)
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/*TODO: WPE base address : 0x15011000
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* for GCE to access physical register addresses
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*/
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#define WPE_BASE_HW 0x15011000
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/*This macro is for setting irq status represnted
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* by a local variable,WPEInfo.IrqInfo.Status[WPE_IRQ_TYPE_INT_WPE_ST]
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*/
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#define WPE_INT_ST (1<<0)
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struct WPE_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct WPE_REG_IO_STRUCT {
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struct WPE_REG_STRUCT *pData; /* pointer to WPE_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/*
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* interrupt clear type
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*/
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enum WPE_IRQ_CLEAR_ENUM {
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WPE_IRQ_CLEAR_NONE,
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/* non-clear wait, clear after wait */
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WPE_IRQ_CLEAR_WAIT,
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/* clear wait, clear before and after wait */
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WPE_IRQ_WAIT_CLEAR,
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/* wait the signal and clear it, avoid the hw executime is too short. */
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WPE_IRQ_CLEAR_STATUS,
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/* clear specific status only */
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WPE_IRQ_CLEAR_ALL
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/* clear all status */
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};
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/*
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum WPE_IRQ_TYPE_ENUM {
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WPE_IRQ_TYPE_INT_WPE_ST, /* WPE */
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WPE_IRQ_TYPE_AMOUNT
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};
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struct WPE_WAIT_IRQ_STRUCT {
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enum WPE_IRQ_CLEAR_ENUM Clear;
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enum WPE_IRQ_TYPE_ENUM Type;
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unsigned int Status;
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/*IRQ Status*/
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unsigned int Timeout;
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int UserKey;
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/* user key for doing interrupt operation */
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int ProcessID;
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/* user ProcessID (will filled in kernel) */
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unsigned int bDumpReg;
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/* check dump register or not*/
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};
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struct WPE_CLEAR_IRQ_STRUCT {
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enum WPE_IRQ_TYPE_ENUM Type;
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int UserKey;
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/* user key for doing interrupt operation */
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unsigned int Status;
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/* Input */
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};
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/* struct for enqueue/dequeue control in ihalpipe wrapper */
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enum ISP_WPE_BUFQUE_CTRL_ENUM {
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ISP_WPE_BUFQUE_CTRL_ENQUE_FRAME = 0,
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/* 0,signal that a specific buffer is enqueued */
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ISP_WPE_BUFQUE_CTRL_WAIT_DEQUE,
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/* 1,a dequeue thread is waiting to do dequeue */
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ISP_WPE_BUFQUE_CTRL_DEQUE_SUCCESS,
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/* 2,signal that a buffer is dequeued (success) */
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ISP_WPE_BUFQUE_CTRL_DEQUE_FAIL,
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/* 3,signal that a buffer is dequeued (fail) */
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ISP_WPE_BUFQUE_CTRL_WAIT_FRAME,
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/* 4,wait for a specific buffer */
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ISP_WPE_BUFQUE_CTRL_WAKE_WAITFRAME,
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/* 5,wake all slept users to check buffer is dequeued or not */
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ISP_WPE_BUFQUE_CTRL_CLAER_ALL,
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/* 6,free all recored dequeued buffer */
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ISP_WPE_BUFQUE_CTRL_MAX
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};
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enum ISP_WPE_BUFQUE_PROPERTY {
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ISP_WPE_BUFQUE_PROPERTY_DIP = 0,
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ISP_WPE_BUFQUE_PROPERTY_WARP,
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ISP_WPE_BUFQUE_PROPERTY_NUM,
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};
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struct ISP_WPE_BUFQUE_STRUCT {
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enum ISP_WPE_BUFQUE_CTRL_ENUM ctrl;
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enum ISP_WPE_BUFQUE_PROPERTY property;
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unsigned int processID; /* judge multi-process */
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unsigned int callerID;
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/* judge multi-thread and different kinds of buffer type */
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int frameNum; /* total frame number in the enque request */
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int cQIdx; /* cq index */
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int dupCQIdx; /* dup cq index */
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int burstQIdx; /* burst queue index */
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unsigned int timeoutIns; /* timeout for wait buffer */
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};
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/*TODO: update WPE register map*/
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struct WPE_Config {
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unsigned int WPE_CTL_MOD_EN;
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unsigned int WPE_CTL_DMA_EN;
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unsigned int WPE_CTL_CFG;
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unsigned int WPE_CTL_FMT_SEL;
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unsigned int WPE_CTL_INT_EN;
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unsigned int WPE_CTL_INT_STATUS;
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unsigned int WPE_CTL_INT_STATUSX;
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unsigned int WPE_CTL_TDR_TILE;
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unsigned int WPE_CTL_TDR_DBG_STATUS;
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unsigned int WPE_CTL_TDR_TCM_EN;
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unsigned int WPE_CTL_SW_CTL;
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unsigned int WPE_CTL_SPARE0;
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unsigned int WPE_CTL_SPARE1;
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unsigned int WPE_CTL_SPARE2;
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unsigned int WPE_CTL_DONE_SEL;
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unsigned int WPE_CTL_DBG_SET;
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unsigned int WPE_CTL_DBG_PORT;
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unsigned int WPE_CTL_DATE_CODE;
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unsigned int WPE_CTL_PROJ_CODE;
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unsigned int WPE_CTL_WPE_DCM_DIS;
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unsigned int WPE_CTL_DMA_DCM_DIS;
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unsigned int WPE_CTL_WPE_DCM_STATUS;
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unsigned int WPE_CTL_DMA_DCM_STATUS;
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unsigned int WPE_CTL_WPE_REQ_STATUS;
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unsigned int WPE_CTL_DMA_REQ_STATUS;
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unsigned int WPE_CTL_WPE_RDY_STATUS;
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unsigned int WPE_CTL_DMA_RDY_STATUS;
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unsigned int WPE_VGEN_CTL;
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unsigned int WPE_VGEN_IN_IMG;
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unsigned int WPE_VGEN_OUT_IMG;
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unsigned int WPE_VGEN_HORI_STEP;
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unsigned int WPE_VGEN_VERT_STEP;
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unsigned int WPE_VGEN_HORI_INT_OFST;
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unsigned int WPE_VGEN_HORI_SUB_OFST;
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unsigned int WPE_VGEN_VERT_INT_OFST;
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unsigned int WPE_VGEN_VERT_SUB_OFST;
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unsigned int WPE_VGEN_POST_CTL;
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unsigned int WPE_VGEN_POST_COMP_X;
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unsigned int WPE_VGEN_POST_COMP_Y;
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unsigned int WPE_VGEN_MAX_VEC;
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unsigned int WPE_VFIFO_CTL;
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unsigned int WPE_CFIFO_CTL;
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unsigned int WPE_RWCTL_CTL;
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unsigned int WPE_CACHI_SPECIAL_FUN_EN;
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unsigned int WPE_C24_TILE_EDGE;
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unsigned int WPE_MDP_CROP_X;
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unsigned int WPE_MDP_CROP_Y;
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unsigned int WPE_ISPCROP_CON1;
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unsigned int WPE_ISPCROP_CON2;
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unsigned int WPE_PSP_CTL;
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unsigned int WPE_PSP2_CTL;
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unsigned int WPE_PSP_BORDER_COLOR;
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unsigned int WPE_ADDR_GEN_SOFT_RSTSTAT_0;
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unsigned int WPE_ADDR_GEN_BASE_ADDR_0;
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unsigned int WPE_ADDR_GEN_OFFSET_ADDR_0;
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unsigned int WPE_ADDR_GEN_STRIDE_0;
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unsigned int WPE_CACHI_CON_0;
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unsigned int WPE_CACHI_CON2_0;
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unsigned int WPE_CACHI_CON3_0;
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unsigned int WPE_ADDR_GEN_ERR_CTRL_0;
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unsigned int WPE_ADDR_GEN_ERR_STAT_0;
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unsigned int WPE_ADDR_GEN_RSV1_0;
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unsigned int WPE_ADDR_GEN_DEBUG_SEL_0;
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unsigned int WPE_ADDR_GEN_SOFT_RSTSTAT_1;
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unsigned int WPE_ADDR_GEN_BASE_ADDR_1;
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unsigned int WPE_ADDR_GEN_OFFSET_ADDR_1;
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unsigned int WPE_ADDR_GEN_STRIDE_1;
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unsigned int WPE_CACHI_CON_1;
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unsigned int WPE_CACHI_CON2_1;
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unsigned int WPE_CACHI_CON3_1;
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unsigned int WPE_ADDR_GEN_ERR_CTRL_1;
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unsigned int WPE_ADDR_GEN_ERR_STAT_1;
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unsigned int WPE_ADDR_GEN_RSV1_1;
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unsigned int WPE_ADDR_GEN_DEBUG_SEL_1;
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unsigned int WPE_ADDR_GEN_SOFT_RSTSTAT_2;
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unsigned int WPE_ADDR_GEN_BASE_ADDR_2;
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unsigned int WPE_ADDR_GEN_OFFSET_ADDR_2;
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unsigned int WPE_ADDR_GEN_STRIDE_2;
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unsigned int WPE_CACHI_CON_2;
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unsigned int WPE_CACHI_CON2_2;
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unsigned int WPE_CACHI_CON3_2;
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unsigned int WPE_ADDR_GEN_ERR_CTRL_2;
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unsigned int WPE_ADDR_GEN_ERR_STAT_2;
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unsigned int WPE_ADDR_GEN_RSV1_2;
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unsigned int WPE_ADDR_GEN_DEBUG_SEL_2;
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unsigned int WPE_ADDR_GEN_SOFT_RSTSTAT_3;
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unsigned int WPE_ADDR_GEN_BASE_ADDR_3;
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unsigned int WPE_ADDR_GEN_OFFSET_ADDR_3;
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unsigned int WPE_ADDR_GEN_STRIDE_3;
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unsigned int WPE_CACHI_CON_3;
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unsigned int WPE_CACHI_CON2_3;
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unsigned int WPE_CACHI_CON3_3;
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unsigned int WPE_ADDR_GEN_ERR_CTRL_3;
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unsigned int WPE_ADDR_GEN_ERR_STAT_3;
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unsigned int WPE_ADDR_GEN_RSV1_3;
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unsigned int WPE_ADDR_GEN_DEBUG_SEL_3;
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unsigned int WPE_DMA_SOFT_RSTSTAT;
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unsigned int WPE_TDRI_BASE_ADDR;
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unsigned int WPE_TDRI_OFST_ADDR;
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unsigned int WPE_TDRI_XSIZE;
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unsigned int WPE_VERTICAL_FLIP_EN;
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unsigned int WPE_DMA_SOFT_RESET;
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unsigned int WPE_LAST_ULTRA_EN;
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unsigned int WPE_SPECIAL_FUN_EN;
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unsigned int WPE_WPEO_BASE_ADDR;
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unsigned int WPE_WPEO_OFST_ADDR;
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unsigned int WPE_WPEO_XSIZE;
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unsigned int WPE_WPEO_YSIZE;
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unsigned int WPE_WPEO_STRIDE;
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unsigned int WPE_WPEO_CON;
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unsigned int WPE_WPEO_CON2;
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unsigned int WPE_WPEO_CON3;
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unsigned int WPE_WPEO_CROP;
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unsigned int WPE_MSKO_BASE_ADDR;
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unsigned int WPE_MSKO_OFST_ADDR;
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unsigned int WPE_MSKO_XSIZE;
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unsigned int WPE_MSKO_YSIZE;
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unsigned int WPE_MSKO_STRIDE;
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unsigned int WPE_MSKO_CON;
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unsigned int WPE_MSKO_CON2;
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unsigned int WPE_MSKO_CON3;
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unsigned int WPE_MSKO_CROP;
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unsigned int WPE_VECI_BASE_ADDR;
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unsigned int WPE_VECI_OFST_ADDR;
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unsigned int WPE_VECI_XSIZE;
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unsigned int WPE_VECI_YSIZE;
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unsigned int WPE_VECI_STRIDE;
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unsigned int WPE_VECI_CON;
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unsigned int WPE_VECI_CON2;
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unsigned int WPE_VECI_CON3;
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unsigned int WPE_VEC2I_BASE_ADDR;
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unsigned int WPE_VEC2I_OFST_ADDR;
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unsigned int WPE_VEC2I_XSIZE;
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unsigned int WPE_VEC2I_YSIZE;
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unsigned int WPE_VEC2I_STRIDE;
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unsigned int WPE_VEC2I_CON;
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unsigned int WPE_VEC2I_CON2;
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unsigned int WPE_VEC2I_CON3;
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unsigned int WPE_VEC3I_BASE_ADDR;
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unsigned int WPE_VEC3I_OFST_ADDR;
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unsigned int WPE_VEC3I_XSIZE;
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unsigned int WPE_VEC3I_YSIZE;
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unsigned int WPE_VEC3I_STRIDE;
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unsigned int WPE_VEC3I_CON;
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unsigned int WPE_VEC3I_CON2;
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unsigned int WPE_VEC3I_CON3;
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unsigned int WPE_DMA_ERR_CTRL;
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unsigned int WPE_WPEO_ERR_STAT;
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unsigned int WPE_MSKO_ERR_STAT;
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unsigned int WPE_VECI_ERR_STAT;
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unsigned int WPE_VEC2I_ERR_STAT;
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unsigned int WPE_VEC3I_ERR_STAT;
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unsigned int WPE_DMA_DEBUG_ADDR;
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unsigned int WPE_DMA_DEBUG_SEL;
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};
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/***********************************************************************
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*
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***********************************************************************/
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enum WPE_CMD_ENUM {
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WPE_CMD_RESET, /* Reset */
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WPE_CMD_DUMP_REG, /* Dump WPE Register */
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WPE_CMD_DUMP_ISR_LOG, /* Dump WPE ISR log */
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WPE_CMD_READ_REG, /* Read register from driver */
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WPE_CMD_WRITE_REG, /* Write register to driver */
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WPE_CMD_WAIT_IRQ, /* Wait IRQ */
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WPE_CMD_CLEAR_IRQ, /* Clear IRQ */
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WPE_CMD_ENQUE_NUM, /* WMFE Enque Number */
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WPE_CMD_ENQUE, /* WMFE Enque */
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WPE_CMD_ENQUE_REQ, /* WMFE Enque Request */
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WPE_CMD_DEQUE_NUM, /* WMFE Deque Number */
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WPE_CMD_DEQUE, /* WMFE Deque */
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WPE_CMD_DEQUE_REQ, /* WMFE Deque Request */
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WPE_CMD_DEQUE_DONE, /* WMFE Deque Done */
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WPE_CMD_WAIT_DEQUE, /* WMFE WAIT Enque Done */
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WPE_CMD_BUFQUE_CTRL,
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WPE_CMD_TOTAL,
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};
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struct WPE_Request {
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unsigned int m_ReqNum;
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struct WPE_Config *m_pWpeConfig;
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};
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#ifdef CONFIG_COMPAT
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struct compat_WPE_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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struct compat_WPE_Request {
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unsigned int m_ReqNum;
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compat_uptr_t m_pWpeConfig;
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};
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#endif
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||
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||
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||
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#define WPE_RESET _IO(WPE_MAGIC, WPE_CMD_RESET)
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||
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#define WPE_DUMP_REG _IO(WPE_MAGIC, WPE_CMD_DUMP_REG)
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||
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#define WPE_DUMP_ISR_LOG _IO(WPE_MAGIC, WPE_CMD_DUMP_ISR_LOG)
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||
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||
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||
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#define WPE_READ_REGISTER \
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||
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_IOWR(WPE_MAGIC, WPE_CMD_READ_REG, struct WPE_REG_IO_STRUCT)
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||
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#define WPE_WRITE_REGISTER \
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||
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_IOWR(WPE_MAGIC, WPE_CMD_WRITE_REG, struct WPE_REG_IO_STRUCT)
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||
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#define WPE_WAIT_IRQ \
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||
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_IOW(WPE_MAGIC, WPE_CMD_WAIT_IRQ, struct WPE_WAIT_IRQ_STRUCT)
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||
|
|
#define WPE_CLEAR_IRQ \
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||
|
|
_IOW(WPE_MAGIC, WPE_CMD_CLEAR_IRQ, struct WPE_CLEAR_IRQ_STRUCT)
|
||
|
|
|
||
|
|
#define WPE_ENQNUE_NUM _IOW(WPE_MAGIC, WPE_CMD_ENQUE_NUM, int)
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||
|
|
#define WPE_ENQUE _IOWR(WPE_MAGIC, WPE_CMD_ENQUE, struct WPE_Config)
|
||
|
|
#define WPE_ENQUE_REQ _IOWR(WPE_MAGIC, WPE_CMD_ENQUE_REQ, struct WPE_Request)
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||
|
|
|
||
|
|
#define WPE_DEQUE_NUM _IOR(WPE_MAGIC, WPE_CMD_DEQUE_NUM, int)
|
||
|
|
#define WPE_DEQUE _IOWR(WPE_MAGIC, WPE_CMD_DEQUE, struct WPE_Config)
|
||
|
|
#define WPE_DEQUE_REQ _IOWR(WPE_MAGIC, WPE_CMD_DEQUE_REQ, struct WPE_Request)
|
||
|
|
#define WPE_DEQUE_DONE _IOWR(WPE_MAGIC, WPE_CMD_DEQUE_DONE, struct WPE_Request)
|
||
|
|
#define WPE_WAIT_DEQUE _IO(WPE_MAGIC, WPE_CMD_WAIT_DEQUE)
|
||
|
|
#define WPE_BUFQUE_CTRL \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_BUFQUE_CTRL, struct ISP_WPE_BUFQUE_STRUCT)
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef CONFIG_COMPAT
|
||
|
|
#define COMPAT_WPE_WRITE_REGISTER \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_WRITE_REG, struct compat_WPE_REG_IO_STRUCT)
|
||
|
|
#define COMPAT_WPE_READ_REGISTER \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_READ_REG, struct compat_WPE_REG_IO_STRUCT)
|
||
|
|
#define COMPAT_WPE_BUFFER_CTRL \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_BUFQUE_CTRL, struct ISP_WPE_BUFQUE_STRUCT)
|
||
|
|
|
||
|
|
#define COMPAT_WPE_ENQUE_REQ \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_ENQUE_REQ, struct compat_WPE_Request)
|
||
|
|
#define COMPAT_WPE_DEQUE_REQ \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_DEQUE_REQ, struct compat_WPE_Request)
|
||
|
|
#define COMPAT_WPE_DEQUE_DONE \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_DEQUE_DONE, struct compat_WPE_Request)
|
||
|
|
#define COMPAT_WPE_WAIT_DEQUE \
|
||
|
|
_IO(WPE_MAGIC, WPE_CMD_WAIT_DEQUE)
|
||
|
|
#define COMPAT_WPE_BUFQUE_CTRL \
|
||
|
|
_IOWR(WPE_MAGIC, WPE_CMD_BUFQUE_CTRL, struct ISP_WPE_BUFQUE_STRUCT)
|
||
|
|
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
|