443 lines
11 KiB
C
443 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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/* system includes */
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/miscdevice.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/kthread.h>
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#include <linux/hrtimer.h>
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#include <linux/sched/rt.h>
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#include <linux/atomic.h>
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#include <linux/clk.h>
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#include <linux/ktime.h>
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#include <linux/time.h>
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#include <linux/jiffies.h>
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#include <linux/bitops.h>
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#include <linux/uaccess.h>
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#include <linux/types.h>
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#include <linux/suspend.h>
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#include <linux/topology.h>
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#include <linux/math64.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_opp.h>
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#ifdef CONFIG_MTK_DVFSRC
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#include <linux/soc/mediatek/mtk_dvfsrc.h>
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#include "dvfsrc-exp.h"
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#endif /* CONFIG_MTK_DVFSRC */
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#include "mtk_cm_mgr_mt6779.h"
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#include "mtk_cm_mgr_common.h"
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#include <linux/soc/mediatek/mtk-pm-qos.h>
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#include <mtk_qos_sram.h>
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#ifndef CONFIG_MTK_BASE_POWER
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/* FIXME: */
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#undef CONFIG_MTK_CPU_FREQ
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#endif /* CONFIG_MTK_BASE_POWER */
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#ifdef CONFIG_MTK_CPU_FREQ
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#include <mtk_cpufreq_platform.h>
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#include <mtk_cpufreq_common_api.h>
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#endif /* CONFIG_MTK_CPU_FREQ */
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static struct delayed_work cm_mgr_work;
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static int cm_mgr_work_ready;
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static struct mtk_pm_qos_request ddr_opp_req_by_cpu_opp;
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static int cm_mgr_cpu_to_dram_opp;
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static unsigned int prev_freq_idx[CM_MGR_CPU_CLUSTER];
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static unsigned int prev_freq[CM_MGR_CPU_CLUSTER];
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static int cm_mgr_idx = -1;
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static int cm_mgr_check_dram_type(void)
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{
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#ifdef CONFIG_MTK_DRAMC_LEGACY
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int ddr_type = get_ddr_type();
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int ddr_hz = dram_steps_freq(0);
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if (ddr_type == TYPE_LPDDR4X || ddr_type == TYPE_LPDDR4)
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cm_mgr_idx = CM_MGR_LP4X_2CH;
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pr_info("#@# %s(%d) ddr_type 0x%x, ddr_hz %d, cm_mgr_idx 0x%x\n",
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__func__, __LINE__, ddr_type, ddr_hz, cm_mgr_idx);
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#else
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cm_mgr_idx = 0;
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pr_info("#@# %s(%d) NO CONFIG_MTK_DRAMC_LEGACY !!! set cm_mgr_idx to 0x%x\n",
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__func__, __LINE__, cm_mgr_idx);
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#endif /* CONFIG_MTK_DRAMC_LEGACY */
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#if defined(CONFIG_MTK_TINYSYS_SSPM_SUPPORT)
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if (cm_mgr_idx >= 0)
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cm_mgr_to_sspm_command(IPI_CM_MGR_DRAM_TYPE, cm_mgr_idx);
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#endif /* CONFIG_MTK_TINYSYS_SSPM_SUPPORT */
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return cm_mgr_idx;
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};
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static int cm_mgr_get_idx(void)
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{
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if (cm_mgr_idx < 0)
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return cm_mgr_check_dram_type();
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else
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return cm_mgr_idx;
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};
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static int cm_mgr_get_dram_opp(void);
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static struct mtk_pm_qos_request ddr_opp_req;
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static ktime_t perf_now;
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void cm_mgr_perf_platform_set_status(int enable)
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{
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if (enable) {
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if (!cm_mgr_perf_enable)
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return;
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debounce_times_perf_down_local = 0;
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perf_now = ktime_get();
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vcore_power_ratio_up[0] = 30;
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vcore_power_ratio_up[1] = 30;
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vcore_power_ratio_up[2] = 30;
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vcore_power_ratio_up[3] = 30;
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#if defined(CONFIG_MTK_TINYSYS_SSPM_SUPPORT)
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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0 << 16 | vcore_power_ratio_up[0]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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1 << 16 | vcore_power_ratio_up[1]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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2 << 16 | vcore_power_ratio_up[2]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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3 << 16 | vcore_power_ratio_up[3]);
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#endif /* CONFIG_MTK_TINYSYS_SSPM_SUPPORT */
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} else {
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if (debounce_times_perf_down_local < 0)
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return;
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if (++debounce_times_perf_down_local <
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debounce_times_perf_down) {
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if (ktime_ms_delta(ktime_get(), perf_now) < PERF_TIME)
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return;
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cm_mgr_dram_opp_base = -1;
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}
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vcore_power_ratio_up[0] = 100;
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vcore_power_ratio_up[1] = 100;
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vcore_power_ratio_up[2] = 100;
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vcore_power_ratio_up[3] = 100;
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#if defined(CONFIG_MTK_TINYSYS_SSPM_SUPPORT)
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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0 << 16 | vcore_power_ratio_up[0]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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1 << 16 | vcore_power_ratio_up[1]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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2 << 16 | vcore_power_ratio_up[2]);
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cm_mgr_to_sspm_command(IPI_CM_MGR_VCORE_POWER_RATIO_UP,
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3 << 16 | vcore_power_ratio_up[3]);
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#endif /* CONFIG_MTK_TINYSYS_SSPM_SUPPORT */
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debounce_times_perf_down_local = -1;
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}
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}
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EXPORT_SYMBOL_GPL(cm_mgr_perf_platform_set_status);
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void cm_mgr_perf_platform_set_force_status(int enable)
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{
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if (enable) {
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if (!cm_mgr_perf_enable)
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return;
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if (!cm_mgr_perf_force_enable)
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return;
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debounce_times_perf_down_force_local = 0;
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if (cm_mgr_dram_opp_base == -1) {
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cm_mgr_dram_opp = cm_mgr_dram_opp_base =
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cm_mgr_get_dram_opp();
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mtk_pm_qos_update_request(&ddr_opp_req,
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cm_mgr_dram_opp);
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} else {
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if (cm_mgr_dram_opp > 0) {
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cm_mgr_dram_opp--;
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mtk_pm_qos_update_request(&ddr_opp_req,
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cm_mgr_dram_opp);
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}
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}
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pm_qos_update_request_status = enable;
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} else {
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if (debounce_times_perf_down_force_local < 0)
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return;
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if (!pm_qos_update_request_status)
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return;
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if ((!cm_mgr_perf_force_enable) ||
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(++debounce_times_perf_down_force_local >=
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debounce_times_perf_force_down)) {
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if (cm_mgr_dram_opp < cm_mgr_dram_opp_base) {
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cm_mgr_dram_opp++;
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mtk_pm_qos_update_request(&ddr_opp_req,
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cm_mgr_dram_opp);
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} else {
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cm_mgr_dram_opp = cm_mgr_dram_opp_base = -1;
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mtk_pm_qos_update_request(&ddr_opp_req,
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE);
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pm_qos_update_request_status = enable;
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debounce_times_perf_down_force_local = -1;
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}
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}
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}
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}
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EXPORT_SYMBOL_GPL(cm_mgr_perf_platform_set_force_status);
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/* no 1200 */
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static int phy_to_virt_dram_opp[] = {
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0x0, 0x1, 0x2, 0x3, 0x5, 0x5
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};
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static int cm_mgr_get_dram_opp(void)
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{
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int dram_opp_cur;
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#ifdef CONFIG_MTK_DVFSRC
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dram_opp_cur = mtk_dvfsrc_query_opp_info(MTK_DVFSRC_CURR_DRAM_OPP);
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#else
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dram_opp_cur = 0;
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#endif /* CONFIG_MTK_DVFSRC */
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if (dram_opp_cur < 0 || dram_opp_cur > cm_mgr_num_perf)
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dram_opp_cur = 0;
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return phy_to_virt_dram_opp[dram_opp_cur];
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}
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static void cm_mgr_process(struct work_struct *work)
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{
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mtk_pm_qos_update_request(&ddr_opp_req_by_cpu_opp,
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cm_mgr_cpu_to_dram_opp);
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}
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static void cm_mgr_update_dram_by_cpu_opp(int cpu_opp)
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{
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int ret = 0;
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int dram_opp = 0;
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if (cm_mgr_disable_fb == 1 && cm_mgr_blank_status == 1) {
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if (cm_mgr_cpu_to_dram_opp !=
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE) {
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cm_mgr_cpu_to_dram_opp =
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE;
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ret = schedule_delayed_work(&cm_mgr_work, 1);
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}
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return;
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}
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if (!cm_mgr_work_ready)
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return;
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if (!cm_mgr_cpu_map_dram_enable) {
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if (cm_mgr_cpu_to_dram_opp !=
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE) {
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cm_mgr_cpu_to_dram_opp =
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE;
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ret = schedule_delayed_work(&cm_mgr_work, 1);
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}
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return;
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}
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if ((cpu_opp >= 0) && (cpu_opp < cm_mgr_cpu_opp_size))
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dram_opp = cm_mgr_cpu_opp_to_dram[cpu_opp];
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if (cm_mgr_cpu_to_dram_opp == dram_opp)
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return;
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cm_mgr_cpu_to_dram_opp = dram_opp;
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ret = schedule_delayed_work(&cm_mgr_work, 1);
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}
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void check_cm_mgr_status_mt6779(unsigned int cluster, unsigned int freq)
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{
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#ifdef CONFIG_MTK_CPU_FREQ
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int freq_idx = 0;
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struct mt_cpu_dvfs *p;
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p = id_to_cpu_dvfs(cluster);
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if (p)
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freq_idx = _search_available_freq_idx(p, freq, 0);
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if (freq_idx == prev_freq_idx[cluster])
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return;
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prev_freq_idx[cluster] = freq_idx;
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prev_freq[cluster] = freq;
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#else
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prev_freq_idx[cluster] = 0;
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prev_freq[cluster] = 0;
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#endif /* CONFIG_MTK_CPU_FREQ */
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if (cm_mgr_use_cpu_to_dram_map)
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cm_mgr_update_dram_by_cpu_opp
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(prev_freq_idx[CM_MGR_CPU_CLUSTER - 1]);
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}
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EXPORT_SYMBOL_GPL(check_cm_mgr_status_mt6779);
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static void cm_mgr_add_cpu_opp_to_ddr_req(void)
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{
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char owner[20] = "cm_mgr_cpu_to_dram";
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mtk_pm_qos_add_request(&ddr_opp_req_by_cpu_opp, MTK_PM_QOS_DDR_OPP,
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MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE);
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strncpy(ddr_opp_req_by_cpu_opp.owner,
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owner, sizeof(ddr_opp_req_by_cpu_opp.owner) - 1);
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if (cm_mgr_use_cpu_to_dram_map_new)
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cm_mgr_cpu_map_update_table();
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}
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static int platform_cm_mgr_probe(struct platform_device *pdev)
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{
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int ret;
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struct device_node *node = pdev->dev.of_node;
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#ifdef CONFIG_MTK_DVFSRC
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int i;
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#endif /* CONFIG_MTK_DVFSRC */
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ret = cm_mgr_common_init();
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if (ret) {
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pr_info("[CM_MGR] FAILED TO INIT(%d)\n", ret);
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return ret;
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}
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(void)cm_mgr_get_idx();
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/* required-opps */
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cm_mgr_num_perf = of_count_phandle_with_args(node,
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"required-opps", NULL);
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pr_info("#@# %s(%d) cm_mgr_num_perf %d\n",
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__func__, __LINE__, cm_mgr_num_perf);
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if (cm_mgr_num_perf > 0) {
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cm_mgr_perfs = devm_kzalloc(&pdev->dev,
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cm_mgr_num_perf * sizeof(int),
|
||
|
|
GFP_KERNEL);
|
||
|
|
|
||
|
|
if (!cm_mgr_num_perf) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto ERROR;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_MTK_DVFSRC
|
||
|
|
for (i = 0; i < cm_mgr_num_perf; i++) {
|
||
|
|
cm_mgr_perfs[i] =
|
||
|
|
dvfsrc_get_required_opp_performance_state
|
||
|
|
(node, i);
|
||
|
|
}
|
||
|
|
#endif /* CONFIG_MTK_DVFSRC */
|
||
|
|
cm_mgr_num_array = cm_mgr_num_perf - 2;
|
||
|
|
} else
|
||
|
|
cm_mgr_num_array = 0;
|
||
|
|
pr_info("#@# %s(%d) cm_mgr_num_array %d\n",
|
||
|
|
__func__, __LINE__, cm_mgr_num_array);
|
||
|
|
|
||
|
|
ret = cm_mgr_check_dts_setting(pdev);
|
||
|
|
if (ret) {
|
||
|
|
pr_info("[CM_MGR] FAILED TO GET DTS DATA(%d)\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
cm_mgr_pdev = pdev;
|
||
|
|
|
||
|
|
pr_info("[CM_MGR] platform-cm_mgr_probe Done.\n");
|
||
|
|
|
||
|
|
#ifdef CONFIG_MTK_CPU_FREQ
|
||
|
|
mt_cpufreq_set_governor_freq_registerCB(check_cm_mgr_status_mt6779);
|
||
|
|
#endif /* CONFIG_MTK_CPU_FREQ */
|
||
|
|
|
||
|
|
mtk_pm_qos_add_request(&ddr_opp_req, MTK_PM_QOS_DDR_OPP,
|
||
|
|
MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE);
|
||
|
|
|
||
|
|
if (cm_mgr_use_cpu_to_dram_map) {
|
||
|
|
cm_mgr_add_cpu_opp_to_ddr_req();
|
||
|
|
|
||
|
|
INIT_DELAYED_WORK(&cm_mgr_work, cm_mgr_process);
|
||
|
|
cm_mgr_work_ready = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
ERROR:
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int platform_cm_mgr_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
cm_mgr_work_ready = 0;
|
||
|
|
|
||
|
|
cm_mgr_common_exit();
|
||
|
|
|
||
|
|
kfree(cm_mgr_perfs);
|
||
|
|
kfree(cm_mgr_cpu_opp_to_dram);
|
||
|
|
kfree(cm_mgr_buf);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id platform_cm_mgr_of_match[] = {
|
||
|
|
{ .compatible = "mediatek,mt6779-cm_mgr", },
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct platform_device_id platform_cm_mgr_id_table[] = {
|
||
|
|
{ "mt6779-cm_mgr", 0},
|
||
|
|
{ },
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver mtk_platform_cm_mgr_driver = {
|
||
|
|
.probe = platform_cm_mgr_probe,
|
||
|
|
.remove = platform_cm_mgr_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "mt6779-cm_mgr",
|
||
|
|
.owner = THIS_MODULE,
|
||
|
|
.of_match_table = platform_cm_mgr_of_match,
|
||
|
|
},
|
||
|
|
.id_table = platform_cm_mgr_id_table,
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* driver initialization entry point
|
||
|
|
*/
|
||
|
|
static int __init platform_cm_mgr_init(void)
|
||
|
|
{
|
||
|
|
return platform_driver_register(&mtk_platform_cm_mgr_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit platform_cm_mgr_exit(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&mtk_platform_cm_mgr_driver);
|
||
|
|
pr_info("[CM_MGR] platform-cm_mgr Exit.\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
late_initcall(platform_cm_mgr_init);
|
||
|
|
module_exit(platform_cm_mgr_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Mediatek cm_mgr driver");
|
||
|
|
MODULE_AUTHOR("Morven-CF Yeh<morven-cf.yeh@mediatek.com>");
|
||
|
|
MODULE_LICENSE("GPL");
|