unplugged-kernel/drivers/misc/mediatek/emi/mt6761/mpu_platform.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Sagy Shih <sagy.shih@mediatek.com>
 */

#ifndef __MPU_PLATFORM_H__
#define __MPU_PLATFORM_H__

enum {
	MT6761_M7_AXI_MST_THERM,
	MT6761_M7_AXI_MST_PWM,
	MT6761_M4_AXI_MST_HRQ_WR,
	MT6761_M5_AXI_MST_DISP_WDMA0,
	MT6761_M2_AXI_MST_MDP_RDMA0,
	MT6761_M4_AXI_MST_DEBUG,
	MT6761_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
	MT6761_M2_AXI_MST_DISP_WDMA0,
	MT6761_M5_AXI_MST_DISP_RDMA0,
	MT6761_M5_AXI_MST_RP,
	MT6761_M4_AXI_MST_TRACE_TOP,
	MT6761_M5_AXI_MST_JPGENC_BSDMA,
	MT6761_M5_AXI_MST_AFO_D,
	MT6761_M5_AXI_MST_JPGENC_RDMA,
	MT6761_M4_AXI_MST_PPPHA,
	MT6761_M2_AXI_MST_VENC_REF_CHROMA,
	MT6761_M2_AXI_MST_AAO,
	MT6761_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
	MT6761_M3_AXI_MST_MD_MMU,
	MT6761_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
	MT6761_M5_AXI_MST_RRZO,
	MT6761_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
	MT6761_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
	MT6761_M7_AXI_MST_USB20,
	MT6761_M5_AXI_MST_IMG2O,
	MT6761_M2_AXI_MST_RB,
	MT6761_M5_AXI_MST_IMGO_S,
	MT6761_M4_AXI_MST_TPC,
	MT6761_M4_AXI_MST_HRQ_WR1,
	MT6761_M2_AXI_MST_RRZO,
	MT6761_M7_AXI_MST_DEBUGTOP,
	MT6761_M3_AXI_MST_USIP_0_DNOCACHE,
	MT6761_M7_AXI_MST_SPM,
	MT6761_M4_AXI_MST_BR_DMA,
	MT6761_M0_AXI_MST_MP0,
	MT6761_M5_AXI_MST_BPCI,
	MT6761_M2_AXI_MST_AFO,
	MT6761_M2_AXI_MST_DISP_RDMA0,
	MT6761_M5_AXI_MST_MDP_WROT0,
	MT6761_M5_AXI_MST_WR,
	MT6761_M2_AXI_MST_BPCI,
	MT6761_M5_AXI_MST_IMGI,
	MT6761_M4_AXI_MST_QP,
	MT6761_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
	MT6761_M2_AXI_MST_AFO_D,
	MT6761_M7_AXI_MST_CONNSYS_N9_MCU_RW,
	MT6761_M2_AXI_MST_IMGO_S,
	MT6761_M2_AXI_MST_IMGI,
	MT6761_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
	MT6761_M4_AXI_MST_DMA_WR,
	MT6761_M2_AXI_MST_DISP_OVL0_2L,
	MT6761_M4_AXI_MST_GDMA,
	MT6761_M4_AXI_MST_VTB,
	MT6761_M2_AXI_MST_IMG2O,
	MT6761_M7_AXI_MST_SPI0,
	MT6761_M2_AXI_MST_DISP_FAKE,
	MT6761_M2_AXI_MST_VIPI,
	MT6761_M5_AXI_MST_IMG3O,
	MT6761_M5_AXI_MST_IMGO_S2,
	MT6761_M4_AXI_MST_RXDFE_DMA,
	MT6761_M7_AXI_MST_SPI2,
	MT6761_M5_AXI_MST_ESFKO,
	MT6761_M2_AXI_MST_JPGENC_RDMA,
	MT6761_M4_AXI_MST_TBO,
	MT6761_M5_AXI_MST_IMGO,
	MT6761_M4_AXI_MST_MRSG0,
	MT6761_M5_AXI_MST_LCEI,
	MT6761_M7_AXI_MST_SPI4,
	MT6761_M5_AXI_MST_VIPI,
	MT6761_M7_AXI_MST_MSDC0,
	MT6761_M4_AXI_MST_CNWDMA,
	MT6761_M4_AXI_MST_IRDMA,
	MT6761_M2_AXI_MST_IMGO,
	MT6761_M2_AXI_MST_LCEI,
	MT6761_M4_AXI_MST_LOG_TOP_DSP,
	MT6761_M7_AXI_MST_MCUPM,
	MT6761_M4_AXI_MST_TXBRP0,
	MT6761_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
	MT6761_M3_AXI_MST_MD_MM,
	MT6761_M3_AXI_MST_USIP_1_DNOCACHE,
	MT6761_M5_AXI_MST_VIP2I,
	MT6761_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
	MT6761_M4_AXI_MST_LOG_TOP_MCU,
	MT6761_M2_AXI_MST_IMG3O,
	MT6761_M2_AXI_MST_RP,
	MT6761_M5_AXI_MST_MDP_WDMA0,
	MT6761_M4_AXI_MST_HRQ_RD,
	MT6761_M7_AXI_MST_CCU,
	MT6761_M2_AXI_MST_ESFKO,
	MT6761_M2_AXI_MST_VENC_REC,
	MT6761_M7_AXI_MST_DX_CC,
	MT6761_M4_AXI_MST_CSH,
	MT6761_M2_AXI_MST_JPGENC_BSDMA,
	MT6761_M2_AXI_MST_MDP_WROT0,
	MT6761_M7_AXI_MST_CONNSYS_WIFI_PDMA,
	MT6761_M4_AXI_MST_IPSEC,
	MT6761_M5_AXI_MST_DISP_OVL0,
	MT6761_M4_AXI_MST_MCUSYS_DFD,
	MT6761_M5_AXI_MST_BPCI_D,
	MT6761_M7_AXI_MST_CONNSYS_RBIST_INTERNAL_CAPTURE,
	MT6761_M5_AXI_MST_LCSO,
	MT6761_M2_AXI_MST_VIP2I,
	MT6761_M5_AXI_MST_RB,
	MT6761_M5_AXI_MST_MDP_RDMA0,
	MT6761_M2_AXI_MST_WR,
	MT6761_M2_AXI_MST_LSCI_D,
	MT6761_M5_AXI_MST_LSCI_D,
	MT6761_M4_AXI_MST_HRQ_RD1,
	MT6761_M2_AXI_MST_LCSO,
	MT6761_M7_AXI_MST_CQ_DMA,
	MT6761_M7_AXI_MST_CONNSYS_NA,
	MT6761_M5_AXI_MST_VIP3I,
	MT6761_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
	MT6761_M5_AXI_MST_AAO,
	MT6761_M3_AXI_MST_USIP_1_I,
	MT6761_M2_AXI_MST_BPCI_D,
	MT6761_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
	MT6761_M5_AXI_MST_VENC_REF_CHROMA,
	MT6761_M4_AXI_MST_DMA_RD,
	MT6761_M5_AXI_MST_DISP_OVL0_2L,
	MT6761_M4_AXI_MST_DBGSYS,
	MT6761_M7_AXI_MST_CLDMA,
	MT6761_M5_AXI_MST_MM_IOMMU,
	MT6761_M7_AXI_MST_DMA_EXT,
	MT6761_M6_AXI_MST_MFG_M0,
	MT6761_M4_AXI_MST_MMU,
	MT6761_M7_AXI_MST_SPI1,
	MT6761_M7_AXI_MST_SSPM,
	MT6761_M5_AXI_MST_AFO,
	MT6761_M4_AXI_MST_DCXO,
	MT6761_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
	MT6761_M7_AXI_MST_GPU,
	MT6761_M7_AXI_MST_AUDIO,
	MT6761_M2_AXI_MST_VIP3I,
	MT6761_M2_AXI_MST_MDP_WDMA0,
	MT6761_M7_AXI_MST_SCP,
	MT6761_M7_AXI_MST_SPI3,
	MT6761_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
	MT6761_M2_AXI_MST_IMGO_S2,
	MT6761_M3_AXI_MST_USIP_1_DCACHE,
	MT6761_M5_AXI_MST_UFDI,
	MT6761_M4_AXI_MST_MRSG1,
	MT6761_M7_AXI_MST_SPI5,
	MT6761_M3_AXI_MST_USIP_0_DCACHE,
	MT6761_M7_AXI_MST_MSDC1,
	MT6761_M5_AXI_MST_LSCI,
	MT6761_M2_AXI_MST_UFDI,
	MT6761_M5_AXI_MST_VENC_REC,
	MT6761_M5_AXI_MST_DISP_FAKE,
	MT6761_M4_AXI_MST_DFE_DUMP,
	MT6761_M2_AXI_MST_DISP_OVL0,
	MT6761_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
	MT6761_M4_AXI_MST_TXBRP1,
	MT6761_M3_AXI_MST_USIP_0_I,
	MT6761_M2_AXI_MST_LSCI,
	MT6761_M4_AXI_MST_TXCAL,
	MT6761_M7_AXI_MST_GCE_M,
	MST_INVALID,
	NR_MST
};

static const struct mst_tbl_entry mst_tbl[] = {
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
		.id_val = 0x0,
		.note = "Core nn system domain store exclusive",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
		.id_val = 0x4,
		.note = "Core nn barrier",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
		.id_val = 0x8,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
		.id_val = 0x49,
		.note = "SCU generated barrier",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFE,
		.id_val = 0xA,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
		.id_val = 0xC,
		.note = "Core nn non-re-orderable device write",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF0,
		.id_val = 0x10,
		.note = "Write to normal memory or re-orderable device memory",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1BFC,
		.id_val = 0x0,
		.note = "Core nn exclusive read or non-reorderable device read",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
		.id_val = 0x4,
		.note = "Core nn barrier",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
		.id_val = 0x8,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
		.id_val = 0x9,
		.note = "SCU generated barrier or DVM complete",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFE,
		.id_val = 0xA,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
		.id_val = 0xC,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF3,
		.id_val = 0x10,
		.note = "ACP read",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF3,
		.id_val = 0x11,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF2,
		.id_val = 0x12,
		.note = "Unused",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE0,
		.id_val = 0x20,
		.note = "Core nn read",
		.name = "MT6761_M0_AXI_MST_MP0"},
	{.master = MT6761_M2_AXI_MST_DISP_OVL0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x0,
		.note = "",
		.name = "MT6761_M2_AXI_MST_DISP_OVL0"},
	{.master = MT6761_M2_AXI_MST_DISP_OVL0_2L, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x4,
		.note = "",
		.name = "MT6761_M2_AXI_MST_DISP_OVL0_2L"},
	{.master = MT6761_M2_AXI_MST_DISP_RDMA0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x8,
		.note = "",
		.name = "MT6761_M2_AXI_MST_DISP_RDMA0"},
	{.master = MT6761_M2_AXI_MST_DISP_WDMA0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0xC,
		.note = "",
		.name = "MT6761_M2_AXI_MST_DISP_WDMA0"},
	{.master = MT6761_M2_AXI_MST_MDP_RDMA0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x10,
		.note = "",
		.name = "MT6761_M2_AXI_MST_MDP_RDMA0"},
	{.master = MT6761_M2_AXI_MST_MDP_WDMA0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x14,
		.note = "",
		.name = "MT6761_M2_AXI_MST_MDP_WDMA0"},
	{.master = MT6761_M2_AXI_MST_MDP_WROT0, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x18,
		.note = "",
		.name = "MT6761_M2_AXI_MST_MDP_WROT0"},
	{.master = MT6761_M2_AXI_MST_DISP_FAKE, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x1C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_DISP_FAKE"},
	{.master = MT6761_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x80,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT"},
	{.master = MT6761_M2_AXI_MST_VENC_REC, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x84,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_REC"},
	{.master = MT6761_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x88,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT"},
	{.master = MT6761_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
		.port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x8C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT"},
	{.master = MT6761_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
		.port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x90,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT"},
	{.master = MT6761_M2_AXI_MST_JPGENC_RDMA, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x94,
		.note = "",
		.name = "MT6761_M2_AXI_MST_JPGENC_RDMA"},
	{.master = MT6761_M2_AXI_MST_JPGENC_BSDMA, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x98,
		.note = "",
		.name = "MT6761_M2_AXI_MST_JPGENC_BSDMA"},
	{.master = MT6761_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0x9C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT"},
	{.master = MT6761_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
		.port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0xA0,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT"
	},
	{.master = MT6761_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
		.port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0xA4,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT"},
	{.master = MT6761_M2_AXI_MST_VENC_REF_CHROMA, .port = 2,
		.id_mask = 0x1FFC,
		.id_val = 0xA8,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VENC_REF_CHROMA"},
	{.master = MT6761_M2_AXI_MST_IMGO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x100,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMGO"},
	{.master = MT6761_M2_AXI_MST_RRZO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x104,
		.note = "",
		.name = "MT6761_M2_AXI_MST_RRZO"},
	{.master = MT6761_M2_AXI_MST_AAO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x108,
		.note = "",
		.name = "MT6761_M2_AXI_MST_AAO"},
	{.master = MT6761_M2_AXI_MST_LCSO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x10C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_LCSO"},
	{.master = MT6761_M2_AXI_MST_ESFKO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x110,
		.note = "",
		.name = "MT6761_M2_AXI_MST_ESFKO"},
	{.master = MT6761_M2_AXI_MST_IMGO_S, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x114,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMGO_S"},
	{.master = MT6761_M2_AXI_MST_IMGO_S2, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x118,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMGO_S2"},
	{.master = MT6761_M2_AXI_MST_LSCI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x11C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_LSCI"},
	{.master = MT6761_M2_AXI_MST_LSCI_D, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x120,
		.note = "",
		.name = "MT6761_M2_AXI_MST_LSCI_D"},
	{.master = MT6761_M2_AXI_MST_AFO, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x124,
		.note = "",
		.name = "MT6761_M2_AXI_MST_AFO"},
	{.master = MT6761_M2_AXI_MST_AFO_D, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x128,
		.note = "",
		.name = "MT6761_M2_AXI_MST_AFO_D"},
	{.master = MT6761_M2_AXI_MST_BPCI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x12C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_BPCI"},
	{.master = MT6761_M2_AXI_MST_BPCI_D, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x130,
		.note = "",
		.name = "MT6761_M2_AXI_MST_BPCI_D"},
	{.master = MT6761_M2_AXI_MST_UFDI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x134,
		.note = "",
		.name = "MT6761_M2_AXI_MST_UFDI"},
	{.master = MT6761_M2_AXI_MST_IMGI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x138,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMGI"},
	{.master = MT6761_M2_AXI_MST_IMG2O, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x13C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMG2O"},
	{.master = MT6761_M2_AXI_MST_IMG3O, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x140,
		.note = "",
		.name = "MT6761_M2_AXI_MST_IMG3O"},
	{.master = MT6761_M2_AXI_MST_VIPI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x144,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VIPI"},
	{.master = MT6761_M2_AXI_MST_VIP2I, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x148,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VIP2I"},
	{.master = MT6761_M2_AXI_MST_VIP3I, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x14C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_VIP3I"},
	{.master = MT6761_M2_AXI_MST_LCEI, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x150,
		.note = "",
		.name = "MT6761_M2_AXI_MST_LCEI"},
	{.master = MT6761_M2_AXI_MST_RB, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x154,
		.note = "",
		.name = "MT6761_M2_AXI_MST_RB"},
	{.master = MT6761_M2_AXI_MST_RP, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x158,
		.note = "",
		.name = "MT6761_M2_AXI_MST_RP"},
	{.master = MT6761_M2_AXI_MST_WR, .port = 2, .id_mask = 0x1FFC,
		.id_val = 0x15C,
		.note = "",
		.name = "MT6761_M2_AXI_MST_WR"},
	{.master = MT6761_M3_AXI_MST_MD_MM, .port = 3, .id_mask = 0x1F83,
		.id_val = 0x0,
		.note = "",
		.name = "MT6761_M3_AXI_MST_MD_MM"},
	{.master = MT6761_M3_AXI_MST_MD_MMU, .port = 3, .id_mask = 0x1F83,
		.id_val = 0x1,
		.note = "",
		.name = "MT6761_M3_AXI_MST_MD_MMU"},
	{.master = MT6761_M3_AXI_MST_USIP_0_I, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0x2,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_0_I"},
	{.master = MT6761_M3_AXI_MST_USIP_0_DCACHE, .port = 3,
		.id_mask = 0x1F1F,
		.id_val = 0x6,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_0_DCACHE"},
	{.master = MT6761_M3_AXI_MST_USIP_0_DNOCACHE, .port = 3,
		.id_mask = 0x1F1F,
		.id_val = 0xA,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_0_DNOCACHE"},
	{.master = MT6761_M3_AXI_MST_USIP_1_I, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0x12,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_1_I"},
	{.master = MT6761_M3_AXI_MST_USIP_1_DCACHE, .port = 3,
		.id_mask = 0x1F1F,
		.id_val = 0x16,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_1_DCACHE"},
	{.master = MT6761_M3_AXI_MST_USIP_1_DNOCACHE, .port = 3,
		.id_mask = 0x1F1F,
		.id_val = 0x1A,
		.note = "",
		.name = "MT6761_M3_AXI_MST_USIP_1_DNOCACHE"},
	{.master = MT6761_M4_AXI_MST_HRQ_RD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1000,
		.note = "",
		.name = "MT6761_M4_AXI_MST_HRQ_RD"},
	{.master = MT6761_M4_AXI_MST_HRQ_RD1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1008,
		.note = "",
		.name = "MT6761_M4_AXI_MST_HRQ_RD1"},
	{.master = MT6761_M4_AXI_MST_HRQ_WR, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1002,
		.note = "",
		.name = "MT6761_M4_AXI_MST_HRQ_WR"},
	{.master = MT6761_M4_AXI_MST_HRQ_WR1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x100A,
		.note = "",
		.name = "MT6761_M4_AXI_MST_HRQ_WR1"},
	{.master = MT6761_M4_AXI_MST_VTB, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x100C,
		.note = "",
		.name = "MT6761_M4_AXI_MST_VTB"},
	{.master = MT6761_M4_AXI_MST_TBO, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1014,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TBO"},
	{.master = MT6761_M4_AXI_MST_DEBUG, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1004,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DEBUG"},
	{.master = MT6761_M4_AXI_MST_DFE_DUMP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x800,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DFE_DUMP"},
	{.master = MT6761_M4_AXI_MST_BR_DMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x802,
		.note = "",
		.name = "MT6761_M4_AXI_MST_BR_DMA"},
	{.master = MT6761_M4_AXI_MST_IRDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x10,
		.note = "",
		.name = "MT6761_M4_AXI_MST_IRDMA"},
	{.master = MT6761_M4_AXI_MST_TXBRP0, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x50,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TXBRP0"},
	{.master = MT6761_M4_AXI_MST_TXBRP1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x150,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TXBRP1"},
	{.master = MT6761_M4_AXI_MST_TXCAL, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xD0,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TXCAL"},
	{.master = MT6761_M4_AXI_MST_TPC, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1D0,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TPC"},
	{.master = MT6761_M4_AXI_MST_RXDFE_DMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x70,
		.note = "",
		.name = "MT6761_M4_AXI_MST_RXDFE_DMA"},
	{.master = MT6761_M4_AXI_MST_MRSG0, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xF0,
		.note = "",
		.name = "MT6761_M4_AXI_MST_MRSG0"},
	{.master = MT6761_M4_AXI_MST_MRSG1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x170,
		.note = "",
		.name = "MT6761_M4_AXI_MST_MRSG1"},
	{.master = MT6761_M4_AXI_MST_CNWDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x130,
		.note = "",
		.name = "MT6761_M4_AXI_MST_CNWDMA"},
	{.master = MT6761_M4_AXI_MST_CSH, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xB0,
		.note = "",
		.name = "MT6761_M4_AXI_MST_CSH"},
	{.master = MT6761_M4_AXI_MST_DCXO, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x30,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DCXO"},
	{.master = MT6761_M4_AXI_MST_DMA_RD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1804,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DMA_RD"},
	{.master = MT6761_M4_AXI_MST_DMA_WR, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1806,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DMA_WR"},
	{.master = MT6761_M4_AXI_MST_MMU, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1800,
		.note = "",
		.name = "MT6761_M4_AXI_MST_MMU"},
	{.master = MT6761_M4_AXI_MST_QP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1802,
		.note = "",
		.name = "MT6761_M4_AXI_MST_QP"},
	{.master = MT6761_M4_AXI_MST_LOG_TOP_MCU, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x24,
		.note = "",
		.name = "MT6761_M4_AXI_MST_LOG_TOP_MCU"},
	{.master = MT6761_M4_AXI_MST_LOG_TOP_DSP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x6,
		.note = "",
		.name = "MT6761_M4_AXI_MST_LOG_TOP_DSP"},
	{.master = MT6761_M4_AXI_MST_TRACE_TOP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x8,
		.note = "",
		.name = "MT6761_M4_AXI_MST_TRACE_TOP"},
	{.master = MT6761_M4_AXI_MST_PPPHA, .port = 4, .id_mask = 0x1FDF,
		.id_val = 0x2,
		.note = "",
		.name = "MT6761_M4_AXI_MST_PPPHA"},
	{.master = MT6761_M4_AXI_MST_IPSEC, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xA,
		.note = "",
		.name = "MT6761_M4_AXI_MST_IPSEC"},
	{.master = MT6761_M4_AXI_MST_GDMA, .port = 4, .id_mask = 0x1E3F,
		.id_val = 0xE,
		.note = "",
		.name = "MT6761_M4_AXI_MST_GDMA"},
	{.master = MT6761_M4_AXI_MST_DBGSYS, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xE,
		.note = "",
		.name = "MT6761_M4_AXI_MST_DBGSYS"},
	{.master = MT6761_M4_AXI_MST_MCUSYS_DFD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1,
		.note = "",
		.name = "MT6761_M4_AXI_MST_MCUSYS_DFD"},
	{.master = MT6761_M5_AXI_MST_DISP_OVL0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x0,
		.note = "",
		.name = "MT6761_M5_AXI_MST_DISP_OVL0"},
	{.master = MT6761_M5_AXI_MST_DISP_OVL0_2L, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x4,
		.note = "",
		.name = "MT6761_M5_AXI_MST_DISP_OVL0_2L"},
	{.master = MT6761_M5_AXI_MST_DISP_RDMA0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x8,
		.note = "",
		.name = "MT6761_M5_AXI_MST_DISP_RDMA0"},
	{.master = MT6761_M5_AXI_MST_DISP_WDMA0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0xC,
		.note = "",
		.name = "MT6761_M5_AXI_MST_DISP_WDMA0"},
	{.master = MT6761_M5_AXI_MST_MDP_RDMA0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x10,
		.note = "",
		.name = "MT6761_M5_AXI_MST_MDP_RDMA0"},
	{.master = MT6761_M5_AXI_MST_MDP_WDMA0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x14,
		.note = "",
		.name = "MT6761_M5_AXI_MST_MDP_WDMA0"},
	{.master = MT6761_M5_AXI_MST_MDP_WROT0, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x18,
		.note = "",
		.name = "MT6761_M5_AXI_MST_MDP_WROT0"},
	{.master = MT6761_M5_AXI_MST_DISP_FAKE, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x1C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_DISP_FAKE"},
	{.master = MT6761_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x80,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT"},
	{.master = MT6761_M5_AXI_MST_VENC_REC, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x84,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_REC"},
	{.master = MT6761_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x88,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT"},
	{.master = MT6761_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
		.port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x8C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT"},
	{.master = MT6761_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
		.port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x90,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT"},
	{.master = MT6761_M5_AXI_MST_JPGENC_RDMA, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x94,
		.note = "",
		.name = "MT6761_M5_AXI_MST_JPGENC_RDMA"},
	{.master = MT6761_M5_AXI_MST_JPGENC_BSDMA, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x98,
		.note = "",
		.name = "MT6761_M5_AXI_MST_JPGENC_BSDMA"},
	{.master = MT6761_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0x9C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT"},
	{.master = MT6761_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
		.port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0xA0,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT"
	},
	{.master = MT6761_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
		.port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0xA4,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT"},
	{.master = MT6761_M5_AXI_MST_VENC_REF_CHROMA, .port = 5,
		.id_mask = 0x1FFC,
		.id_val = 0xA8,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VENC_REF_CHROMA"},
	{.master = MT6761_M5_AXI_MST_IMGO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x100,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMGO"},
	{.master = MT6761_M5_AXI_MST_RRZO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x104,
		.note = "",
		.name = "MT6761_M5_AXI_MST_RRZO"},
	{.master = MT6761_M5_AXI_MST_AAO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x108,
		.note = "",
		.name = "MT6761_M5_AXI_MST_AAO"},
	{.master = MT6761_M5_AXI_MST_LCSO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x10C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_LCSO"},
	{.master = MT6761_M5_AXI_MST_ESFKO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x110,
		.note = "",
		.name = "MT6761_M5_AXI_MST_ESFKO"},
	{.master = MT6761_M5_AXI_MST_IMGO_S, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x114,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMGO_S"},
	{.master = MT6761_M5_AXI_MST_IMGO_S2, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x118,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMGO_S2"},
	{.master = MT6761_M5_AXI_MST_LSCI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x11C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_LSCI"},
	{.master = MT6761_M5_AXI_MST_LSCI_D, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x120,
		.note = "",
		.name = "MT6761_M5_AXI_MST_LSCI_D"},
	{.master = MT6761_M5_AXI_MST_AFO, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x124,
		.note = "",
		.name = "MT6761_M5_AXI_MST_AFO"},
	{.master = MT6761_M5_AXI_MST_AFO_D, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x128,
		.note = "",
		.name = "MT6761_M5_AXI_MST_AFO_D"},
	{.master = MT6761_M5_AXI_MST_BPCI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x12C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_BPCI"},
	{.master = MT6761_M5_AXI_MST_BPCI_D, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x130,
		.note = "",
		.name = "MT6761_M5_AXI_MST_BPCI_D"},
	{.master = MT6761_M5_AXI_MST_UFDI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x134,
		.note = "",
		.name = "MT6761_M5_AXI_MST_UFDI"},
	{.master = MT6761_M5_AXI_MST_IMGI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x138,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMGI"},
	{.master = MT6761_M5_AXI_MST_IMG2O, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x13C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMG2O"},
	{.master = MT6761_M5_AXI_MST_IMG3O, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x140,
		.note = "",
		.name = "MT6761_M5_AXI_MST_IMG3O"},
	{.master = MT6761_M5_AXI_MST_VIPI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x144,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VIPI"},
	{.master = MT6761_M5_AXI_MST_VIP2I, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x148,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VIP2I"},
	{.master = MT6761_M5_AXI_MST_VIP3I, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x14C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_VIP3I"},
	{.master = MT6761_M5_AXI_MST_LCEI, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x150,
		.note = "",
		.name = "MT6761_M5_AXI_MST_LCEI"},
	{.master = MT6761_M5_AXI_MST_RB, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x154,
		.note = "",
		.name = "MT6761_M5_AXI_MST_RB"},
	{.master = MT6761_M5_AXI_MST_RP, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x158,
		.note = "",
		.name = "MT6761_M5_AXI_MST_RP"},
	{.master = MT6761_M5_AXI_MST_WR, .port = 5, .id_mask = 0x1FFC,
		.id_val = 0x15C,
		.note = "",
		.name = "MT6761_M5_AXI_MST_WR"},
	{.master = MT6761_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
		.id_val = 0x3FC,
		.note = "",
		.name = "MT6761_M5_AXI_MST_MM_IOMMU"},
	{.master = MT6761_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
		.id_val = 0x3FD,
		.note = "",
		.name = "MT6761_M5_AXI_MST_MM_IOMMU"},
	{.master = MT6761_M6_AXI_MST_MFG_M0, .port = 6, .id_mask = 0x1FC0,
		.id_val = 0x0,
		.note = "",
		.name = "MT6761_M6_AXI_MST_MFG_M0"},
	{.master = MT6761_M7_AXI_MST_CONNSYS_WIFI_PDMA, .port = 7,
		.id_mask = 0x1FEF,
		.id_val = 0x0,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CONNSYS_WIFI_PDMA"},
	{.master = MT6761_M7_AXI_MST_CONNSYS_RBIST_INTERNAL_CAPTURE, .port = 7,
		.id_mask = 0x1FEF,
		.id_val = 0x4,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CONNSYS_RBIST_INTERNAL_CAPTURE"},
	{.master = MT6761_M7_AXI_MST_CONNSYS_N9_MCU_RW, .port = 7,
		.id_mask = 0x1FEF,
		.id_val = 0x8,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CONNSYS_N9_MCU_RW"},
	{.master = MT6761_M7_AXI_MST_CONNSYS_NA, .port = 7, .id_mask = 0x1FEF,
		.id_val = 0xC,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CONNSYS_NA"},
	{.master = MT6761_M7_AXI_MST_DEBUGTOP, .port = 7, .id_mask = 0x1FDF,
		.id_val = 0x2,
		.note = "",
		.name = "MT6761_M7_AXI_MST_DEBUGTOP"},
	{.master = MT6761_M7_AXI_MST_MSDC0, .port = 7, .id_mask = 0x1CFF,
		.id_val = 0x6,
		.note = "",
		.name = "MT6761_M7_AXI_MST_MSDC0"},
	{.master = MT6761_M7_AXI_MST_SPI0, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x326,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI0"},
	{.master = MT6761_M7_AXI_MST_AUDIO, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x226,
		.note = "",
		.name = "MT6761_M7_AXI_MST_AUDIO"},
	{.master = MT6761_M7_AXI_MST_MSDC1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x126,
		.note = "",
		.name = "MT6761_M7_AXI_MST_MSDC1"},
	{.master = MT6761_M7_AXI_MST_PWM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x26,
		.note = "",
		.name = "MT6761_M7_AXI_MST_PWM"},
	{.master = MT6761_M7_AXI_MST_USB20, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x46,
		.note = "",
		.name = "MT6761_M7_AXI_MST_USB20"},
	{.master = MT6761_M7_AXI_MST_SPI1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x346,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI1"},
	{.master = MT6761_M7_AXI_MST_SPI2, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x246,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI2"},
	{.master = MT6761_M7_AXI_MST_THERM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x366,
		.note = "",
		.name = "MT6761_M7_AXI_MST_THERM"},
	{.master = MT6761_M7_AXI_MST_CCU, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x266,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CCU"},
	{.master = MT6761_M7_AXI_MST_SPM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x166,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPM"},
	{.master = MT6761_M7_AXI_MST_MCUPM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x66,
		.note = "",
		.name = "MT6761_M7_AXI_MST_MCUPM"},
	{.master = MT6761_M7_AXI_MST_DMA_EXT, .port = 7, .id_mask = 0x1EFF,
		.id_val = 0x86,
		.note = "",
		.name = "MT6761_M7_AXI_MST_DMA_EXT"},
	{.master = MT6761_M7_AXI_MST_SPI5, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x3A6,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI5"},
	{.master = MT6761_M7_AXI_MST_SPI4, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x2A6,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI4"},
	{.master = MT6761_M7_AXI_MST_SPI3, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x1A6,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SPI3"},
	{.master = MT6761_M7_AXI_MST_DX_CC, .port = 7, .id_mask = 0x1E1F,
		.id_val = 0xE,
		.note = "",
		.name = "MT6761_M7_AXI_MST_DX_CC"},
	{.master = MT6761_M7_AXI_MST_CQ_DMA, .port = 7, .id_mask = 0x1F1F,
		.id_val = 0x12,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CQ_DMA"},
	{.master = MT6761_M7_AXI_MST_CLDMA, .port = 7, .id_mask = 0x1F9F,
		.id_val = 0x16,
		.note = "",
		.name = "MT6761_M7_AXI_MST_CLDMA"},
	{.master = MT6761_M7_AXI_MST_GCE_M, .port = 7, .id_mask = 0x1F9F,
		.id_val = 0x1A,
		.note = "",
		.name = "MT6761_M7_AXI_MST_GCE_M"},
	{.master = MT6761_M7_AXI_MST_SCP, .port = 7, .id_mask = 0x1F3F,
		.id_val = 0x1E,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SCP"},
	{.master = MT6761_M7_AXI_MST_SSPM, .port = 7, .id_mask = 0x1F3F,
		.id_val = 0x3E,
		.note = "",
		.name = "MT6761_M7_AXI_MST_SSPM"},
	{.master = MT6761_M7_AXI_MST_GPU, .port = 7, .id_mask = 0x1F81,
		.id_val = 0x1,
		.note = "",
		.name = "MT6761_M7_AXI_MST_GPU"},
};

#endif /* __MPU_PLATFORM_H__ */