81 lines
1.8 KiB
C
81 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_EMI_BW_LIMITER__
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#define __MT_EMI_BW_LIMITER__
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/*
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* Define EMI hardware registers.
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*/
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#define EMI_CONM (CEN_EMI_BASE + 0x0060)
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#define EMI_MDCT (CEN_EMI_BASE + 0x0078)
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#define EMI_ARBA (CEN_EMI_BASE + 0x0100)
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#define EMI_ARBB (CEN_EMI_BASE + 0x0108)
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#define EMI_ARBC (CEN_EMI_BASE + 0x0110)
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#define EMI_ARBD (CEN_EMI_BASE + 0x0118)
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#define EMI_ARBE (CEN_EMI_BASE + 0x0120)
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#define EMI_ARBF (CEN_EMI_BASE + 0x0128)
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#define EMI_ARBG (CEN_EMI_BASE + 0x0130)
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#define EMI_ARBH (CEN_EMI_BASE + 0x0138)
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/*
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* Define constants.
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*/
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#define MAX_CH 2
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#define MAX_RK 2
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/* define concurrency scenario ID */
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enum {
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#define X_CON_SCE(con_sce, arba, arbb, arbc, arbd, arbe, arbf, arbg, arbh, \
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conm, mdct) con_sce,
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#include "con_sce_lpddr3.h"
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#undef X_CON_SCE
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NR_CON_SCE
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};
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/* define control operation */
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enum {
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ENABLE_CON_SCE = 0,
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DISABLE_CON_SCE = 1
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};
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#define EN_CON_SCE_STR "ON"
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#define DIS_CON_SCE_STR "OFF"
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/*
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* Define data structures.
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*/
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/* define control table entry */
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struct emi_bwl_ctrl {
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unsigned int ref_cnt;
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};
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struct emi_info_t {
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unsigned int dram_type;
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unsigned int ch_num;
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unsigned int rk_num;
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unsigned int rank_size[MAX_RK];
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};
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/*
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* Define function prototype.
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*/
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extern int mtk_mem_bw_ctrl(int sce, int op);
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extern unsigned int get_ch_num(void);
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extern unsigned int get_rk_num(void);
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extern unsigned int get_rank_size(unsigned int rank_index); /* unit: all channels */
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extern unsigned int get_dram_type(void);
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extern void __iomem *mt_emi_base_get(void); /* legacy API */
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extern void __iomem *mt_cen_emi_base_get(void);
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extern void __iomem *mt_chn_emi_base_get(void);
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extern void __iomem *mt_emi_mpu_base_get(void);
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extern unsigned int mt_emi_mpu_irq_get(void);
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#endif /* !__MT_EMI_BWL_H__ */
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