321 lines
7.6 KiB
C
321 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2011 MediaTek Inc.
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*/
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/*#include <mach/mt_typedefs.h>
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* #include <mach/mt_reg_base.h>
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*/
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#include "sec_error.h"
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#include "hacc_mach.h"
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#include <linux/io.h>
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/******************************************************************************
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* this file contains the hardware secure engine low-level operations
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* note that : all the functions in this file are ONLY for HACC internal usages.
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******************************************************************************/
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/******************************************************************************
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* CONSTANT DEFINITIONS
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******************************************************************************/
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#define MOD "HACC"
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#define HACC_TEST (0)
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/******************************************************************************
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* DEBUG
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******************************************************************************/
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#define SEC_DEBUG (0)
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#define SMSG
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#define DMSG
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#if SEC_DEBUG
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#else
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#define DMSG
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#endif
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/******************************************************************************
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* LOCAL VERIABLE
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******************************************************************************/
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static struct hacc_context hacc_ctx;
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/******************************************************************************
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* LOCAL FUNCTIONS
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******************************************************************************/
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#if HACC_TEST
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static void hacc_test(void)
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{
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unsigned int i, test_sz = HACC_AES_MAX_KEY_SZ * 24;
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unsigned int test_keysz = AES_KEY_256;
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unsigned char *test_src = (unsigned char *)HACC_AES_TEST_SRC;
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unsigned char *test_dst = (unsigned char *)HACC_AES_TEST_DST;
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unsigned char *test_tmp = (unsigned char *)HACC_AES_TEST_TMP;
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/* prepare data */
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for (i = 0; i < test_sz; i++)
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test_src[i] = i + 1;
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hacc_set_key(AES_HW_WRAP_KEY, test_keysz);
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hacc_do_aes(AES_ENC, test_src, test_tmp, test_sz);
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hacc_set_key(AES_HW_WRAP_KEY, test_keysz);
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hacc_do_aes(AES_DEC, test_tmp, test_dst, test_sz);
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for (i = 0; i < test_sz; i++) {
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if (test_src[i] != test_dst[i]) {
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DMSG("[%s] mismatch at %d, ", MOD, i);
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DMSG("src = 0x%x, ", test_src[i]);
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DMSG("dst = 0x%x\n", test_dst[i]);
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}
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}
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DMSG("[%s] encrypt & descrypt unit test pass. (Key = %dbits)\n",
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MOD,
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test_keysz << 3);
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}
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#else
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#define hacc_test() do {} while (0)
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#endif
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/******************************************************************************
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* GLOBAL FUNCTIONS
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******************************************************************************/
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static unsigned int hacc_set_cfg(struct aes_cfg *cfg)
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{
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memcpy(&hacc_ctx.cfg, cfg, sizeof(struct aes_cfg));
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return SEC_OK;
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}
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static unsigned int hacc_set_mode(enum aes_mode mode)
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{
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struct aes_cfg cfg;
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writel(readl((const void *)HACC_ACON) & ~(HACC_AES_MODE_MASK),
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(void *)HACC_ACON);
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switch (mode) {
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case AES_ECB_MODE:
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/* no need cfg */
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memset(&cfg.config[0], 0, sizeof(cfg.config));
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writel(readl((const void *)HACC_ACON) | HACC_AES_ECB,
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(void *)HACC_ACON);
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break;
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case AES_CBC_MODE:
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writel(readl((const void *)HACC_ACON) | HACC_AES_CBC,
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(void *)HACC_ACON);
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break;
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default:
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return ERR_HACC_MODE_INVALID;
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}
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return SEC_OK;
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}
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unsigned int hacc_set_key(enum aes_key_id id, enum aes_key key)
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{
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unsigned int i, acon = 0;
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unsigned int akey;
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unsigned char *tkey;
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switch (key) {
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case AES_KEY_128:
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acon |= HACC_AES_128;
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break;
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case AES_KEY_192:
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acon |= HACC_AES_192;
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break;
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case AES_KEY_256:
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acon |= HACC_AES_256;
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break;
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default:
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return ERR_HACC_KEY_INVALID;
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}
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/* set aes block size */
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hacc_ctx.blk_sz = key;
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/* set aes key length */
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writel(readl((const void *)HACC_ACON) & ~(HACC_AES_TYPE_MASK),
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(void *)HACC_ACON);
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writel(readl((const void *)HACC_ACON) | acon, (void *)HACC_ACON);
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/* clear key */
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for (i = 0; i < HACC_AES_MAX_KEY_SZ; i += 4)
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writel(0, (void *)(HACC_AKEY0 + i));
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/* set aes key */
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switch (id) {
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case AES_HW_KEY:
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writel(readl((const void *)HACC_ACONK) | HACC_AES_BK2C,
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(void *)HACC_ACONK);
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return 0;
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case AES_HW_WRAP_KEY:
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tkey = &hacc_ctx.hw_key[0];
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break;
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case AES_SW_KEY:
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default:
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tkey = &hacc_ctx.sw_key[0];
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break;
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}
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/* non hardware binding key */
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writel(readl((const void *)HACC_ACONK) & ~(HACC_AES_BK2C),
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(void *)HACC_ACONK);
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/* update key. note that don't use key directly */
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for (i = 0; i < HACC_AES_MAX_KEY_SZ; i += 4) {
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akey = (tkey[i] << 24) |
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(tkey[i + 1] << 16) |
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(tkey[i + 2] << 8) |
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(tkey[i + 3]);
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writel(akey, (void *)(HACC_AKEY0 + i));
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}
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return SEC_OK;
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}
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unsigned int hacc_do_aes(enum aes_ops ops,
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unsigned char *src,
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unsigned char *dst,
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unsigned int size)
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{
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unsigned int i;
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unsigned int *ds, *dt, *vt;
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/* make sure size is aligned to aes block size */
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if ((size % AES_BLK_SZ) != 0) {
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SMSG("[%s] size = %d is not %d bytes alignment\n",
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MOD,
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size,
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AES_BLK_SZ);
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return ERR_HACC_DATA_UNALIGNED;
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}
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vt = (unsigned int *)&hacc_ctx.cfg.config[0];
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/* erase src, cfg, out register */
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writel(readl((const void *)HACC_ACON2) | HACC_AES_CLR,
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(void *)HACC_ACON2);
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/* set init config */
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for (i = 0; i < AES_CFG_SZ; i += 4)
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writel(*vt++, (void *)(HACC_ACFG0 + i));
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if (ops == AES_ENC)
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writel(readl((const void *)HACC_ACON) | HACC_AES_ENC,
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(void *)HACC_ACON);
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else
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writel(readl((const void *)HACC_ACON) & ~HACC_AES_ENC,
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(void *)HACC_ACON);
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ds = (unsigned int *)src;
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dt = (unsigned int *)dst;
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do {
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/* fill in the data */
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for (i = 0; i < AES_BLK_SZ; i += 4)
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writel(*ds++, (void *)(HACC_ASRC0 + i));
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/* start aes engine */
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writel(readl((const void *)HACC_ACON2) | HACC_AES_START,
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(char *)HACC_ACON2);
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/* wait for aes engine ready */
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while ((readl((const void *)HACC_ACON2) & HACC_AES_RDY) == 0)
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;
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/* read out the data */
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for (i = 0; i < AES_BLK_SZ; i += 4)
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* dt++ = readl((const void *)(HACC_AOUT0 + i));
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if (size == 0)
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goto end;
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size -= AES_BLK_SZ;
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} while (size != 0);
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end:
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return SEC_OK;
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}
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unsigned int hacc_deinit(void)
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{
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unsigned int ret = 0;
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/* clear aes module */
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writel(readl((const void *)HACC_ACON2) | HACC_AES_CLR,
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(void *)HACC_ACON2);
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return ret;
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}
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unsigned int hacc_init(struct aes_key_seed *keyseed)
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{
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unsigned int i = 0;
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unsigned int *config;
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unsigned int ret = 0;
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hacc_deinit();
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/* clear aes module */
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writel(readl((const void *)HACC_ACON2) | HACC_AES_CLR,
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(void *)HACC_ACON2);
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/* set aes module in cbc mode with no byte order change */
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writel(readl((const void *)HACC_ACON2) &
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~(HACC_AES_CHG_BO_MASK |
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HACC_AES_MODE_MASK),
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(void *)HACC_ACON2);
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writel(readl((const void *)HACC_ACON2) |
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(HACC_AES_CHG_BO_OFF |
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HACC_AES_CBC),
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(void *)HACC_ACON2);
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/* aes secure initialiation */
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memset(&hacc_ctx, 0, sizeof(struct hacc_context));
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for (i = 0; i < keyseed->size; i++)
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hacc_ctx.sw_key[i] = keyseed->seed[i];
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config = (unsigned int *)&hacc_ctx.cfg.config[0];
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*config++ = HACC_CFG_0;
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*config++ = HACC_CFG_1;
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*config++ = HACC_CFG_2;
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*config = HACC_CFG_3;
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ret = hacc_set_cfg(&hacc_ctx.cfg);
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if (ret != SEC_OK)
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goto end;
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ret = hacc_set_mode(AES_CBC_MODE);
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if (ret != SEC_OK)
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goto end;
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/* derive the hardware wrapper key */
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ret = hacc_set_key(AES_HW_KEY, HACC_HW_KEY_SZ);
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if (ret != SEC_OK)
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goto end;
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ret = hacc_do_aes(AES_ENC,
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&hacc_ctx.sw_key[0],
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&hacc_ctx.hw_key[0],
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AES_KEY_256);
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if (ret != SEC_OK)
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goto end;
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ret = hacc_set_key(AES_HW_WRAP_KEY, AES_KEY_256);
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if (ret != SEC_OK)
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goto end;
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hacc_test();
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/* from now on, HACC HW wrap key can be used */
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bHACC_HWWrapKeyInit = 1;
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/* from now on, HACC SW key can be used */
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bHACC_SWKeyInit = 1;
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end:
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return ret;
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}
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