54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MDP_BASE_H__
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#define __MDP_BASE_H__
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#define MDP_HW_CHECK
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#include "mach/mt_iommu.h"
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static u32 mdp_engine_port[ENGBASE_COUNT] = {
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0, //ENGBASE_MMSYS_CONFIG,
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M4U_PORT_L2_MDP_RDMA0, //ENGBASE_MDP_RDMA0,
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0, //ENGBASE_MDP_AAL0,
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0, //ENGBASE_MDP_HDR0,
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0, //ENGBASE_MDP_RSZ0,
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0, //ENGBASE_MDP_RSZ1,
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M4U_PORT_L2_MDP_WROT0, //ENGBASE_MDP_WROT0,
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M4U_PORT_L2_MDP_WROT1, //ENGBASE_MDP_WROT1,
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0, //ENGBASE_MDP_TDSHP0,
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0, //ENGBASE_MMSYS_MUTEX,
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0, //ENGINE_IMGSYS
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0, //ENGINE_IMGSYS2_CONFIG
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0, //ENGBASE_ISP_DIP_A0
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0, //ENGBASE_ISP_DIP_A1
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0, //ENGBASE_ISP_DIP_A7
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0, //ENGBASE_ISP_MSS_B
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0, //ENGBASE_ISP_MFB_B
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};
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static u32 mdp_base[ENGBASE_COUNT] = {
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[ENGBASE_MMSYS_CONFIG] = 0x1b000000,
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[ENGBASE_MDP_RDMA0] = 0x1b003000,
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[ENGBASE_MDP_AAL0] = 0x1b005000,
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[ENGBASE_MDP_HDR0] = 0x1b007000,
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[ENGBASE_MDP_RSZ0] = 0x1b008000,
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[ENGBASE_MDP_RSZ1] = 0x1b009000,
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[ENGBASE_MDP_WROT0] = 0x1b00a000,
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[ENGBASE_MDP_WROT1] = 0x1b00b000,
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[ENGBASE_MDP_TDSHP0] = 0x1b00c000,
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[ENGBASE_MMSYS_MUTEX] = 0x1b001000,
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[ENGBASE_IMGSYS] = 0x15020000,
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[ENGBASE_IMGSYS2_CONFIG] = 0x15820000,
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[ENGBASE_ISP_DIP_A0] = 0x15021000,
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[ENGBASE_ISP_DIP_A1] = 0x15022000,
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[ENGBASE_ISP_DIP_A7] = 0x15028000,
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[ENGBASE_ISP_MSS_B] = 0x15812000,
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[ENGBASE_ISP_MFB_B] = 0x15810000,
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};
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#endif
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