292 lines
10 KiB
C
292 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __LINUX_MFD_MT6370_PMU_H
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#define __LINUX_MFD_MT6370_PMU_H
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#include <mt-plat/rt-regmap.h>
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#include <linux/rtmutex.h>
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#include <linux/interrupt.h>
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#define mt_dbg(dev, fmt, ...) \
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do { \
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if (dbg_log_en) \
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dev_dbg(dev, fmt, ##__VA_ARGS__); \
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} while (0)
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enum {
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MT6370_PMU_COREDEV,
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MT6370_PMU_CHGDEV,
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MT6370_PMU_FLEDDEV1,
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MT6370_PMU_FLEDDEV2,
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MT6370_PMU_LDODEV,
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MT6370_PMU_RGBLEDDEV,
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MT6370_PMU_BLEDDEV,
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MT6370_PMU_DSVDEV,
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MT6370_PMU_DEV_MAX,
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};
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struct mt6370_pmu_irq_desc {
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const char *name;
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irq_handler_t irq_handler;
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int irq;
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};
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#define MT6370_PMU_IRQDESC(name) { #name, mt6370_pmu_##name##_irq_handler, -1}
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struct mt6370_pmu_platform_data {
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int intr_gpio;
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void *platform_data[MT6370_PMU_DEV_MAX];
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size_t pdata_size[MT6370_PMU_DEV_MAX];
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const char **irq_enable[MT6370_PMU_DEV_MAX];
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int num_irq_enable[MT6370_PMU_DEV_MAX];
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};
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struct mt6370_pmu_chip {
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struct i2c_client *i2c;
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struct device *dev;
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struct irq_domain *irq_domain;
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struct rt_regmap_device *rd;
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struct mutex io_lock;
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int irq;
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uint8_t chip_rev;
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uint8_t chip_vid;
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};
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#define RT5081_VENDOR_ID (0x80)
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#define MT6370_VENDOR_ID (0xE0)
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#define MT6371_VENDOR_ID (0xF0)
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#define MT6372_VENDOR_ID (0x90)
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#define MT6372C_VENDOR_ID (0xB0)
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/* core control */
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#define MT6370_PMU_REG_DEVINFO (0x00)
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#define MT6370_PMU_REG_CORECTRL1 (0x01)
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#define MT6370_PMU_REG_CORECTRL2 (0x02)
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#define MT6370_PMU_REG_RSTPASCODE1 (0x03)
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#define MT6370_PMU_REG_RSTPASCODE2 (0x04)
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#define MT6370_PMU_REG_HIDDENPASCODE1 (0x07)
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#define MT6370_PMU_REG_HIDDENPASCODE2 (0x08)
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#define MT6370_PMU_REG_HIDDENPASCODE3 (0x09)
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#define MT6370_PMU_REG_HIDDENPASCODE4 (0x0A)
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#define MT6370_PMU_REG_IRQIND (0x0B)
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#define MT6370_PMU_REG_IRQMASK (0x0C)
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#define MT6370_PMU_REG_IRQSET (0x0D)
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#define MT6370_PMU_REG_SHDNCTRL1 (0x0E)
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#define MT6370_PMU_REG_SHDNCTRL2 (0x0F)
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#define MT6370_PMU_REG_OSCCTRL (0x10)
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/* charger control */
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#define MT6370_PMU_REG_CHGCTRL1 (0x11)
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#define MT6370_PMU_REG_CHGCTRL2 (0x12)
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#define MT6370_PMU_REG_CHGCTRL3 (0x13)
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#define MT6370_PMU_REG_CHGCTRL4 (0x14)
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#define MT6370_PMU_REG_CHGCTRL5 (0x15)
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#define MT6370_PMU_REG_CHGCTRL6 (0x16)
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#define MT6370_PMU_REG_CHGCTRL7 (0x17)
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#define MT6370_PMU_REG_CHGCTRL8 (0x18)
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#define MT6370_PMU_REG_CHGCTRL9 (0x19)
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#define MT6370_PMU_REG_CHGCTRL10 (0x1A)
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#define MT6370_PMU_REG_CHGCTRL11 (0x1B)
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#define MT6370_PMU_REG_CHGCTRL12 (0x1C)
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#define MT6370_PMU_REG_CHGCTRL13 (0x1D)
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#define MT6370_PMU_REG_CHGCTRL14 (0x1E)
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#define MT6370_PMU_REG_CHGCTRL15 (0x1F)
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#define MT6370_PMU_REG_CHGCTRL16 (0x20)
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#define MT6370_PMU_REG_CHGADC (0x21)
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#define MT6370_PMU_REG_DEVICETYPE (0x22)
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#define MT6370_PMU_REG_QCCTRL1 (0x23)
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#define MT6370_PMU_REG_QCCTRL2 (0x24)
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#define MT6370_PMU_REG_QC3P0CTRL1 (0x25)
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#define MT6370_PMU_REG_QC3P0CTRL2 (0x26)
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#define MT6370_PMU_REG_USBSTATUS1 (0x27)
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#define MT6370_PMU_REG_QCSTATUS1 (0x28)
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#define MT6370_PMU_REG_QCSTATUS2 (0x29)
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#define MT6370_PMU_REG_CHGPUMP (0x2A)
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#define MT6370_PMU_REG_CHGCTRL17 (0x2B)
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#define MT6370_PMU_REG_CHGCTRL18 (0x2C)
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#define MT6370_PMU_REG_CHGDIRCHG1 (0x2D)
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#define MT6370_PMU_REG_CHGDIRCHG2 (0x2E)
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#define MT6370_PMU_REG_CHGDIRCHG3 (0x2F)
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#define MT6370_PMU_REG_CHGHIDDENCTRL0 (0x30)
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#define MT6370_PMU_REG_CHGHIDDENCTRL1 (0x31)
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#define MT6370_PMU_REG_LG_CONTROL (0x33)
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#define MT6370_PMU_REG_CHGHIDDENCTRL6 (0x35)
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#define MT6370_PMU_REG_CHGHIDDENCTRL7 (0x36)
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#define MT6370_PMU_REG_CHGHIDDENCTRL8 (0x37)
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#define MT6370_PMU_REG_CHGHIDDENCTRL9 (0x38)
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#define MT6370_PMU_REG_CHGHIDDENCTRL15 (0x3E)
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#define MT6370_PMU_REG_CHGHIDDENCTRL22 (0x45)
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#define MT6370_PMU_REG_CHGSTAT (0x4A)
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#define MT6370_PMU_REG_CHGNTC (0x4B)
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#define MT6370_PMU_REG_ADCDATAH (0x4C)
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#define MT6370_PMU_REG_ADCDATAL (0x4D)
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#define MT6370_PMU_REG_ADCDATATUNEH (0x4E)
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#define MT6370_PMU_REG_ADCDATATUNEL (0x4F)
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#define MT6370_PMU_REG_ADCDATAORGH (0x50)
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#define MT6370_PMU_REG_ADCDATAORGL (0x51)
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#define MT6370_PMU_REG_ADCBATDATAH (0x52)
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#define MT6370_PMU_REG_ADCBATDATAL (0x53)
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#define MT6370_PMU_REG_CHGCTRL19 (0x60)
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#define MT6370_PMU_REG_OVPCTRL (0x61)
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#define MT6370_PMU_REG_VDDASUPPLY (0x62)
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/* flashled control */
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#define MT6370_PMU_REG_FLEDCFG (0x70)
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#define MT6370_PMU_REG_FLED1CTRL (0x72)
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#define MT6370_PMU_REG_FLEDSTRBCTRL (0x73)
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#define MT6370_PMU_REG_FLED1STRBCTRL (0x74)
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#define MT6370_PMU_REG_FLED1TORCTRL (0x75)
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#define MT6370_PMU_REG_FLED2CTRL (0x76)
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#define MT6370_PMU_REG_FLED2STRBCTRL2 (0x78)
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#define MT6370_PMU_REG_FLED2TORCTRL (0x79)
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#define MT6370_PMU_REG_FLEDVMIDTRKCTRL1 (0x7A)
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#define MT6370_PMU_REG_FLEDVMIDRTM (0x7B)
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#define MT6370_PMU_REG_FLEDVMIDTRKCTRL2 (0x7C)
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#define MT6370_PMU_REG_FLEDEN (0x7E)
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/* ldo control */
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#define MT6370_PMU_REG_LDOCFG (0x80)
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#define MT6370_PMU_REG_LDOVOUT (0x81)
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/* rgb control */
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#define MT6370_PMU_REG_RGB1DIM (0x82)
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#define MT6370_PMU_REG_RGB2DIM (0x83)
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#define MT6370_PMU_REG_RGB3DIM (0x84)
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#define MT6370_PMU_REG_RGBEN (0x85)
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#define MT6370_PMU_REG_RGB1ISINK (0x86)
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#define MT6370_PMU_REG_RGB2ISINK (0x87)
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#define MT6370_PMU_REG_RGB3ISINK (0x88)
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#define MT6370_PMU_REG_RGB1TR (0x89)
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#define MT6370_PMU_REG_RGB1TF (0x8A)
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#define MT6370_PMU_REG_RGB1TONTOFF (0x8B)
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#define MT6370_PMU_REG_RGB2TR (0x8C)
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#define MT6370_PMU_REG_RGB2TF (0x8D)
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#define MT6370_PMU_REG_RGB2TONTOFF (0x8E)
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#define MT6370_PMU_REG_RGB3TR (0x8F)
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#define MT6370_PMU_REG_RGB3TF (0x90)
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#define MT6370_PMU_REG_RGB3TONTOFF (0x91)
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#define MT6370_PMU_REG_RGBCHRINDDIM (0x92)
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#define MT6370_PMU_REG_RGBCHRINDCTRL (0x93)
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#define MT6370_PMU_REG_RGBCHRINDTR (0x94)
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#define MT6370_PMU_REG_RGBCHRINDTF (0x95)
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#define MT6370_PMU_REG_RGBCHRINDTONTOFF (0x96)
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#define MT6370_PMU_REG_RGBOPENSHORTEN (0x97)
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#define MT6370_PMU_REG_RGBTONTOFF (0x98)
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#define MT6370_PMU_REG_RGBHIDDEN1 (0x99)
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#define MT6370_PMU_REG_RGBHIDDEN2 (0x9A)
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#define MT6370_PMU_REG_RESERVED1 (0x9F)
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/* backlight control */
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#define MT6370_PMU_REG_BLEN (0xA0)
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#define MT6370_PMU_REG_BLBSTCTRL (0xA1)
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#define MT6370_PMU_REG_BLPWM (0xA2)
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#define MT6370_PMU_REG_BLCTRL (0xA3)
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#define MT6370_PMU_REG_BLDIM2 (0xA4)
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#define MT6370_PMU_REG_BLDIM1 (0xA5)
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#define MT6370_PMU_REG_BLAFH (0xA6)
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#define MT6370_PMU_REG_BLFL (0xA7)
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#define MT6370_PMU_REG_BLFLTO (0xA8)
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#define MT6370_PMU_REG_BLTORCTRL (0xA9)
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#define MT6370_PMU_REG_BLSTRBCTRL (0xAA)
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#define MT6370_PMU_REG_BLAVG (0xAB)
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#define MT6370_PMU_REG_BLMODECTRL (0xAD)
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/* display bias control */
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#define MT6370_PMU_REG_DBCTRL1 (0xB0)
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#define MT6370_PMU_REG_DBCTRL2 (0xB1)
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#define MT6370_PMU_REG_DBVBST (0xB2)
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#define MT6370_PMU_REG_DBVPOS (0xB3)
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#define MT6370_PMU_REG_DBVNEG (0xB4)
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/* irq event */
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#define MT6370_PMU_REG_CHGIRQ1 (0xC0)
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#define MT6370_PMU_REG_CHGIRQ2 (0xC1)
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#define MT6370_PMU_REG_CHGIRQ3 (0xC2)
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#define MT6370_PMU_REG_CHGIRQ4 (0xC3)
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#define MT6370_PMU_REG_CHGIRQ5 (0xC4)
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#define MT6370_PMU_REG_CHGIRQ6 (0xC5)
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#define MT6370_PMU_REG_QCIRQ (0xC6)
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#define MT6370_PMU_REG_DICHGIRQ7 (0xC7)
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#define MT6370_PMU_REG_OVPCTRLIRQ (0xC8)
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#define MT6370_PMU_REG_FLEDIRQ1 (0xC9)
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#define MT6370_PMU_REG_FLEDIRQ2 (0xCA)
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#define MT6370_PMU_REG_BASEIRQ (0xCB)
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#define MT6370_PMU_REG_LDOIRQ (0xCC)
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#define MT6370_PMU_REG_RGBIRQ (0xCD)
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#define MT6370_PMU_REG_BLIRQ (0xCE)
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#define MT6370_PMU_REG_DBIRQ (0xCF)
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/* status event */
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#define MT6370_PMU_REG_CHGSTAT1 (0xD0)
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#define MT6370_PMU_REG_CHGSTAT2 (0xD1)
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#define MT6370_PMU_REG_CHGSTAT3 (0xD2)
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#define MT6370_PMU_REG_CHGSTAT4 (0xD3)
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#define MT6370_PMU_REG_CHGSTAT5 (0xD4)
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#define MT6370_PMU_REG_CHGSTAT6 (0xD5)
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#define MT6370_PMU_REG_QCSTAT (0xD6)
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#define MT6370_PMU_REG_DICHGSTAT (0xD7)
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#define MT6370_PMU_REG_OVPCTRLSTAT (0xD8)
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#define MT6370_PMU_REG_FLEDSTAT1 (0xD9)
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#define MT6370_PMU_REG_FLEDSTAT2 (0xDA)
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#define MT6370_PMU_REG_BASESTAT (0xDB)
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#define MT6370_PMU_REG_LDOSTAT (0xDC)
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#define MT6370_PMU_REG_RGBSTAT (0xDD)
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#define MT6370_PMU_REG_BLSTAT (0xDE)
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#define MT6370_PMU_REG_DBSTAT (0xDF)
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/* irq mask */
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#define MT6370_PMU_CHGMASK1 (0xE0)
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#define MT6370_PMU_CHGMASK2 (0xE1)
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#define MT6370_PMU_CHGMASK3 (0xE2)
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#define MT6370_PMU_CHGMASK4 (0xE3)
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#define MT6370_PMU_CHGMASK5 (0xE4)
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#define MT6370_PMU_CHGMASK6 (0xE5)
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#define MT6370_PMU_DPDMMASK1 (0xE6)
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#define MT6370_PMU_DICHGMASK (0xE7)
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#define MT6370_PMU_OVPCTRLMASK (0xE8)
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#define MT6370_PMU_FLEDMASK1 (0xE9)
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#define MT6370_PMU_FLEDMASK2 (0xEA)
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#define MT6370_PMU_BASEMASK (0xEB)
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#define MT6370_PMU_LDOMASK (0xEC)
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#define MT6370_PMU_RGBMASK (0xED)
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#define MT6370_PMU_BLMASK (0xEE)
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#define MT6370_PMU_DBMASK (0xEF)
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/* general io ops start */
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extern int mt6370_pmu_reg_read(struct mt6370_pmu_chip *chip, u8 addr);
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extern int mt6370_pmu_reg_write(struct mt6370_pmu_chip *chip,
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u8 addr, u8 data);
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extern int mt6370_pmu_reg_update_bits(struct mt6370_pmu_chip *chip, u8 addr,
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u8 mask, u8 data);
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static inline int mt6370_pmu_reg_set_bit(struct mt6370_pmu_chip *chip, u8 addr,
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u8 mask)
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{
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return mt6370_pmu_reg_update_bits(chip, addr, mask, mask);
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}
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static inline int mt6370_pmu_reg_clr_bit(struct mt6370_pmu_chip *chip, u8 addr,
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u8 mask)
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{
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return mt6370_pmu_reg_update_bits(chip, addr, mask, 0x00);
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}
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extern int mt6370_pmu_reg_block_read(struct mt6370_pmu_chip *chip, u8 addr,
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int len, u8 *dest);
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extern int mt6370_pmu_reg_block_write(struct mt6370_pmu_chip *chip, u8 addr,
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int len, const u8 *src);
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/* general io ops end */
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/* extern function from other files start */
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extern int mt6370_pmu_regmap_register(struct mt6370_pmu_chip *chip,
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struct rt_regmap_fops *regmap_ops);
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extern void mt6370_pmu_regmap_unregister(struct mt6370_pmu_chip *chip);
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extern int mt6370_pmu_get_virq_number(struct mt6370_pmu_chip *chip,
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const char *name);
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extern const char *mt6370_pmu_get_hwirq_name(struct mt6370_pmu_chip *chip,
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int id);
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extern int mt6370_pmu_irq_register(struct mt6370_pmu_chip *chip);
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extern void mt6370_pmu_irq_unregister(struct mt6370_pmu_chip *chip);
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extern void mt6370_pmu_irq_suspend(struct mt6370_pmu_chip *chip);
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extern void mt6370_pmu_irq_resume(struct mt6370_pmu_chip *chip);
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extern int mt6370_pmu_subdevs_register(struct mt6370_pmu_chip *chip);
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extern void mt6370_pmu_subdevs_unregister(struct mt6370_pmu_chip *chip);
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/* extern function from other files end */
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#endif /* #ifndef __LINUX_MFD_MT6370_PMU_H */
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