83 lines
1.9 KiB
C
83 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DDP_CLK_MGR_H__
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#define __DDP_CLK_MGR_H__
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#include "ddp_hal.h"
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#include <linux/clk.h>
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/* display clk id
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* -- by chip
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*/
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enum DDP_CLK_ID {
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/* mmsys top clk */
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DISP_MTCMOS_CLK = 0,
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DISP0_SMI_COMMON,
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DISP0_SMI_LARB0,
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CLK_MM_GALS_COMM0,
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CLK_MM_GALS_COMM1,
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/* module clk */
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DISP0_DISP_OVL0,
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DISP0_DISP_RDMA0,
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DISP0_DISP_WDMA0,
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DISP0_DISP_COLOR0,
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DISP0_DISP_CCORR0,
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DISP0_DISP_AAL0,
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DISP0_DISP_GAMMA0,
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DISP0_DISP_DITHER0,
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DISP1_DSI0_MM_CLOCK,
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DISP1_DSI0_INTERFACE_CLOCK,
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DISP0_DISP_26M,
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MDP_WROT0,
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DISP_PWM,
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MUX_PWM,
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CLK26M,
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UNIVPLL2_D4,
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UNIVPLL2_D8,
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UNIVPLL3_D8,
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MAX_DISP_CLK_CNT
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};
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struct ddp_clk {
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struct clk *pclk;
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const char *clk_name;
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int refcnt;
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/* bit 0: main display , bit 1: second display */
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unsigned int belong_to;
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enum DISP_MODULE_ENUM module_id;
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};
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const char *ddp_get_clk_name(unsigned int n);
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int ddp_set_clk_handle(struct clk *pclk, unsigned int n);
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#if 0
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int ddp_clk_prepare(enum DDP_CLK_ID id);
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int ddp_clk_unprepare(enum DDP_CLK_ID id);
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int ddp_clk_enable(enum DDP_CLK_ID id);
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int ddp_clk_disable(enum DDP_CLK_ID id);
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#endif
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int ddp_clk_prepare_enable(enum DDP_CLK_ID id);
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int ddp_clk_disable_unprepare(enum DDP_CLK_ID id);
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int ddp_clk_set_parent(enum DDP_CLK_ID id, enum DDP_CLK_ID parent);
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int ddp_set_mipi26m(enum DISP_MODULE_ENUM module, int en);
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int ddp_parse_apmixed_base(void);
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int ddp_main_modules_clk_on(void);
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int ddp_main_modules_clk_off(void);
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int ddp_ext_modules_clk_on(void);
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int ddp_ext_modules_clk_off(void);
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int ddp_ovl2mem_modules_clk_on(void);
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int ddp_ovl2mem_modules_clk_off(void);
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int ddp_module_clk_enable(enum DISP_MODULE_TYPE_ENUM module_t);
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int ddp_module_clk_disable(enum DISP_MODULE_TYPE_ENUM module_t);
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enum DDP_CLK_ID ddp_get_module_clk_id(enum DISP_MODULE_ENUM module_id);
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void ddp_clk_force_on(unsigned int on);
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extern void check_mm0_clk_sts(void);
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void ddp_clk_tree_dump(void);
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#endif
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