307 lines
9.8 KiB
C
307 lines
9.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DDP_REG_H_
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#define _DDP_REG_H_
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#include "mt-plat/sync_write.h"
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#include "display_recorder.h"
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#include "cmdq_record.h"
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#include "cmdq_core.h"
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#include "ddp_hal.h"
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#define ENABLE_CLK_MGR
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#define UINT32 unsigned int
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/* ////////////////////////////// macro //////////////////////////// */
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#ifndef READ_REGISTER_UINT32
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#define READ_REGISTER_UINT32(reg) (*(UINT32 * const)(reg))
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#endif
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#ifndef WRITE_REGISTER_UINT32
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#define WRITE_REGISTER_UINT32(reg, val) \
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((*(UINT32 * const)(reg)) = (val))
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#endif
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#ifndef READ_REGISTER_UINT16
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#define READ_REGISTER_UINT16(reg) ((*(UINT16 * const)(reg)))
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#endif
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#ifndef WRITE_REGISTER_UINT16
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#define WRITE_REGISTER_UINT16(reg, val) \
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((*(UINT16 * const)(reg)) = (val))
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#endif
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#ifndef READ_REGISTER_UINT8
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#define READ_REGISTER_UINT8(reg) ((*(UINT8 * const)(reg)))
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#endif
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#ifndef WRITE_REGISTER_UINT8
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#define WRITE_REGISTER_UINT8(reg, val) \
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((*(UINT8 * const)(reg)) = (val))
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#endif
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#define INREG8(x) READ_REGISTER_UINT8((UINT8 *)((void *)(x)))
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#define OUTREG8(x, y) \
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WRITE_REGISTER_UINT8((UINT8 *)((void *)(x)), (UINT8)(y))
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#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
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#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
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#define MASKREG8(x, y, z) OUTREG8(x, (INREG8(x)&~(y))|(z))
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#define INREG16(x) READ_REGISTER_UINT16((UINT16 *)((void *)(x)))
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#define OUTREG16(x, y) \
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WRITE_REGISTER_UINT16((UINT16 *)((void *)(x)), (UINT16)(y))
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#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
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#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
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#define MASKREG16(x, y, z) OUTREG16(x, (INREG16(x)&~(y))|(z))
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#define INREG32(x) READ_REGISTER_UINT32((UINT32 *)((void *)(x)))
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#define OUTREG32(x, y) \
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WRITE_REGISTER_UINT32((UINT32 *)((void *)(x)), (UINT32)(y))
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#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
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#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
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#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
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#ifndef ASSERT
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#define ASSERT(expr) WARN_ON(!(expr))
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#endif
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#define AS_INT32(x) (*(INT32 *)((void *)x))
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#define AS_INT16(x) (*(INT16 *)((void *)x))
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#define AS_INT8(x) (*(INT8 *)((void *)x))
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#define AS_UINT32(x) (*(UINT32 *)((void *)x))
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#define AS_UINT16(x) (*(UINT16 *)((void *)x))
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#define AS_UINT8(x) (*(UINT8 *)((void *)x))
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#ifndef FALSE
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#define FALSE (0)
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#endif
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#ifndef TRUE
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#define TRUE (1)
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#endif
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extern cmdqBackupSlotHandle dispsys_slot;
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#define DISP_RDMA_INDEX_OFFSET (0)
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#define DISP_WDMA_INDEX_OFFSET (0)
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#define DISP_OVL_INDEX_OFFSET (0)
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#define DISP_MIPI_INDEX_OFFSET (0)
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#define DISPSYS_CONFIG_BASE ddp_get_module_va(DISP_MODULE_CONFIG)
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#define DISPSYS_OVL0_BASE ddp_get_module_va(DISP_MODULE_OVL0)
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#define DISPSYS_OVL1_BASE ddp_get_module_va(DISP_MODULE_OVL1)
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#define DISPSYS_OVL0_2L_BASE ddp_get_module_va(DISP_MODULE_OVL0_2L)
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#define DISPSYS_OVL1_2L_BASE ddp_get_module_va(DISP_MODULE_OVL1_2L)
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#define DISPSYS_OVL2_2L_BASE ddp_get_module_va(DISP_MODULE_OVL2_2L)
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#define DISPSYS_OVL3_2L_BASE ddp_get_module_va(DISP_MODULE_OVL3_2L)
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#define DISPSYS_RDMA0_BASE ddp_get_module_va(DISP_MODULE_RDMA0)
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#define DISPSYS_RDMA1_BASE ddp_get_module_va(DISP_MODULE_RDMA1)
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#define DISPSYS_RDMA4_BASE ddp_get_module_va(DISP_MODULE_RDMA4)
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#define DISPSYS_RDMA5_BASE ddp_get_module_va(DISP_MODULE_RDMA5)
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#define DISPSYS_MDP_RDMA4_BASE ddp_get_module_va(DISP_MODULE_MDP_RDMA4)
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#define DISPSYS_MDP_RDMA5_BASE ddp_get_module_va(DISP_MODULE_MDP_RDMA5)
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#define DISPSYS_WDMA0_BASE ddp_get_module_va(DISP_MODULE_WDMA0)
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#define DISPSYS_WDMA1_BASE ddp_get_module_va(DISP_MODULE_WDMA1)
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#define DISPSYS_COLOR0_BASE ddp_get_module_va(DISP_MODULE_COLOR0)
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#define DISPSYS_COLOR1_BASE ddp_get_module_va(DISP_MODULE_COLOR1)
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#define DISPSYS_CCORR0_BASE ddp_get_module_va(DISP_MODULE_CCORR0)
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#define DISPSYS_CCORR1_BASE ddp_get_module_va(DISP_MODULE_CCORR1)
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#define DISPSYS_AAL0_BASE ddp_get_module_va(DISP_MODULE_AAL0)
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#define DISPSYS_AAL1_BASE ddp_get_module_va(DISP_MODULE_AAL1)
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#define DISPSYS_MDP_AAL4_BASE ddp_get_module_va(DISP_MODULE_MDP_AAL4)
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#define DISPSYS_MDP_AAL5_BASE ddp_get_module_va(DISP_MODULE_MDP_AAL5)
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#define DISPSYS_GAMMA0_BASE ddp_get_module_va(DISP_MODULE_GAMMA0)
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#define DISPSYS_GAMMA1_BASE ddp_get_module_va(DISP_MODULE_GAMMA1)
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#define DISPSYS_DITHER0_BASE ddp_get_module_va(DISP_MODULE_DITHER0)
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#define DISPSYS_DITHER1_BASE ddp_get_module_va(DISP_MODULE_DITHER1)
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#define DISPSYS_DSI0_BASE ddp_get_module_va(DISP_MODULE_DSI0)
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#define DISPSYS_DSI1_BASE ddp_get_module_va(DISP_MODULE_DSI1)
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#define DISPSYS_RSZ0_BASE ddp_get_module_va(DISP_MODULE_RSZ0)
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#define DISPSYS_RSZ1_BASE ddp_get_module_va(DISP_MODULE_RSZ1)
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#define DISPSYS_MDP_RSZ4_BASE ddp_get_module_va(DISP_MODULE_MDP_RSZ4)
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#define DISPSYS_MDP_RSZ5_BASE ddp_get_module_va(DISP_MODULE_MDP_RSZ5)
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#define DISPSYS_POSTMASK0_BASE ddp_get_module_va(DISP_MODULE_POSTMASK0)
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#define DISPSYS_POSTMASK1_BASE ddp_get_module_va(DISP_MODULE_POSTMASK1)
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#define DISPSYS_MERGE0_BASE ddp_get_module_va(DISP_MODULE_MERGE0)
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#define DISPSYS_MERGE1_BASE ddp_get_module_va(DISP_MODULE_MERGE1)
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#define DISPSYS_DP_INTF_BASE ddp_get_module_va(DISP_MODULE_DP_INTF)
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#define DISPSYS_DISP_DSC_BASE ddp_get_module_va(DISP_MODULE_DSC)
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#define DISPSYS_PWM0_BASE ddp_get_module_va(DISP_MODULE_PWM0)
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#define DISPSYS_MUTEX_BASE ddp_get_module_va(DISP_MODULE_MUTEX)
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#define DISPSYS_SMI_LARB0_BASE ddp_get_module_va(DISP_MODULE_SMI_LARB0)
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#define DISPSYS_SMI_LARB1_BASE ddp_get_module_va(DISP_MODULE_SMI_LARB1)
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#define DISPSYS_SMI_COMMON_BASE ddp_get_module_va(DISP_MODULE_SMI_COMMON)
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#define DISPSYS_MIPITX0_BASE ddp_get_module_va(DISP_MODULE_MIPI0)
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#define DISPSYS_MIPITX1_BASE ddp_get_module_va(DISP_MODULE_MIPI1)
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#define DISPSYS_SLOT_BASE dispsys_slot
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#ifdef INREG32
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#undef INREG32
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#define INREG32(x) (__raw_readl((unsigned long *)(x)))
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#endif
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/* ------------------------------------------------------------------------- */
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/* Register Field Access */
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/* ------------------------------------------------------------------------- */
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#define REG_FLD(width, shift) \
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((unsigned int)((((width) & 0xFF) << 16) | ((shift) & 0xFF)))
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#define REG_FLD_MSB_LSB(msb, lsb) REG_FLD((msb) - (lsb) + 1, (lsb))
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#define REG_FLD_WIDTH(field) \
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((unsigned int)(((field) >> 16) & 0xFF))
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#define REG_FLD_SHIFT(field) \
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((unsigned int)((field) & 0xFF))
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#define REG_FLD_MASK(field) \
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((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) << \
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REG_FLD_SHIFT(field))
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#define REG_FLD_VAL(field, val) \
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(((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
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#define REG_FLD_VAL_GET(field, regval) \
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(((regval) & REG_FLD_MASK(field)) >> REG_FLD_SHIFT(field))
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#define DISP_REG_GET(reg32) __raw_readl((unsigned long *)(reg32))
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#define DISP_REG_GET_FIELD(field, reg32) \
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REG_FLD_VAL_GET(field, __raw_readl((unsigned long *)(reg32)))
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/* polling register until masked bit is 1 */
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#define DDP_REG_POLLING(reg32, mask) \
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do { \
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while (!((DISP_REG_GET(reg32))&mask))\
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; \
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} while (0)
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/* Polling register until masked bit is 0 */
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#define DDP_REG_POLLING_NEG(reg32, mask) \
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do { \
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while ((DISP_REG_GET(reg32))&mask)\
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; \
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} while (0)
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#define DISP_CPU_REG_SET(reg32, val) \
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mt_reg_sync_writel(val, (unsigned long *)(reg32))
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/* after apply device tree va/pa is not mapped by a fixed offset */
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static inline unsigned long disp_addr_convert(unsigned long va)
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{
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unsigned int i = 0;
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for (i = 0; i < DISP_MODULE_NUM; i++) {
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if (ddp_get_module_va(i) == (va & (~0xfffl)))
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return ddp_get_module_pa(i) + (va & 0xfffl);
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}
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pr_info("DDP/can not find reg addr for va=0x%lx!\n", va);
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ASSERT(0);
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return 0;
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}
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#define DISP_REG_MASK(handle, reg32, val, mask) \
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do { \
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if (handle == NULL) { \
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mt_reg_sync_writel((unsigned int)(INREG32(reg32)& \
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~(mask))|(val), (reg32));\
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} else { \
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cmdqRecWrite(handle, \
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disp_addr_convert((unsigned long)(reg32)), \
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val, mask); \
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} \
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} while (0)
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#define DISP_REG_SET(handle, reg32, val) \
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do { \
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if (handle == NULL) { \
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mt_reg_sync_writel(val, (unsigned long *)(reg32));\
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} else { \
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cmdqRecWrite(handle, \
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disp_addr_convert((unsigned long)(reg32)), \
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val, ~0); \
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} \
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} while (0)
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#define DISP_REG_SET_FIELD(handle, field, reg32, val) \
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do { \
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if (handle == NULL) { \
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unsigned int regval; \
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regval = __raw_readl((unsigned long *)(reg32)); \
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regval = (regval & ~REG_FLD_MASK(field)) | \
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(REG_FLD_VAL((field), (val))); \
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mt_reg_sync_writel(regval, (reg32)); \
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} else { \
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cmdqRecWrite(handle, disp_addr_convert(reg32), \
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(val)<<REG_FLD_SHIFT(field), \
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REG_FLD_MASK(field));\
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} \
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} while (0)
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#define DISP_REG_CMDQ_POLLING(handle, reg32, val, mask) \
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do { \
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if (handle == NULL) { \
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while ((DISP_REG_GET(reg32) & (mask)) != \
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((val) & (mask)))\
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; \
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} else { \
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cmdqRecPoll(handle, \
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disp_addr_convert((unsigned long)(reg32)), \
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val, mask); \
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} \
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} while (0)
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#define DISP_REG_BACKUP(handle, hSlot, idx, reg32) \
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do { \
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if (handle != NULL) { \
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if (hSlot) \
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cmdqRecBackupRegisterToSlot(handle, hSlot, idx,\
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disp_addr_convert((unsigned long)(reg32)));\
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} \
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} while (0)
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#define DISP_SLOT_SET(handle, hSlot, idx, val) \
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do { \
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if (handle != NULL) { \
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if (hSlot) \
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cmdqRecBackupUpdateSlot(handle, hSlot, \
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idx, val); \
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} \
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} while (0)
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/* Helper macros for local command queue */
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#define DISP_CMDQ_BEGIN(__cmdq, scenario) \
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do { \
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cmdqRecCreate(scenario, &__cmdq);\
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cmdqRecReset(__cmdq);\
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ddp_insert_config_allow_rec(__cmdq);\
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} while (0)
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#define DISP_CMDQ_REG_SET(__cmdq, reg32, val, mask) \
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DISP_REG_MASK(__cmdq, reg32, val, mask)
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#define DISP_CMDQ_CONFIG_STREAM_DIRTY(__cmdq) \
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ddp_insert_config_dirty_rec(__cmdq)
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#define DISP_CMDQ_END(__cmdq) \
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do { \
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cmdqRecFlush(__cmdq); \
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cmdqRecDestroy(__cmdq); \
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} while (0)
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/********************************/
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#include "ddp_reg_mmsys.h"
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#include "ddp_reg_mutex.h"
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#include "ddp_reg_ovl.h"
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#include "ddp_reg_pq.h"
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#include "ddp_reg_dma.h"
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#include "ddp_reg_dsi.h"
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#include "ddp_reg_mipi.h"
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#include "ddp_reg_rsz.h"
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#include "ddp_reg_postmask.h"
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#endif /* _DDP_REG_H_ */
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