Initial commit: Linux kernel 4.19 for Unplugged OS

drivers/misc/mediatek/dfd/Kconfig

@@ -0,0 +1,9 @@
+config MTK_DFD_INTERNAL_DUMP
+	bool "Enable MediaTek DFD internal dump"
+	select MTK_PLAT_SRAM_FLAG
+	help
+	  DFD (Design for Debug) is a debugging tool,
+	  which scans flip-flops and dumps to internal
+	  RAM on the WDT reset. After system reboots,
+	  those values could be showed in exception db
+	  for debugging.

drivers/misc/mediatek/dfd/Makefile

@@ -0,0 +1 @@
+obj-y += dfd.o

drivers/misc/mediatek/dfd/dfd.c

@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+#include <linux/module.h>
+#include <linux/of_fdt.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/of_address.h>
+#include <linux/arm-smccc.h>
+
+#include <linux/soc/mediatek/mtk_sip_svc.h> /* for SMC ID table */
+#include <mt-plat/mtk_platform_debug.h>
+#include "dfd.h"
+
+static struct dfd_drv *drv;
+
+/* return -1 for error indication */
+int dfd_setup(int version)
+{
+	int ret;
+	int dfd_doe;
+	struct arm_smccc_res res;
+
+	if (drv && (drv->enabled == 1) && (drv->base_addr > 0)) {
+		/* check support or not first */
+		if (!drv->check_dfd_support)
+			return -EINVAL;
+
+		pr_info("dfd setup\n");
+
+		ret = mtk_dbgtop_dfd_count_en(1);
+		ret = mtk_dbgtop_dfd_therm1_dis(1);
+		ret = mtk_dbgtop_dfd_therm2_dis(0);
+		ret = mtk_dbgtop_dfd_timeout(drv->rg_dfd_timeout);
+		if (drv->mem_reserve && drv->cachedump_en) {
+			dfd_doe = DFD_CACHE_DUMP_ENABLE;
+			if (drv->l2c_trigger)
+				dfd_doe |= DFD_PARITY_ERR_TRIGGER;
+			if (version == DFD_EXTENDED_DUMP)
+				arm_smccc_smc(MTK_SIP_KERNEL_DFD,
+					DFD_SMC_MAGIC_SETUP,
+					(u64) drv->base_addr,
+					drv->chain_length,
+					dfd_doe, 0, 0, 0, &res);
+			else
+				arm_smccc_smc(MTK_SIP_KERNEL_DFD,
+					DFD_SMC_MAGIC_SETUP,
+					(u64) drv->base_addr,
+					drv->chain_length,
+					0, 0, 0, 0, &res);
+		} else {
+			arm_smccc_smc(MTK_SIP_KERNEL_DFD, DFD_SMC_MAGIC_SETUP,
+				(u64) drv->base_addr, drv->chain_length,
+				0, 0, 0, 0, &res);
+		}
+
+		if (set_sram_flag_dfd_valid() < 0)
+			return -1;
+
+		return ret;
+	} else
+		return -1;
+}
+
+static int __init fdt_get_chosen(unsigned long node, const char *uname,
+		int depth, void *data)
+{
+	if (depth != 1 || (strcmp(uname, "chosen") != 0
+				&& strcmp(uname, "chosen@0") != 0))
+		return 0;
+
+	*(unsigned long *)data = node;
+	return 1;
+}
+
+static int __init dfd_init(void)
+{
+	struct device_node *dev_node, *infra_node, *rgu_node;
+	unsigned long node;
+	const void *prop;
+	unsigned int val;
+	int ret = 0;
+	void __iomem *toprgu_base;
+
+	drv = kzalloc(sizeof(struct dfd_drv), GFP_KERNEL);
+	if (!drv)
+		return -ENOMEM;
+
+	pr_info("In dfd init\n");
+
+	/* get dfd settings */
+	dev_node = of_find_compatible_node(NULL, NULL, "mediatek,dfd");
+	if (dev_node) {
+		if (of_property_read_u32(dev_node, "mediatek,dfd_latch_offset", &val)) {
+			pr_info("%s: Latch offset not found.\n", __func__);
+			ret = -EINVAL;
+			goto error_get_dts;
+		}
+		pr_info("%s: Latch offset is 0x%x\n", __func__, val);
+		rgu_node = of_find_compatible_node(NULL, NULL, "mediatek,toprgu");
+		toprgu_base = of_iomap(rgu_node, 0);
+
+		if (!toprgu_base)
+			pr_info("%s: RGU base not found.\n", __func__);
+		else
+			pr_info("%s: get topdbg base success\n", __func__);
+		get_dfd_base(toprgu_base, val);
+
+		if (of_property_read_u32(dev_node, "mediatek,enabled", &val))
+			drv->enabled = 0;
+		else
+			drv->enabled = val;
+
+		if (of_property_read_u32(dev_node,
+					"mediatek,chain_length", &val))
+			drv->chain_length = 0;
+		else
+			drv->chain_length = val;
+
+		if (of_property_read_u32(dev_node,
+					"mediatek,rg_dfd_timeout", &val))
+			drv->rg_dfd_timeout = 0;
+		else
+			drv->rg_dfd_timeout = val;
+
+		if (of_property_read_u32(dev_node,
+					"mediatek,check_dfd_support", &val))
+			drv->check_dfd_support = 0;
+		else
+			drv->check_dfd_support = val;
+
+		if (of_property_read_u32(dev_node,
+					"mediatek,dfd_infra_base", &val))
+			drv->dfd_infra_base = 0;
+		else
+			drv->dfd_infra_base = val;
+
+		if (of_property_read_u32(dev_node,
+					"mediatek,dfd_ap_addr_offset", &val))
+			drv->dfd_ap_addr_offset = 0;
+		else
+			drv->dfd_ap_addr_offset = val;
+	} else {
+		ret = -ENODEV;
+		goto error_get_dts;
+	}
+
+	/* for cachedump enable */
+	dev_node = of_find_compatible_node(NULL, NULL,
+		"mediatek,dfd_cache");
+	if (dev_node) {
+		if (of_property_read_u32(dev_node, "mediatek,enabled", &val))
+			drv->cachedump_en = 0;
+		else
+			drv->cachedump_en = val;
+
+		if (drv->cachedump_en) {
+			if (!of_property_read_u32(dev_node,
+				"mediatek,rg_dfd_timeout", &val))
+				drv->rg_dfd_timeout = val;
+			if (!of_property_read_u32(dev_node,
+				"mediatek,l2c_trigger", &val))
+				drv->l2c_trigger = val;
+		}
+	}
+
+	if (drv->enabled == 0)
+		return 0;
+
+	of_scan_flat_dt(fdt_get_chosen, &node);
+	if (node) {
+		prop = of_get_flat_dt_prop(node, "dfd,base_addr_msb", NULL);
+		drv->base_addr_msb = (prop) ? of_read_number(prop, 1) : 0;
+	} else {
+		drv->base_addr_msb = 0;
+	}
+
+	of_scan_flat_dt(fdt_get_chosen, &node);
+	if (node) {
+		prop = of_get_flat_dt_prop(node,
+			"dfd,cache_dump_support", NULL);
+		drv->mem_reserve = (prop) ? of_read_number(prop, 1) : 0;
+	} else {
+		drv->mem_reserve = 0;
+	}
+
+	infra_node = of_find_compatible_node(NULL, NULL,
+			"mediatek,common-infracfg_ao");
+	if (infra_node) {
+		void __iomem *infra = of_iomap(infra_node, 0);
+
+		if (infra && drv->base_addr_msb) {
+			infra += drv->dfd_infra_base;
+			writel(readl(infra)
+				| (drv->base_addr_msb >>
+					drv->dfd_ap_addr_offset),
+				infra);
+			iounmap(infra);
+		}
+	}
+
+	/* get base address if enabled */
+	of_scan_flat_dt(fdt_get_chosen, &node);
+	if (node) {
+		prop = of_get_flat_dt_prop(node, "dfd,base_addr", NULL);
+		drv->base_addr = (prop) ? (u64) of_read_number(prop, 2) : 0;
+	} else {
+		ret = -ENODEV;
+		goto error_get_dts;
+	}
+	return 0;
+
+error_get_dts:
+	kfree(drv);
+	drv = NULL;
+	return ret;
+}
+
+core_initcall(dfd_init);

drivers/misc/mediatek/dfd/dfd.h

@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+#ifndef __DFD_H__
+#define __DFD_H__
+
+#define DFD_SMC_MAGIC_SETUP (0x99716150)
+#define DFD_CACHE_DUMP_ENABLE	1
+#define DFD_PARITY_ERR_TRIGGER	2
+
+struct dfd_drv {
+	u64 base_addr;
+	u32 base_addr_msb;
+	unsigned long chain_length;
+	unsigned long rg_dfd_timeout;
+	unsigned int enabled;
+	unsigned int cachedump_en;
+	unsigned int mem_reserve;
+	unsigned int l2c_trigger;
+	unsigned int check_dfd_support;
+	unsigned long dfd_infra_base;
+	unsigned int dfd_ap_addr_offset;
+};
+
+extern int mtk_dbgtop_dfd_count_en(int value);
+extern int mtk_dbgtop_dfd_therm1_dis(int value);
+extern int mtk_dbgtop_dfd_therm2_dis(int value);
+extern int mtk_dbgtop_dfd_timeout(int value);
+extern void get_dfd_base(void __iomem *dfd_base, unsigned int latch_offset);
+extern unsigned int check_dfd_support(void);
+extern unsigned int dfd_infra_base(void);
+extern unsigned int dfd_ap_addr_offset(void);
+
+#endif

drivers/misc/mediatek/dfd/mt6768/Makefile

@@ -0,0 +1 @@
+obj-y += plat_dfd.o

drivers/misc/mediatek/dfd/mt6768/plat_dfd.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+unsigned int check_dfd_support(void)
+{
+	return 1;
+}
+
+unsigned int dfd_infra_base(void)
+{
+	return 0x390;
+}
+
+/* DFD_V30_BASE_ADDR_IN_INFRA
+ * bit[9:0] : AP address bit[33:24]
+ */
+unsigned int dfd_ap_addr_offset(void)
+{
+	return 24;
+}

drivers/misc/mediatek/dfd/mt6785/Makefile

@@ -0,0 +1 @@
+obj-y += plat_dfd.o

drivers/misc/mediatek/dfd/mt6785/plat_dfd.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+
+unsigned int check_dfd_support(void)
+{
+	return 1;
+}
+
+unsigned int dfd_infra_base(void)
+{
+	return 0x390;
+}
+
+/* DFD_V30_BASE_ADDR_IN_INFRA
+ * bit[9:0] : AP address bit[33:24]
+ */
+unsigned int dfd_ap_addr_offset(void)
+{
+	return 24;
+}

drivers/misc/mediatek/dfd/mt6853/Makefile

@@ -0,0 +1 @@
+obj-y += plat_dfd.o

drivers/misc/mediatek/dfd/mt6853/plat_dfd.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+unsigned int check_dfd_support(void)
+{
+	return 1;
+}
+
+unsigned int dfd_infra_base(void)
+{
+	return 0x34;
+}
+
+/* DFD_V30_BASE_ADDR_IN_INFRA
+ * bit[10:0] : AP address bit[34:24]
+ */
+unsigned int dfd_ap_addr_offset(void)
+{
+	return 24;
+}

drivers/misc/mediatek/dfd/mt6873/Makefile

@@ -0,0 +1 @@
+obj-y += plat_dfd.o

drivers/misc/mediatek/dfd/mt6873/plat_dfd.c

@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+unsigned int check_dfd_support(void)
+{
+	return 1;
+}
+
+unsigned int dfd_infra_base(void)
+{
+	return 0x34;
+}
+
+/* DFD_V30_BASE_ADDR_IN_INFRA
+ * bit[10:0] : AP address bit[34:24]
+ */
+unsigned int dfd_ap_addr_offset(void)
+{
+	return 24;
+}

drivers/misc/mediatek/dfd/mt6885/Makefile

@@ -0,0 +1 @@
+obj-y += plat_dfd.o

drivers/misc/mediatek/dfd/mt6885/plat_dfd.c

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+
+unsigned int check_dfd_support(void)
+{
+	return 1;
+}
+
+unsigned int dfd_infra_base(void)
+{
+	return 0x34;
+}
+
+/* DFD_V30_BASE_ADDR_IN_INFRA
+ * bit[10:0] : AP address bit[34:24]
+ */
+unsigned int dfd_ap_addr_offset(void)
+{
+	return 24;
+}