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Initial commit: Linux kernel 4.19 for Unplugged OS

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ziv committed 2025-10-06 13:52:42 +00:00
commit d30235b04c
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drivers/misc/mediatek/include/mt-plat/aee.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 MediaTek Inc.
*/
#if !defined(__AEE_H__)
#define __AEE_H__
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/ratelimit.h>
#include <linux/sched.h>
#define AEE_MODULE_NAME_LENGTH 64
#define AEE_PROCESS_NAME_LENGTH 256
#define AEE_BACKTRACE_LENGTH 3072
#define MODULES_INFO_BUF_SIZE SZ_16K
enum AEE_REBOOT_MODE {
AEE_REBOOT_MODE_NORMAL = 0,
AEE_REBOOT_MODE_KERNEL_OOPS,
AEE_REBOOT_MODE_KERNEL_PANIC,
AEE_REBOOT_MODE_NESTED_EXCEPTION,
AEE_REBOOT_MODE_WDT,
AEE_REBOOT_MODE_MANUAL_KDUMP,
AEE_REBOOT_MODE_MRDUMP_KEY,
AEE_REBOOT_MODE_GZ_KE,
AEE_REBOOT_MODE_GZ_WDT,
AEE_REBOOT_MODE_HANG_DETECT,
};
#define AEE_SZ_SYMBOL_L 140
#define AEE_SZ_SYMBOL_S 80
struct aee_bt_frame {
__u64 pc;
__u64 lr;
__u32 pad[5];
/* Now we use different symbol length for PC &LR */
char pc_symbol[AEE_SZ_SYMBOL_S];
char lr_symbol[AEE_SZ_SYMBOL_L];
};
/* aee_process_info struct should strictly small than ipanic_buffer, now 4KB */
struct aee_process_info {
char process_path[AEE_PROCESS_NAME_LENGTH];
char backtrace[AEE_BACKTRACE_LENGTH];
struct aee_bt_frame ke_frame;
};
struct aee_process_bt {
__u32 pid;
__u32 nr_entries;
struct aee_bt_frame *entries;
};
struct aee_thread_reg {
pid_t tid;
struct pt_regs regs;
};
struct aee_user_thread_stack {
pid_t tid;
int StackLength;
/*8k stack ,define to char only for match 64bit/32bit*/
unsigned char *Userthread_Stack;
};
struct aee_user_thread_maps {
pid_t tid;
int Userthread_mapsLength;
/*8k stack ,define to char only for match 64bit/32bit*/
unsigned char *Userthread_maps;
};
struct unwind_info_stack {
pid_t tid __packed __aligned(8);
#ifdef __aarch64__
__u64 sp;
#else
long sp __packed __aligned(8);
#endif
int StackLength __packed __aligned(8);
unsigned char *Userthread_Stack __packed __aligned(8);
};
struct unwind_info_rms {
pid_t tid __packed __aligned(8);
struct pt_regs *regs __packed __aligned(8);
int StackLength __packed __aligned(8);
unsigned char *Userthread_Stack __packed __aligned(8);
int Userthread_mapsLength __packed __aligned(8);
unsigned char *Userthread_maps __packed __aligned(8);
};
#ifdef CONFIG_CONSOLE_LOCK_DURATION_DETECT
extern char *mtk8250_uart_dump(void);
#endif
#define AEE_MTK_CPU_NUMS 16
/* powerkey press,modules use bits */
#define AE_WDT_Powerkey_DEVICE_PATH "/dev/kick_powerkey"
#define WDT_SETBY_DEFAULT (0)
#define WDT_SETBY_Backlight (1<<0)
#define WDT_SETBY_Display (1<<1)
#define WDT_SETBY_SF (1<<2)
#define WDT_SETBY_PM (1<<3)
#define WDT_SETBY_WMS_DISABLE_PWK_MONITOR (0xAEEAEE00)
#define WDT_SETBY_WMS_ENABLE_PWK_MONITOR (0xAEEAEE01)
#define WDT_PWK_HANG_FORCE_HWT (0xAEE0FFFF)
/* QHQ RT Monitor */
#define AEEIOCTL_RT_MON_Kick _IOR('p', 0x0A, int)
#define AE_WDT_DEVICE_PATH "/dev/RT_Monitor"
/* QHQ RT Monitor end */
/* DB dump option bits, set relative bit to 1 to include related file in db */
#define DB_OPT_DEFAULT (0)
#define DB_OPT_FTRACE (1<<0)
#define DB_OPT_PRINTK_TOO_MUCH (1<<1)
#define DB_OPT_NE_JBT_TRACES (1<<2)
#define DB_OPT_SWT_JBT_TRACES (1<<3)
#define DB_OPT_VM_TRACES (1<<4)
#define DB_OPT_DUMPSYS_ACTIVITY (1<<5)
#define DB_OPT_DUMPSYS_WINDOW (1<<6)
#define DB_OPT_DUMPSYS_GFXINFO (1<<7)
#define DB_OPT_DUMPSYS_SURFACEFLINGER (1<<8)
#define DB_OPT_DISPLAY_HANG_DUMP (1<<9)
#define DB_OPT_LOW_MEMORY_KILLER (1<<10)
#define DB_OPT_PROC_MEM (1<<11)
#define DB_OPT_FS_IO_LOG (1<<12)
#define DB_OPT_PROCESS_COREDUMP (1<<13)
#define DB_OPT_VM_HPROF (1<<14)
#define DB_OPT_PROCMEM (1<<15)
#define DB_OPT_DUMPSYS_INPUT (1<<16)
#define DB_OPT_MMPROFILE_BUFFER (1<<17)
#define DB_OPT_BINDER_INFO (1<<18)
#define DB_OPT_WCN_ISSUE_INFO (1<<19)
#define DB_OPT_DUMMY_DUMP (1<<20)
#define DB_OPT_PID_MEMORY_INFO (1<<21)
#define DB_OPT_VM_OOME_HPROF (1<<22)
#define DB_OPT_PID_SMAPS (1<<23)
#define DB_OPT_PROC_CMDQ_INFO (1<<24)
#define DB_OPT_PROC_USKTRK (1<<25)
#define DB_OPT_SF_RTT_DUMP (1<<26)
#define DB_OPT_PAGETYPE_INFO (1<<27)
#define DB_OPT_DUMPSYS_PROCSTATS (1<<28)
#define DB_OPT_DUMP_DISPLAY (1<<29)
#define DB_OPT_NATIVE_BACKTRACE (1<<30)
#define DB_OPT_AARCH64 (1<<31)
#define AEE_API_CALL_INTERVAL (120 * HZ)
#define AEE_API_CALL_BURST 2
#if defined(MODULE) || IS_BUILTIN(CONFIG_MTK_AEE_AED)
#define aee_kernel_exception(module, msg...) \
({ \
static DEFINE_RATELIMIT_STATE(__func__##_rs, \
AEE_API_CALL_INTERVAL, \
AEE_API_CALL_BURST); \
\
if (__ratelimit(&(__func__##_rs))) \
aee_kernel_exception_api_func(__FILE__, __LINE__, \
DB_OPT_DEFAULT, module, msg); \
})
#define aee_kernel_warning(module, msg...) \
({ \
static DEFINE_RATELIMIT_STATE(__func__##_rs, \
AEE_API_CALL_INTERVAL, \
AEE_API_CALL_BURST); \
\
if (__ratelimit(&(__func__##_rs))) \
aee_kernel_warning_api_func(__FILE__, __LINE__, \
DB_OPT_DEFAULT, module, msg); \
})
#define aee_kernel_exception_api(file, line, db_opt, module, msg...) \
({ \
static DEFINE_RATELIMIT_STATE(__func__##_rs, \
AEE_API_CALL_INTERVAL, \
AEE_API_CALL_BURST); \
if (__ratelimit(&(__func__##_rs))) \
aee_kernel_exception_api_func(__FILE__, __LINE__, \
db_opt, module, msg); \
})
#define aee_kernel_warning_api(file, line, db_opt, module, msg...) \
({ \
static DEFINE_RATELIMIT_STATE(__func__##_rs, \
AEE_API_CALL_INTERVAL, \
AEE_API_CALL_BURST); \
if (aee_is_printk_too_much(module)) \
aee_kernel_warning_api_func(__FILE__, __LINE__, db_opt, \
module, msg); \
else if (__ratelimit(&(__func__##_rs))) \
aee_kernel_warning_api_func(__FILE__, __LINE__, db_opt, \
module, msg); \
})
#else
#undef aee_kernel_warning
#define aee_kernel_warning(module, msg...) WARN(1, msg)
#undef aee_kernel_warning_api
#define aee_kernel_warning_api(file, line, db_opt, module, msg...) \
WARN(1, msg)
#undef aee_kernel_exception
#define aee_kernel_exception(module, msg...) WARN(1, msg)
#undef aee_kernel_exception_api
#define aee_kernel_exception_api(file, line, db_opt, module, msg...) \
WARN(1, msg)
#endif
#define aee_kernel_reminding(module, msg...) \
aee_kernel_reminding_api(__FILE__, __LINE__, DB_OPT_DEFAULT, \
module, msg)
#define aed_md_exception(log, log_size, phy, phy_size, detail) \
aed_md_exception_api(log, log_size, phy, phy_size, detail, \
DB_OPT_DEFAULT)
#define aed_md32_exception(log, log_size, phy, phy_size, detail) \
aed_md32_exception_api(log, log_size, phy, phy_size, detail, \
DB_OPT_DEFAULT)
#define aed_scp_exception(log, log_size, phy, phy_size, detail) \
aed_scp_exception_api(log, log_size, phy, phy_size, detail, \
DB_OPT_DEFAULT)
#define aed_combo_exception(log, log_size, phy, phy_size, detail) \
aed_combo_exception_api(log, log_size, phy, phy_size, detail, \
DB_OPT_DEFAULT)
#define aed_common_exception(assert_type, log, log_size, phy, phy_size, \
detail) \
aed_common_exception_api(assert_type, log, log_size, phy, \
phy_size, detail, DB_OPT_DEFAULT)
void aee_kernel_exception_api_func(const char *file, const int line,
const int db_opt, const char *module, const char *msg, ...);
void aee_kernel_warning_api_func(const char *file, const int line,
const int db_opt, const char *module, const char *msg, ...);
void aee_kernel_reminding_api(const char *file, const int line,
const int db_opt, const char *module, const char *msg, ...);
void aed_md_exception_api(const int *log, int log_size, const int *phy,
int phy_size, const char *detail, const int db_opt);
void aed_md32_exception_api(const int *log, int log_size, const int *phy,
int phy_size, const char *detail, const int db_opt);
void aed_scp_exception_api(const int *log, int log_size, const int *phy,
int phy_size, const char *detail, const int db_opt);
void aed_combo_exception_api(const int *log, int log_size, const int *phy,
int phy_size, const char *detail, const int db_opt);
void aed_common_exception_api(const char *assert_type, const int *log, int
log_size, const int *phy, int phy_size, const char
*detail, const int db_opt);
int aed_get_status(void);
int aee_is_printk_too_much(const char *module);
void aee_sram_printk(const char *fmt, ...);
int aee_is_enable(void);
#endif/* __AEE_H__ */
drivers/misc/mediatek/include/mt-plat/core_ctl.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2022 MediaTek Inc.
*/
#ifndef __CORE_CTL_H
#define __CORE_CTL_H
extern void core_ctl_tick(u64 wallclock);
extern int core_ctl_set_min_cpus(unsigned int cid, unsigned int min);
extern int core_ctl_set_max_cpus(unsigned int cid, unsigned int max);
extern int core_ctl_set_offline_throttle_ms(unsigned int cid,
unsigned int throttle_ms);
extern int core_ctl_set_limit_cpus(unsigned int cid,
unsigned int min,
unsigned int max);
extern int core_ctl_set_not_preferred(int cid, int cpu, bool enable);
extern int core_ctl_set_boost(bool boost);
extern int core_ctl_set_btask_up_thresh(int cid, unsigned int val);
extern int core_ctl_set_cpu_tj_degree(int cid, unsigned int degree);
extern int core_ctl_set_cpu_tj_btask_thresh(int cid, unsigned int val);
#endif
drivers/misc/mediatek/include/mt-plat/cpu_ctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _CPU_CTRL_H
#define _CPU_CTRL_H
enum {
CPU_KIR_PERF = 0,
CPU_KIR_FPSGO,
CPU_KIR_WIFI,
CPU_KIR_BOOT,
CPU_KIR_TOUCH,
CPU_KIR_PERFTOUCH,
CPU_KIR_USB,
CPU_KIR_AMMS,
CPU_KIR_GBE,
CPU_KIR_CCCI,
CPU_KIR_SYSLIM,
CPU_KIR_CORE_CTL,
CPU_MAX_KIR
};
enum {
CPU_ISO_KIR_PERF_CORE = 0,
CPU_ISO_KIR_PERF_ISO,
CPU_ISO_KIR_FPSGO,
CPU_ISO_KIR_CPU_CTRL,
CPU_ISO_MAX_KIR
};
struct cpu_ctrl_data {
int min;
int max;
};
#ifdef CONFIG_MTK_CPU_FREQ
#include <mtk_cpufreq_common_api.h>
unsigned int __attribute__ ((weak)) mt_cpufreq_get_freq_by_idx(
unsigned int cid, int idx) { return 0; }
#else
#ifdef MTK_MT6739_MTK_CPU_FREQ
extern unsigned int mt_cpufreq_get_freq_by_idx(int id, int idx);
#else
static inline unsigned int mt_cpufreq_get_freq_by_idx(
int cid, int idx) { return 0; }
#endif
#endif
extern int update_userlimit_cpu_freq(int kicker, int num_cluster
, struct cpu_ctrl_data *freq_limit);
extern int update_userlimit_cpu_core(int kicker, int num_cluster
, struct cpu_ctrl_data *core_limit);
extern int sched_isolate_cpu(int cpu);
extern int sched_deisolate_cpu(int cpu);
int update_cpu_core_limit(int kicker, int cid, int min, int max);
void update_isolation_cpu(int kicker, int enable, int cpu);
#endif /* _CPU_CTRL_H */
drivers/misc/mediatek/include/mt-plat/devapc_public.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2021 MediaTek Inc.
*/
#ifndef __DEVAPC_PUBLIC_H__
#define __DEVAPC_PUBLIC_H__
#include <linux/types.h>
enum infra_subsys_id {
INFRA_SUBSYS_MD = 0,
INFRA_SUBSYS_CONN,
INFRA_SUBSYS_ADSP,
INFRA_SUBSYS_GCE,
INFRA_SUBSYS_APMCU,
INFRA_SUBSYS_GZ,
INFRA_SUBSYS_AUDIO,
DEVAPC_SUBSYS_CLKMGR,
DEVAPC_SUBSYS_TEST,
DEVAPC_SUBSYS_RESERVED,
};
enum devapc_cb_status {
DEVAPC_OK = 0,
DEVAPC_NOT_KE,
};
struct devapc_vio_callbacks {
struct list_head list;
enum infra_subsys_id id;
void (*debug_dump)(void);
enum devapc_cb_status (*debug_dump_adv)(uint32_t vio_addr);
};
uint32_t devapc_vio_check(void);
void dump_dbg_info(void);
void register_devapc_vio_callback(struct devapc_vio_callbacks *viocb);
void devapc_catch_illegal_range(phys_addr_t phys_addr, size_t size);
#endif /* __DEVAPC_PUBLIC_H__ */
drivers/misc/mediatek/include/mt-plat/dma.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#define MAX_DMA_ADDRESS (0xFFFFFFFF)
#define MAX_DMA_CHANNELS (0)
#endif /* !__ASM_ARCH_DMA_H */
#ifndef __MT_DMA_H__
#define __MT_DMA_H__
/* define DMA channels */
enum {
G_DMA_1 = 0, G_DMA_2,
P_DMA_AP_HIF, P_DMA_MD_HIF,
P_DMA_SIM1, P_DMA_SIM2,
P_DMA_IRDA,
P_DMA_UART1_TX, P_DMA_UART1_RX,
P_DMA_UART2_TX, P_DMA_UART2_RX,
P_DMA_UART3_TX, P_DMA_UART3_RX,
};
/* define DMA error code */
enum {
DMA_ERR_CH_BUSY = 1,
DMA_ERR_INVALID_CH = 2,
DMA_ERR_CH_FREE = 3,
DMA_ERR_NO_FREE_CH = 4,
DMA_ERR_INV_CONFIG = 5,
};
/* define DMA ISR callback function's prototype */
typedef void (*DMA_ISR_CALLBACK) (void *);
/*
* NoteXXX: Implementation below is obsolete and deprecated.
*/
#include <linux/types.h>
typedef u32 INFO;
enum {
DMA_FALSE = 0,
DMA_TRUE
};
enum {
DMA_OK = 0,
DMA_FAIL
};
enum {
REMAINING_LENGTH = 0, /* not valid for virtual FIFO */
VF_READPTR, /* only valid for virtual FIFO */
VF_WRITEPTR, /* only valid for virtual FIFO */
VF_FFCNT, /* only valid for virtual FIFO */
VF_ALERT, /* only valid for virtual FIFO */
VF_EMPTY, /* only valid for virtual FIFO */
VF_FULL, /* only valid for virtual FIFO */
VF_PORT
};
enum {
GDMA_1 = 0,
GDMA_2,
GDMA_ANY
};
enum {
ALL = 0,
SRC,
DST,
SRC_AND_DST
};
/* define GDMA configurations */
struct mt_gdma_conf {
unsigned int count;
int iten;
unsigned int burst;
int dfix;
int sfix;
unsigned int limiter;
dma_addr_t src;
dma_addr_t dst;
dma_addr_t jump;
int wpen;
int wpsd;
unsigned int wplen;
unsigned int wpto;
/* unsigned int cohen; */
unsigned int domain;
void (*isr_cb)(void *param);
void *data;
};
/* burst */
#define DMA_CON_BURST_SINGLE (0x00000000)
#define DMA_CON_BURST_2BEAT (0x00010000)
#define DMA_CON_BURST_3BEAT (0x00020000)
#define DMA_CON_BURST_4BEAT (0x00030000)
#define DMA_CON_BURST_5BEAT (0x00040000)
#define DMA_CON_BURST_6BEAT (0x00050000)
#define DMA_CON_BURST_7BEAT (0x00060000)
#define DMA_CON_BURST_8BEAT (0x00070000)
/* size */
/* keep for backward compatibility only */
#define DMA_CON_SIZE_BYTE (0x00000000)
#define DMA_CON_SIZE_SHORT (0x00000001)
#define DMA_CON_SIZE_LONG (0x00000002)
extern int mt65xx_free_gdma(int channel);
extern int mt65xx_req_gdma(DMA_ISR_CALLBACK cb, void *data);
extern int mt65xx_start_gdma(int channel);
extern int mt65xx_stop_gdma(int channel);
extern void mt_reset_dma(const unsigned int iChannel);
extern void mt65xx_dma_running_status(void);
extern void mt_reset_gdma_conf(const unsigned int iChannel);
extern int mt_config_gdma(int channel, struct mt_gdma_conf *config, int flag);
extern int mt_free_gdma(int channel);
extern int mt_req_gdma(int chan);
extern int mt_start_gdma(int channel);
extern int mt_polling_gdma(int channel, unsigned long timeout);
extern int mt_stop_gdma(int channel);
extern int mt_dump_gdma(int channel);
extern int mt_warm_reset_gdma(int channel);
extern int mt_hard_reset_gdma(int channel);
extern int mt_reset_gdma(int channel);
extern void mt_dma_running_status(void);
/* This channel is used for APDMA Dummy READ.
* in MT6592 this channel will be used by Frequency hopping all the time
* .Owner: Chieh-Jay Liu
*/
#define DFS_APDMA_CHANNEL 0
#endif /* !__MT_DMA_H__ */
drivers/misc/mediatek/include/mt-plat/dvfsrc-exp.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __DVFSRC_EXP_H
#define __DVFSRC_EXP_H
#define MTK_DVFSRC_NUM_DVFS_OPP 0
#define MTK_DVFSRC_NUM_DRAM_OPP 1
#define MTK_DVFSRC_NUM_VCORE_OPP 2
#define MTK_DVFSRC_CURR_DVFS_OPP 3
#define MTK_DVFSRC_CURR_DRAM_OPP 4
#define MTK_DVFSRC_CURR_VCORE_OPP 5
#define MTK_DVFSRC_CURR_DVFS_LEVEL 6
#define MTK_DVFSRC_CURR_DRAM_KHZ 7
#define MTK_DVFSRC_CURR_VCORE_UV 8
#if IS_ENABLED(CONFIG_MTK_DVFSRC)
extern int mtk_dvfsrc_query_opp_info(u32 id);
extern int mtk_dvfsrc_vcore_opp_count(void);
extern int mtk_dvfsrc_vcore_uv_table(u32 opp);
extern int vcorefs_get_num_opp(void);
extern int vcorefs_get_opp_info_num(void);
extern int vcorefs_get_src_req_num(void);
extern char **vcorefs_get_opp_info_name(void);
extern unsigned int *vcorefs_get_opp_info(void);
extern char **vcorefs_get_src_req_name(void);
extern unsigned int *vcorefs_get_src_req(void);
extern void dvfsrc_set_power_model_ddr_request(u32 level);
extern void dvfsrc_enable_dvfs_freq_hopping(int on);
extern int register_dvfsrc_vchk_notifier(struct notifier_block *nb);
extern int unregister_dvfsrc_vchk_notifier(struct notifier_block *nb);
extern int register_dvfsrc_dump_notifier(struct notifier_block *nb);
extern int unregister_dvfsrc_dump_notifier(struct notifier_block *nb);
extern u32 dvfsrc_get_md_scenario(void);
#else
static inline int mtk_dvfsrc_query_opp_info(u32 id)
{ return 0; }
static inline int mtk_dvfsrc_vcore_opp_count(void)
{ return 0; }
static inline int mtk_dvfsrc_vcore_uv_table(u32 opp)
{ return 0; }
static inline int vcorefs_get_num_opp(void)
{ return 0; }
static inline int vcorefs_get_opp_info_num(void)
{ return 0; }
static inline int vcorefs_get_src_req_num(void)
{ return 0; }
static inline char **vcorefs_get_opp_info_name(void)
{ return NULL; }
static inline unsigned int *vcorefs_get_opp_info(void)
{ return NULL; }
static inline char **vcorefs_get_src_req_name(void)
{ return NULL; }
static inline unsigned int *vcorefs_get_src_req(void)
{ return NULL; }
static inline void dvfsrc_set_power_model_ddr_request(u32 level)
{ }
static inline void dvfsrc_enable_dvfs_freq_hopping(int on)
{ }
static inline int register_dvfsrc_vchk_notifier(struct notifier_block *nb)
{ return 0; }
static inline int unregister_dvfsrc_vchk_notifier(struct notifier_block *nb)
{ return 0; }
static inline int register_dvfsrc_dump_notifier(struct notifier_block *nb)
{ return 0; }
static inline int unregister_dvfsrc_dump_notifier(struct notifier_block *nb)
{ return 0; }
static inline u32 dvfsrc_get_md_scenario(void)
{ return 0; }
#endif /* CONFIG_MTK_DVFSRC */
#endif
drivers/misc/mediatek/include/mt-plat/eas_ctrl.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _EAS_CTRL_H
#define _EAS_CTRL_H
enum {
CGROUP_ROOT = 0,
CGROUP_FG,
CGROUP_BG,
CGROUP_TA,
CGROUP_RT,
NR_CGROUP
};
enum {
EAS_KIR_PERF = 0,
EAS_KIR_BOOT,
EAS_KIR_TOUCH,
EAS_MAX_KIR
};
enum {
EAS_UCLAMP_KIR_PERF = 0,
EAS_UCLAMP_KIR_BOOT,
EAS_UCLAMP_KIR_TOUCH,
EAS_UCLAMP_KIR_FPSGO,
EAS_UCLAMP_KIR_WIFI,
EAS_UCLAMP_KIR_BIG_TASK,
EAS_UCLAMP_MAX_KIR
};
/* stune down thres */
enum {
EAS_THRES_KIR_PERF = 0,
EAS_THRES_KIR_FPSGO,
EAS_THRES_MAX_KIR
};
enum {
EAS_SYNC_FLAG_KIR_PERF = 0,
EAS_SYNC_FLAG_KIR_FPSGO,
EAS_SYNC_FLAG_MAX_KIR
};
enum {
EAS_PREFER_IDLE_KIR_PERF = 0,
EAS_PREFER_IDLE_KIR_FPSGO,
EAS_PREFER_IDLE_MAX_KIR = 16
};
extern int boost_write_for_perf_idx(int group_idx, int boost_value);
extern int uclamp_min_for_perf_idx(int group_idx, int min_value);
extern int prefer_idle_for_perf_idx(int idx, int prefer_idle);
/* perfmgr */
extern int update_eas_uclamp_min(int kicker, int cgroup_idx, int value);
extern int update_schedplus_down_throttle_ns(int kicker, int nsec);
extern int update_schedplus_up_throttle_ns(int kicker, int nsec);
extern int update_schedplus_sync_flag(int kicker, int enable);
extern int update_prefer_idle_value(int kicker, int cgroup_idx, int value);
#define SCHED__UTIL_API_READY 1
#if SCHED__UTIL_API_READY
extern int schedutil_set_down_rate_limit_us(int cpu,
unsigned int rate_limit_us);
extern int schedutil_set_up_rate_limit_us(int cpu,
unsigned int rate_limit_us);
#endif
#endif /* _EAS_CTRL_H */
drivers/misc/mediatek/include/mt-plat/fpsgo_common.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _FPSGO_COMMON_H_
#define _FPSGO_COMMON_H_
#include <linux/hrtimer.h>
#include <linux/ktime.h>
#include <linux/fs.h>
struct fps_level {
int start;
int end;
};
#if defined(CONFIG_MTK_FPSGO) || defined(CONFIG_MTK_FPSGO_V3)
#define FPSGO_SYSTRACE_LIST(macro) \
macro(MANDATORY, 0), \
macro(FBT_GM, 1), \
macro(FSTB, 2), \
macro(XGF, 3), \
macro(MAX, 4), \
#define GENERATE_ENUM(name, shft) FPSGO_DEBUG_##name = 1U << shft
enum {
FPSGO_SYSTRACE_LIST(GENERATE_ENUM)
};
#define FPSFO_DECLARE_SYSTRACE(prefix, name) \
extern struct tracepoint __tracepoint_##name; \
int prefix##_reg_trace_##name(void *probe, void *data) \
{ \
return tracepoint_probe_register( \
&__tracepoint_##name, (void *)probe, data); \
} \
int prefix##_unreg_trace_##name(void *probe, void *data) \
{ \
return tracepoint_probe_unregister( \
&__tracepoint_##name, (void *)probe, data); \
}
extern uint32_t fpsgo_systrace_mask;
extern struct dentry *fpsgo_debugfs_dir;
extern int game_ppid;
void __fpsgo_systrace_c(pid_t pid, unsigned long long bufID,
int value, const char *name, ...);
void __fpsgo_systrace_b(pid_t pid, const char *name, ...);
void __fpsgo_systrace_e(void);
#define fpsgo_systrace_c(mask, pid, bufID, val, fmt...) \
do { \
if (fpsgo_systrace_mask & mask) \
__fpsgo_systrace_c(pid, bufID, val, fmt); \
} while (0)
#define fpsgo_systrace_b(mask, tgid, fmt, ...) \
do { \
if (fpsgo_systrace_mask & mask) \
__fpsgo_systrace_b(tgid, fmt); \
} while (0)
#define fpsgo_systrace_e(mask) \
do { \
if (fpsgo_systrace_mask & mask) \
__fpsgo_systrace_e(); \
} while (0)
#define fpsgo_systrace_c_fbt_gm(pid, bufID, val, fmt...) \
fpsgo_systrace_c(FPSGO_DEBUG_FBT_GM, pid, bufID, val, fmt)
#define fpsgo_systrace_c_fstb(pid, bufID, val, fmt...) \
fpsgo_systrace_c(FPSGO_DEBUG_FSTB, pid, bufID, val, fmt)
#define fpsgo_systrace_c_xgf(pid, bufID, val, fmt...) \
fpsgo_systrace_c(FPSGO_DEBUG_XGF, pid, bufID, val, fmt)
#define fpsgo_systrace_c_log(val, fmt...) \
do { \
if (game_ppid > 0) \
fpsgo_systrace_c(FPSGO_DEBUG_MANDATORY, \
game_ppid, val, fmt); \
} while (0)
#define fpsgo_systrace_c_fbt(pid, bufID, val, fmt...) \
fpsgo_systrace_c(FPSGO_DEBUG_MANDATORY, pid, bufID, val, fmt)
int fpsgo_is_fstb_enable(void);
int fpsgo_switch_fstb(int enable);
int fpsgo_fstb_sample_window(long long time_usec);
int fpsgo_fstb_fps_range(int nr_level, struct fps_level *level);
int fpsgo_fstb_fps_error_threhosld(int threshold);
int fpsgo_fstb_percentile_frametime(int ratio);
int fpsgo_fstb_force_vag(int arg);
int fpsgo_fstb_vag_fps(int arg);
void fpsgo_switch_enable(int enable);
int fpsgo_is_enable(void);
int fbt_cpu_set_bhr(int new_bhr);
int fbt_cpu_set_bhr_opp(int new_opp);
int fbt_cpu_set_rescue_opp_c(int new_opp);
int fbt_cpu_set_rescue_opp_f(int new_opp);
int fbt_cpu_set_rescue_percent(int percent);
int fbt_cpu_set_variance(int var);
int fbt_cpu_set_floor_bound(int bound);
int fbt_cpu_set_floor_kmin(int k);
int fbt_cpu_set_floor_opp(int new_opp);
#else
static inline void fpsgo_systrace_c(uint32_t m, pid_t id,
unsigned long long bufID, int val, const char *s, ...) { }
static inline void fpsgo_systrace_b(uint32_t m, pid_t id,
const char *s, ...) { }
static inline void fpsgo_systrace_e(uint32_t m) { }
static inline void fpsgo_systrace_c_fbt_gm(pid_t id,
unsigned long long bufID, int val, const char *s, ...) { }
static inline void fpsgo_systrace_c_fstb(pid_t id,
unsigned long long bufID, int val, const char *s, ...) { }
static inline void fpsgo_systrace_c_xgf(pid_t id,
unsigned long long bufID, int val, const char *s, ...) { }
static inline void fpsgo_systrace_c_log(pid_t id, int val,
const char *s, ...) { }
static inline int fpsgo_is_fstb_enable(void) { return 0; }
static inline int fpsgo_switch_fstb(int en) { return 0; }
static inline int fpsgo_fstb_sample_window(long long time_usec) { return 0; }
static inline int fpsgo_fstb_fps_range(int nr_level, struct fps_level *level)
{ return 0; }
static inline int fpsgo_fstb_fps_error_threhosld(int threshold) { return 0; }
static inline int fpsgo_fstb_percentile_frametime(int ratio) { return 0; }
static inline int fpsgo_fstb_force_vag(int arg) { return 0; }
static inline int fpsgo_fstb_vag_fps(int arg) { return 0; }
static inline void fpsgo_switch_enable(int enable) { }
static inline int fpsgo_is_enable(void) { return 0; }
static inline int fbt_cpu_set_bhr(int new_bhr) { return 0; }
static inline int fbt_cpu_set_bhr_opp(int new_opp) { return 0; }
static inline int fbt_cpu_set_rescue_opp_c(int new_opp) { return 0; }
static inline int fbt_cpu_set_rescue_opp_f(int new_opp) { return 0; }
static inline int fbt_cpu_set_rescue_percent(int percent) { return 0; }
static inline int fbt_cpu_set_variance(int var) { return 0; }
static inline int fbt_cpu_set_floor_bound(int bound) { return 0; }
static inline int fbt_cpu_set_floor_kmin(int k) { return 0; }
static inline int fbt_cpu_set_floor_opp(int new_opp) { return 0; }
#endif
#if defined(CONFIG_MTK_FPSGO) || defined(CONFIG_MTK_FPSGO_V3)
void xgf_igather_timer(const void * const t, int v);
void xgf_epoll_igather_timer(const void * const t, ktime_t *to, int v);
void xgf_qudeq_notify(unsigned int cmd, unsigned long arg);
void fpsgo_update_render_dep(struct task_struct *p);
#else
static inline void xgf_igather_timer(const void * const t, int v) { }
static inline void xgf_epoll_igather_timer(const void * const t,
ktime_t *to, int v) { }
static inline void xgf_qudeq_notify(unsigned int cmd, unsigned long arg) { }
static inline void fpsgo_update_render_dep(struct task_struct *p) { }
#endif
#if defined(CONFIG_MTK_FPSGO_V3)
int fpsgo_notify_gpu_block(int tid, unsigned long long mid, int begin);
#else
static inline int fpsgo_notify_gpu_block(int tid,
unsigned long long mid, int begin) { return -1; }
#endif
#endif
drivers/misc/mediatek/include/mt-plat/leakage_table_v2/mtk_spower_data.h
+85
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 MediaTek Inc.
*/
#ifndef __MTK_SPOWER_DATA_H__
#define __MTK_SPOWER_DATA_H__
#include "mtk_static_power.h"
struct spower_raw_t {
int vsize;
int tsize;
int table_size;
int *table[3];
unsigned int devinfo_domain;
unsigned int spower_id;
unsigned int leakage_id;
unsigned int instance;
bool print_leakage;
};
#if defined(CONFIG_MTK_STATIC_POWER)
#include "mtk_spower_data_platform.h"
#endif
struct voltage_row_s {
int mV[VSIZE];
};
struct temperature_row_s {
int deg;
int mA[VSIZE];
};
struct sptab_s {
int vsize;
int tsize;
int *data; /* array[VSIZE + TSIZE + (VSIZE*TSIZE)] */
struct voltage_row_s *vrow; /* pointer to voltage row of data */
struct temperature_row_s *trow; /* pointer to temperature row of data */
unsigned int devinfo_domain;
unsigned int spower_id;
unsigned int leakage_id;
unsigned int instance;
bool print_leakage;
};
struct sptab_list {
struct sptab_s tab_raw[MAX_TABLE_SIZE];
};
#define trow(tab, ti) ((tab)->trow[ti])
#define mA(tab, vi, ti) ((tab)->trow[ti].mA[vi])
#define mV(tab, vi) ((tab)->vrow[0].mV[vi])
#define deg(tab, ti) ((tab)->trow[ti].deg)
#define vsize(tab) ((tab)->vsize)
#define tsize(tab) ((tab)->tsize)
#define tab_validate(tab) (!!(tab) && (tab)->data != NULL)
static inline void spower_tab_construct(struct sptab_s *tab,
struct spower_raw_t *raw, unsigned int id)
{
int i;
struct sptab_s *ptab = (struct sptab_s *)tab;
for (i = 0; i < raw->table_size; i++) {
ptab->vsize = raw->vsize;
ptab->tsize = raw->tsize;
ptab->data = raw->table[i];
ptab->vrow = (struct voltage_row_s *)ptab->data;
ptab->trow = (struct temperature_row_s *)
(ptab->data + ptab->vsize);
ptab->devinfo_domain = raw->devinfo_domain;
ptab->spower_id = id;
ptab->leakage_id = raw->leakage_id;
ptab->instance = raw->instance;
ptab->print_leakage = raw->print_leakage;
ptab++;
}
}
#endif
drivers/misc/mediatek/include/mt-plat/leakage_table_v2/mtk_spower_data_platform.h
+1200
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drivers/misc/mediatek/include/mt-plat/leakage_table_v2/mtk_static_power.h
+32
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@@ -0,0 +1,32 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2017 MediaTek Inc.
*/
#ifndef __MTK_STATIC_POWER_H__
#define __MTK_STATIC_POWER_H__
#include <linux/types.h>
/* #define MTK_SPOWER_UT */
#if defined(CONFIG_MTK_STATIC_POWER)
#include "mtk_static_power_platform.h"
#endif
/*
* @argument
* dev: the enum of MT_SPOWER_xxx
* voltage: the operating voltage, mV.
* degree: the Tj. (degree C)
* @return
* -1, means sptab is not yet ready.
* other value: the mW of leakage value.
*/
extern int mt_spower_get_leakage(int dev, unsigned int voltage, int degree);
extern int mt_spower_get_efuse_lkg(int dev);
extern int mt_spower_init(void);
#endif
drivers/misc/mediatek/include/mt-plat/leakage_table_v2/mtk_static_power_platform.h
+104
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2015 MediaTek Inc.
*/
#ifndef __MTK_STATIC_POWER_MTK6779_H__
#define __MTK_STATIC_POWER_MTK6779_H__
/* #define SPOWER_NOT_READY 1 */
/* #define WITHOUT_LKG_EFUSE */
/* mv */
#define V_OF_FUSE_CPU 900
#define V_OF_FUSE_GPU 800
#define V_OF_FUSE_VCORE 800
#define V_OF_FUSE_MODEM 850
#define V_OF_FUSE_VPU 800
#define T_OF_FUSE 30
/* devinfo offset for each bank */
/* CCI use LL leakage */
#define DEVINFO_IDX_LL 0x220 /* 07B8 */
#define DEVINFO_IDX_L 0x220 /* 07B8 */
#define DEVINFO_IDX_CCI 0x220 /* 07BC */
#define DEVINFO_IDX_GPU 0x224 /* 07BC */
#define DEVINFO_IDX_VCORE 0x224 /* 07BC */
#define DEVINFO_IDX_MODEM 0x224 /* 07BC */
#define DEVINFO_IDX_VPU 0x220 /* 07B8 */
#define DEVINFO_OFF_LL 0
#define DEVINFO_OFF_L 8
#define DEVINFO_OFF_CCI 24
#define DEVINFO_OFF_GPU 16
#define DEVINFO_OFF_VCORE 8
#define DEVINFO_OFF_MODEM 0
#define DEVINFO_OFF_VPU 16
/* default leakage value for each bank */
#define DEF_CPULL_LEAKAGE 60
#define DEF_CPUL_LEAKAGE 54
#define DEF_CCI_LEAKAGE 10
#define DEF_GPU_LEAKAGE 32
#define DEF_VCORE_LEAKAGE 41
#define DEF_MODEM_LEAKAGE 39
#define DEF_VPU_LEAKAGE 2
enum {
MTK_SPOWER_CPULL,
MTK_SPOWER_CPUL,
MTK_SPOWER_CCI,
MTK_SPOWER_GPU,
MTK_SPOWER_VCORE,
MTK_SPOWER_MODEM,
MTK_SPOWER_VPU,
MTK_SPOWER_MAX
};
enum {
MTK_LL_LEAKAGE,
MTK_L_LEAKAGE,
MTK_CCI_LEAKAGE,
MTK_GPU_LEAKAGE,
MTK_VCORE_LEAKAGE,
MTK_MODEM_LEAKAGE,
MTK_VPU_LEAKAGE,
MTK_LEAKAGE_MAX
};
/* record leakage information that read from efuse */
struct spower_leakage_info {
const char *name;
unsigned int devinfo_idx;
unsigned int devinfo_offset;
unsigned int value;
unsigned int v_of_fuse;
int t_of_fuse;
};
extern struct spower_leakage_info spower_lkg_info[MTK_SPOWER_MAX];
/* efuse mapping */
/* 3967 modify */
#define LL_DEVINFO_DOMAIN (BIT(MTK_SPOWER_CPULL))
#define L_DEVINFO_DOMAIN (BIT(MTK_SPOWER_CPUL))
#define CCI_DEVINFO_DOMAIN (BIT(MTK_SPOWER_CCI))
#define GPU_DEVINFO_DOMAIN (BIT(MTK_SPOWER_GPU))
#define VCORE_DEVINFO_DOMAIN (BIT(MTK_SPOWER_VCORE))
#define MODEM_DEVINFO_DOMAIN (BIT(MTK_SPOWER_MODEM))
#define VPU_DEVINFO_DOMAIN (BIT(MTK_SPOWER_VPU))
/* used to calculate total leakage that search from raw table */
#define DEFAULT_CORE_INSTANCE 4
#define DEFAULT_LL_CORE_INSTANCE 6
#define DEFAULT_L_CORE_INSTANCE 2
#define DEFAULT_INSTANCE 1
extern char *spower_name[];
extern char *leakage_name[];
extern int default_leakage[];
extern int devinfo_idx[];
extern int devinfo_offset[];
extern int devinfo_table[];
#endif
drivers/misc/mediatek/include/mt-plat/mboot_params.h
+1054
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drivers/misc/mediatek/include/mt-plat/met_drv.h
+602
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef MET_DRV
#define MET_DRV
#include <linux/version.h>
#include <linux/device.h>
#include <linux/percpu.h>
#include <linux/hardirq.h>
#include <linux/clk.h>
extern int met_mode;
#define MET_MODE_TRACE_CMD_OFFSET (1)
#define MET_MODE_TRACE_CMD (1<<MET_MODE_TRACE_CMD_OFFSET)
#define MET_STRBUF_SIZE 1024
DECLARE_PER_CPU(char[MET_STRBUF_SIZE], met_strbuf_nmi);
DECLARE_PER_CPU(char[MET_STRBUF_SIZE], met_strbuf_irq);
DECLARE_PER_CPU(char[MET_STRBUF_SIZE], met_strbuf_sirq);
DECLARE_PER_CPU(char[MET_STRBUF_SIZE], met_strbuf);
#ifdef CONFIG_TRACING
#define TRACE_PUTS(p) \
do { \
trace_puts(p);; \
} while (0)
#else
#define TRACE_PUTS(p) do {} while (0)
#endif
#define GET_MET_PRINTK_BUFFER_ENTER_CRITICAL() \
({ \
char *pmet_strbuf; \
preempt_disable(); \
if (in_nmi()) \
pmet_strbuf = per_cpu(met_strbuf_nmi, \
smp_processor_id()); \
else if (in_irq()) \
pmet_strbuf = per_cpu(met_strbuf_irq, \
smp_processor_id()); \
else if (in_softirq()) \
pmet_strbuf = per_cpu(met_strbuf_sirq, \
smp_processor_id()); \
else \
pmet_strbuf = per_cpu(met_strbuf, \
smp_processor_id()); \
pmet_strbuf;\
})
#define PUT_MET_PRINTK_BUFFER_EXIT_CRITICAL(pmet_strbuf) \
do {\
if (pmet_strbuf)\
TRACE_PUTS(pmet_strbuf); \
preempt_enable_no_resched(); \
} while (0)
#define MET_PRINTK(FORMAT, args...) \
do { \
char *pmet_strbuf; \
preempt_disable(); \
if (in_nmi()) \
pmet_strbuf = per_cpu(met_strbuf_nmi, \
smp_processor_id()); \
else if (in_irq()) \
pmet_strbuf = per_cpu(met_strbuf_irq, \
smp_processor_id()); \
else if (in_softirq()) \
pmet_strbuf = per_cpu(met_strbuf_sirq, \
smp_processor_id()); \
else \
pmet_strbuf = per_cpu(met_strbuf, smp_processor_id()); \
if (met_mode & MET_MODE_TRACE_CMD) \
snprintf(pmet_strbuf, \
MET_STRBUF_SIZE, \
"%s: " FORMAT, \
__func__, \
##args); \
else \
snprintf(pmet_strbuf, \
MET_STRBUF_SIZE, \
FORMAT, \
##args); \
TRACE_PUTS(pmet_strbuf); \
preempt_enable_no_resched(); \
} while (0)
/*
* SOB: start of buf
* EOB: end of buf
*/
#define MET_PRINTK_GETBUF(pSOB, pEOB) \
({ \
preempt_disable(); \
if (in_nmi()) \
*pSOB = per_cpu(met_strbuf_nmi, smp_processor_id()); \
else if (in_irq()) \
*pSOB = per_cpu(met_strbuf_irq, smp_processor_id()); \
else if (in_softirq()) \
*pSOB = per_cpu(met_strbuf_sirq, smp_processor_id()); \
else \
*pSOB = per_cpu(met_strbuf, smp_processor_id()); \
*pEOB = *pSOB; \
if (met_mode & MET_MODE_TRACE_CMD) \
*pEOB += snprintf(*pEOB, \
MET_STRBUF_SIZE, \
"%s: ", \
__func__); \
})
#define MET_PRINTK_PUTBUF(SOB, EOB) \
({ \
__trace_puts(_THIS_IP_, (SOB), (uintptr_t)((EOB)-(SOB))); \
preempt_enable_no_resched(); \
})
#define MET_FTRACE_PRINTK(TRACE_NAME, args...) \
do { \
trace_##TRACE_NAME(args);; \
} while (0)
#define MET_TYPE_PMU 1
#define MET_TYPE_BUS 2
#define MET_TYPE_MISC 3
struct metdevice {
struct list_head list;
int type;
const char *name;
struct module *owner;
struct kobject *kobj;
int (*create_subfs)(struct kobject *parent);
void (*delete_subfs)(void);
int mode;
int ondiemet_mode; /* new for ondiemet; 1: call ondiemet functions */
int cpu_related;
int polling_interval;
int polling_count_reload;
int __percpu *polling_count;
int header_read_again; /*for header size > 1 page*/
void (*start)(void);
void (*stop)(void);
int (*reset)(void);
void (*timed_polling)(unsigned long long stamp, int cpu);
void (*tagged_polling)(unsigned long long stamp, int cpu);
int (*print_help)(char *buf, int len);
int (*print_header)(char *buf, int len);
int (*process_argument)(const char *arg, int len);
void (*ondiemet_start)(void);
void (*ondiemet_stop)(void);
int (*ondiemet_reset)(void);
int (*ondiemet_print_help)(char *buf, int len);
int (*ondiemet_print_header)(char *buf, int len);
int (*ondiemet_process_argument)(const char *arg, int len);
void (*ondiemet_timed_polling)(unsigned long long stamp, int cpu);
void (*ondiemet_tagged_polling)(unsigned long long stamp, int cpu);
struct list_head exlist; /* for linked list before register */
void (*suspend)(void);
void (*resume)(void);
unsigned long long prev_stamp;
spinlock_t my_lock;
void *reversed1;
};
int met_register(struct metdevice *met);
int met_deregister(struct metdevice *met);
int met_set_platform(const char *plf_name, int flag);
int met_set_topology(const char *topology_name, int flag);
int met_devlink_add(struct metdevice *met);
int met_devlink_del(struct metdevice *met);
int met_devlink_register_all(void);
int met_devlink_deregister_all(void);
int fs_reg(void);
void fs_unreg(void);
/******************************************************************************
* Tracepoints
******************************************************************************/
#define MET_DEFINE_PROBE(probe_name, proto) \
static void probe_##probe_name(void *data, PARAMS(proto))
#define MET_REGISTER_TRACE(probe_name) \
register_trace_##probe_name(probe_##probe_name, NULL)
#define MET_UNREGISTER_TRACE(probe_name) \
unregister_trace_##probe_name(probe_##probe_name, NULL)
/* ====================== Tagging API ================================ */
#define MAX_EVENT_CLASS 31
#define MAX_TAGNAME_LEN 128
#define MET_CLASS_ALL 0x80000000
/* IOCTL commands of MET tagging */
struct mtag_cmd_t {
unsigned int class_id;
unsigned int value;
unsigned int slen;
char tname[MAX_TAGNAME_LEN];
void *data;
unsigned int size;
};
#define TYPE_START 1
#define TYPE_END 2
#define TYPE_ONESHOT 3
#define TYPE_ENABLE 4
#define TYPE_DISABLE 5
#define TYPE_REC_SET 6
#define TYPE_DUMP 7
#define TYPE_DUMP_SIZE 8
#define TYPE_DUMP_SAVE 9
#define TYPE_USRDATA 10
#define TYPE_DUMP_AGAIN 11
#define TYPE_ASYNC_START 12
#define TYPE_ASYNC_END 13
/* Use 'm' as magic number */
#define MTAG_IOC_MAGIC 'm'
/* Please use a different 8-bit number in your code */
#define MTAG_CMD_START _IOW(MTAG_IOC_MAGIC, \
TYPE_START, \
struct mtag_cmd_t)
#define MTAG_CMD_END _IOW(MTAG_IOC_MAGIC, \
TYPE_END, \
struct mtag_cmd_t)
#define MTAG_CMD_ONESHOT _IOW(MTAG_IOC_MAGIC, \
TYPE_ONESHOT, \
struct mtag_cmd_t)
#define MTAG_CMD_ENABLE _IOW(MTAG_IOC_MAGIC, \
TYPE_ENABLE, \
int)
#define MTAG_CMD_DISABLE _IOW(MTAG_IOC_MAGIC, \
TYPE_DISABLE, \
int)
#define MTAG_CMD_REC_SET _IOW(MTAG_IOC_MAGIC, \
TYPE_REC_SET, \
int)
#define MTAG_CMD_DUMP _IOW(MTAG_IOC_MAGIC, \
TYPE_DUMP, \
struct mtag_cmd_t)
#define MTAG_CMD_DUMP_SIZE _IOWR(MTAG_IOC_MAGIC, \
TYPE_DUMP_SIZE, \
int)
#define MTAG_CMD_DUMP_SAVE _IOW(MTAG_IOC_MAGIC, \
TYPE_DUMP_SAVE, \
struct mtag_cmd_t)
#define MTAG_CMD_USRDATA _IOW(MTAG_IOC_MAGIC, \
TYPE_USRDATA, \
struct mtag_cmd_t)
#define MTAG_CMD_DUMP_AGAIN _IOW(MTAG_IOC_MAGIC, \
TYPE_DUMP_AGAIN, \
void *)
#define MTAG_CMD_ASYNC_START _IOW(MTAG_IOC_MAGIC, \
TYPE_ASYNC_START, \
struct mtag_cmd_t)
#define MTAG_CMD_ASYNC_END _IOW(MTAG_IOC_MAGIC, \
TYPE_ASYNC_END, \
struct mtag_cmd_t)
/* include file */
#ifndef MET_USER_EVENT_SUPPORT
#define met_tag_init() ({ 0; })
#define met_tag_uninit() ({ 0; })
#define met_tag_start(id, name) ({ 0; })
#define met_tag_end(id, name) ({ 0; })
#define met_tag_async_start(id, name, cookie) ({0; })
#define met_tag_async_end(id, name, cookie) ({0; })
#define met_tag_oneshot(id, name, value) ({ 0; })
#define met_tag_userdata(pData) ({ 0; })
#define met_tag_dump(id, name, data, length) ({ 0; })
#define met_tag_disable(id) ({ 0; })
#define met_tag_enable(id) ({ 0; })
#define met_set_dump_buffer(size) ({ 0; })
#define met_save_dump_buffer(pathname) ({ 0; })
#define met_save_log(pathname) ({ 0; })
#define met_record_on() ({ 0; })
#define met_record_off() ({ 0; })
#define met_show_bw_limiter() ({ 0; })
#define met_reg_bw_limiter() ({ 0; })
#define met_show_clk_tree() ({ 0; })
#define met_reg_clk_tree() ({ 0; })
#define met_ccf_clk_enable(clk) ({ 0; })
#define met_ccf_clk_disable(clk) ({ 0; })
#define met_ccf_clk_set_rate(clk, top) ({ 0; })
#define met_ccf_clk_set_parent(clk, parent) ({ 0; })
#define met_fh_print_dds(pll_id, dds_value) ({ 0; })
#define enable_met_backlight_tag() ({ 0; })
#define output_met_backlight_tag(level) ({ 0; })
#define met_show_pmic_info(RegNum, pmic_reg) ({ 0; })
#else
#include <linux/kernel.h>
extern int met_tag_init(void);
extern int met_tag_uninit(void);
extern int met_tag_start(unsigned int class_id,
const char *name);
extern int met_tag_end(unsigned int class_id,
const char *name);
extern int met_tag_async_start(unsigned int class_id,
const char *name,
unsigned int cookie);
extern int met_tag_async_end(unsigned int class_id,
const char *name,
unsigned int cookie);
extern int met_tag_oneshot(unsigned int class_id,
const char *name,
unsigned int value);
extern int met_tag_userdata(char *pData);
extern int met_tag_dump(unsigned int class_id,
const char *name,
void *data,
unsigned int length);
extern int met_tag_disable(unsigned int class_id);
extern int met_tag_enable(unsigned int class_id);
extern int met_set_dump_buffer(int size);
extern int met_save_dump_buffer(const char *pathname);
extern int met_save_log(const char *pathname);
extern int met_show_bw_limiter(void);
extern int met_reg_bw_limiter(void *fp);
extern int met_show_clk_tree(const char *name,
unsigned int addr,
unsigned int status);
extern int met_reg_clk_tree(void *fp);
#if 0 /* no used now */
extern int met_ccf_clk_enable(struct clk *clk);
extern int met_ccf_clk_disable(struct clk *clk);
extern int met_ccf_clk_set_rate(struct clk *clk,
struct clk *top);
extern int met_ccf_clk_set_parent(struct clk *clk,
struct clk *parent);
extern unsigned int __attribute__((weak)) met_fh_dds[];
extern int met_fh_print_dds(int pll_id, unsigned int dds_value);
#endif /* no used now */
extern int enable_met_backlight_tag(void);
extern int output_met_backlight_tag(int level);
extern void met_show_pmic_info(unsigned int RegNum,
unsigned int pmic_reg);
#define met_record_on() tracing_on()
#define met_record_off() tracing_off()
#endif /* MET_USER_EVENT_SUPPORT */
/*
* udmet API ( user-defined met )
*/
#if 0 /* no support 1 */
typedef void (*MET_UDMET_POLLING_FUNC)(unsigned long long stamp, int cpu);
extern void _met_udmet_register_polling(char *mod_name,
MET_UDMET_POLLING_FUNC polling_func,
unsigned int period_multiply);
#define met_udmet_register_polling(mod_name, polling_func, period_multiply) \
{\
if (_met_udmet_register_polling)\
_met_udmet_register_polling(mod_name, \
polling_func, \
period_multiply); \
}
#endif /* no support 1 */
/*
* Wrapper for DISP/MDP/GCE mmsys profiling
*/
extern void met_mmsys_event_gce_thread_begin(ulong thread_no,
ulong task_handle,
ulong engineFlag,
void *pCmd,
ulong size);
extern void met_mmsys_event_gce_thread_end(ulong thread_no,
ulong task_handle,
ulong engineFlag);
extern void met_mmsys_event_disp_sof(int mutex_id);
extern void met_mmsys_event_disp_mutex_eof(int mutex_id);
extern void met_mmsys_event_disp_ovl_eof(int ovl_id);
extern void met_mmsys_config_isp_base_addr(unsigned long *isp_reg_list);
extern void met_mmsys_event_isp_pass1_begin(int sensor_id);
extern void met_mmsys_event_isp_pass1_end(int sensor_id);
#if 0 /* no support 2 */
/* ====================== SPO API ================================ */
enum MET_SPO_MEM_MODULE {
MSMM_ISP_P1_IMGO,
MSMM_ISP_P1_RRZO,
MSMM_ISP_P2_IMGI,
MSMM_MDP_RDMA0,
MSMM_MDP_RDMA1,
MSMM_MDP_WDMA0,
MSMM_MDP_WDMA1,
MSMM_CODEC_READ,
MSMM_CODE_WRITE,
MSMM_DISP_RDMA0,
MSMM_DISP_RDMA1,
MSMM_DISP_WDMA0,
MSMM_DISP_WDMA1,
/*Base index of OVL layers, use param1 to assign layer offset*/
MSMM_DISP_OVL_L_0,
MSMM_DISP_OVL_L_1,
MSMM_DISP_OVL_L_2,
MSMM_DISP_OVL_L_3,
MSMM_DISP_OVL_L_4,
MSMM_DISP_OVL_L_5,
MSMM_DISP_OVL_L_6,
MSMM_DISP_OVL_L_7,
MSMM_DISP_OVL_L_8,
MSMM_DISP_OVL_L_9,
MSMM_DISP_OVL_L_10,
MSMM_DISP_OVL_L_11,
MSMM_DISP_OVL_L_12,
MSMM_DISP_OVL_L_13,
MSMM_DISP_OVL_L_14,
MSMM_DISP_OVL_L_15,
};
enum MET_SPO_MEM_ACCESS_TYPE {
MSMA_READ = 0,
MSMA_WRITE
};
extern void _met_spo_mem_decl(enum MET_SPO_MEM_MODULE mod,
enum MET_SPO_MEM_ACCESS_TYPE type,
unsigned long memory_bw_in_bit,
unsigned long estimated_exe_time_in_us,
unsigned long param1,
unsigned long param2);
extern void _met_spo_mem_alloc(enum MET_SPO_MEM_MODULE mod,
unsigned long param1,
unsigned long param2);
extern void _met_spo_mem_free(enum MET_SPO_MEM_MODULE mod,
unsigned long param1,
unsigned long param2);
/*invoke before SOF*/
#define met_spo_mem_decl(...) \
do { \
if (_met_spo_mem_decl) \
_met_spo_mem_decl(__VA_ARGS__); \
} while (0)
/*invoke when SOF*/
#define met_spo_mem_alloc(...) \
do { \
if (_met_spo_mem_alloc) \
_met_spo_mem_alloc(__VA_ARGS__);\
} while (0)
/*invoke when EOF*/
#define met_spo_mem_free(...) \
do { \
if (_met_spo_mem_free) \
_met_spo_mem_free(__VA_ARGS__); \
} while (0)
#endif /* no support 2 */
/* =================== MMSYS Platform Depend ============================= */
#if defined(CONFIG_MTK_MET)
#if defined(CONFIG_MACH_MT6757)
/* #pragma message("MET MMSYS 6757 include") */
#include "../met/mt6757/platform/mt6757/met_drv_udtl.h"
#elif defined(CONFIG_MACH_MT6799)
/* #pragma message("MET MMSYS 6799 include") */
#include "../met/mt6799/platform/mt6799/met_drv_udtl.h"
#else
/* #pragma message("MET MMSYS include not found!") */
#include "met_drv_udtl_null.h"
#endif
#else
/* #pragma message("MET MMSYS Null include") */
#include "met_drv_udtl_null.h"
#endif
/* ====================== SMI/EMI Interface ================================ */
enum SMI_DEST {
SMI_DEST_ALL = 0,
SMI_DEST_EMI = 1,
SMI_DEST_INTERNAL = 2,
SMI_DEST_NONE = 9
};
enum SMI_RW {
SMI_RW_ALL = 0,
SMI_READ_ONLY = 1,
SMI_WRITE_ONLY = 2,
SMI_RW_RESPECTIVE = 3,
SMI_RW_NONE = 9
};
enum SMI_BUS {
SMI_BUS_GMC = 0,
SMI_BUS_AXI = 1,
SMI_BUS_NONE = 9
};
enum SMI_REQUEST {
SMI_REQ_ALL = 0,
SMI_REQ_ULTRA = 1,
SMI_REQ_PREULTRA = 2,
SMI_NORMAL_ULTRA = 3,
SMI_REQ_NONE = 9
};
struct met_smi_conf {
/* Ex : Whitney: 0~8 for larb0~larb8, 9 for common larb */
unsigned int master;
/*
* port select:
* [0] only for legacy mode,
* [0~3] ports for parallel mode, -1 no select
*/
int port[4];
/*
* Selects request type:
* 0 for all,
* 1 for ultra,
* 2 for preultra,
* 3 for normal
*/
unsigned int reqtype;
/*
* Selects read/write:
* 0 for R+W,
* 1 for read,
* 2 for write
*
* [0] for legacy and parallel larb0~8,
* [0~3] for parallel mode common
*/
unsigned int rwtype[4];
/*
* Selects destination:
* 0 and 3 for all memory,
* 1 for External,
* 2 for internal
*/
unsigned int desttype;
};
#endif /* MET_DRV */
drivers/misc/mediatek/include/mt-plat/met_drv_udtl_null.h
+56
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef MET_DRV_UDTL_H
#define MET_DRV_UDTL_H
/******************************************************************************
* User-Defined Trace Line
******************************************************************************/
#define MET_UDTL_PROP_TYPE ulong
/*
* Declare PROPS Data Structure
*/
/*
* Instance a PROPS Structure
*/
#define MET_UDTL_DEFINE_PROP(_PROPS_NAME_)
/*
* PROPS Structure related
*/
#define MET_UDTL_PROP_DATATYPE(_PROPS_NAME_)
#define MET_UDTL_PROP_SIZE(_PROPS_NAME_) (0)
/*
* Access PROPS Structure
*/
#define MET_UDTL_GET_PROP_POINTER(_PROPS_NAME_) (NULL)
#define MET_UDTL_SET_PROP(_PROPS_NAME_, _FIELD_NAME_, _VALUE_)
#define MET_UDTL_SET_PROP_POINTER(_PROPS_POINTER_NAME_, _FIELD_NAME_, _VALUE_)
#define MET_UDTL_CLEAR_PROP(_PROPS_NAME_)
/*
* Functions Call
*/
#define MET_UDTL_TRACELINE_BEGIN(_PAGE_NAME_, _TRACELINE_NAME_, _FMTSTR_, ...)
#define MET_UDTL_TRACELINE_END(_PAGE_NAME_, _TRACELINE_NAME_, _FMTSTR_, ...)
#define MET_UDTL_TRACELINE_PROP(_PAGE_NAME_, _TRACELINE_NAME_, _PROPS_NAME_)
#define MET_UDTL_TRACELINE_DEBUG(_PAGE_NAME_, _TRACELINE_NAME_, _DEBUG_STR_)
#define MET_UDTL_IS_TRACELINE_ON(_PAGE_NAME_, _TRACELINE_NAME_) (0)
#endif /* MET_DRV_UDTL_H */
drivers/misc/mediatek/include/mt-plat/mmpath.h
+45
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Joey Pan <joey.pan@mediatek.com>
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM mmpath
#if !defined(MMPATH_H) || defined(TRACE_HEADER_MULTI_READ)
#define MMPATH_H
#include <linux/tracepoint.h>
#ifndef TRACING_UNIT
#define TRACING_UNIT
#endif /* TRACING_UNIT */
TRACE_EVENT(MMPath,
TP_PROTO(char *string),
TP_ARGS(string),
TP_STRUCT__entry(
__string(str, string)
),
TP_fast_assign(
__assign_str(str, string);
),
TP_printk("%s", __get_str(str))
);
#endif /* MMPATH_H */
/* This part must be outside protection */
#undef TRACE_INCLUDE_PATH
#define TRACE_INCLUDE_PATH .
#undef TRACE_INCLUDE_FILE
#define TRACE_INCLUDE_FILE mmpath
#include <trace/define_trace.h>
drivers/misc/mediatek/include/mt-plat/monitor_hang.h
+46
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2019 MediaTek Inc.
*/
#if !defined(__MONITOR_HANG_H__)
#define __MONITOR_HANG_H__
#define HD_PROC "hang_detect"
#define HD_INTER 30 /* 1 tick is 30 seconds*/
struct name_list {
char name[TASK_COMM_LEN + 1];
struct name_list *next;
};
/* hang detect timeout value*/
#define COUNT_SWT_INIT 0
#define COUNT_SWT_NORMAL 10
#define COUNT_SWT_FIRST 12
#define COUNT_ANDROID_REBOOT 11
#define COUNT_SWT_CREATE_DB 14
#define COUNT_NE_EXCEPION 20
#define COUNT_AEE_COREDUMP 40
#define COUNT_COREDUMP_DONE 19
/*monitor hang ioctl*/
#define HANG_KICK _IOR('p', 0x0A, int)
#define HANG_SET_SF_STATE _IOR('p', 0x0C, long long)
#define HANG_GET_SF_STATE _IOW('p', 0x0D, long long)
#define HANG_SET_FLAG _IOW('p', 0x11, int)
#define HANG_SET_REBOOT _IO('p', 0x12)
#define HANG_ADD_WHITE_LIST _IOR('p', 0x13, char [TASK_COMM_LEN])
#define HANG_DEL_WHITE_LIST _IOR('p', 0x14, char [TASK_COMM_LEN])
extern void show_task_mem(void) __attribute__((weak));
extern void mtk_dump_gpu_memory_usage(void) __attribute__((weak));
#ifdef CONFIG_MTK_HANG_DETECT_LOG
#define hang_log pr_info
#else
#define hang_log no_printk
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mrdump.h
+223
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if !defined(__MRDUMP_H__)
#define __MRDUMP_H__
#include <asm/ptrace.h>
#include <linux/elf.h>
#include <linux/elfcore.h>
#include <stdarg.h>
#include <mt-plat/aee.h>
#ifdef __aarch64__
#define reg_pc pc
#define reg_lr regs[30]
#define reg_sp sp
#define reg_fp regs[29]
#else
#define reg_pc ARM_pc
#define reg_lr ARM_lr
#define reg_sp ARM_sp
#define reg_ip ARM_ip
#define reg_fp ARM_fp
#endif
#define MRDUMP_CPU_MAX 12
#define MRDUMP_ENABLE_COOKIE 0x590d2ba3
#define MRDUMP_GO_DUMP "MRDUMP11"
#define KSYM_32 1
#define KSYM_64 2
typedef uint32_t arm32_gregset_t[18];
typedef uint64_t aarch64_gregset_t[34];
struct arm32_ctrl_regs {
uint32_t sctlr;
uint64_t ttbcr;
uint64_t ttbr0;
uint64_t ttbr1;
};
struct aarch64_ctrl_regs {
uint64_t sctlr_el1;
uint64_t sctlr_el2;
uint64_t sctlr_el3;
uint64_t tcr_el1;
uint64_t tcr_el2;
uint64_t tcr_el3;
uint64_t ttbr0_el1;
uint64_t ttbr0_el2;
uint64_t ttbr0_el3;
uint64_t ttbr1_el1;
uint64_t sp_el[4];
};
struct mrdump_arm32_reg {
arm32_gregset_t arm32_regs;
struct arm32_ctrl_regs arm32_creg;
};
struct mrdump_arm64_reg {
aarch64_gregset_t arm64_regs;
struct aarch64_ctrl_regs arm64_creg;
};
struct mrdump_crash_record {
int reboot_mode;
char msg[128];
uint32_t fault_cpu;
union {
struct mrdump_arm32_reg arm32_reg;
struct mrdump_arm64_reg arm64_reg;
} cpu_reg[0];
};
struct mrdump_ksyms_param {
char tag[4];
uint32_t flag;
uint32_t crc;
uint64_t start_addr;
uint32_t size;
uint32_t addresses_off;
uint32_t num_syms_off;
uint32_t names_off;
uint32_t markers_off;
uint32_t token_table_off;
uint32_t token_index_off;
} __packed;
struct mrdump_machdesc {
uint32_t nr_cpus;
uint64_t page_offset;
uint64_t high_memory;
uint64_t kimage_vaddr;
uint64_t dram_start;
uint64_t dram_end;
uint64_t kimage_stext;
uint64_t kimage_etext;
uint64_t kimage_stext_real;
uint64_t kimage_voffset;
uint64_t kimage_sdata;
uint64_t kimage_edata;
uint64_t vmalloc_start;
uint64_t vmalloc_end;
uint64_t modules_start;
uint64_t modules_end;
uint64_t phys_offset;
uint64_t master_page_table;
uint64_t memmap;
uint64_t pageflags;
uint32_t struct_page_size;
uint64_t dfdmem_pa;
struct mrdump_ksyms_param kallsyms;
};
struct mrdump_control_block {
char sig[8];
struct mrdump_machdesc machdesc;
uint32_t machdesc_crc;
uint32_t enabled;
uint32_t output_fs_lbaooo;
struct mrdump_crash_record crash_record;
};
/* NOTE!! any change to this struct should be compatible in aed */
struct mrdump_mini_reg_desc {
unsigned long reg; /* register value */
unsigned long kstart; /* start kernel addr of memory dump */
unsigned long kend; /* end kernel addr of memory dump */
unsigned long pos; /* next pos to dump */
int valid; /* 1: valid regiser, 0: invalid regiser */
int pad; /* reserved */
loff_t offset; /* offset in buffer */
};
/* it should always be smaller than MRDUMP_MINI_HEADER_SIZE */
struct mrdump_mini_header {
struct mrdump_mini_reg_desc reg_desc[ELF_NGREG];
};
#define MRDUMP_MINI_NR_SECTION 60
#define MRDUMP_MINI_SECTION_SIZE (32 * 1024)
#define NT_IPANIC_MISC 4095
#define MRDUMP_MINI_NR_MISC 40
#define MRDUMP_MINI_MISC_LOAD "load"
struct mrdump_mini_elf_misc {
unsigned long vaddr;
unsigned long paddr;
unsigned long start;
unsigned long size;
};
#define NOTE_NAME_SHORT 12
#define NOTE_NAME_LONG 20
struct mrdump_mini_elf_psinfo {
struct elf_note note;
char name[NOTE_NAME_SHORT];
struct elf_prpsinfo data;
};
struct mrdump_mini_elf_prstatus {
struct elf_note note;
char name[NOTE_NAME_SHORT];
struct elf_prstatus data;
};
struct mrdump_mini_elf_note {
struct elf_note note;
char name[NOTE_NAME_LONG];
struct mrdump_mini_elf_misc data;
};
struct mrdump_mini_elf_header {
struct elfhdr ehdr;
struct elf_phdr phdrs[MRDUMP_MINI_NR_SECTION];
struct mrdump_mini_elf_psinfo psinfo;
struct mrdump_mini_elf_prstatus prstatus[AEE_MTK_CPU_NUMS];
struct mrdump_mini_elf_note misc[MRDUMP_MINI_NR_MISC];
};
#define MRDUMP_MINI_HEADER_SIZE \
ALIGN(sizeof(struct mrdump_mini_elf_header), PAGE_SIZE)
#define MRDUMP_MINI_DATA_SIZE \
(MRDUMP_MINI_NR_SECTION * MRDUMP_MINI_SECTION_SIZE)
#define MRDUMP_MINI_BUF_SIZE (MRDUMP_MINI_HEADER_SIZE + MRDUMP_MINI_DATA_SIZE)
int mrdump_init(void);
void __mrdump_create_oops_dump(enum AEE_REBOOT_MODE reboot_mode,
struct pt_regs *regs, const char *msg, ...);
int mrdump_common_die(u8 fiq_step, int reboot_reason, const char *msg,
struct pt_regs *regs);
void mrdump_mini_add_hang_raw(unsigned long vaddr, unsigned long size);
void mrdump_mini_add_extra_misc(void);
extern void mlog_get_buffer(char **ptr, int *size)__attribute__((weak));
extern void get_msdc_aee_buffer(unsigned long *buff,
unsigned long *size)__attribute__((weak));
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/emi_mpu.h
+65
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_EMI_MPU_H
#define __MT_EMI_MPU_H
#define EMI_MPU_START (0x0)
#define EMI_MPU_END (0x91C)
#define NO_PROTECTION 0
#define SEC_RW 1
#define SEC_RW_NSEC_R 2
#define SEC_RW_NSEC_W 3
#define SEC_R_NSEC_R 4
#define FORBIDDEN 5
#define SEC_R_NSEC_RW 6
#define EN_MPU_STR "ON"
#define DIS_MPU_STR "OFF"
#define EN_WP_STR "ON"
#define DIS_WP_STR "OFF"
#define MAX_CHANNELS (1)
#define MAX_RANKS (2)
/* Basic DRAM setting */
struct basic_dram_setting {
/* Number of channels */
unsigned channel_nr;
/* Per-channel information */
struct {
/* Per-rank information */
struct {
/* Does this rank exist */
bool valid_rank;
/* Rank size - (in Gb)*/
unsigned rank_size;
/* Number of segments */
unsigned segment_nr;
} rank[MAX_RANKS];
} channel[MAX_CHANNELS];
};
#define LOCK 1
#define UNLOCK 0
#define SET_ACCESS_PERMISSON(lock, d7, d6, d5, d4, d3, d2, d1, d0) \
((((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | (((unsigned int) d5) << 15) | \
(((unsigned int) d4) << 12) | (((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
(((unsigned int) d1) << 3) | ((unsigned int) d0) | ((unsigned long long) lock << 26))
extern int emi_mpu_set_region_protection(unsigned long long start_addr,
unsigned long long end_addr, int region, unsigned int access_permission);
#if defined(CONFIG_MTKPASR)
extern void acquire_dram_setting(struct basic_dram_setting *pasrdpd);
#endif
extern void *mt_emi_reg_base_get(void);
extern int emi_mpu_get_violation_port(void);
extern unsigned int mt_emi_reg_read(unsigned int offset);
extern void mt_emi_reg_write(unsigned int data, unsigned int offset);
extern void dump_emi_latency(void);
#endif /* !__MT_EMI_MPU_H */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/memory_layout.h
+11
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _H_MEMORY_LAYOUT_H_
#define _H_MEMORY_LAYOUT_H_
/* dummy header */
#define DUMMY_MEMORY_LAYOUT
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_battery_property.h
+277
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_BATTERY_PROPERTY_H
#define _MTK_BATTERY_PROPERTY_H
/* customize */
#define DIFFERENCE_FULLOCV_ITH 200 /* mA */
#define MTK_CHR_EXIST 1
#define KEEP_100_PERCENT 1
#define R_FG_VALUE 10 /* mOhm */
#define EMBEDDED_SEL 0
#define PMIC_SHUTDOWN_CURRENT 20 /* 0.01 mA */
#define FG_METER_RESISTANCE 100
#define CAR_TUNE_VALUE 100 /*1.00 */
#define NO_BAT_TEMP_COMPENSATE 0
/* NO_BAT_TEMP_COMPENSATE 1 = don't need bat_temper compensate, */
/* but fg_meter_resistance still use for SWOCV */
/* enable that soc = 0 , shutdown */
#define SHUTDOWN_GAUGE0 1
/* enable that uisoc = 1 and wait xmins then shutdown */
#define SHUTDOWN_GAUGE1_XMINS 1
/* define Xmins to shutdown*/
#define SHUTDOWN_1_TIME 5
#define SHUTDOWN_GAUGE1_VBAT_EN 0
#define SHUTDOWN_GAUGE1_VBAT 34000
#define SHUTDOWN_GAUGE0_VOLTAGE 34000
#define POWERON_SYSTEM_IBOOT 500 /* mA */
/*
* LOW_TEMP_MODE = 0
* disable LOW_TEMP_MODE
* LOW_TEMP_MODE = 1
* if battery temperautre < LOW_TEMP_MODE_TEMP
* when bootup , force C mode
* LOW_TEMP_MODE = 2
* if battery temperautre < LOW_TEMP_MODE_TEMP
* force C mode
*/
#define LOW_TEMP_MODE 0
#define LOW_TEMP_MODE_TEMP 0
#define D0_SEL 0 /* not implement */
#define AGING_SEL 0 /* not implement */
#define DLPT_UI_REMAP_EN 0
/* ADC resistor */
#define R_BAT_SENSE 4
#define R_I_SENSE 4
#define R_CHARGER_1 330
#define R_CHARGER_2 39
#define QMAX_SEL 1
#define IBOOT_SEL 0
#define SHUTDOWN_SYSTEM_IBOOT 15000 /* 0.1mA */
#define PMIC_MIN_VOL 33500
/*ui_soc related */
#define DIFFERENCE_FULL_CV 1000 /*0.01%*/
#define PSEUDO1_EN 1
#define PSEUDO100_EN 1
#define PSEUDO100_EN_DIS 1
#define DIFF_SOC_SETTING 50 /* 0.01% */
#define DIFF_BAT_TEMP_SETTING 1
#define DIFF_BAT_TEMP_SETTING_C 10
#define DISCHARGE_TRACKING_TIME 10
#define CHARGE_TRACKING_TIME 60
#define DIFFERENCE_FULLOCV_VTH 1000 /* 0.1mV */
#define CHARGE_PSEUDO_FULL_LEVEL 8000
#define FULL_TRACKING_BAT_INT2_MULTIPLY 6
/* pre tracking */
#define FG_PRE_TRACKING_EN 1
#define VBAT2_DET_TIME 5
#define VBAT2_DET_COUNTER 6
#define VBAT2_DET_VOLTAGE1 34500
#define VBAT2_DET_VOLTAGE2 32000
#define VBAT2_DET_VOLTAGE3 35000
/* PCB setting */
#define CALIBRATE_CAR_TUNE_VALUE_BY_META_TOOL
#define CALI_CAR_TUNE_AVG_NUM 60
/* Aging Compensation 1*/
#define AGING_FACTOR_MIN 75
#define AGING_FACTOR_DIFF 10
#define DIFFERENCE_VOLTAGE_UPDATE 50
#define AGING_ONE_EN 1
#define AGING1_UPDATE_SOC 30
#define AGING1_LOAD_SOC 70
#define AGING_TEMP_DIFF 10
#define AGING_TEMP_LOW_LIMIT 15
#define AGING_TEMP_HIGH_LIMIT 50
#define AGING_100_EN 1
/* Aging Compensation 2*/
#define AGING_TWO_EN 1
/* Aging Compensation 3*/
#define AGING_THIRD_EN 1
#define AGING_4_EN 1
#define AGING_5_EN 1
#define AGING_6_EN 1
#define AGING4_UPDATE_SOC 40
#define AGING4_LOAD_SOC 70
#define AGING5_UPDATE_SOC 30
#define AGING5_LOAD_SOC 70
#define AGING6_UPDATE_SOC 30
#define AGING6_LOAD_SOC 70
/* threshold */
#define HWOCV_SWOCV_DIFF 300
#define HWOCV_SWOCV_DIFF_LT 1500
#define HWOCV_SWOCV_DIFF_LT_TEMP 5
#define HWOCV_OLDOCV_DIFF 300
#define HWOCV_OLDOCV_DIFF_CHR 800
#define SWOCV_OLDOCV_DIFF 300
#define SWOCV_OLDOCV_DIFF_CHR 800
#define VBAT_OLDOCV_DIFF 1000
#define SWOCV_OLDOCV_DIFF_EMB 1000 /* 100mV */
#define VIR_OLDOCV_DIFF_EMB 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_LT 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_TMP 5
#define TNEW_TOLD_PON_DIFF 5
#define TNEW_TOLD_PON_DIFF2 15
#define PMIC_SHUTDOWN_TIME 30
#define BAT_PLUG_OUT_TIME 32
#define EXT_HWOCV_SWOCV 300
#define EXT_HWOCV_SWOCV_LT 1500
#define EXT_HWOCV_SWOCV_LT_TEMP 5
/* fgc & fgv threshold */
#define DIFFERENCE_FGC_FGV_TH1 300
#define DIFFERENCE_FGC_FGV_TH2 500
#define DIFFERENCE_FGC_FGV_TH3 300
#define DIFFERENCE_FGC_FGV_TH_SOC1 7000
#define DIFFERENCE_FGC_FGV_TH_SOC2 3000
#define NAFG_TIME_SETTING 10
#define NAFG_RATIO 100
#define NAFG_RATIO_EN 0
#define NAFG_RATIO_TMP_THR 1
#define NAFG_RESISTANCE 1500
#define PMIC_SHUTDOWN_SW_EN 1
#define FORCE_VC_MODE 0 /* 0: mix, 1:Coulomb, 2:voltage */
#define LOADING_1_EN 0
#define LOADING_2_EN 2
#define DIFF_IAVG_TH 3000
/* ZCV INTR */
#define ZCV_SUSPEND_TIME 29
#define SLEEP_CURRENT_AVG 200 /*0.1mA*/
#define ZCV_COM_VOL_LIMIT 50 /* 50mv */
#define ZCV_CAR_GAP_PERCENTAGE 5
/* Additional battery table */
#define ADDITIONAL_BATTERY_TABLE_EN 1
#define DC_RATIO_SEL 5
#define DC_R_CNT 1000 /* if set 0, dcr_start will not be 1*/
#define BAT_PAR_I 4000 /* not implement */
#define PSEUDO1_SEL 2
#define FG_TRACKING_CURRENT 30000 /* not implement */
#define FG_TRACKING_CURRENT_IBOOT_EN 0 /* not implement */
#define UI_FAST_TRACKING_EN 0
#define UI_FAST_TRACKING_GAP 300
#define KEEP_100_PERCENT_MINSOC 9000
#define SHUTDOWN_CONDITION_LOW_BAT_VOLT
#define LOW_TEMP_DISABLE_LOW_BAT_SHUTDOWN 1
#define LOW_TEMP_THRESHOLD 5
#define BATTERY_TMP_TO_DISABLE_GM30 -50
#define BATTERY_TMP_TO_DISABLE_NAFG -35
#define DEFAULT_BATTERY_TMP_WHEN_DISABLE_NAFG 25
#define BATTERY_TMP_TO_ENABLE_NAFG -20
/* #define GM30_DISABLE_NAFG */
#define POWER_ON_CAR_CHR 5
#define POWER_ON_CAR_NOCHR -35
#define SHUTDOWN_CAR_RATIO 1
#define MULTI_TEMP_GAUGE0 1 /* different temp using different gauge 0% */
#define OVER_DISCHARGE_LEVEL -1500
#define UISOC_UPDATE_TYPE 0
/*
* uisoc_update_type:
* 0: only ui_soc interrupt update ui_soc
* 1: coulomb/nafg will update ui_soc if delta car > ht/lt_gap /2
* 2: coulomb/nafg will update ui_soc
*/
/* using current to limit uisoc in 100% case*/
/* UI_FULL_LIMIT_ITH0 3000 means 300ma */
#define UI_FULL_LIMIT_EN 0
#define UI_FULL_LIMIT_SOC0 9900
#define UI_FULL_LIMIT_ITH0 2200
#define UI_FULL_LIMIT_SOC1 9900
#define UI_FULL_LIMIT_ITH1 2200
#define UI_FULL_LIMIT_SOC2 9900
#define UI_FULL_LIMIT_ITH2 2200
#define UI_FULL_LIMIT_SOC3 9900
#define UI_FULL_LIMIT_ITH3 2200
#define UI_FULL_LIMIT_SOC4 9900
#define UI_FULL_LIMIT_ITH4 2200
#define UI_FULL_LIMIT_TIME 99999
#define UI_FULL_LIMIT_FC_SOC0 9900
#define UI_FULL_LIMIT_FC_ITH0 3000
#define UI_FULL_LIMIT_FC_SOC1 9900
#define UI_FULL_LIMIT_FC_ITH1 3100
#define UI_FULL_LIMIT_FC_SOC2 9900
#define UI_FULL_LIMIT_FC_ITH2 3200
#define UI_FULL_LIMIT_FC_SOC3 9900
#define UI_FULL_LIMIT_FC_ITH3 3300
#define UI_FULL_LIMIT_FC_SOC4 9900
#define UI_FULL_LIMIT_FC_ITH4 3400
/* using voltage to limit uisoc in 1% case */
/* UI_LOW_LIMIT_VTH0=36000 means 3.6v */
#define UI_LOW_LIMIT_EN 0
#define UI_LOW_LIMIT_SOC0 200
#define UI_LOW_LIMIT_VTH0 34500
#define UI_LOW_LIMIT_SOC1 200
#define UI_LOW_LIMIT_VTH1 34500
#define UI_LOW_LIMIT_SOC2 200
#define UI_LOW_LIMIT_VTH2 34500
#define UI_LOW_LIMIT_SOC3 200
#define UI_LOW_LIMIT_VTH3 34500
#define UI_LOW_LIMIT_SOC4 200
#define UI_LOW_LIMIT_VTH4 34500
#define UI_LOW_LIMIT_TIME 99999
#define MOVING_BATTEMP_EN 1
#define MOVING_BATTEMP_THR 20
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_battery_table.h
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drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_charger_init.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MTK_CHARGER_INIT_H__
#define __MTK_CHARGER_INIT_H__
#define BATTERY_CV 4350000
#define V_CHARGER_MAX 6500000 /* 6.5 V */
#define V_CHARGER_MIN 4600000 /* 4.6 V */
#define USB_CHARGER_CURRENT_SUSPEND 0 /* def CONFIG_USB_IF */
#define USB_CHARGER_CURRENT_UNCONFIGURED 70000 /* 70mA */
#define USB_CHARGER_CURRENT_CONFIGURED 500000 /* 500mA */
#define USB_CHARGER_CURRENT 500000 /* 500mA */
#define AC_CHARGER_CURRENT 2050000
#define AC_CHARGER_INPUT_CURRENT 3200000
#define NON_STD_AC_CHARGER_CURRENT 500000
#define CHARGING_HOST_CHARGER_CURRENT 650000
#define APPLE_1_0A_CHARGER_CURRENT 650000
#define APPLE_2_1A_CHARGER_CURRENT 800000
#define TA_AC_CHARGING_CURRENT 3000000
/* sw jeita */
#define JEITA_TEMP_ABOVE_T4_CV_VOLTAGE 4240000
#define JEITA_TEMP_T3_TO_T4_CV_VOLTAGE 4240000
#define JEITA_TEMP_T2_TO_T3_CV_VOLTAGE 4340000
#define JEITA_TEMP_T1_TO_T2_CV_VOLTAGE 4240000
#define JEITA_TEMP_T0_TO_T1_CV_VOLTAGE 4040000
#define JEITA_TEMP_BELOW_T0_CV_VOLTAGE 4040000
#define TEMP_T4_THRESHOLD 50
#define TEMP_T4_THRES_MINUS_X_DEGREE 47
#define TEMP_T3_THRESHOLD 45
#define TEMP_T3_THRES_MINUS_X_DEGREE 39
#define TEMP_T2_THRESHOLD 10
#define TEMP_T2_THRES_PLUS_X_DEGREE 16
#define TEMP_T1_THRESHOLD 0
#define TEMP_T1_THRES_PLUS_X_DEGREE 6
#define TEMP_T0_THRESHOLD 0
#define TEMP_T0_THRES_PLUS_X_DEGREE 0
#define TEMP_NEG_10_THRESHOLD 0
/* Battery Temperature Protection */
#define MIN_CHARGE_TEMPERATURE 0
#define MIN_CHARGE_TEMPERATURE_PLUS_X_DEGREE 6
#define MAX_CHARGE_TEMPERATURE 50
#define MAX_CHARGE_TEMPERATURE_MINUS_X_DEGREE 47
/* pe */
#define PE_ICHG_LEAVE_THRESHOLD 1000 /* mA */
#define TA_AC_12V_INPUT_CURRENT 3200000
#define TA_AC_9V_INPUT_CURRENT 3200000
#define TA_AC_7V_INPUT_CURRENT 3200000
#define TA_9V_SUPPORT
#define TA_12V_SUPPORT
/* pe2.0 */
#define PE20_ICHG_LEAVE_THRESHOLD 1000 /* mA */
#define TA_START_BATTERY_SOC 0
#define TA_STOP_BATTERY_SOC 85
/* dual charger */
#define TA_AC_MASTER_CHARGING_CURRENT 1500000
#define TA_AC_SLAVE_CHARGING_CURRENT 1500000
/* cable measurement impedance */
#define CABLE_IMP_THRESHOLD 699
#define VBAT_CABLE_IMP_THRESHOLD 3900
/* bif */
#define BIF_THRESHOLD1 4250000 /* UV */
#define BIF_THRESHOLD2 4300000 /* UV */
#define BIF_CV_UNDER_THRESHOLD2 4450000 /* UV */
#define BIF_CV BATTERY_CV /* UV */
#define R_SENSE 56 /* mohm */
#define MAX_CHARGING_TIME (12 * 60 * 60) /* 12 hours */
/* battery warning */
#define BATTERY_NOTIFY_CASE_0001_VCHARGER
#define BATTERY_NOTIFY_CASE_0002_VBATTEMP
/* TODO :need change to CONFIG_MTK_SWCHR_SUPPORT config */
/* #define SWCHR_POWER_PATH */
#endif /*__MTK_CHARGER_INIT_H__*/
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_charging.h
+167
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _CUST_BAT_H_
#define _CUST_BAT_H_
/* stop charging while in talking mode */
#define STOP_CHARGING_IN_TAKLING
#define TALKING_RECHARGE_VOLTAGE 3800
#define TALKING_SYNC_TIME 60
/* Battery Temperature Protection */
#define MTK_TEMPERATURE_RECHARGE_SUPPORT
#define MAX_CHARGE_TEMPERATURE 50
#define MAX_CHARGE_TEMPERATURE_MINUS_X_DEGREE 47
#define MIN_CHARGE_TEMPERATURE 0
#define MIN_CHARGE_TEMPERATURE_PLUS_X_DEGREE 6
#define ERR_CHARGE_TEMPERATURE 0xFF
/* Linear Charging Threshold */
#define V_PRE2CC_THRES 3400 /* mV */
#define V_CC2TOPOFF_THRES 4352
#define RECHARGING_VOLTAGE 4110
#define CHARGING_FULL_CURRENT 150 /* mA */
/* Charging Current Setting */
/* #define CONFIG_USB_IF */
#define USB_CHARGER_CURRENT_SUSPEND 0 /* def CONFIG_USB_IF */
#define USB_CHARGER_CURRENT_UNCONFIGURED CHARGE_CURRENT_70_00_MA /* 70mA */
#define USB_CHARGER_CURRENT_CONFIGURED CHARGE_CURRENT_500_00_MA /* 500mA */
#define USB_CHARGER_CURRENT CHARGE_CURRENT_500_00_MA /* 500mA */
/* #define AC_CHARGER_CURRENT CHARGE_CURRENT_650_00_MA */
#define AC_CHARGER_CURRENT CHARGE_CURRENT_2050_00_MA
#define AC_CHARGER_INPUT_CURRENT CHARGE_CURRENT_3200_00_MA
#define NON_STD_AC_CHARGER_CURRENT CHARGE_CURRENT_500_00_MA
#define CHARGING_HOST_CHARGER_CURRENT CHARGE_CURRENT_650_00_MA
#define APPLE_0_5A_CHARGER_CURRENT CHARGE_CURRENT_500_00_MA
#define APPLE_1_0A_CHARGER_CURRENT CHARGE_CURRENT_650_00_MA
#define APPLE_2_1A_CHARGER_CURRENT CHARGE_CURRENT_800_00_MA
/* Precise Tunning */
#define BATTERY_AVERAGE_DATA_NUMBER 3
#define BATTERY_AVERAGE_SIZE 30
/* charger error check */
/* #define BAT_LOW_TEMP_PROTECT_ENABLE // stop charging if temp < MIN_CHARGE_TEMPERATURE */
#define V_CHARGER_ENABLE 0 /* 1:ON , 0:OFF */
#define V_CHARGER_MAX 6500 /* 6.5 V */
#define V_CHARGER_MIN 4400 /* 4.4 V */
/* Tracking TIME */
#define ONEHUNDRED_PERCENT_TRACKING_TIME 10 /* 10 second */
#define NPERCENT_TRACKING_TIME 20 /* 20 second */
#define SYNC_TO_REAL_TRACKING_TIME 60 /* 60 second */
#define V_0PERCENT_TRACKING 3450 /* 3450mV */
/* Battery Notify */
#define BATTERY_NOTIFY_CASE_0001_VCHARGER
#define BATTERY_NOTIFY_CASE_0002_VBATTEMP
/* #define BATTERY_NOTIFY_CASE_0003_ICHARGING */
/* #define BATTERY_NOTIFY_CASE_0004_VBAT */
/* #define BATTERY_NOTIFY_CASE_0005_TOTAL_CHARGINGTIME */
/* High battery support */
#define HIGH_BATTERY_VOLTAGE_SUPPORT
/* JEITA parameter */
/* #define MTK_JEITA_STANDARD_SUPPORT */
#define CUST_SOC_JEITA_SYNC_TIME 30
#define JEITA_RECHARGE_VOLTAGE 4110 /* for linear charging */
#ifdef HIGH_BATTERY_VOLTAGE_SUPPORT
#define JEITA_TEMP_ABOVE_POS_60_CV_VOLTAGE BATTERY_VOLT_04_240000_V
#define JEITA_TEMP_POS_45_TO_POS_60_CV_VOLTAGE BATTERY_VOLT_04_240000_V
#define JEITA_TEMP_POS_10_TO_POS_45_CV_VOLTAGE BATTERY_VOLT_04_340000_V
#define JEITA_TEMP_POS_0_TO_POS_10_CV_VOLTAGE BATTERY_VOLT_04_240000_V
#define JEITA_TEMP_NEG_10_TO_POS_0_CV_VOLTAGE BATTERY_VOLT_04_040000_V
#define JEITA_TEMP_BELOW_NEG_10_CV_VOLTAGE BATTERY_VOLT_04_040000_V
#else
#define JEITA_TEMP_ABOVE_POS_60_CV_VOLTAGE BATTERY_VOLT_04_100000_V
#define JEITA_TEMP_POS_45_TO_POS_60_CV_VOLTAGE BATTERY_VOLT_04_100000_V
#define JEITA_TEMP_POS_10_TO_POS_45_CV_VOLTAGE BATTERY_VOLT_04_200000_V
#define JEITA_TEMP_POS_0_TO_POS_10_CV_VOLTAGE BATTERY_VOLT_04_100000_V
#define JEITA_TEMP_NEG_10_TO_POS_0_CV_VOLTAGE BATTERY_VOLT_03_900000_V
#define JEITA_TEMP_BELOW_NEG_10_CV_VOLTAGE BATTERY_VOLT_03_900000_V
#endif
/* For JEITA Linear Charging only */
#define JEITA_NEG_10_TO_POS_0_FULL_CURRENT 120 /* mA */
#define JEITA_TEMP_POS_45_TO_POS_60_RECHARGE_VOLTAGE 4000
#define JEITA_TEMP_POS_10_TO_POS_45_RECHARGE_VOLTAGE 4100
#define JEITA_TEMP_POS_0_TO_POS_10_RECHARGE_VOLTAGE 4000
#define JEITA_TEMP_NEG_10_TO_POS_0_RECHARGE_VOLTAGE 3800
#define JEITA_TEMP_POS_45_TO_POS_60_CC2TOPOFF_THRESHOLD 4050
#define JEITA_TEMP_POS_10_TO_POS_45_CC2TOPOFF_THRESHOLD 4050
#define JEITA_TEMP_POS_0_TO_POS_10_CC2TOPOFF_THRESHOLD 4050
#define JEITA_TEMP_NEG_10_TO_POS_0_CC2TOPOFF_THRESHOLD 3850
/* For CV_E1_INTERNAL */
#define CV_E1_INTERNAL
/* Disable Battery check for HQA */
#ifdef CONFIG_MTK_DISABLE_POWER_ON_OFF_VOLTAGE_LIMITATION
#define CONFIG_DIS_CHECK_BATTERY
#endif
#ifdef CONFIG_MTK_FAN5405_SUPPORT
#define FAN5405_BUSNUM 1
#endif
/*VINDPM moved from cust_pe.h to de-relating from PE+*/
#define SWITCH_CHR_VINDPM_5V 0x13 /* 4.5V */
#define SWITCH_CHR_VINDPM_7V 0x25 /* 6.3V */
#define SWITCH_CHR_VINDPM_9V 0x37 /* 8.1V */
#define SWITCH_CHR_VINDPM_12V 0x54 /* 11.0 set this tp prevent adapters from failure and reset*/
/*Added switch chr OPTIONS for BQ25896*/
/*switch charger input/output current separation; moved to Kconfig.driver*/
/*#define CONFIG_MTK_SWITCH_INPUT_OUTPUT_CURRENT_SUPPORT*/
/*Dynamic CV using BIF
* Note: CONFIG_MTK_BAT_BIF_SUPPORT=yes, otherwise default constant CV
*/
/*Define this macro for thermal team experiment:no current limitation*/
#define CONFIG_MTK_THERMAL_TEST_SUPPORT
/*enable to save charger in detection power by turning off Chr clock*/
#define CONFIG_MTK_CHRIND_CLK_PDN_SUPPORT
/*Added battery_common options*/
/*enable this to change thread wakeup period to 10 secs to avoid suspend failure*/
#define CONFIG_MTK_I2C_CHR_SUPPORT
#define BATTERY_MODULE_INIT
#if defined(CONFIG_MTK_BQ24196_SUPPORT)\
|| defined(CONFIG_MTK_BQ24296_SUPPORT)\
|| defined(CONFIG_MTK_BQ24160_SUPPORT)\
|| defined(CONFIG_MTK_BQ25896_SUPPORT)\
|| defined(CONFIG_MTK_BQ24261_SUPPORT)\
|| defined(CONFIG_MTK_RT9466_SUPPORT)
#define SWCHR_POWER_PATH
#endif
#if defined(CONFIG_MTK_FAN5402_SUPPORT) \
|| defined(CONFIG_MTK_FAN5405_SUPPORT) \
|| defined(CONFIG_MTK_BQ24158_SUPPORT) \
|| defined(CONFIG_MTK_BQ24196_SUPPORT) \
|| defined(CONFIG_MTK_BQ24296_SUPPORT) \
|| defined(CONFIG_MTK_NCP1851_SUPPORT) \
|| defined(CONFIG_MTK_NCP1854_SUPPORT) \
|| defined(CONFIG_MTK_BQ24160_SUPPORT) \
|| defined(CONFIG_MTK_BQ24157_SUPPORT) \
|| defined(CONFIG_MTK_BQ24250_SUPPORT) \
|| defined(CONFIG_MTK_BQ24261_SUPPORT)
#define EXTERNAL_SWCHR_SUPPORT
#endif
/* Dynamic CV threshold */
#define MTK_DYNAMIC_CV_THRESHOLD 4300 /* mV */
#define MTK_DYNAMIC_CV_VOLTAGE 4550 /* mV */
#define MTK_CV_VOLTAGE 4350000 /* uV */
#define MTK_IRCMP_VOLT_CLAMP 200 /* mV */
#define MTK_IRCMP_RESISTOR 80 /* mohm */
#endif /* _CUST_BAT_H_ */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_cpufreq_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_CPUFREQ_API_H__
#define __MT_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id, unsigned int freq);
#if 0
extern int mt_cpufreq_set_by_schedule_load(unsigned int cpu, enum cpu_dvfs_sched_type state, unsigned int freq);
#else
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id, unsigned int freq);
#endif
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id, unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* ICCS */
extern int mt_cpufreq_set_iccs_frequency_by_cluster(int en, unsigned int cluster_id, unsigned int freq);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id, int idx);
extern unsigned int mt_cpufreq_get_cpu_freq(int cpu, int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id, int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
/* extern void mt_cpufreq_restore_default_volt(unsigned int cluster_id); */
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id, int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id, unsigned int *volt_tbl,
int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void notify_cpu_volt_sampler(unsigned int cluster_id, unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id, unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PBM */
extern unsigned int mt_cpufreq_get_leakage_mw(unsigned int cluster_id);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_pbm.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PBM_
#define _MT_PBM_
/* #include <cust_pmic.h> */
#include <mach/mtk_pmic.h>
#ifdef DISABLE_DLPT_FEATURE
#define DISABLE_PBM_FEATURE
#endif
#define MD1_MAX_PW 4000 /* mW */
#define POWER_FLASH 3500 /* mW */
#define GUARDING_PATTERN 0
#define _BIT_(_bit_) (unsigned)(1 << (_bit_))
#define _BITMASK_(_bits_) (((unsigned) -1 >> (31 - ((1) ? _bits_))) & ~((1U << ((0) ? _bits_)) - 1))
struct pbm {
u8 feature_en;
u8 pbm_drv_done;
u32 hpf_en;
};
struct hpf {
bool switch_md1;
bool switch_gpu;
bool switch_flash;
bool md1_ccci_ready;
int cpu_volt;
int gpu_volt;
int cpu_num;
unsigned long loading_leakage;
unsigned long loading_dlpt;
unsigned long loading_md1;
unsigned long loading_cpu;
unsigned long loading_gpu;
unsigned long loading_flash;
};
struct mrp {
bool switch_md;
bool switch_gpu;
bool switch_flash;
int cpu_volt;
int gpu_volt;
int cpu_num;
unsigned long loading_dlpt;
unsigned long loading_cpu;
unsigned long loading_gpu;
};
enum pbm_kicker {
KR_DLPT, /* 0 */
KR_MD1, /* 1 */
KR_MD3, /* 2 */
KR_CPU, /* 3 */
KR_GPU, /* 4 */
KR_FLASH /* 5 */
};
#define MD_POWER_METER_ENABLE 1
/*#define TEST_MD_POWER*/
#define SECTION_LEN 0xFFFFFFFF /* total 4 byte, 6 section = 11 11111 11111 11111 11111 11111 11111 */
#define SECTION_VALUE 0x1F /* each section is 0x1F = bit(11111) */
enum section_level_tbl {
BIT_SECTION_1 = 0,
BIT_SECTION_2 = 5,
BIT_SECTION_3 = 10,
BIT_SECTION_4 = 15,
BIT_SECTION_5 = 20,
BIT_SECTION_6 = 25,
SECTION_NUM = 6
};
enum md1_scenario {
S_STANDBY = 0,
S_2G_TALKING_OR_DATALINK,
S_3G_TALKING,
S_3G_DATALINK,
S_4G_DL_1CC,
SCENARIO_NUM
};
enum share_mem_mapping { /* each of 4 byte */
DBM_2G_TABLE = 0,
DBM_3G_TABLE,
DBM_4G_TABLE,
DBM_4G_1_TABLE,
DBM_4G_2_TABLE,
DBM_4G_3_TABLE,
DBM_4G_4_TABLE,
DBM_4G_5_TABLE,
DBM_4G_6_TABLE,
DBM_4G_7_TABLE,
DBM_4G_8_TABLE,
DBM_4G_9_TABLE,
DBM_4G_10_TABLE,
DBM_4G_11_TABLE,
DBM_4G_12_TABLE,
DBM_TDD_TABLE,
DBM_C2K_1_TABLE,
DBM_C2K_2_TABLE,
DBM_C2K_3_TABLE,
DBM_C2K_4_TABLE,
SECTION_LEVLE_2G,
SECTION_LEVLE_3G,
SECTION_LEVLE_4G,
SECTION_1_LEVLE_4G,
SECTION_2_LEVLE_4G,
SECTION_3_LEVLE_4G,
SECTION_4_LEVLE_4G,
SECTION_5_LEVLE_4G,
SECTION_6_LEVLE_4G,
SECTION_7_LEVLE_4G,
SECTION_8_LEVLE_4G,
SECTION_9_LEVLE_4G,
SECTION_10_LEVLE_4G,
SECTION_11_LEVLE_4G,
SECTION_12_LEVLE_4G,
SECTION_LEVLE_TDD,
SECTION_1_LEVLE_C2K,
SECTION_2_LEVLE_C2K,
SECTION_3_LEVLE_C2K,
SECTION_4_LEVLE_C2K,
SHARE_MEM_BLOCK_NUM
};
/*
* MD1 Section level (can't more than SECTION_VALUE)
*/
/* Each section has only 5 bits. The range is from 0 to 31 */
enum md1_section_level_tbl_2g {
VAL_MD1_2G_SECTION_1 = 31,
VAL_MD1_2G_SECTION_2 = 29,
VAL_MD1_2G_SECTION_3 = 27,
VAL_MD1_2G_SECTION_4 = 25,
VAL_MD1_2G_SECTION_5 = 21,
VAL_MD1_2G_SECTION_6 = 0
};
enum md1_section_level_tbl_3g {
VAL_MD1_3G_SECTION_1 = 22,
VAL_MD1_3G_SECTION_2 = 20,
VAL_MD1_3G_SECTION_3 = 17,
VAL_MD1_3G_SECTION_4 = 16,
VAL_MD1_3G_SECTION_5 = 12,
VAL_MD1_3G_SECTION_6 = 0
};
enum md1_section_level_tbl_4g_upL1 {
VAL_MD1_4G_upL1_SECTION_1 = 21,
VAL_MD1_4G_upL1_SECTION_2 = 19,
VAL_MD1_4G_upL1_SECTION_3 = 17,
VAL_MD1_4G_upL1_SECTION_4 = 14,
VAL_MD1_4G_upL1_SECTION_5 = 12,
VAL_MD1_4G_upL1_SECTION_6 = 0
};
enum md1_section_level_tbl_tdd {
VAL_MD1_TDD_SECTION_1 = 21,
VAL_MD1_TDD_SECTION_2 = 19,
VAL_MD1_TDD_SECTION_3 = 18,
VAL_MD1_TDD_SECTION_4 = 16,
VAL_MD1_TDD_SECTION_5 = 13,
VAL_MD1_TDD_SECTION_6 = 0
};
enum md1_section_level_tbl_c2k {
VAL_MD1_C2K_SECTION_1 = 23,
VAL_MD1_C2K_SECTION_2 = 21,
VAL_MD1_C2K_SECTION_3 = 20,
VAL_MD1_C2K_SECTION_4 = 17,
VAL_MD1_C2K_SECTION_5 = 13,
VAL_MD1_C2K_SECTION_6 = 0
};
/*
* MD1 Scenario power
*/
enum md1_scenario_pwr_tbl {
PW_STANDBY = 2,
PW_2G_TALKING_OR_DATALINK = 76,
PW_3G_TALKING = 182,
PW_3G_DATALINK = 398,
PW_4G_DL_1CC = 499
};
/*
* MD1 PA power
*/
enum md1_pa_pwr_tbl_2g {
PW_MD1_PA_2G_SECTION_1 = 660,
PW_MD1_PA_2G_SECTION_2 = 430,
PW_MD1_PA_2G_SECTION_3 = 357,
PW_MD1_PA_2G_SECTION_4 = 335,
PW_MD1_PA_2G_SECTION_5 = 197,
PW_MD1_PA_2G_SECTION_6 = 130
};
enum md1_pa_pwr_tbl_3g {
PW_MD1_PA_3G_SECTION_1 = 1745,
PW_MD1_PA_3G_SECTION_2 = 1403,
PW_MD1_PA_3G_SECTION_3 = 834,
PW_MD1_PA_3G_SECTION_4 = 627,
PW_MD1_PA_3G_SECTION_5 = 439,
PW_MD1_PA_3G_SECTION_6 = 318
};
enum md1_pa_pwr_tbl_4g_upL1 {
PW_MD1_PA_4G_upL1_SECTION_1 = 1252,
PW_MD1_PA_4G_upL1_SECTION_2 = 865,
PW_MD1_PA_4G_upL1_SECTION_3 = 690,
PW_MD1_PA_4G_upL1_SECTION_4 = 432,
PW_MD1_PA_4G_upL1_SECTION_5 = 323,
PW_MD1_PA_4G_upL1_SECTION_6 = 190
};
enum md1_pa_pwr_tbl_c2k {
PW_MD1_PA_C2K_SECTION_1 = 1444,
PW_MD1_PA_C2K_SECTION_2 = 1120,
PW_MD1_PA_C2K_SECTION_3 = 792,
PW_MD1_PA_C2K_SECTION_4 = 697,
PW_MD1_PA_C2K_SECTION_5 = 478,
PW_MD1_PA_C2K_SECTION_6 = 230
};
/*
* MD1 RF power
*/
enum md1_rf_pwr_tbl_2g {
PW_MD1_RF_2G_SECTION_1 = 44,
PW_MD1_RF_2G_SECTION_2 = 42,
PW_MD1_RF_2G_SECTION_3 = 42,
PW_MD1_RF_2G_SECTION_4 = 42,
PW_MD1_RF_2G_SECTION_5 = 42,
PW_MD1_RF_2G_SECTION_6 = 42
};
enum md1_rf_pwr_tbl_3g {
PW_MD1_RF_3G_SECTION_1 = 158,
PW_MD1_RF_3G_SECTION_2 = 154,
PW_MD1_RF_3G_SECTION_3 = 146,
PW_MD1_RF_3G_SECTION_4 = 139,
PW_MD1_RF_3G_SECTION_5 = 135,
PW_MD1_RF_3G_SECTION_6 = 115
};
enum md1_rf_pwr_tbl_4g_upL1 {
PW_MD1_RF_4G_upL1_SECTION_1 = 243,
PW_MD1_RF_4G_upL1_SECTION_2 = 243,
PW_MD1_RF_4G_upL1_SECTION_3 = 234,
PW_MD1_RF_4G_upL1_SECTION_4 = 216,
PW_MD1_RF_4G_upL1_SECTION_5 = 216,
PW_MD1_RF_4G_upL1_SECTION_6 = 159
};
enum md1_rf_pwr_tbl_c2k {
PW_MD1_RF_C2K_SECTION_1 = 284,
PW_MD1_RF_C2K_SECTION_2 = 262,
PW_MD1_RF_C2K_SECTION_3 = 226,
PW_MD1_RF_C2K_SECTION_4 = 202,
PW_MD1_RF_C2K_SECTION_5 = 173,
PW_MD1_RF_C2K_SECTION_6 = 163
};
extern void kicker_pbm_by_dlpt(unsigned int i_max);
extern void kicker_pbm_by_md(enum pbm_kicker kicker, bool status);
extern void kicker_pbm_by_cpu(unsigned int loading, int core, int voltage);
extern void kicker_pbm_by_gpu(bool status, unsigned int loading, int voltage);
extern void kicker_pbm_by_flash(bool status);
extern void init_md_section_level(enum pbm_kicker);
#ifndef DISABLE_PBM_FEATURE
extern int g_dlpt_stop;
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_pmic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _CUST_PMIC_H_
#define _CUST_PMIC_H_
/*#define PMIC_VDVFS_CUST_ENABLE*/
#define LOW_POWER_LIMIT_LEVEL_1 15
#define PT_DLPT_BRINGUP 0
#if defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP
/* Define for disable low battery protect feature,
* default no define for enable low battery protect.
*/
#define DISABLE_LOW_BATTERY_PROTECT
/*Define for disable battery OC protect*/
#define DISABLE_BATTERY_OC_PROTECT
/*Define for disable battery 15% protect*/
#define DISABLE_BATTERY_PERCENT_PROTECT
/*Define for DLPT*/
#define DISABLE_DLPT_FEATURE
#endif /* defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP */
#define POWER_UVLO_VOLT_LEVEL 2600
#define IMAX_MAX_VALUE 5500
#define POWER_INT0_VOLT 3400
#define POWER_INT1_VOLT 3250
#define POWER_INT2_VOLT 3100
#define POWER_BAT_OC_CURRENT_H 4670
#define POWER_BAT_OC_CURRENT_L 5500
#define POWER_BAT_OC_CURRENT_H_RE 4670
#define POWER_BAT_OC_CURRENT_L_RE 5500
#define DLPT_POWER_OFF_EN
#define POWEROFF_BAT_CURRENT 3000
#define DLPT_POWER_OFF_THD 100
#define DLPT_VOLT_MIN 3100
#define BATTERY_MODULE_INIT
/* ADC Channel Number, not uesed and removed */
extern const char *pmic_auxadc_channel_name[];
/* Legacy pmic auxadc interface */
enum {
/* mt6357 */
AUXADC_LIST_BATADC,
AUXADC_LIST_START = AUXADC_LIST_BATADC,
AUXADC_LIST_VCDT,
AUXADC_LIST_BATTEMP,
AUXADC_LIST_VBIF,
AUXADC_LIST_MT6357_CHIP_TEMP,
AUXADC_LIST_DCXO,
AUXADC_LIST_ACCDET,
AUXADC_LIST_TSX,
AUXADC_LIST_HPOFS_CAL,
AUXADC_LIST_ISENSE,
AUXADC_LIST_MT6357_BUCK1_TEMP,
AUXADC_LIST_MT6357_BUCK2_TEMP,
AUXADC_LIST_END = AUXADC_LIST_MT6357_BUCK2_TEMP,
AUXADC_LIST_MAX,
};
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_dump_regs(char *buf);
extern int pmic_get_auxadc_channel_max(void);
extern int mt_get_auxadc_value(u8 channel);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
#endif /* _CUST_PMIC_H_ */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_pmic_ipi.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PMIC_IPI_H_
#define _MT_PMIC_IPI_H_
void pmic_ipi_write_test(void);
#ifdef CONFIG_MTK_EXTBUCK
enum { /* must compatible with sspm EXTBUCK ID */
EXTBUCK_ID_GPU,
EXTBUCK_ID_PROC2,
EXTBUCK_ID_PROC1,
};
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en);
#else
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en)
{
return -1;
}
#endif /* CONFIG_MTK_EXTBUCK */
unsigned int pmic_ipi_read_interface(unsigned int RegNum,
unsigned int *val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_ipi_config_interface(unsigned int RegNum,
unsigned int val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_regulator_profiling(unsigned char type);
unsigned int sub_pmic_ipi_interface(unsigned int type, unsigned int ctrl);
unsigned int mt6311_ipi_set_mode(unsigned char mode);
#endif /* _MT_PMIC_IPI_H_*/
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_pmic_wrap.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PMIC_WRAP_H__
#define __MT_PMIC_WRAP_H__
/* #include <mach/typedefs.h> */
/* #include <linux/smp.h> */
#include <linux/types.h>
#include <linux/device.h>
#include <mach/upmu_hw.h>
struct mt_pmic_wrap_driver {
struct device_driver driver;
s32 (*wacs2_hal)(u32 write, u32 adr, u32 wdata, u32 *rdata);
s32 (*show_hal)(char *buf);
s32 (*store_hal)(const char *buf, size_t count);
s32 (*suspend)(void);
void (*resume)(void);
};
#define PWRAP_READ 0
#define PWRAP_WRITE 1
/* ------external API for pmic_wrap user------------------------------------- */
s32 pwrap_read(u32 adr, u32 *rdata);
s32 pwrap_write(u32 adr, u32 wdata);
s32 pwrap_wacs2(u32 write, u32 adr, u32 wdata, u32 *rdata);
/*_____________ROME only_____________________________________________*/
/********************************************************************/
#define PWRAP_TRACE
#ifdef CONFIG_FPGA_EARLY_PORTING
#define tracepwrap(addr, wdata)
#else /*--!CONFIG_FPGA_EARLY_PORTING --*/
extern unsigned int gPWRAPHCK;
extern unsigned int gPWRAPDBGADDR;
#define PWRAP_HCK_LEVEL 4
#define tracepwrap(addr, wdata) do { \
if (gPWRAPHCK >= PWRAP_HCK_LEVEL) \
if (addr == gPWRAPDBGADDR) { \
unsigned int rdata; \
pwrap_read(addr, &rdata); \
pr_notice("pwrap addr = 0x%x\n", addr); \
pr_notice("pwrap wdata = 0x%x\n", wdata); \
pr_notice("pwrap rdata = 0x%x\n", rdata); \
WARN_ON(1); \
} \
} while (0)
#endif /*--End of CONFIG_FPGA_EARLY_PORTING --*/
/********************************************************************/
/********************************************************************/
/* return value : EINT_STA: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/********************************************************************/
u32 pmic_wrap_eint_status(void);
/********************************************************************/
/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/* para: offset is shift of clear bit which needs to clear */
/********************************************************************/
void pmic_wrap_eint_clr(int offset);
/*--------------------------------------------------------------------*/
u32 mt_pmic_wrap_eint_status(void);
void mt_pmic_wrap_eint_clr(int offset);
s32 pwrap_init(void);
struct mt_pmic_wrap_driver *get_mt_pmic_wrap_drv(void);
/* MTS debug only */
void pwrap_dump_all_register(void);
/* dump ap/pmic register and recovery WACS2 */
void pwrap_dump_and_recovery(void);
#endif /* __MT_PMIC_WRAP_H__ */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_ppm_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PPM_API_H__
#define __MT_PPM_API_H__
#ifdef __cplusplus
extern "C" {
#endif
#include <linux/cpufreq.h>
#include <linux/cpumask.h>
/*==============================================================*/
/* Enum */
/*==============================================================*/
enum ppm_client {
PPM_CLIENT_DVFS = 0,
PPM_CLIENT_HOTPLUG,
NR_PPM_CLIENTS,
};
enum dvfs_table_type {
DVFS_TABLE_TYPE_FY = 0,
DVFS_TABLE_TYPE_SB,
NR_DVFS_TABLE_TYPE,
};
enum ppm_sysboost_user {
BOOST_BY_UT = 0,
BOOST_BY_WIFI,
BOOST_BY_PERFSERV,
BOOST_BY_USB,
BOOST_BY_USB_PD,
/* dedicate ID for debugd to avoid over-writing other kernel users */
BOOST_BY_DEBUGD = 5,
BOOST_BY_DEBUGD_64,
BOOST_BY_BOOT_TIME_OPT,
NR_PPM_SYSBOOST_USER,
};
enum ppm_cluster_lkg {
CLUSTER_LL_LKG = 0,
TOTAL_CLUSTER_LKG,
};
/*==============================================================*/
/* Definition */
/*==============================================================*/
typedef void (*met_set_ppm_state_funcMET)(unsigned int state);
/*==============================================================*/
/* Data Structures */
/*==============================================================*/
struct ppm_client_req {
unsigned int cluster_num;
unsigned int root_cluster;
bool is_ptp_policy_activate;
unsigned int smart_detect;
cpumask_var_t online_core;
struct ppm_client_limit {
unsigned int cluster_id;
unsigned int cpu_id;
int min_cpufreq_idx;
int max_cpufreq_idx;
unsigned int min_cpu_core;
unsigned int max_cpu_core;
bool has_advise_freq;
bool has_advise_core;
int advise_cpufreq_idx;
int advise_cpu_core;
} *cpu_limit;
};
struct ppm_client_data {
const char *name;
enum ppm_client client;
/* callback */
void (*limit_cb)(struct ppm_client_req req);
};
struct ppm_cluster_status {
int core_num;
int freq_idx; /* -1 if core_num = 0 */
int volt;
};
struct ppm_limit_data {
int min;
int max;
};
/*==============================================================*/
/* APIs */
/*==============================================================*/
extern void mt_ppm_set_dvfs_table(unsigned int cpu, struct cpufreq_frequency_table *tbl,
unsigned int num, enum dvfs_table_type type);
extern void mt_ppm_register_client(enum ppm_client client, void (*limit)(struct ppm_client_req req));
extern void mt_ppm_set_5A_limit_throttle(bool enable);
extern void mt_ppm_limit_freq_when_ke(void);
/* SYS boost policy */
extern void mt_ppm_sysboost_core(enum ppm_sysboost_user user, unsigned int core_num);
extern void mt_ppm_sysboost_freq(enum ppm_sysboost_user user, unsigned int freq);
extern void mt_ppm_sysboost_set_core_limit(enum ppm_sysboost_user user, unsigned int cluster,
int min_core, int max_core);
extern void mt_ppm_sysboost_set_freq_limit(enum ppm_sysboost_user user, unsigned int cluster,
int min_freq, int max_freq);
/* DLPT policy */
extern void mt_ppm_dlpt_set_limit_by_pbm(unsigned int limited_power);
extern void mt_ppm_dlpt_kick_PBM(struct ppm_cluster_status *cluster_status, unsigned int cluster_num);
/* Thermal policy */
extern void mt_ppm_cpu_thermal_protect(unsigned int limited_power);
extern unsigned int mt_ppm_thermal_get_min_power(void);
extern unsigned int mt_ppm_thermal_get_max_power(void);
extern unsigned int mt_ppm_thermal_get_cur_power(void);
extern int ppm_find_pwr_idx(struct ppm_cluster_status *cluster_status);
/* User limit policy */
extern unsigned int mt_ppm_userlimit_cpu_core(unsigned int cluster_num, struct ppm_limit_data *data);
extern unsigned int mt_ppm_userlimit_cpu_freq(unsigned int cluster_num, struct ppm_limit_data *data);
extern unsigned int mt_ppm_userlimit_freq_limit_by_others(unsigned int cluster);
extern void ppm_game_mode_change_cb(int is_game_mode);
/* Force limit policy */
extern unsigned int mt_ppm_forcelimit_cpu_core(unsigned int cluster_num, struct ppm_limit_data *data);
/* PTPOD policy */
extern void mt_ppm_ptpod_policy_activate(void);
extern void mt_ppm_ptpod_policy_deactivate(void);
/* HICA policy */
extern void mt_ppm_hica_update_algo_data(unsigned int cur_loads,
unsigned int cur_nr_heavy_task, unsigned int cur_tlp);
extern int mt_ppm_main(void);
/* MET */
extern void mt_set_ppm_state_registerCB(met_set_ppm_state_funcMET pCB);
extern unsigned int mt_ppm_get_leakage_mw(enum ppm_cluster_lkg cluster);
/* CPI */
extern unsigned int ppm_get_cluster_cpi(unsigned int cluster);
#ifdef __cplusplus
}
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_pwm_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PWM_HAL_H__
#define __MT_PWM_HAL_H__
#include <linux/types.h>
#include <mt-plat/sync_write.h>
/**********************************
* Global enum data
***********************************/
/******************* Register Manipulations*****************/
#define INREG32(reg) __raw_readl((void *)reg)
#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
enum PWN_NO {
PWM_MIN,
PWM1 = PWM_MIN,
PWM2,
PWM3,
PWM4,
PWM5,
PWM6,
PWM7,
PWM_NUM,
PWM_MAX = PWM_NUM
};
enum TEST_SEL_BIT {
TEST_SEL_FALSE,
TEST_SEL_TRUE
};
enum PWM_CON_MODE_BIT {
PERIOD,
RAND
};
enum PWM_CON_SRCSEL_BIT {
PWM_FIFO,
MEMORY
};
enum PWM_CON_IDLE_BIT {
IDLE_FALSE,
IDLE_TRUE,
IDLE_MAX
};
enum PWM_CON_GUARD_BIT {
GUARD_FALSE,
GUARD_TRUE,
GUARD_MAX
};
enum OLD_MODE_BIT {
OLDMODE_DISABLE,
OLDMODE_ENABLE
};
enum PWM_BUF_VALID_BIT {
BUF0_VALID,
BUF0_EN_VALID,
BUF1_VALID,
BUF1_EN_VALID,
BUF_EN_MAX
};
enum CLOCK_SRC {
CLK_BLOCK,
CLK_BLOCK_BY_1625_OR_32K
};
enum PWM_CLK_DIV {
CLK_DIV_MIN,
CLK_DIV1 = CLK_DIV_MIN,
CLK_DIV2,
CLK_DIV4,
CLK_DIV8,
CLK_DIV16,
CLK_DIV32,
CLK_DIV64,
CLK_DIV128,
CLK_DIV_MAX
};
enum PWM_INT_ENABLE_BITS {
PWM1_INT_FINISH_EN,
PWM1_INT_UNDERFLOW_EN,
PWM2_INT_FINISH_EN,
PWM2_INT_UNDERFLOW_EN,
PWM3_INT_FINISH_EN,
PWM3_INT_UNDERFLOW_EN,
PWM4_INT_FINISH_EN,
PWM4_INT_UNDERFLOW_EN,
PWM5_INT_FINISH_EN,
PWM5_INT_UNDERFLOW_EN,
PWM_INT_ENABLE_BITS_MAX,
};
enum PWM_INT_STATUS_BITS {
PWM1_INT_FINISH_ST,
PWM1_INT_UNDERFLOW_ST,
PWM2_INT_FINISH_ST,
PWM2_INT_UNDERFLOW_ST,
PWM3_INT_FINISH_ST,
PWM3_INT_UNDERFLOW_ST,
PWM4_INT_FINISH_ST,
PWM4_INT_UNDERFLOW_ST,
PWM5_INT_FINISH_ST,
PWM5_INT_UNDERFLOW_ST,
PWM_INT_STATUS_BITS_MAX,
};
enum PWM_INT_ACK_BITS {
PWM1_INT_FINISH_ACK,
PWM1_INT_UNDERFLOW_ACK,
PWM2_INT_FINISH_ACK,
PWM2_INT_UNDERFLOW_ACK,
PWM3_INT_FINISH_ACK,
PWM3_INT_UNDERFLOW_ACK,
PWM4_INT_FINISH_ACK,
PWM4_INT_UNDERFLOW_ACK,
PWM5_INT_FINISH_ACK,
PWM5_INT_UNDERFLOW_ACK,
PWM_INT_ACK_BITS_MAX,
};
enum PWM_CLOCK_SRC_ENUM {
PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_32K,
PWM_CLK_NEW_MODE_BLOCK,
PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
PWM_CLK_SRC_NUM,
PWM_CLK_SRC_INVALID,
};
enum PWM_MODE_ENUM {
PWM_MODE_MIN,
PWM_MODE_OLD = PWM_MODE_MIN,
PWM_MODE_FIFO,
PWM_MODE_MEMORY,
PWM_MODE_RANDOM,
PWM_MODE_DELAY,
PWM_MODE_INVALID,
};
#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
void mt_set_pwm_3dlcm_enable_hal(u8 enable);
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
void mt_pwm_26M_clk_enable_hal(u32 enable);
#endif
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/mtk_thermal.h
+123
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT6739_THERMAL_H__
#define __MT6739_THERMAL_H__
#include <linux/module.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/uaccess.h>
#include "mt-plat/sync_write.h"
#include "mtk_thermal_typedefs.h"
/*
* Bank0: CPU (TS_MCU1)
* Bank1: GPU+SOC+MD (TS_MCU2)
*/
enum thermal_sensor {
TS_MCU1 = 0,
TS_MCU2,
TS_MCU3,
TS_ABB, /* TODO: double check if TS_ABB exists. */
TS_ENUM_MAX,
};
enum thermal_bank_name {
THERMAL_BANK0 = 0,
THERMAL_BANK1 = 1,
THERMAL_BANK_NUM
};
struct TS_PTPOD {
unsigned int ts_MTS;
unsigned int ts_BTS;
};
extern int mtktscpu_limited_dmips;
extern int tscpu_get_temperature_range(void);
/* Valid if it returns 1, invalid if it returns 0. */
extern int tscpu_is_temp_valid(void);
extern void get_thermal_slope_intercept(struct TS_PTPOD *ts_info, enum thermal_bank_name ts_bank);
extern void set_taklking_flag(bool flag);
extern int tscpu_get_cpu_temp(void);
extern int tscpu_get_temp_by_bank(enum thermal_bank_name ts_bank);
#define THERMAL_WRAP_WR32(val, addr) mt_reg_sync_writel((val), ((void *)addr))
extern int get_immediate_cpu_wrap(void);
extern int get_immediate_gpu_wrap(void);
extern int get_immediate_soc_wrap(void);
extern int get_immediate_md_wrap(void);
/* Added for DLPT. */
extern int tscpu_get_min_cpu_pwr(void);
extern int tscpu_get_min_gpu_pwr(void);
/* Five thermal sensors. */
enum mtk_thermal_sensor_cpu_id_met {
MTK_THERMAL_SENSOR_TS1 = 0,
MTK_THERMAL_SENSOR_TS2,
MTK_THERMAL_SENSOR_TS3,
MTK_THERMAL_SENSOR_TSABB,
ATM_CPU_LIMIT,
ATM_GPU_LIMIT,
MTK_THERMAL_SENSOR_CPU_COUNT
};
extern int tscpu_get_cpu_temp_met(enum mtk_thermal_sensor_cpu_id_met id);
typedef void (*met_thermalsampler_funcMET)(void);
extern void mt_thermalsampler_registerCB(met_thermalsampler_funcMET pCB);
extern void mtkTTimer_cancel_timer(void);
extern void mtkTTimer_start_timer(void);
extern int mtkts_bts_get_hw_temp(void);
extern int get_immediate_ts1_wrap(void);
extern int get_immediate_ts2_wrap(void);
extern int get_immediate_ts3_wrap(void);
extern int get_immediate_tsabb_wrap(void);
extern int (*get_immediate_tsX[TS_ENUM_MAX])(void);
extern int is_cpu_power_unlimit(void); /* in mtk_ts_cpu.c */
extern int is_cpu_power_min(void); /* in mtk_ts_cpu.c */
extern int get_cpu_target_tj(void);
extern int get_cpu_target_offset(void);
extern int get_target_tj(void);
extern int mtk_thermal_get_tpcb_target(void);
extern void thermal_set_big_core_speed(unsigned int tempMonCtl1, unsigned int tempMonCtl2, unsigned int tempAhbPoll);
/* return value(1): cooler of abcct/abcct_lcmoff is deactive, and no thermal current limit. */
extern int mtk_cooler_is_abcct_unlimit(void);
#endif /* __MT6739_THERMAL_H__ */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/upmu_hw.h
+23025
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drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/upmu_sw.h
+371
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PMIC_UPMU_SW_MT6357_H_
#define _MT_PMIC_UPMU_SW_MT6357_H_
#include <mach/upmu_hw.h>
#define AUXADC_SUPPORT_IMM_CURRENT_MODE
#define BATTERY_SW_INIT
/* #define RBAT_PULL_UP_VOLT_BY_BIF*/
/* #define INIT_BAT_CUR_FROM_PTIM */
#define FG_RG_INT_EN_CHRDET INT_CHRDET
#define FG_RG_INT_EN_BAT2_H INT_ENUM_MAX
#define FG_RG_INT_EN_BAT2_L INT_ENUM_MAX
#define FG_RG_INT_EN_BAT_TEMP_H INT_ENUM_MAX
#define FG_RG_INT_EN_BAT_TEMP_L INT_ENUM_MAX
#define FG_RG_INT_EN_NAG_C_DLTV INT_NAG_C_DLTV
#define FG_BAT0_INT_H_NO INT_ENUM_MAX
#define FG_BAT0_INT_L_NO INT_ENUM_MAX
#define FG_BAT_INT_H_NO INT_ENUM_MAX
#define FG_BAT_INT_L_NO INT_ENUM_MAX
#define FG_CUR_H_NO INT_ENUM_MAX
#define FG_CUR_L_NO INT_ENUM_MAX
#define FG_ZCV_NO INT_FG_ZCV
#define FG_BAT1_INT_H_NO INT_FG_BAT0_H
#define FG_BAT1_INT_L_NO INT_FG_BAT0_L
#define FG_N_CHARGE_L_NO INT_ENUM_MAX
#define FG_IAVG_H_NO INT_ENUM_MAX
#define FG_IAVG_L_NO INT_ENUM_MAX
#define FG_TIME_NO INT_ENUM_MAX
#define FG_BAT_PLUGOUT_NO NO_USE_0_6
/* =============================================================================
* Low battery level define
* =============================================================================
*/
#define LOW_BATTERY_LEVEL enum LOW_BATTERY_LEVEL_TAG
#define LOW_BATTERY_PRIO enum LOW_BATTERY_PRIO_TAG
enum LOW_BATTERY_LEVEL_TAG {
LOW_BATTERY_LEVEL_0 = 0,
LOW_BATTERY_LEVEL_1 = 1,
LOW_BATTERY_LEVEL_2 = 2
};
enum LOW_BATTERY_PRIO_TAG {
LOW_BATTERY_PRIO_CPU_B = 0,
LOW_BATTERY_PRIO_CPU_L = 1,
LOW_BATTERY_PRIO_GPU = 2,
LOW_BATTERY_PRIO_MD = 3,
LOW_BATTERY_PRIO_MD5 = 4,
LOW_BATTERY_PRIO_FLASHLIGHT = 5,
LOW_BATTERY_PRIO_VIDEO = 6,
LOW_BATTERY_PRIO_WIFI = 7,
LOW_BATTERY_PRIO_BACKLIGHT = 8
};
extern void (*low_battery_callback)(LOW_BATTERY_LEVEL);
extern void register_low_battery_notify(
void (*low_battery_callback)(LOW_BATTERY_LEVEL),
LOW_BATTERY_PRIO prio_val);
/* =============================================================================
* Battery OC level define
* =============================================================================
*/
#define BATTERY_OC_LEVEL enum BATTERY_OC_LEVEL_TAG
#define BATTERY_OC_PRIO enum BATTERY_OC_PRIO_TAG
enum BATTERY_OC_LEVEL_TAG {
BATTERY_OC_LEVEL_0 = 0,
BATTERY_OC_LEVEL_1 = 1
};
enum BATTERY_OC_PRIO_TAG {
BATTERY_OC_PRIO_CPU_B = 0,
BATTERY_OC_PRIO_CPU_L = 1,
BATTERY_OC_PRIO_GPU = 2,
BATTERY_OC_PRIO_MD = 3,
BATTERY_OC_PRIO_MD5 = 4,
BATTERY_OC_PRIO_FLASHLIGHT = 5
};
extern void (*battery_oc_callback)(BATTERY_OC_LEVEL);
extern void register_battery_oc_notify(
void (*battery_oc_callback)(BATTERY_OC_LEVEL),
BATTERY_OC_PRIO prio_val);
/* =============================================================================
* Battery percent define
* =============================================================================
*/
#define BATTERY_PERCENT_LEVEL enum BATTERY_PERCENT_LEVEL_TAG
#define BATTERY_PERCENT_PRIO enum BATTERY_PERCENT_PRIO_TAG
enum BATTERY_PERCENT_LEVEL_TAG {
BATTERY_PERCENT_LEVEL_0 = 0,
BATTERY_PERCENT_LEVEL_1 = 1
};
enum BATTERY_PERCENT_PRIO_TAG {
BATTERY_PERCENT_PRIO_CPU_B = 0,
BATTERY_PERCENT_PRIO_CPU_L = 1,
BATTERY_PERCENT_PRIO_GPU = 2,
BATTERY_PERCENT_PRIO_MD = 3,
BATTERY_PERCENT_PRIO_MD5 = 4,
BATTERY_PERCENT_PRIO_FLASHLIGHT = 5,
BATTERY_PERCENT_PRIO_VIDEO = 6,
BATTERY_PERCENT_PRIO_WIFI = 7,
BATTERY_PERCENT_PRIO_BACKLIGHT = 8
};
extern void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL);
extern void
register_battery_percent_notify(
void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL),
BATTERY_PERCENT_PRIO prio_val);
/*=============================================================================
* DLPT define
*=============================================================================
*/
#define DLPT_PRIO enum DLPT_PRIO_TAG
enum DLPT_PRIO_TAG {
DLPT_PRIO_PBM = 0,
DLPT_PRIO_CPU_B = 1,
DLPT_PRIO_CPU_L = 2,
DLPT_PRIO_GPU = 3,
DLPT_PRIO_MD = 4,
DLPT_PRIO_MD5 = 5,
DLPT_PRIO_FLASHLIGHT = 6,
DLPT_PRIO_VIDEO = 7,
DLPT_PRIO_WIFI = 8,
DLPT_PRIO_BACKLIGHT = 9
};
extern void (*dlpt_callback)(unsigned int dlpt_val);
extern void register_dlpt_notify(void (*dlpt_callback)(unsigned int dlpt_val),
DLPT_PRIO prio_val);
extern const PMU_FLAG_TABLE_ENTRY pmu_flags_table[];
extern unsigned short is_battery_remove;
extern unsigned short is_wdt_reboot_pmic;
extern unsigned short is_wdt_reboot_pmic_chk;
/*=============================================================================
* PMIC IRQ ENUM define
*=============================================================================
*/
enum PMIC_IRQ_ENUM {
INT_VPROC_OC,
SP_BUCK_TOP_START = INT_VPROC_OC,
INT_VCORE_OC,
INT_VMODEM_OC,
INT_VS1_OC,
INT_VPA_OC,
INT_VCORE_PREOC,
NO_USE_0_6,
NO_USE_0_7,
NO_USE_0_8,
NO_USE_0_9,
NO_USE_0_10,
NO_USE_0_11,
NO_USE_0_12,
NO_USE_0_13,
NO_USE_0_14,
NO_USE_0_15,
INT_VFE28_OC,
SP_LDO_TOP_START = INT_VFE28_OC,
INT_VXO22_OC,
INT_VRF18_OC,
INT_VRF12_OC,
INT_VEFUSE_OC,
INT_VCN33_OC,
INT_VCN28_OC,
INT_VCN18_OC,
INT_VCAMA_OC,
INT_VCAMD_OC,
INT_VCAMIO_OC,
INT_VLDO28_OC,
INT_VUSB33_OC,
INT_VAUX18_OC,
INT_VAUD28_OC,
INT_VIO28_OC,
INT_VIO18_OC,
INT_VSRAM_PROC_OC,
INT_VSRAM_OTHERS_OC,
INT_VIBR_OC,
INT_VDRAM_OC,
INT_VMC_OC,
INT_VMCH_OC,
INT_VEMC_OC,
INT_VSIM1_OC,
INT_VSIM2_OC,
NO_USE_2_10,
NO_USE_2_11,
NO_USE_2_12,
NO_USE_2_13,
NO_USE_2_14,
NO_USE_2_15,
INT_PWRKEY,
SP_PSC_TOP_START = INT_PWRKEY,
INT_HOMEKEY,
INT_PWRKEY_R,
INT_HOMEKEY_R,
INT_NI_LBAT_INT,
INT_CHRDET,
INT_CHRDET_EDGE,
INT_VCDT_HV_DET,
NO_USE_3_8,
NO_USE_3_9,
INT_WATCHDOG,
INT_VBATON_UNDET,
INT_BVALID_DET,
INT_OV,
NO_USE_3_14,
NO_USE_3_15,
INT_RTC,
SP_SCK_TOP_START = INT_RTC,
NO_USE_4_1,
NO_USE_4_2,
NO_USE_4_3,
NO_USE_4_4,
NO_USE_4_5,
NO_USE_4_6,
NO_USE_4_7,
NO_USE_4_8,
NO_USE_4_9,
NO_USE_4_10,
NO_USE_4_11,
NO_USE_4_12,
NO_USE_4_13,
NO_USE_4_14,
NO_USE_4_15,
INT_FG_BAT0_H,
SP_BM_TOP_START = INT_FG_BAT0_H,
INT_FG_BAT0_L,
INT_FG_CUR_H,
INT_FG_CUR_L,
INT_FG_ZCV,
NO_USE_5_5,
NO_USE_5_6,
NO_USE_5_7,
NO_USE_5_8,
NO_USE_5_9,
NO_USE_5_10,
NO_USE_5_11,
NO_USE_5_12,
NO_USE_5_13,
NO_USE_5_14,
NO_USE_5_15,
INT_BATON_LV,
INT_BATON_HT,
NO_USE_6_2,
NO_USE_6_3,
NO_USE_6_4,
NO_USE_6_5,
NO_USE_6_6,
NO_USE_6_7,
NO_USE_6_8,
NO_USE_6_9,
NO_USE_6_10,
NO_USE_6_11,
NO_USE_6_12,
NO_USE_6_13,
NO_USE_6_14,
NO_USE_6_15,
NO_USE_7_0,
SP_HK_TOP_START = NO_USE_7_0,
NO_USE_7_1,
INT_BAT_H,
INT_BAT_L,
NO_USE_7_4,
NO_USE_7_5,
NO_USE_7_6,
NO_USE_7_7,
INT_AUXADC_IMP,
INT_NAG_C_DLTV,
NO_USE_7_10,
NO_USE_7_11,
NO_USE_7_12,
NO_USE_7_13,
NO_USE_7_14,
NO_USE_7_15,
INT_AUDIO,
SP_AUD_TOP_START = INT_AUDIO,
NO_USE_8_1,
NO_USE_8_2,
NO_USE_8_3,
NO_USE_8_4,
INT_ACCDET,
INT_ACCDET_EINT0,
INT_ACCDET_EINT1,
NO_USE_8_8,
NO_USE_8_9,
NO_USE_8_10,
NO_USE_8_11,
NO_USE_8_12,
NO_USE_8_13,
NO_USE_8_14,
NO_USE_8_15,
INT_SPI_CMD_ALERT,
SP_MISC_TOP_START = INT_SPI_CMD_ALERT,
NO_USE_9_1,
NO_USE_9_2,
NO_USE_9_3,
NO_USE_9_4,
NO_USE_9_5,
NO_USE_9_6,
NO_USE_9_7,
NO_USE_9_8,
NO_USE_9_9,
NO_USE_9_10,
NO_USE_9_11,
NO_USE_9_12,
NO_USE_9_13,
NO_USE_9_14,
NO_USE_9_15,
INT_ENUM_MAX,
};
/*=============================================================================
* PMIC auxadc define
*=============================================================================
*/
extern signed int g_I_SENSE_offset;
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
extern void mt_power_off(void);
/*=============================================================================
* PMIC fg define
*=============================================================================
*/
extern unsigned int bat_get_ui_percentage(void);
extern signed int fgauge_read_v_by_d(int d_val);
extern signed int fgauge_read_r_bat_by_v(signed int voltage);
extern signed int fgauge_read_IM_current(void *data);
extern void kpd_pwrkey_pmic_handler(unsigned long pressed);
extern void kpd_pmic_rstkey_handler(unsigned long pressed);
extern int is_mt6311_sw_ready(void);
extern int is_mt6311_exist(void);
extern int get_mt6311_i2c_ch_num(void);
/*extern bool crystal_exist_status(void);*/
#if defined CONFIG_MTK_LEGACY
extern void pmu_drv_tool_customization_init(void);
#endif
extern int batt_init_cust_data(void);
extern void PMIC_INIT_SETTING_V1(void);
extern int do_ptim_ex(bool isSuspend, unsigned int *bat, signed int *cur);
/*=============================================================================
* Others: only for mt6357
*=============================================================================
*/
extern unsigned int PMIC_LP_CHIP_VER(void);
extern unsigned int is_pmic_mrv(void);
#endif /* _MT_PMIC_UPMU_SW_MT6357_H_ */
drivers/misc/mediatek/include/mt-plat/mt6739/include/mach/wd_api.h
+99
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#if defined(CONFIG_MTK_WATCHDOG_COMMON)
/* use common wd api */
#include <mt-plat/mtk_wd_api.h>
#else
/* WD MODE MARK BIT */
#define MTK_WDT_REQ_DEBUG_EN_MARK (0x80000)
#define MTK_WDT_REQ_SPM_THERMAL_MARK (0x0001)
#define MTK_WDT_REQ_SPM_SCPSYS_MARK (0x0002)
#define MTK_WDT_REQ_EINT_MARK (1<<2)
#define MTK_WDT_REQ_SYSRST_MARK (1<<3)
#define MTK_WDT_REQ_THERMAL_MARK (1<<18)
/* wd_sw_reset options */
#define WD_SW_RESET_BYPASS_PWR_KEY (1 << 0)
#define WD_SW_RESET_KEEP_DDR_RESERVE (1 << 1)
#ifndef FALSE
#define FALSE (0)
#endif
#ifndef TRUE
#define TRUE (1)
#endif
enum ext_wdt_mode {
WDT_IRQ_ONLY_MODE,
WDT_HW_REBOOT_ONLY_MODE,
WDT_DUAL_MODE,
};
enum wk_wdt_en {
WK_WDT_DIS,
WK_WDT_EN,
};
enum wd_restart_type {
WD_TYPE_NORMAL,
WD_TYPE_NOLOCK,
};
enum wk_req_en {
WD_REQ_DIS,
WD_REQ_EN,
};
enum wk_req_mode {
WD_REQ_IRQ_MODE,
WD_REQ_RST_MODE,
};
struct wd_api {
long ready;
int (*wd_restart)(enum wd_restart_type type);
int (*wd_cpu_hot_plug_on_notify)(int cpu);
int (*wd_cpu_hot_plug_off_notify)(int cpu);
int (*wd_sw_reset)(int cpu);
int (*wd_config)(enum ext_wdt_mode, int timeout_val);
int (*wd_disable_ext)(void);
int (*wd_disable_local)(void);
int (*wd_disable_all)(void);
int (*wd_set_mode)(enum ext_wdt_mode);
int (*wd_aee_confirm_hwreboot)(void);
void (*wd_suspend_notify)(void);
void (*wd_resume_notify)(void);
unsigned int (*wd_get_check_bit)(void);
unsigned int (*wd_get_kick_bit)(void);
int (*wd_spmwdt_mode_config)(enum wk_req_en en,
enum wk_req_mode mode);
int (*wd_thermal_mode_config)(enum wk_req_en en,
enum wk_req_mode mode);
int (*wd_dram_reserved_mode)(bool enabled);
int (*wd_mcu_cache_preserve)(bool enabled);
int (*wd_thermal_direct_mode_config)(enum wk_req_en en,
enum wk_req_mode mode);
int (*wd_debug_key_eint_config)(enum wk_req_en en,
enum wk_req_mode mode);
int (*wd_debug_key_sysrst_config)(enum wk_req_en en,
enum wk_req_mode mode);
int (*wd_dfd_count_en)(int value);
int (*wd_dfd_thermal1_dis)(int value);
int (*wd_dfd_thermal2_dis)(int value);
int (*wd_dfd_timeout)(int value);
};
unsigned int get_check_bit(void);
unsigned int get_kick_bit(void);
int get_wd_api(struct wd_api **obj);
int wd_api_init(void);
void wk_cpu_update_bit_flag(int cpu, int plug_status);
extern void aee_wdt_printf(const char *fmt, ...);
#endif
drivers/misc/mediatek/include/mt-plat/mt6761/include/mach/mtk_cpufreq_api.h
+80
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* ICCS */
extern int mt_cpufreq_set_iccs_frequency_by_cluster(int en,
unsigned int cluster_id, unsigned int freq);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_phy_freq_no_lock(
unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6761/include/mach/mtk_pwm_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PWM_HAL_H__
#define __MT_PWM_HAL_H__
#include <linux/types.h>
#include <mt-plat/sync_write.h>
/**********************************
* Global enum data
*/
/******************* Register Manipulations*****************/
#define INREG32(reg) __raw_readl((void *)reg)
#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
enum PWN_NO {
PWM_MIN,
PWM1 = PWM_MIN,
PWM2,
PWM3,
PWM4,
PWM5,
PWM6,
PWM_NUM,
PWM_MAX = PWM_NUM
};
enum TEST_SEL_BIT {
TEST_SEL_FALSE,
TEST_SEL_TRUE
};
enum PWM_CON_MODE_BIT {
PERIOD,
RAND
};
enum PWM_CON_SRCSEL_BIT {
PWM_FIFO,
MEMORY
};
enum PWM_CON_IDLE_BIT {
IDLE_FALSE,
IDLE_TRUE,
IDLE_MAX
};
enum PWM_CON_GUARD_BIT {
GUARD_FALSE,
GUARD_TRUE,
GUARD_MAX
};
enum OLD_MODE_BIT {
OLDMODE_DISABLE,
OLDMODE_ENABLE
};
enum PWM_BUF_VALID_BIT {
BUF0_VALID,
BUF0_EN_VALID,
BUF1_VALID,
BUF1_EN_VALID,
BUF_EN_MAX
};
enum CLOCK_SRC {
CLK_BLOCK,
CLK_BLOCK_BY_1625_OR_32K
};
enum PWM_CLK_DIV {
CLK_DIV_MIN,
CLK_DIV1 = CLK_DIV_MIN,
CLK_DIV2,
CLK_DIV4,
CLK_DIV8,
CLK_DIV16,
CLK_DIV32,
CLK_DIV64,
CLK_DIV128,
CLK_DIV_MAX
};
enum PWM_INT_ENABLE_BITS {
PWM1_INT_FINISH_EN,
PWM1_INT_UNDERFLOW_EN,
PWM2_INT_FINISH_EN,
PWM2_INT_UNDERFLOW_EN,
PWM3_INT_FINISH_EN,
PWM3_INT_UNDERFLOW_EN,
PWM4_INT_FINISH_EN,
PWM4_INT_UNDERFLOW_EN,
PWM5_INT_FINISH_EN,
PWM5_INT_UNDERFLOW_EN,
PWM6_INT_FINISH_EN,
PWM6_INT_UNDERFLOW_EN,
PWM_INT_ENABLE_BITS_MAX,
};
enum PWM_INT_STATUS_BITS {
PWM1_INT_FINISH_ST,
PWM1_INT_UNDERFLOW_ST,
PWM2_INT_FINISH_ST,
PWM2_INT_UNDERFLOW_ST,
PWM3_INT_FINISH_ST,
PWM3_INT_UNDERFLOW_ST,
PWM4_INT_FINISH_ST,
PWM4_INT_UNDERFLOW_ST,
PWM5_INT_FINISH_ST,
PWM5_INT_UNDERFLOW_ST,
PWM6_INT_FINISH_ST,
PWM6_INT_UNDERFLOW_ST,
PWM_INT_STATUS_BITS_MAX,
};
enum PWM_INT_ACK_BITS {
PWM1_INT_FINISH_ACK,
PWM1_INT_UNDERFLOW_ACK,
PWM2_INT_FINISH_ACK,
PWM2_INT_UNDERFLOW_ACK,
PWM3_INT_FINISH_ACK,
PWM3_INT_UNDERFLOW_ACK,
PWM4_INT_FINISH_ACK,
PWM4_INT_UNDERFLOW_ACK,
PWM_INT_ACK_BITS_MAX,
};
enum PWM_CLOCK_SRC_ENUM {
PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_32K,
PWM_CLK_NEW_MODE_BLOCK,
PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
PWM_CLK_SRC_NUM,
PWM_CLK_SRC_INVALID,
};
enum PWM_MODE_ENUM {
PWM_MODE_MIN,
PWM_MODE_OLD = PWM_MODE_MIN,
PWM_MODE_FIFO,
PWM_MODE_MEMORY,
PWM_MODE_RANDOM,
PWM_MODE_DELAY,
PWM_MODE_INVALID,
};
enum INFRA_CLK_SRC_CTRL {
CLK_32K = 0x00,
CLK_26M = 0x01,
CLK_78M = 0x2,
CLK_SEL_TOPCKGEN = 0x3,
};
#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
void mt_set_pwm_3dlcm_enable_hal(u8 enable);
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
void mt_pwm_26M_clk_enable_hal(u32 enable);
#endif
drivers/misc/mediatek/include/mt-plat/mt6765/include/mach/mtk_cpufreq_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* ICCS */
extern int mt_cpufreq_set_iccs_frequency_by_cluster(int en,
unsigned int cluster_id, unsigned int freq);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_phy_freq_no_lock(
unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6765/include/mach/mtk_pwm_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PWM_HAL_H__
#define __MT_PWM_HAL_H__
#include <linux/types.h>
#include <mt-plat/sync_write.h>
/**********************************
* Global enum data
*/
/******************* Register Manipulations*****************/
#define INREG32(reg) __raw_readl((void *)reg)
#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
enum PWN_NO {
PWM_MIN,
PWM1 = PWM_MIN,
PWM2,
PWM3,
PWM4,
PWM5,
PWM6,
PWM_NUM,
PWM_MAX = PWM_NUM
};
enum TEST_SEL_BIT {
TEST_SEL_FALSE,
TEST_SEL_TRUE
};
enum PWM_CON_MODE_BIT {
PERIOD,
RAND
};
enum PWM_CON_SRCSEL_BIT {
PWM_FIFO,
MEMORY
};
enum PWM_CON_IDLE_BIT {
IDLE_FALSE,
IDLE_TRUE,
IDLE_MAX
};
enum PWM_CON_GUARD_BIT {
GUARD_FALSE,
GUARD_TRUE,
GUARD_MAX
};
enum OLD_MODE_BIT {
OLDMODE_DISABLE,
OLDMODE_ENABLE
};
enum PWM_BUF_VALID_BIT {
BUF0_VALID,
BUF0_EN_VALID,
BUF1_VALID,
BUF1_EN_VALID,
BUF_EN_MAX
};
enum CLOCK_SRC {
CLK_BLOCK,
CLK_BLOCK_BY_1625_OR_32K
};
enum PWM_CLK_DIV {
CLK_DIV_MIN,
CLK_DIV1 = CLK_DIV_MIN,
CLK_DIV2,
CLK_DIV4,
CLK_DIV8,
CLK_DIV16,
CLK_DIV32,
CLK_DIV64,
CLK_DIV128,
CLK_DIV_MAX
};
enum PWM_INT_ENABLE_BITS {
PWM1_INT_FINISH_EN,
PWM1_INT_UNDERFLOW_EN,
PWM2_INT_FINISH_EN,
PWM2_INT_UNDERFLOW_EN,
PWM3_INT_FINISH_EN,
PWM3_INT_UNDERFLOW_EN,
PWM4_INT_FINISH_EN,
PWM4_INT_UNDERFLOW_EN,
PWM5_INT_FINISH_EN,
PWM5_INT_UNDERFLOW_EN,
PWM6_INT_FINISH_EN,
PWM6_INT_UNDERFLOW_EN,
PWM_INT_ENABLE_BITS_MAX,
};
enum PWM_INT_STATUS_BITS {
PWM1_INT_FINISH_ST,
PWM1_INT_UNDERFLOW_ST,
PWM2_INT_FINISH_ST,
PWM2_INT_UNDERFLOW_ST,
PWM3_INT_FINISH_ST,
PWM3_INT_UNDERFLOW_ST,
PWM4_INT_FINISH_ST,
PWM4_INT_UNDERFLOW_ST,
PWM5_INT_FINISH_ST,
PWM5_INT_UNDERFLOW_ST,
PWM6_INT_FINISH_ST,
PWM6_INT_UNDERFLOW_ST,
PWM_INT_STATUS_BITS_MAX,
};
enum PWM_INT_ACK_BITS {
PWM1_INT_FINISH_ACK,
PWM1_INT_UNDERFLOW_ACK,
PWM2_INT_FINISH_ACK,
PWM2_INT_UNDERFLOW_ACK,
PWM3_INT_FINISH_ACK,
PWM3_INT_UNDERFLOW_ACK,
PWM4_INT_FINISH_ACK,
PWM4_INT_UNDERFLOW_ACK,
PWM_INT_ACK_BITS_MAX,
};
enum PWM_CLOCK_SRC_ENUM {
PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_32K,
PWM_CLK_NEW_MODE_BLOCK,
PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
PWM_CLK_SRC_NUM,
PWM_CLK_SRC_INVALID,
};
enum PWM_MODE_ENUM {
PWM_MODE_MIN,
PWM_MODE_OLD = PWM_MODE_MIN,
PWM_MODE_FIFO,
PWM_MODE_MEMORY,
PWM_MODE_RANDOM,
PWM_MODE_DELAY,
PWM_MODE_INVALID,
};
enum INFRA_CLK_SRC_CTRL {
CLK_32K = 0x00,
CLK_26M = 0x01,
CLK_78M = 0x2,
CLK_SEL_TOPCKGEN = 0x3,
};
#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
void mt_set_pwm_3dlcm_enable_hal(u8 enable);
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
void mt_pwm_26M_clk_enable_hal(u32 enable);
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/memory_layout.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _H_MEMORY_LAYOUT_H_
#define _H_MEMORY_LAYOUT_H_
#define LK_KERNEL_32_BASE (0x40008000)
#define LK_KERNEL_32_MAX_SIZE (0x7C00000)
#define LK_KERNEL_64_BASE (0x40080000)
#define LK_KERNEL_64_MAX_SIZE (0x7C00000)
#define KERN_RAMCONSOLE_BASE (0x4D000000)
#define KERN_RAMCONSOLE_MAX_SIZE (0x10000)
#define KERN_PSTORE_BASE (0x4D010000)
#define KERN_PSTORE_MAX_SIZE (0xE0000)
#define KERN_MINIDUMP_BASE (0x4D0F0000)
#define KERN_MINIDUMP_MAX_SIZE (0x10000)
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mt_iommu.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_H__
#define __MT_IOMMU_H__
#include <dt-bindings/memory/mt6768-larb-port.h>
#include "mtk_iommu_ext.h"
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mt_iommu_plat.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PLAT_H__
#define __MT_IOMMU_PLAT_H__
/* ================ register control ================ */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
inline void iommu_set_field_by_mask(void __iomem *M4UBase,
unsigned int reg,
unsigned long mask,
unsigned int val)
{
unsigned int regval;
regval = readl_relaxed(M4UBase + reg);
regval = (regval & (~mask)) | val;
writel_relaxed(regval, M4UBase + reg);
}
/* ================ register defination ================ */
#define REG_MMU_PT_BASE_ADDR (0x0)
#define REG_MMU_PT_BASE_SEC_ADDR (0x4)
#define F_MMU_PT_VA_MSK 0xffffff80
#define F_MMU_PT_VA_MSK_SEC 0xffffff80
#define F_PGD_REG_BIT32 F_BIT_SET(0)
#define F_PGD_REG_BIT33 F_BIT_SET(1)
#define REG_MMU_INVALIDATE (0x20)
#define F_ALL_INVLD (0x2)
#define F_MMU_INV_RANGE (0x1)
#define REG_MMU_INVLD_START_A (0x24)
#define REG_MMU_INVLD_END_A (0x28)
#define REG_MMU_INV_SEL (0x2c)
#define F_INVLD_EN0 BIT(0)
#define F_INVLD_EN1 BIT(1)
#define REG_INVLID_SEL (0x38)
#define F_MMU_INV_EN_L2 (1<<1)
#define F_MMU_INV_EN_L1 (1<<0)
#define REG_MMU_DUMMY 0x44
#define F_REG_MMU_IDLE_ENABLE F_BIT_SET(0)
#define REG_MMU_MISC_CRTL (0x48)
#define REG_MMU0_STANDARD_AXI_MODE F_BIT_SET(0)
#define REG_MMU1_STANDARD_AXI_MODE F_BIT_SET(1)
#define REG_MMU_DCM_DIS (0x50)
#define REG_MMU_WR_LEN (0x54)
#define F_MMU_MMU0_WR_THROT_DIS F_BIT_SET(10)
#define F_MMU_MMU1_WR_THROT_DIS F_BIT_SET(11)
#define F_MMU_MMU1_WRITE_LEN F_MSK(9, 5)
#define F_MMU_MMU0_WRITE_LEN F_MSK(4, 0)
#define REG_MMU_COHERENCE_EN (0x80)
#define F_MMU_MMU0_COHERENCE_EN F_BIT_SET(0)
#define F_MMU_MMU1_COHERENCE_EN F_BIT_SET(1)
#define REG_MMU_IN_ORDER_WR_EN (0x84)
#define F_MMU_MMU0_IN_ORDER_WR_EN F_BIT_SET(0)
#define F_MMU_MMU1_IN_ORDER_WR_EN F_BIT_SET(1)
#define REG_MMU_CTRL_REG (0x110)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 10)
#define F_MMU_CTRL_HANG_PREVENTION(en) F_BIT_VAL(en, 9)
#define F_MMU_CTRL_INVALID_FIFO_EN(en) F_BIT_VAL(en, 8)
#define F_MMU_CTRL_LAYER2_PFH_DIS(dis) F_BIT_VAL(dis, 7)
#define F_MMU_CTRL_INT_HANG_EN(en) F_BIT_VAL(en, 6)
#define F_MMU_CTRL_TF_PROTECT_SEL(en) F_VAL(en, 5, 4)
#define F_MMU_CTRL_MONITOR_CLR(clr) F_BIT_VAL(clr, 2)
#define F_MMU_CTRL_MONITOR_EN(en) F_BIT_VAL(en, 1)
#define F_MMU_CTRL_PFH_DIS(dis) F_BIT_VAL(dis, 0)
#define REG_MMU_IVRP_PADDR (0x114)
#define F_MMU_IVRP_PA_SET(PA, EXT) (\
(((unsigned long long)PA) & F_MSK(31, 7)) | \
((((unsigned long long)PA) >> 32) & F_MSK(1, 0)))
#define F_RP_PA_REG_BIT32 F_BIT_SET(0)
#define F_RP_PA_REG_BIT33 F_BIT_SET(1)
#define REG_MMU_INT_CONTROL0 (0x120)
#define F_L2_MULIT_HIT_EN BIT(0)
#define F_TABLE_WALK_FAULT_INT_EN BIT(1)
#define F_PREETCH_FIFO_OVERFLOW_INT_EN BIT(2)
#define F_MISS_FIFO_OVERFLOW_INT_EN BIT(3)
#define F_L2_INVALIDATION_DONE_INT_EN BIT(4)
#define F_PREFETCH_FIFO_ERR_INT_EN BIT(5)
#define F_MISS_FIFO_ERR_INT_EN BIT(6)
#define F_INT_CLR_BIT BIT(12)
#define REG_MMU_INT_MAIN_CONTROL (0x124)
#define F_INT_TRANSLATION_FAULT(MMU) BIT(0+(MMU)*7)
#define F_INT_MAIN_MULTI_HIT_FAULT(MMU) BIT(1+(MMU)*7)
#define F_INT_INVALID_PA_FAULT(MMU) BIT(2+(MMU)*7)
#define F_INT_ENTRY_REPLACEMENT_FAULT(MMU) BIT(3+(MMU)*7)
#define F_INT_TLB_MISS_FAULT(MMU) BIT(4+(MMU)*7)
#define F_INT_MISS_TRANSACTION_FIFO_FAULT(MMU) BIT(5+(MMU)*7)
#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT(MMU) BIT(6+(MMU)*7)
#define F_INT_MMU0_MAIN_MSK F_MSK(6, 0)
#define F_INT_MMU1_MAIN_MSK F_MSK(13, 7)
#define F_INT_MMU0_MAU_MSK F_MSK(14, 14)
#define F_INT_MMU1_MAU_MSK F_MSK(15, 15)
#define REG_MMU_CPE_DONE (0x12C)
#define REG_MMU_L2_FAULT_ST (0x130)
#define REG_MMU_FAULT_ST1 (0x134)
#define REG_MMU_FAULT_VA(mmu) (0x13c+((mmu)<<3))
#define F_MMU_FAULT_VA_MSK F_MSK(31, 12)
#define F_MMU_FAULT_CATCH_INVPA F_BIT_SET(11)
#define F_MMU_FAULT_CATCH_TF F_BIT_SET(10)
#define F_MMU_FAULT_PA_B33_32 F_MSK(9, 8)
#define F_MMU_FAULT_VA_WRITE_BIT F_BIT_SET(1)
#define F_MMU_FAULT_VA_LAYER_BIT F_BIT_SET(0)
#define REG_MMU_INVLD_PA(mmu) (0x140+((mmu)<<3))
#define REG_MMU_INT_ID(mmu) (0x150+((mmu)<<2))
#define F_MMU0_INT_ID_TF_MSK (~0x3) /* only for MM iommu.*/
#define F_MMU_INT_TF_MSK F_MSK(11, 0)
/* bit[9:7] indicate larbid */
#define F_MMU0_INT_ID_LARB_ID(a) (((a) >> 7) & 0xf)
/*
* bit[6:2] indicate portid, bit[1:0] indicate master id, every port
* have four types of command, master id indicate the m4u port's command
* type, iommu do not care about this.
*/
#define F_MMU0_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
/*
* reserved IOVA Domain for IOMMU users of HW limitation.
*/
#define MTK_IOVA_DOMAIN_COUNT (2) // Domain count
enum mtk_reserve_region_type {
// no reserved region
IOVA_REGION_UNDEFINE,
// users cannot touch the IOVA in the reserved region
IOVA_REGION_REMOVE,
// users can only touch the IOVA in the reserved region
IOVA_REGION_STAY,
};
/*
* struct mtk_iova_domain_data: domain configuration
* @min_iova: start address of IOVAD
* @max_iova: end address of IOVAD
* @resv_start: the start address of reserved region
* @resv_size: the size of reserved region
* @resv_type: the type of reserve region
* @port_mask: the user list of IOVAD
* One user can only belongs to one IOVAD, the port mask is in unit of SMI larb.
*/
struct mtk_iova_domain_data {
unsigned long min_iova;
unsigned long max_iova;
unsigned long resv_start;
unsigned long resv_size;
unsigned int resv_type;
unsigned int port_mask[MTK_IOMMU_LARB_NR];
};
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT))
{
.min_iova = 0x48000000,
.max_iova = DMA_BIT_MASK(32),
.resv_start = 0x0,
.resv_size = 0x0,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0xff, 0x1ff, 0xfff, 0xe7fff, 0x7ff}
},
#else
{
.min_iova = 0x1000,
.max_iova = DMA_BIT_MASK(32),
.resv_start = 0x40000000,
.resv_size = 0x8000000,
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0xff, 0x1ff, 0xfff, 0xe7fff, 0x7ff}
},
#endif
{
.min_iova = 0x40000000,
.max_iova = 0x48000000 - 1,
.resv_start = 0x0,
.resv_size = 0x0,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x118000, 0x0}
}
};
#define MTK_IOMMU_PAGE_TABLE_SHARE (1)
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mt_iommu_port.h
+119
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
* this header file is only used for mtk_iomm module
* the definition of header file is platform dependency.
*/
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK
struct mtk_iommu_port {
char *name;
unsigned m4u_id: 2;
unsigned m4u_slave: 2;
unsigned larb_id: 4;
unsigned larb_port: 8;
unsigned tf_id: 12; /* 12 bits */
bool enable_tf;
mtk_iommu_fault_callback_t fault_fn;
void *fault_data;
};
#define MTK_IOMMU_PORT_INIT(name, slave, larb, port) {\
name, 0, slave, larb, port, (((larb)<<7)|((port)<<2)), 1\
}
#define M4U_SLAVE0 (0)
#define M4U_SLAVE1 (0)
#define M4U_SLAVE2 (0)
#define M4U_SLAVE3 (0)
#define M4U_SLAVE4 (0)
#define M4U_LARB0 (0)
#define M4U_LARB1 (1)
#define M4U_LARB2 (2)
#define M4U_LARB3 (3)
#define M4U_LARB4 (4)
#define MTK_IOMMU_LARB_NR (5)
struct mtk_iommu_port iommu_port[] = {
/*Larb0 */
MTK_IOMMU_PORT_INIT("DISP_OVL0", M4U_SLAVE0, M4U_LARB0, 0),
MTK_IOMMU_PORT_INIT("DISP_2L_OVL0_LARB0", M4U_SLAVE0, M4U_LARB0, 1),
MTK_IOMMU_PORT_INIT("DISP_RDMA0", M4U_SLAVE0, M4U_LARB0, 2),
MTK_IOMMU_PORT_INIT("DISP_WDMA0", M4U_SLAVE0, M4U_LARB0, 3),
MTK_IOMMU_PORT_INIT("MDP_RDMA0", M4U_SLAVE0, M4U_LARB0, 4),
MTK_IOMMU_PORT_INIT("MDP_WDMA0", M4U_SLAVE0, M4U_LARB0, 5),
MTK_IOMMU_PORT_INIT("MDP_WROT0", M4U_SLAVE0, M4U_LARB0, 6),
MTK_IOMMU_PORT_INIT("DISP_FAKE0", M4U_SLAVE0, M4U_LARB0, 7),
/*Larb1 */
MTK_IOMMU_PORT_INIT("VDEC_MC", M4U_SLAVE1, M4U_LARB1, 0),
MTK_IOMMU_PORT_INIT("VDEC_PP", M4U_SLAVE1, M4U_LARB1, 1),
MTK_IOMMU_PORT_INIT("VDEC_VLD", M4U_SLAVE1, M4U_LARB1, 2),
MTK_IOMMU_PORT_INIT("VDEC_VLD2", M4U_SLAVE1, M4U_LARB1, 3),
MTK_IOMMU_PORT_INIT("VDEC_AVC_MV", M4U_SLAVE1, M4U_LARB1, 4),
MTK_IOMMU_PORT_INIT("VDEC_PRED_RD", M4U_SLAVE1, M4U_LARB1, 5),
MTK_IOMMU_PORT_INIT("VDEC_PRED_WR", M4U_SLAVE1, M4U_LARB1, 6),
MTK_IOMMU_PORT_INIT("VDEC_PPWRAP", M4U_SLAVE1, M4U_LARB1, 7),
MTK_IOMMU_PORT_INIT("VDEC_TILE", M4U_SLAVE1, M4U_LARB1, 8),
/*Larb2 */
MTK_IOMMU_PORT_INIT("CAM_IMGI", M4U_SLAVE2, M4U_LARB2, 0),
MTK_IOMMU_PORT_INIT("CAM_IMG2O", M4U_SLAVE2, M4U_LARB2, 1),
MTK_IOMMU_PORT_INIT("CAM_IMG3O", M4U_SLAVE2, M4U_LARB2, 2),
MTK_IOMMU_PORT_INIT("CAM_VIPI", M4U_SLAVE2, M4U_LARB2, 3),
MTK_IOMMU_PORT_INIT("CAM_LCEI", M4U_SLAVE2, M4U_LARB2, 4),
MTK_IOMMU_PORT_INIT("CAM_FD_RP", M4U_SLAVE2, M4U_LARB2, 5),
MTK_IOMMU_PORT_INIT("CAM_FD_WR", M4U_SLAVE2, M4U_LARB2, 6),
MTK_IOMMU_PORT_INIT("CAM_FD_RB", M4U_SLAVE2, M4U_LARB2, 7),
MTK_IOMMU_PORT_INIT("CAM_DPE_RDMA", M4U_SLAVE2, M4U_LARB2, 8),
MTK_IOMMU_PORT_INIT("CAM_DPE_WDMA", M4U_SLAVE2, M4U_LARB2, 9),
MTK_IOMMU_PORT_INIT("CAM_RSC_RDMA", M4U_SLAVE2, M4U_LARB2, 10),
MTK_IOMMU_PORT_INIT("CAM_RSC_WDMA", M4U_SLAVE2, M4U_LARB2, 11),
/*Larb3 */
MTK_IOMMU_PORT_INIT("CAM_IMGO", M4U_SLAVE3, M4U_LARB3, 0),
MTK_IOMMU_PORT_INIT("CAM_RRZO", M4U_SLAVE3, M4U_LARB3, 1),
MTK_IOMMU_PORT_INIT("CAM_AAO", M4U_SLAVE3, M4U_LARB3, 2),
MTK_IOMMU_PORT_INIT("CAM_AFO", M4U_SLAVE3, M4U_LARB3, 3),
MTK_IOMMU_PORT_INIT("CAM_LSCI0", M4U_SLAVE3, M4U_LARB3, 4),
MTK_IOMMU_PORT_INIT("CAM_LSCI1", M4U_SLAVE3, M4U_LARB3, 5),
MTK_IOMMU_PORT_INIT("CAM_PDO", M4U_SLAVE3, M4U_LARB3, 6),
MTK_IOMMU_PORT_INIT("CAM_BPCI", M4U_SLAVE3, M4U_LARB3, 7),
MTK_IOMMU_PORT_INIT("CAM_LCSO", M4U_SLAVE3, M4U_LARB3, 8),
MTK_IOMMU_PORT_INIT("CAM_RSSO_A", M4U_SLAVE3, M4U_LARB3, 9),
MTK_IOMMU_PORT_INIT("CAM_RSSO_B", M4U_SLAVE3, M4U_LARB3, 10),
MTK_IOMMU_PORT_INIT("CAM_UFEO", M4U_SLAVE3, M4U_LARB3, 11),
MTK_IOMMU_PORT_INIT("CAM_SOCO", M4U_SLAVE3, M4U_LARB3, 12),
MTK_IOMMU_PORT_INIT("CAM_SOC1", M4U_SLAVE3, M4U_LARB3, 13),
MTK_IOMMU_PORT_INIT("CAM_SOC2", M4U_SLAVE3, M4U_LARB3, 14),
MTK_IOMMU_PORT_INIT("CAM_CCUI", M4U_SLAVE3, M4U_LARB3, 15),
MTK_IOMMU_PORT_INIT("CAM_CCUO", M4U_SLAVE3, M4U_LARB3, 16),
MTK_IOMMU_PORT_INIT("CAM_CACI", M4U_SLAVE3, M4U_LARB3, 17),
MTK_IOMMU_PORT_INIT("CAM_RAWI_A", M4U_SLAVE3, M4U_LARB3, 18),
MTK_IOMMU_PORT_INIT("CAM_RAWI_B", M4U_SLAVE3, M4U_LARB3, 19),
MTK_IOMMU_PORT_INIT("CAM_CCUG", M4U_SLAVE3, M4U_LARB3, 20),
/*Larb4 */
MTK_IOMMU_PORT_INIT("VENC_RCPU", M4U_SLAVE4, M4U_LARB4, 0),
MTK_IOMMU_PORT_INIT("VENC_REC", M4U_SLAVE4, M4U_LARB4, 1),
MTK_IOMMU_PORT_INIT("VENC_BSDMA", M4U_SLAVE4, M4U_LARB4, 2),
MTK_IOMMU_PORT_INIT("VENC_SV_COMV", M4U_SLAVE4, M4U_LARB4, 3),
MTK_IOMMU_PORT_INIT("VENC_RD_COMV", M4U_SLAVE4, M4U_LARB4, 4),
MTK_IOMMU_PORT_INIT("JPGENC_RDMA", M4U_SLAVE4, M4U_LARB4, 5),
MTK_IOMMU_PORT_INIT("JPGENC_BSDMA", M4U_SLAVE4, M4U_LARB4, 6),
MTK_IOMMU_PORT_INIT("VENC_CUR_LUMA", M4U_SLAVE4, M4U_LARB4, 7),
MTK_IOMMU_PORT_INIT("VENC_CUR_CHROMA", M4U_SLAVE4, M4U_LARB4, 8),
MTK_IOMMU_PORT_INIT("VENC_REF_LUMA", M4U_SLAVE4, M4U_LARB4, 9),
MTK_IOMMU_PORT_INIT("VENC_REF_CHROMA", M4U_SLAVE4, M4U_LARB4, 10),
MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0)
};
#ifndef M4U_PORT_NR
#define M4U_PORT_NR (61)
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_battery.h
+67
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_BATTERY_H
#define _MTK_BATTERY_H
#ifndef _DEA_MODIFY_
#include <linux/list.h>
#include <linux/notifier.h>
#else
#include "simulator_kernel.h"
#endif
/* ============================================================ */
/* typedef */
/* ============================================================ */
/* coulomb service */
struct gauge_consumer {
char *name;
struct device *dev;
long start;
long end;
int variable;
int (*callback)(struct gauge_consumer *gc);
struct list_head list;
};
extern void gauge_coulomb_service_init(void);
extern void gauge_coulomb_consumer_init(struct gauge_consumer *coulomb,
struct device *dev, char *name);
extern void gauge_coulomb_start(struct gauge_consumer *coulomb, int car);
extern void gauge_coulomb_stop(struct gauge_consumer *coulomb);
extern void gauge_coulomb_dump_list(void);
extern void gauge_coulomb_before_reset(void);
extern void gauge_coulomb_after_reset(void);
extern void gauge_coulomb_set_log_level(int x);
/* coulomb sub system end */
/* battery notify charger_consumer */
enum {
EVENT_BATTERY_PLUG_OUT,
};
extern int register_battery_notifier(struct notifier_block *nb);
extern int unregister_battery_notifier(struct notifier_block *nb);
/* battery notify charger_consumer end*/
/* battery common interface */
extern signed int battery_get_bat_voltage(void);
extern signed int battery_get_bat_current(void);
extern signed int battery_get_bat_current_mA(void);
extern signed int battery_get_soc(void);
extern signed int battery_get_uisoc(void);
extern signed int battery_get_bat_temperature(void);
extern signed int battery_get_ibus(void);
extern signed int battery_get_vbus(void);
extern signed int battery_get_bat_avg_current(void);
#endif /* End of _FUEL_GAUGE_GM_30_H */
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_battery_property.h
+277
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_BATTERY_PROPERTY_H
#define _MTK_BATTERY_PROPERTY_H
/* customize */
#define DIFFERENCE_FULLOCV_ITH 200 /* mA */
#define MTK_CHR_EXIST 1
#define KEEP_100_PERCENT 1
#define R_FG_VALUE 5 /* mOhm */
#define EMBEDDED_SEL 0
#define PMIC_SHUTDOWN_CURRENT 20 /* 0.01 mA */
#define FG_METER_RESISTANCE 100
#define CAR_TUNE_VALUE 100 /*1.00 */
#define NO_BAT_TEMP_COMPENSATE 0
/* NO_BAT_TEMP_COMPENSATE 1 = don't need bat_temper compensate, */
/* but fg_meter_resistance still use for SWOCV */
/* enable that soc = 0 , shutdown */
#define SHUTDOWN_GAUGE0 1
/* enable that uisoc = 1 and wait xmins then shutdown */
#define SHUTDOWN_GAUGE1_XMINS 1
/* define Xmins to shutdown*/
#define SHUTDOWN_1_TIME 5
#define SHUTDOWN_GAUGE1_VBAT_EN 0
#define SHUTDOWN_GAUGE1_VBAT 34000
#define SHUTDOWN_GAUGE0_VOLTAGE 34000
#define POWERON_SYSTEM_IBOOT 500 /* mA */
/*
* LOW_TEMP_MODE = 0
* disable LOW_TEMP_MODE
* LOW_TEMP_MODE = 1
* if battery temperautre < LOW_TEMP_MODE_TEMP
* when bootup , force C mode
* LOW_TEMP_MODE = 2
* if battery temperautre < LOW_TEMP_MODE_TEMP
* force C mode
*/
#define LOW_TEMP_MODE 0
#define LOW_TEMP_MODE_TEMP 0
#define D0_SEL 0 /* not implement */
#define AGING_SEL 0 /* not implement */
#define DLPT_UI_REMAP_EN 0
/* ADC resistor */
#define R_BAT_SENSE 4
#define R_I_SENSE 4
#define R_CHARGER_1 330
#define R_CHARGER_2 39
#define QMAX_SEL 1
#define IBOOT_SEL 0
#define SHUTDOWN_SYSTEM_IBOOT 15000 /* 0.1mA */
#define PMIC_MIN_VOL 33500
/*ui_soc related */
#define DIFFERENCE_FULL_CV 1000 /*0.01%*/
#define PSEUDO1_EN 1
#define PSEUDO100_EN 1
#define PSEUDO100_EN_DIS 1
#define DIFF_SOC_SETTING 50 /* 0.01% */
#define DIFF_BAT_TEMP_SETTING 1
#define DIFF_BAT_TEMP_SETTING_C 10
#define DISCHARGE_TRACKING_TIME 10
#define CHARGE_TRACKING_TIME 60
#define DIFFERENCE_FULLOCV_VTH 1000 /* 0.1mV */
#define CHARGE_PSEUDO_FULL_LEVEL 8000
#define FULL_TRACKING_BAT_INT2_MULTIPLY 6
/* pre tracking */
#define FG_PRE_TRACKING_EN 1
#define VBAT2_DET_TIME 5
#define VBAT2_DET_COUNTER 6
#define VBAT2_DET_VOLTAGE1 34500
#define VBAT2_DET_VOLTAGE2 32000
#define VBAT2_DET_VOLTAGE3 35000
/* PCB setting */
#define CALIBRATE_CAR_TUNE_VALUE_BY_META_TOOL
#define CALI_CAR_TUNE_AVG_NUM 60
/* Aging Compensation 1*/
#define AGING_FACTOR_MIN 75
#define AGING_FACTOR_DIFF 10
#define DIFFERENCE_VOLTAGE_UPDATE 50
#define AGING_ONE_EN 1
#define AGING1_UPDATE_SOC 30
#define AGING1_LOAD_SOC 70
#define AGING_TEMP_DIFF 10
#define AGING_TEMP_LOW_LIMIT 15
#define AGING_TEMP_HIGH_LIMIT 50
#define AGING_100_EN 1
/* Aging Compensation 2*/
#define AGING_TWO_EN 1
/* Aging Compensation 3*/
#define AGING_THIRD_EN 1
#define AGING_4_EN 1
#define AGING_5_EN 1
#define AGING_6_EN 1
#define AGING4_UPDATE_SOC 40
#define AGING4_LOAD_SOC 70
#define AGING5_UPDATE_SOC 30
#define AGING5_LOAD_SOC 70
#define AGING6_UPDATE_SOC 30
#define AGING6_LOAD_SOC 70
/* threshold */
#define HWOCV_SWOCV_DIFF 300
#define HWOCV_SWOCV_DIFF_LT 1500
#define HWOCV_SWOCV_DIFF_LT_TEMP 5
#define HWOCV_OLDOCV_DIFF 300
#define HWOCV_OLDOCV_DIFF_CHR 800
#define SWOCV_OLDOCV_DIFF 300
#define SWOCV_OLDOCV_DIFF_CHR 800
#define VBAT_OLDOCV_DIFF 1000
#define SWOCV_OLDOCV_DIFF_EMB 1000 /* 100mV */
#define VIR_OLDOCV_DIFF_EMB 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_LT 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_TMP 5
#define TNEW_TOLD_PON_DIFF 5
#define TNEW_TOLD_PON_DIFF2 15
#define PMIC_SHUTDOWN_TIME 30
#define BAT_PLUG_OUT_TIME 32
#define EXT_HWOCV_SWOCV 300
#define EXT_HWOCV_SWOCV_LT 1500
#define EXT_HWOCV_SWOCV_LT_TEMP 5
/* fgc & fgv threshold */
#define DIFFERENCE_FGC_FGV_TH1 300
#define DIFFERENCE_FGC_FGV_TH2 500
#define DIFFERENCE_FGC_FGV_TH3 300
#define DIFFERENCE_FGC_FGV_TH_SOC1 7000
#define DIFFERENCE_FGC_FGV_TH_SOC2 3000
#define NAFG_TIME_SETTING 10
#define NAFG_RATIO 100
#define NAFG_RATIO_EN 0
#define NAFG_RATIO_TMP_THR 1
#define NAFG_RESISTANCE 1500
#define PMIC_SHUTDOWN_SW_EN 1
#define FORCE_VC_MODE 0 /* 0: mix, 1:Coulomb, 2:voltage */
#define LOADING_1_EN 0
#define LOADING_2_EN 2
#define DIFF_IAVG_TH 3000
/* ZCV INTR */
#define ZCV_SUSPEND_TIME 3
#define SLEEP_CURRENT_AVG 200 /*0.1mA*/
#define ZCV_COM_VOL_LIMIT 50 /* 50mv */
#define ZCV_CAR_GAP_PERCENTAGE 5
/* Additional battery table */
#define ADDITIONAL_BATTERY_TABLE_EN 1
#define DC_RATIO_SEL 5
#define DC_R_CNT 1000 /* if set 0, dcr_start will not be 1*/
#define BAT_PAR_I 4000 /* not implement */
#define PSEUDO1_SEL 2
#define FG_TRACKING_CURRENT 30000 /* not implement */
#define FG_TRACKING_CURRENT_IBOOT_EN 0 /* not implement */
#define UI_FAST_TRACKING_EN 0
#define UI_FAST_TRACKING_GAP 300
#define KEEP_100_PERCENT_MINSOC 9000
#define SHUTDOWN_CONDITION_LOW_BAT_VOLT
#define LOW_TEMP_DISABLE_LOW_BAT_SHUTDOWN 1
#define LOW_TEMP_THRESHOLD 5
#define BATTERY_TMP_TO_DISABLE_GM30 -50
#define BATTERY_TMP_TO_DISABLE_NAFG -35
#define DEFAULT_BATTERY_TMP_WHEN_DISABLE_NAFG 25
#define BATTERY_TMP_TO_ENABLE_NAFG -20
/* #define GM30_DISABLE_NAFG */
#define POWER_ON_CAR_CHR 5
#define POWER_ON_CAR_NOCHR -35
#define SHUTDOWN_CAR_RATIO 1
#define MULTI_TEMP_GAUGE0 1 /* different temp using different gauge 0% */
#define OVER_DISCHARGE_LEVEL -1500
#define UISOC_UPDATE_TYPE 0
/*
* uisoc_update_type:
* 0: only ui_soc interrupt update ui_soc
* 1: coulomb/nafg will update ui_soc if delta car > ht/lt_gap /2
* 2: coulomb/nafg will update ui_soc
*/
/* using current to limit uisoc in 100% case*/
/* UI_FULL_LIMIT_ITH0 3000 means 300ma */
#define UI_FULL_LIMIT_EN 0
#define UI_FULL_LIMIT_SOC0 9900
#define UI_FULL_LIMIT_ITH0 2200
#define UI_FULL_LIMIT_SOC1 9900
#define UI_FULL_LIMIT_ITH1 2200
#define UI_FULL_LIMIT_SOC2 9900
#define UI_FULL_LIMIT_ITH2 2200
#define UI_FULL_LIMIT_SOC3 9900
#define UI_FULL_LIMIT_ITH3 2200
#define UI_FULL_LIMIT_SOC4 9900
#define UI_FULL_LIMIT_ITH4 2200
#define UI_FULL_LIMIT_TIME 99999
#define UI_FULL_LIMIT_FC_SOC0 9900
#define UI_FULL_LIMIT_FC_ITH0 3000
#define UI_FULL_LIMIT_FC_SOC1 9900
#define UI_FULL_LIMIT_FC_ITH1 3100
#define UI_FULL_LIMIT_FC_SOC2 9900
#define UI_FULL_LIMIT_FC_ITH2 3200
#define UI_FULL_LIMIT_FC_SOC3 9900
#define UI_FULL_LIMIT_FC_ITH3 3300
#define UI_FULL_LIMIT_FC_SOC4 9900
#define UI_FULL_LIMIT_FC_ITH4 3400
/* using voltage to limit uisoc in 1% case */
/* UI_LOW_LIMIT_VTH0=36000 means 3.6v */
#define UI_LOW_LIMIT_EN 0
#define UI_LOW_LIMIT_SOC0 200
#define UI_LOW_LIMIT_VTH0 34500
#define UI_LOW_LIMIT_SOC1 200
#define UI_LOW_LIMIT_VTH1 34500
#define UI_LOW_LIMIT_SOC2 200
#define UI_LOW_LIMIT_VTH2 34500
#define UI_LOW_LIMIT_SOC3 200
#define UI_LOW_LIMIT_VTH3 34500
#define UI_LOW_LIMIT_SOC4 200
#define UI_LOW_LIMIT_VTH4 34500
#define UI_LOW_LIMIT_TIME 99999
#define MOVING_BATTEMP_EN 1
#define MOVING_BATTEMP_THR 20
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_battery_table.h
+4203
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drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_clkmgr.h
+11
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@@ -0,0 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_CLKMGR_H
#define _MT_CLKMGR_H
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_cpufreq_api.h
+94
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
enum cci_tbl_use_id {
BY_PROC_FS,
BY_AP,
BY_SSPM,
NUM_USE_ID
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cpu_freq(int cpu, int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void mt_cpufreq_ctrl_cci_volt(unsigned int volt);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
extern unsigned int mt_cpufreq_find_Vboot_idx(unsigned int cluster_id);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_cci_freq_idx(void);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
/* CCI */
extern void mt_cpufreq_update_cci_map_tbl(unsigned int idx_1,
unsigned int idx_2, unsigned char result, unsigned int mode,
enum cci_tbl_use_id use_id);
extern void mt_cpufreq_update_cci_mode(unsigned int mode,
enum cci_tbl_use_id use_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_eem_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_EEM_API_H__
#define __MT_EEM_API_H__
/* DRCC */
extern void drcc_fail_composite(void);
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_mdpm_api.h
+30
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_MDPM_API_H_
#define _MTK_MDPM_API_H_
#include <mach/mtk_pmic.h>
#include <mach/mtk_pbm.h>
enum power_category {
MAX_POWER = 0,
AVG_POWER,
POWER_CATEGORY_NUM
};
enum pbm_kicker {
KR_DLPT, /* 0 */
KR_MD1, /* 1 */
KR_MD3, /* 2 */
KR_CPU, /* 3 */
KR_GPU, /* 4 */
KR_FLASH /* 5 */
};
extern void init_md_section_level(enum pbm_kicker kicker);
extern int get_md1_power(unsigned int power_category, bool need_update);
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_pbm.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PBM_
#define _MT_PBM_
/* #include <cust_pmic.h> */
#include <mach/mtk_pmic.h>
#include <mach/mtk_mdpm_api.h>
#ifdef DISABLE_DLPT_FEATURE
#define DISABLE_PBM_FEATURE
#endif
extern void kicker_pbm_by_dlpt(unsigned int i_max);
extern void kicker_pbm_by_md(enum pbm_kicker kicker, bool status);
extern void kicker_pbm_by_cpu(unsigned int loading, int core, int voltage);
extern void kicker_pbm_by_gpu(bool status, unsigned int loading, int voltage);
extern void kicker_pbm_by_flash(bool status);
#ifndef DISABLE_PBM_FEATURE
extern int g_dlpt_stop;
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_pmic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _CUST_PMIC_H_
#define _CUST_PMIC_H_
/*#define PMIC_VDVFS_CUST_ENABLE*/
#define LOW_POWER_LIMIT_LEVEL_1 15
#define PT_DLPT_BRINGUP 0
#if defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP
/* Define for disable low battery protect feature,
* default no define for enable low battery protect.
*/
#define DISABLE_LOW_BATTERY_PROTECT
/*Define for disable battery OC protect*/
#define DISABLE_BATTERY_OC_PROTECT
/*Define for disable battery 15% protect*/
#define DISABLE_BATTERY_PERCENT_PROTECT
/*Define for DLPT*/
#define DISABLE_DLPT_FEATURE
#endif /* defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP */
#define POWER_UVLO_VOLT_LEVEL 2600
#define IMAX_MAX_VALUE 5500
#define POWER_INT0_VOLT 3400
#define POWER_INT1_VOLT 3250
#define POWER_INT2_VOLT 3100
#define POWER_INT0_VOLT_EXT 3700
#define POWER_INT1_VOLT_EXT 3550
#define POWER_INT2_VOLT_EXT 1000
#define POWER_BAT_OC_CURRENT_H 4670
#define POWER_BAT_OC_CURRENT_L 5500
#define POWER_BAT_OC_CURRENT_H_RE 4670
#define POWER_BAT_OC_CURRENT_L_RE 5500
#define DLPT_POWER_OFF_EN
#define POWEROFF_BAT_CURRENT 3000
#define DLPT_POWER_OFF_THD 100
#define DLPT_VOLT_MIN 3100
#define BATTERY_MODULE_INIT
/* ADC Channel Number, not uesed and removed */
extern const char *pmic_auxadc_channel_name[];
/* Legacy pmic auxadc interface */
enum {
AUXADC_LIST_BATADC,
AUXADC_LIST_START = AUXADC_LIST_BATADC,
AUXADC_LIST_VCDT,
AUXADC_LIST_BATTEMP,
AUXADC_LIST_VBIF,
AUXADC_LIST_CHIP_TEMP,
AUXADC_LIST_DCXO,
AUXADC_LIST_ACCDET,
AUXADC_LIST_TSX,
AUXADC_LIST_HPOFS_CAL,
AUXADC_LIST_VCORE_TEMP,
AUXADC_LIST_VPROC_TEMP,
AUXADC_LIST_VGPU_TEMP,
AUXADC_LIST_DCXO_VOLT,
AUXADC_LIST_END = AUXADC_LIST_DCXO_VOLT,
AUXADC_LIST_ISENSE,
};
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_dump_regs(char *buf);
extern int pmic_get_auxadc_channel_max(void);
extern int mt_get_auxadc_value(u8 channel);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
#endif /* _CUST_PMIC_H_ */
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_pmic_ipi.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PMIC_IPI_H_
#define _MT_PMIC_IPI_H_
void pmic_ipi_write_test(void);
#ifdef CONFIG_MTK_EXTBUCK
enum { /* must compatible with sspm EXTBUCK ID */
EXTBUCK_ID_GPU,
EXTBUCK_ID_PROC2,
EXTBUCK_ID_PROC1,
};
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en);
#else
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en)
{
return -1;
}
#endif /* CONFIG_MTK_EXTBUCK */
unsigned int pmic_ipi_read_interface(unsigned int RegNum,
unsigned int *val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_ipi_config_interface(unsigned int RegNum,
unsigned int val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_regulator_profiling(unsigned char type);
unsigned int sub_pmic_ipi_interface(unsigned int type, unsigned int ctrl);
unsigned int mt6311_ipi_set_mode(unsigned char mode);
#endif /* _MT_PMIC_IPI_H_*/
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_pmic_wrap.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PMIC_WRAP_H__
#define __MT_PMIC_WRAP_H__
/* #include <mach/typedefs.h> */
/* #include <linux/smp.h> */
#include <linux/types.h>
#include <linux/device.h>
#include <mach/upmu_hw.h>
struct mt_pmic_wrap_driver {
struct device_driver driver;
s32 (*wacs2_hal)(u32 write, u32 adr, u32 wdata, u32 *rdata);
s32 (*show_hal)(char *buf);
s32 (*store_hal)(const char *buf, size_t count);
s32 (*suspend)(void);
void (*resume)(void);
};
#define PWRAP_READ 0
#define PWRAP_WRITE 1
/* ------external API for pmic_wrap user------------------------ */
s32 pwrap_read(u32 adr, u32 *rdata);
s32 pwrap_write(u32 adr, u32 wdata);
s32 pwrap_wacs2(u32 write, u32 adr, u32 wdata, u32 *rdata);
/*_____________ROME only_____________________________________________*/
/********************************************************************/
#define PWRAP_TRACE
#ifdef CONFIG_FPGA_EARLY_PORTING
#define tracepwrap(addr, wdata)
#else /*--!CONFIG_FPGA_EARLY_PORTING --*/
extern unsigned int gPWRAPHCK;
extern unsigned int gPWRAPDBGADDR;
#define PWRAP_HCK_LEVEL 4
#define tracepwrap(addr, wdata) do { \
if (gPWRAPHCK >= PWRAP_HCK_LEVEL) \
if (addr == gPWRAPDBGADDR) { \
unsigned int rdata; \
pwrap_read(addr, &rdata); \
pr_notice("addr = 0x%x, wdata = 0x%x, rdata = 0x%x\n", \
addr, wdata, rdata); \
WARN_ON(1); \
} \
} while (0)
#endif /*--End of CONFIG_FPGA_EARLY_PORTING --*/
/********************************************************************/
/********************************************************************/
/* return value : EINT_STA: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/********************************************************************/
u32 pmic_wrap_eint_status(void);
/********************************************************************/
/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/* para: offset is shift of clear bit which needs to clear */
/********************************************************************/
void pmic_wrap_eint_clr(int offset);
/*--------------------------------------------------------------------*/
u32 mt_pmic_wrap_eint_status(void);
void mt_pmic_wrap_eint_clr(int offset);
s32 pwrap_init(void);
struct mt_pmic_wrap_driver *get_mt_pmic_wrap_drv(void);
/* MTS debug only */
void pwrap_dump_all_register(void);
/* dump ap/pmic register and recovery WACS2 */
void pwrap_dump_and_recovery(void);
#endif /* __MT_PMIC_WRAP_H__ */
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/mtk_pwm_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_PWM_HAL_H__
#define __MT_PWM_HAL_H__
#include <linux/types.h>
#include <mt-plat/sync_write.h>
/**********************************
* Global enum data
*/
/******************* Register Manipulations*****************/
#define INREG32(reg) __raw_readl((void *)reg)
#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
enum PWN_NO {
PWM_MIN,
PWM1 = PWM_MIN,
PWM2,
PWM3,
PWM4,
PWM5,
PWM6,
PWM_NUM,
PWM_MAX = PWM_NUM
};
enum TEST_SEL_BIT {
TEST_SEL_FALSE,
TEST_SEL_TRUE
};
enum PWM_CON_MODE_BIT {
PERIOD,
RAND
};
enum PWM_CON_SRCSEL_BIT {
PWM_FIFO,
MEMORY
};
enum PWM_CON_IDLE_BIT {
IDLE_FALSE,
IDLE_TRUE,
IDLE_MAX
};
enum PWM_CON_GUARD_BIT {
GUARD_FALSE,
GUARD_TRUE,
GUARD_MAX
};
enum OLD_MODE_BIT {
OLDMODE_DISABLE,
OLDMODE_ENABLE
};
enum PWM_BUF_VALID_BIT {
BUF0_VALID,
BUF0_EN_VALID,
BUF1_VALID,
BUF1_EN_VALID,
BUF_EN_MAX
};
enum CLOCK_SRC {
CLK_BLOCK,
CLK_BLOCK_BY_1625_OR_32K
};
enum PWM_CLK_DIV {
CLK_DIV_MIN,
CLK_DIV1 = CLK_DIV_MIN,
CLK_DIV2,
CLK_DIV4,
CLK_DIV8,
CLK_DIV16,
CLK_DIV32,
CLK_DIV64,
CLK_DIV128,
CLK_DIV_MAX
};
enum PWM_INT_ENABLE_BITS {
PWM1_INT_FINISH_EN,
PWM1_INT_UNDERFLOW_EN,
PWM2_INT_FINISH_EN,
PWM2_INT_UNDERFLOW_EN,
PWM3_INT_FINISH_EN,
PWM3_INT_UNDERFLOW_EN,
PWM4_INT_FINISH_EN,
PWM4_INT_UNDERFLOW_EN,
PWM5_INT_FINISH_EN,
PWM5_INT_UNDERFLOW_EN,
PWM6_INT_FINISH_EN,
PWM6_INT_UNDERFLOW_EN,
PWM_INT_ENABLE_BITS_MAX,
};
enum PWM_INT_STATUS_BITS {
PWM1_INT_FINISH_ST,
PWM1_INT_UNDERFLOW_ST,
PWM2_INT_FINISH_ST,
PWM2_INT_UNDERFLOW_ST,
PWM3_INT_FINISH_ST,
PWM3_INT_UNDERFLOW_ST,
PWM4_INT_FINISH_ST,
PWM4_INT_UNDERFLOW_ST,
PWM5_INT_FINISH_ST,
PWM5_INT_UNDERFLOW_ST,
PWM6_INT_FINISH_ST,
PWM6_INT_UNDERFLOW_ST,
PWM_INT_STATUS_BITS_MAX,
};
enum PWM_INT_ACK_BITS {
PWM1_INT_FINISH_ACK,
PWM1_INT_UNDERFLOW_ACK,
PWM2_INT_FINISH_ACK,
PWM2_INT_UNDERFLOW_ACK,
PWM3_INT_FINISH_ACK,
PWM3_INT_UNDERFLOW_ACK,
PWM4_INT_FINISH_ACK,
PWM4_INT_UNDERFLOW_ACK,
PWM5_INT_FINISH_ACK,
PWM5_INT_UNDERFLOW_ACK,
PWM6_INT_FINISH_ACK,
PWM6_INT_UNDERFLOW_ACK,
PWM_INT_ACK_BITS_MAX,
};
enum PWM_CLOCK_SRC_ENUM {
PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_32K,
PWM_CLK_NEW_MODE_BLOCK,
PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
PWM_CLK_SRC_NUM,
PWM_CLK_SRC_INVALID,
};
enum PWM_MODE_ENUM {
PWM_MODE_MIN,
PWM_MODE_OLD = PWM_MODE_MIN,
PWM_MODE_FIFO,
PWM_MODE_MEMORY,
PWM_MODE_RANDOM,
PWM_MODE_DELAY,
PWM_MODE_INVALID,
};
enum INFRA_CLK_SRC_CTRL {
CLK_32K = 0x00,
CLK_26M = 0x01,
CLK_78M = 0x2,
CLK_SEL_TOPCKGEN = 0x3,
};
#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
void mt_set_pwm_3dlcm_enable_hal(u8 enable);
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
void mt_pwm_26M_clk_enable_hal(u32 enable);
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/pseudo_m4u.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __PSEUDO_M4U_PORT_H__
#define __PSEUDO_M4U_PORT_H__
#include <linux/ioctl.h>
#include <linux/fs.h>
#include <dt-bindings/memory/mt6768-larb-port.h>
#include <linux/list.h>
#include <linux/iova.h>
#include <linux/iommu.h>
#if (defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
defined(CONFIG_MICROTRUST_TEE_SUPPORT)) && \
defined(CONFIG_MTK_TEE_GP_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#endif
#endif
#if defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#endif
#endif
#define M4U_PAGE_SIZE 0x1000
#define M4U_DEVNAME "m4u"
#define NORMAL_M4U_NUMBER 1
#define TOTAL_M4U_NUM 1
#define M4U_REG_SIZE 0x5e0
#ifndef SMI_LARB_NR
#define SMI_LARB_NR MTK_IOMMU_LARB_NR
#endif
#define M4U_PAGE_MASK 0xfff
/* public flags */
/* engine access this buffer in sequncial way. */
#define M4U_FLAGS_SEQ_ACCESS (1<<0)
/* fix allocation, we will use mva user specified. */
#define M4U_FLAGS_FIX_MVA (1<<1)
/* the mva will share in SWd */
#define M4U_FLAGS_SEC_SHAREABLE (1<<2)
/* the allocator will search free mva from user specified. */
#define M4U_FLAGS_START_FROM (1<<3)
#define M4U_FLAGS_SG_READY (1<<4)
/* port related: virtuality, security, distance */
struct M4U_PORT_STRUCT {
int ePortID;
unsigned int Virtuality;
unsigned int Security;
unsigned int domain; /*domain : 0 1 2 3*/
unsigned int Distance;
unsigned int Direction; /* 0:- 1:+*/
};
/* module related: alloc/dealloc MVA buffer */
struct M4U_MOUDLE_STRUCT {
int port;
unsigned long BufAddr;
unsigned int BufSize;
unsigned int prot;
unsigned int MVAStart;
unsigned int MVAEnd;
unsigned int flags;
};
struct mva_info_t {
struct list_head link;
unsigned long bufAddr;
unsigned int mvaStart;
unsigned int size;
int eModuleId;
unsigned int flags;
int security;
int cache_coherent;
unsigned int mapped_kernel_va_for_debug;
};
struct m4u_buf_info_t {
struct list_head link;
unsigned long va;
unsigned int mva;
unsigned int size;
int port;
unsigned int prot;
unsigned int flags;
struct sg_table *sg_table;
unsigned int mva_align;
unsigned int size_align;
int seq_id;
unsigned long mapped_kernel_va_for_debug;
};
struct m4u_client_t {
/* mutex to protect mvaList */
/* should get this mutex whenever add/delete/interate mvaList */
struct mutex dataMutex;
pid_t open_pid;
pid_t open_tgid;
struct list_head mvaList;
};
struct port_mva_info_t {
int emoduleid;
unsigned long va;
unsigned int buf_size;
int security;
int cache_coherent;
unsigned int flags;
unsigned int iova_start;
unsigned int iova_end;
unsigned int mva;
};
struct m4u_device {
/*struct miscdevice dev;*/
struct proc_dir_entry *m4u_dev_proc_entry;
};
/* we use this for trace the mva<-->sg_table relation ship */
struct mva_sglist {
struct list_head list;
unsigned int mva;
struct iova *iova;
struct sg_table *table;
};
struct pseudo_device {
struct device *dev; /* record the device for config mmu use. */
int larbid; /* the larb id of this device*/
bool mmuen; /* whether this larb have been configed. */
};
struct m4u_port_array {
#define M4U_PORT_ATTR_EN (1<<0)
#define M4U_PORT_ATTR_VIRTUAL (1<<1)
#define M4U_PORT_ATTR_SEC (1<<2)
unsigned char ports[M4U_PORT_NR];
};
extern unsigned long max_pfn;
extern unsigned char *pMlock_cnt;
extern unsigned int mlock_cnt_size;
extern unsigned long pagetable_pa;
struct sg_table *m4u_create_sgtable(unsigned long va, unsigned int size);
int m4u_dealloc_mva_sg(int eModuleID,
struct sg_table *sg_table,
const unsigned int BufSize,
const unsigned int MVA);
int m4u_alloc_mva_sg(struct port_mva_info_t *port_info,
struct sg_table *sg_table);
int m4u_mva_map_kernel(unsigned int mva, unsigned int size,
unsigned long *map_va, unsigned int *map_size);
int m4u_mva_unmap_kernel(unsigned int mva, unsigned int size,
unsigned long va);
#ifndef IOVA_PFN
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
#endif
int m4u_config_port(struct M4U_PORT_STRUCT *pM4uPort);
int pseudo_config_port_tee(int kernelport);
static inline bool m4u_enable_4G(void)
{
return (max_pfn > (0xffffffffUL >> PAGE_SHIFT));
}
struct iova *__alloc_iova(struct iova_domain *iovad, size_t size,
dma_addr_t dma_limit);
void __free_iova(struct iova_domain *iovad, struct iova *iova);
void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr);
/* IOCTL commnad */
#define MTK_M4U_MAGICNO 'g'
#define MTK_M4U_T_POWER_ON _IOW(MTK_M4U_MAGICNO, 0, int)
#define MTK_M4U_T_POWER_OFF _IOW(MTK_M4U_MAGICNO, 1, int)
#define MTK_M4U_T_DUMP_REG _IOW(MTK_M4U_MAGICNO, 2, int)
#define MTK_M4U_T_DUMP_INFO _IOW(MTK_M4U_MAGICNO, 3, int)
#define MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define MTK_M4U_T_INSERT_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 6, int)
#define MTK_M4U_T_INVALID_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 7, int)
#define MTK_M4U_T_INVALID_TLB_ALL _IOW(MTK_M4U_MAGICNO, 8, int)
#define MTK_M4U_T_MANUAL_INSERT_ENTRY _IOW(MTK_M4U_MAGICNO, 9, int)
#define MTK_M4U_T_CACHE_SYNC _IOW(MTK_M4U_MAGICNO, 10, int)
#define MTK_M4U_T_CONFIG_PORT _IOW(MTK_M4U_MAGICNO, 11, int)
#define MTK_M4U_T_CONFIG_ASSERT _IOW(MTK_M4U_MAGICNO, 12, int)
#define MTK_M4U_T_INSERT_WRAP_RANGE _IOW(MTK_M4U_MAGICNO, 13, int)
#define MTK_M4U_T_MONITOR_START _IOW(MTK_M4U_MAGICNO, 14, int)
#define MTK_M4U_T_MONITOR_STOP _IOW(MTK_M4U_MAGICNO, 15, int)
#define MTK_M4U_T_RESET_MVA_RELEASE_TLB _IOW(MTK_M4U_MAGICNO, 16, int)
#define MTK_M4U_T_CONFIG_PORT_ROTATOR _IOW(MTK_M4U_MAGICNO, 17, int)
#define MTK_M4U_T_QUERY_MVA _IOW(MTK_M4U_MAGICNO, 18, int)
#define MTK_M4U_T_M4UDrv_CONSTRUCT _IOW(MTK_M4U_MAGICNO, 19, int)
#define MTK_M4U_T_M4UDrv_DECONSTRUCT _IOW(MTK_M4U_MAGICNO, 20, int)
#define MTK_M4U_T_DUMP_PAGETABLE _IOW(MTK_M4U_MAGICNO, 21, int)
#define MTK_M4U_T_REGISTER_BUFFER _IOW(MTK_M4U_MAGICNO, 22, int)
#define MTK_M4U_T_CACHE_FLUSH_ALL _IOW(MTK_M4U_MAGICNO, 23, int)
#define MTK_M4U_T_CONFIG_PORT_ARRAY _IOW(MTK_M4U_MAGICNO, 26, int)
#define MTK_M4U_T_CONFIG_MAU _IOW(MTK_M4U_MAGICNO, 27, int)
#define MTK_M4U_T_CONFIG_TF _IOW(MTK_M4U_MAGICNO, 28, int)
#define MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#if IS_ENABLED(CONFIG_COMPAT)
struct COMPAT_M4U_MOUDLE_STRUCT {
compat_uint_t port;
compat_ulong_t BufAddr;
compat_uint_t BufSize;
compat_uint_t prot;
compat_uint_t MVAStart;
compat_uint_t MVAEnd;
compat_uint_t flags;
};
#define COMPAT_MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define COMPAT_MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define COMPAT_MTK_M4U_T_CACHE_SYNC _IOW(MTK_M4U_MAGICNO, 10, int)
#define COMPAT_MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#endif
#ifdef M4U_MTEE_SERVICE_ENABLE
extern bool m4u_tee_en;
int smi_reg_restore_sec(void);
int smi_reg_backup_sec(void);
/*int m4u_config_port_array_tee(unsigned char* port_array);*/
int m4u_dump_secpgd(unsigned int port, unsigned int faultmva);
#endif
/* =========== register defination =========== */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define SMI_LARB_NON_SEC_CONx(larb_port) (0x380 + ((larb_port)<<2))
#define F_SMI_NON_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_MMU_EN F_BIT_SET(0)
#define SMI_LARB_SEC_CONx(larb_port) (0xf80 + ((larb_port)<<2))
#define F_SMI_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_SEC_EN(sec) F_BIT_VAL(sec, 1)
#define F_SMI_DOMN(domain) F_VAL(domain, 8, 4)
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/upmu_hw.h
+23825
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drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/upmu_sw.h
+364
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MT_PMIC_UPMU_SW_H_
#define _MT_PMIC_UPMU_SW_H_
#include <mach/upmu_hw.h>
#define AUXADC_SUPPORT_IMM_CURRENT_MODE
#define BATTERY_SW_INIT
#define RBAT_PULL_UP_VOLT_BY_BIF
/* #define INIT_BAT_CUR_FROM_PTIM */
#define FG_RG_INT_EN_CHRDET INT_CHRDET
#define FG_RG_INT_EN_BAT2_H INT_BAT2_H
#define FG_RG_INT_EN_BAT2_L INT_BAT2_L
#define FG_RG_INT_EN_BAT_TEMP_H INT_BAT_TEMP_H
#define FG_RG_INT_EN_BAT_TEMP_L INT_BAT_TEMP_L
#define FG_RG_INT_EN_NAG_C_DLTV INT_NAG_C_DLTV
#define FG_BAT0_INT_H_NO INT_FG_BAT0_H
#define FG_BAT0_INT_L_NO INT_FG_BAT0_L
#define FG_BAT_INT_H_NO INT_FG_BAT0_H
#define FG_BAT_INT_L_NO INT_FG_BAT0_L
#define FG_CUR_H_NO INT_FG_CUR_H
#define FG_CUR_L_NO INT_FG_CUR_L
#define FG_ZCV_NO INT_FG_ZCV
#define FG_BAT1_INT_H_NO INT_FG_BAT1_H
#define FG_BAT1_INT_L_NO INT_FG_BAT1_L
#define FG_N_CHARGE_L_NO INT_FG_N_CHARGE_L
#define FG_IAVG_H_NO INT_FG_IAVG_H
#define FG_IAVG_L_NO INT_FG_IAVG_L
#define FG_TIME_NO INT_FG_TIME_H
#define FG_BAT_PLUGOUT_NO INT_BATON_BAT_OUT
/* =============================================================================
* Low battery level define
* =============================================================================
*/
#define LOW_BATTERY_LEVEL enum LOW_BATTERY_LEVEL_TAG
#define LOW_BATTERY_PRIO enum LOW_BATTERY_PRIO_TAG
enum LOW_BATTERY_LEVEL_TAG {
LOW_BATTERY_LEVEL_0 = 0,
LOW_BATTERY_LEVEL_1 = 1,
LOW_BATTERY_LEVEL_2 = 2
};
enum LOW_BATTERY_PRIO_TAG {
LOW_BATTERY_PRIO_CPU_B = 0,
LOW_BATTERY_PRIO_CPU_L = 1,
LOW_BATTERY_PRIO_GPU = 2,
LOW_BATTERY_PRIO_MD = 3,
LOW_BATTERY_PRIO_MD5 = 4,
LOW_BATTERY_PRIO_FLASHLIGHT = 5,
LOW_BATTERY_PRIO_VIDEO = 6,
LOW_BATTERY_PRIO_WIFI = 7,
LOW_BATTERY_PRIO_BACKLIGHT = 8
};
extern void (*low_battery_callback)(LOW_BATTERY_LEVEL tag);
extern void register_low_battery_notify(
void (*low_battery_callback)(LOW_BATTERY_LEVEL tag),
LOW_BATTERY_PRIO prio_val);
/* =============================================================================
* Battery OC level define
* =============================================================================
*/
#define BATTERY_OC_LEVEL enum BATTERY_OC_LEVEL_TAG
#define BATTERY_OC_PRIO enum BATTERY_OC_PRIO_TAG
enum BATTERY_OC_LEVEL_TAG {
BATTERY_OC_LEVEL_0 = 0,
BATTERY_OC_LEVEL_1 = 1
};
enum BATTERY_OC_PRIO_TAG {
BATTERY_OC_PRIO_CPU_B = 0,
BATTERY_OC_PRIO_CPU_L = 1,
BATTERY_OC_PRIO_GPU = 2,
BATTERY_OC_PRIO_MD = 3,
BATTERY_OC_PRIO_MD5 = 4,
BATTERY_OC_PRIO_FLASHLIGHT = 5
};
extern void (*battery_oc_callback)(BATTERY_OC_LEVEL tag);
extern void register_battery_oc_notify(
void (*battery_oc_callback)(BATTERY_OC_LEVEL tag),
BATTERY_OC_PRIO prio_val);
/* =============================================================================
* Battery percent define
* =============================================================================
*/
#define BATTERY_PERCENT_LEVEL enum BATTERY_PERCENT_LEVEL_TAG
#define BATTERY_PERCENT_PRIO enum BATTERY_PERCENT_PRIO_TAG
enum BATTERY_PERCENT_LEVEL_TAG {
BATTERY_PERCENT_LEVEL_0 = 0,
BATTERY_PERCENT_LEVEL_1 = 1
};
enum BATTERY_PERCENT_PRIO_TAG {
BATTERY_PERCENT_PRIO_CPU_B = 0,
BATTERY_PERCENT_PRIO_CPU_L = 1,
BATTERY_PERCENT_PRIO_GPU = 2,
BATTERY_PERCENT_PRIO_MD = 3,
BATTERY_PERCENT_PRIO_MD5 = 4,
BATTERY_PERCENT_PRIO_FLASHLIGHT = 5,
BATTERY_PERCENT_PRIO_VIDEO = 6,
BATTERY_PERCENT_PRIO_WIFI = 7,
BATTERY_PERCENT_PRIO_BACKLIGHT = 8
};
extern void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL tag);
extern void
register_battery_percent_notify(
void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL tag),
BATTERY_PERCENT_PRIO prio_val);
/*=============================================================================
* DLPT define
*=============================================================================
*/
#define DLPT_PRIO enum DLPT_PRIO_TAG
enum DLPT_PRIO_TAG {
DLPT_PRIO_PBM = 0,
DLPT_PRIO_CPU_B = 1,
DLPT_PRIO_CPU_L = 2,
DLPT_PRIO_GPU = 3,
DLPT_PRIO_MD = 4,
DLPT_PRIO_MD5 = 5,
DLPT_PRIO_FLASHLIGHT = 6,
DLPT_PRIO_VIDEO = 7,
DLPT_PRIO_WIFI = 8,
DLPT_PRIO_BACKLIGHT = 9
};
extern void (*dlpt_callback)(unsigned int);
extern void register_dlpt_notify(
void (*dlpt_callback)(unsigned int), DLPT_PRIO prio_val);
extern const PMU_FLAG_TABLE_ENTRY pmu_flags_table[];
extern unsigned short is_battery_remove;
extern unsigned short is_wdt_reboot_pmic;
extern unsigned short is_wdt_reboot_pmic_chk;
/*=============================================================================
* PMIC IRQ ENUM define
*=============================================================================
*/
enum PMIC_IRQ_ENUM {
INT_VPROC11_OC,
SP_BUCK_TOP_START = INT_VPROC11_OC,
INT_VPROC12_OC,
INT_VCORE_OC,
INT_VGPU_OC,
INT_VMODEM_OC,
INT_VDRAM1_OC,
INT_VS1_OC,
INT_VS2_OC,
INT_VPA_OC,
INT_VCORE_PREOC,
NO_USE_0_10,
NO_USE_0_11,
NO_USE_0_12,
NO_USE_0_13,
NO_USE_0_14,
NO_USE_0_15,
INT_VFE28_OC,
SP_LDO_TOP_START = INT_VFE28_OC,
INT_VXO22_OC,
INT_VRF18_OC,
INT_VRF12_OC,
INT_VEFUSE_OC,
INT_VCN33_OC,
INT_VCN28_OC,
INT_VCN18_OC,
INT_VCAMA1_OC,
INT_VCAMA2_OC,
INT_VCAMD_OC,
INT_VCAMIO_OC,
INT_VLDO28_OC,
INT_VA12_OC,
INT_VAUX18_OC,
INT_VAUD28_OC,
INT_VIO28_OC,
INT_VIO18_OC,
INT_VSRAM_PROC11_OC,
INT_VSRAM_PROC12_OC,
INT_VSRAM_OTHERS_OC,
INT_VSRAM_GPU_OC,
INT_VDRAM2_OC,
INT_VMC_OC,
INT_VMCH_OC,
INT_VEMC_OC,
INT_VSIM1_OC,
INT_VSIM2_OC,
INT_VIBR_OC,
INT_VUSB_OC,
INT_VBIF28_OC,
NO_USE_2_15,
INT_PWRKEY,
SP_PSC_TOP_START = INT_PWRKEY,
INT_HOMEKEY,
INT_PWRKEY_R,
INT_HOMEKEY_R,
INT_NI_LBAT_INT,
INT_CHRDET,
INT_CHRDET_EDGE,
INT_VCDT_HV_DET,
NO_USE_3_8,
NO_USE_3_9,
NO_USE_3_10,
NO_USE_3_11,
NO_USE_3_12,
NO_USE_3_13,
NO_USE_3_14,
NO_USE_3_15,
INT_RTC,
SP_SCK_TOP_START = INT_RTC,
NO_USE_4_1,
NO_USE_4_2,
NO_USE_4_3,
NO_USE_4_4,
NO_USE_4_5,
NO_USE_4_6,
NO_USE_4_7,
NO_USE_4_8,
NO_USE_4_9,
NO_USE_4_10,
NO_USE_4_11,
NO_USE_4_12,
NO_USE_4_13,
NO_USE_4_14,
NO_USE_4_15,
INT_FG_BAT0_H,
SP_BM_TOP_START = INT_FG_BAT0_H,
INT_FG_BAT0_L,
INT_FG_CUR_H,
INT_FG_CUR_L,
INT_FG_ZCV,
INT_FG_BAT1_H,
INT_FG_BAT1_L,
INT_FG_N_CHARGE_L,
INT_FG_IAVG_H,
INT_FG_IAVG_L,
INT_FG_TIME_H,
INT_FG_DISCHARGE,
INT_FG_CHARGE,
NO_USE_5_13,
NO_USE_5_14,
NO_USE_5_15,
INT_BATON_LV,
INT_BATON_HT,
INT_BATON_BAT_IN,
INT_BATON_BAT_OUT,
INT_BIF,
NO_USE_6_5,
NO_USE_6_6,
NO_USE_6_7,
NO_USE_6_8,
NO_USE_6_9,
NO_USE_6_10,
NO_USE_6_11,
NO_USE_6_12,
NO_USE_6_13,
NO_USE_6_14,
NO_USE_6_15,
INT_BAT_H,
SP_HK_TOP_START = INT_BAT_H,
INT_BAT_L,
INT_BAT2_H,
INT_BAT2_L,
INT_BAT_TEMP_H,
INT_BAT_TEMP_L,
INT_AUXADC_IMP,
INT_NAG_C_DLTV,
NO_USE_7_8,
NO_USE_7_9,
NO_USE_7_10,
NO_USE_7_11,
NO_USE_7_12,
NO_USE_7_13,
NO_USE_7_14,
NO_USE_7_15,
INT_AUDIO,
SP_AUD_TOP_START = INT_AUDIO,
NO_USE_8_1,
NO_USE_8_2,
NO_USE_8_3,
NO_USE_8_4,
INT_ACCDET,
INT_ACCDET_EINT0,
INT_ACCDET_EINT1,
NO_USE_8_8,
NO_USE_8_9,
NO_USE_8_10,
NO_USE_8_11,
NO_USE_8_12,
NO_USE_8_13,
NO_USE_8_14,
NO_USE_8_15,
INT_SPI_CMD_ALERT,
SP_MISC_TOP_START = INT_SPI_CMD_ALERT,
NO_USE_9_1,
NO_USE_9_2,
NO_USE_9_3,
NO_USE_9_4,
NO_USE_9_5,
NO_USE_9_6,
NO_USE_9_7,
NO_USE_9_8,
NO_USE_9_9,
NO_USE_9_10,
NO_USE_9_11,
NO_USE_9_12,
NO_USE_9_13,
NO_USE_9_14,
NO_USE_9_15,
INT_ENUM_MAX,
};
/*=============================================================================
* PMIC auxadc define
*=============================================================================
*/
extern signed int g_I_SENSE_offset;
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
extern void mt_power_off(void);
/*=============================================================================
* PMIC fg define
*=============================================================================
*/
extern unsigned int bat_get_ui_percentage(void);
extern signed int fgauge_read_v_by_d(int d_val);
extern signed int fgauge_read_r_bat_by_v(signed int voltage);
extern signed int fgauge_read_IM_current(void *data);
extern void kpd_pwrkey_pmic_handler(unsigned long pressed);
extern void kpd_pmic_rstkey_handler(unsigned long pressed);
extern int is_mt6311_sw_ready(void);
extern int is_mt6311_exist(void);
extern int get_mt6311_i2c_ch_num(void);
/*extern bool crystal_exist_status(void);*/
#if defined CONFIG_MTK_LEGACY
extern void pmu_drv_tool_customization_init(void);
#endif
extern int batt_init_cust_data(void);
extern void PMIC_INIT_SETTING_V1(void);
extern int do_ptim_ex(bool isSuspend, unsigned int *bat, signed int *cur);
#endif /* _MT_PMIC_UPMU_SW_H_ */
drivers/misc/mediatek/include/mt-plat/mt6768/include/mach/wd_api.h
+11
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#if defined(CONFIG_MTK_WATCHDOG_COMMON)
/* use common wd api */
#include <mt-plat/mtk_wd_api.h>
#else
#error "watchdog: common wd_api.h shall be used."
#endif
drivers/misc/mediatek/include/mt-plat/mt6768/include/trustzone/m4u/tz_m4u.h
+162
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __TZ_M4U_H__
#define __TZ_M4U_H__
/* #include "drStd.h" */
#ifdef CONFIG_MTK_PSEUDO_M4U
#include "mach/mt_iommu.h"
#else
#include "m4u_port.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/* #define __M4U_SECURE_SYSTRACE_ENABLE__ */
#define M4U_NONSEC_MVA_START (0x40000000)
#define CMD_M4U_MAGIC (0x77880000)
enum m4u_cmd {
CMD_M4U_ADD = CMD_M4U_MAGIC,
CMD_M4U_CFG_PORT,
CMD_M4U_MAP_NONSEC_BUFFER,
CMD_M4U_SEC_INIT,
CMD_M4U_ALLOC_MVA,
CMD_M4U_DEALLOC_MVA,
CMD_M4U_REG_BACKUP,
CMD_M4U_REG_RESTORE,
CMD_M4U_PRINT_PORT,
CMD_M4U_DUMP_SEC_PGTABLE,
CMD_M4UTL_INIT,
CMD_M4U_OPEN_SESSION,
CMD_M4U_CLOSE_SESSION,
CMD_M4U_CFG_PORT_ARRAY,
CMD_M4U_SYSTRACE_MAP,
CMD_M4U_SYSTRACE_UNMAP,
CMD_M4U_SYSTRACE_TRANSACT,
CMD_M4U_LARB_BACKUP,
CMD_M4U_LARB_RESTORE,
CMD_M4U_UNMAP_NONSEC_BUFFER,
CMD_M4U_GET_RESERVED_MEMORY,
CMD_M4U_GET_SEC_MEM,
CMD_M4U_NUM,
};
#define M4U_RET_OK 0
#define M4U_RET_UNKNOWN_CMD -1
#define M4U_RET_NO_PERM -2
#define EXIT_ERROR ((uint32_t)(-1))
struct m4u_add_param {
int a;
int b;
int result;
};
#define M4U_SIN_NAME_LEN 12
struct m4u_session_param {
int sid;
char name[M4U_SIN_NAME_LEN];
};
struct m4u_cfg_port_param {
int port;
int virt;
int sec;
int distance;
int direction;
};
struct m4u_buf_param {
int port;
unsigned int mva;
unsigned int size;
unsigned long long pa;
};
#define TZ_M4U_MAX_MEM_CHUNK_NR 2
struct m4u_sec_mem_param {
uint64_t pa[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t sz[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t mva[TZ_M4U_MAX_MEM_CHUNK_NR];
unsigned int nr;
};
struct m4u_init_param {
unsigned long long nonsec_pt_pa;
int l2_en;
unsigned int sec_pt_pa;
struct m4u_sec_mem_param sec_mem;
unsigned int chunk_nr;
int reinit;
};
struct m4u_systrace_param {
unsigned long pa;
unsigned long size;
};
struct m4u_cfg_port_array_param {
unsigned char m4u_port_array[M4U_PORT_NR];
};
struct m4u_larb_restore_param {
unsigned int larb_idx;
};
struct m4u_reserved_memory_param {
unsigned int reserved_mem_start;
unsigned int reserved_mem_size;
};
struct m4u_msg {
unsigned int cmd;
unsigned int retval_for_tbase; /* it must be 0 */
unsigned int rsp;
union {
struct m4u_session_param session_param;
struct m4u_cfg_port_param port_param;
struct m4u_buf_param buf_param;
struct m4u_init_param init_param;
struct m4u_cfg_port_array_param port_array_param;
#ifdef __M4U_SECURE_SYSTRACE_ENABLE__
struct m4u_systrace_param systrace_param;
#endif
struct m4u_larb_restore_param larb_param;
struct m4u_reserved_memory_param reserved_memory_param;
struct m4u_sec_mem_param sec_mem_param;
};
};
/* logs */
#define M4U_U64_FMT "0x%08x_%08x"
#define M4U_U64_PR(u64) ((uint32_t)((u64) >> 32), (uint32_t)(u64))
/* should be removed before MP */
#define TZ_M4U_DBG
#if defined(__cplusplus)
}
#endif
#endif /* TLFOO_H_ */
drivers/misc/mediatek/include/mt-plat/mt6779/include/mach/mtk_cpufreq_api.h
+96
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2020 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
enum cci_tbl_use_id {
BY_PROC_FS,
BY_AP,
BY_SSPM,
NUM_USE_ID
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void mt_cpufreq_ctrl_cci_volt(unsigned int volt);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
extern unsigned int mt_cpufreq_find_Vboot_idx(unsigned int cluster_id);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_cci_freq_idx(void);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
/* CCI */
extern void mt_cpufreq_update_cci_map_tbl(unsigned int idx_1,
unsigned int idx_2, unsigned char result, unsigned int mode,
enum cci_tbl_use_id use_id);
extern void mt_cpufreq_update_cci_mode(unsigned int mode,
enum cci_tbl_use_id use_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/mt_iommu.h
+13
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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_IOMMU_H__
#define __MT_IOMMU_H__
#include <dt-bindings/memory/mt6781-larb-port.h>
#include "mtk_iommu_ext.h"
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/mt_iommu_plat.h
+794
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@@ -0,0 +1,794 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PLAT_H__
#define __MT_IOMMU_PLAT_H__
#define MTK_IOMMU_PAGE_TABLE_SHARE (1)
//#define MTK_APU_TFRP_SUPPORT no need for mt6781
#define MTK_IOMMU_SIZE_NOT_ALIGNMENT
#ifndef CONFIG_FPGA_EARLY_PORTING
#define IOMMU_POWER_CLK_SUPPORT
#define MTK_IOMMU_BANK_IRQ_SUPPORT
#ifdef IOMMU_POWER_CLK_SUPPORT
#define MTK_IOMMU_LOW_POWER_SUPPORT
#define MTK_WARN_PSEDUO_FIND_SG
#include "clk-mt6781-pg.h"
enum subsys_id iommu_mtcmos_subsys[MTK_IOMMU_M4U_COUNT] = {
SYS_DIS,
#ifdef CONFIG_MTK_APUSYS_SUPPORT
SYS_VPU
#endif
};
#endif
#endif
#if (defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
defined(CONFIG_MICROTRUST_TEE_SUPPORT)) && \
defined(CONFIG_MTK_TEE_GP_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) && \
!defined(CONFIG_MTK_SVP_ON_MTEE_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#elif defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#endif
#elif defined(MTK_IOMMU_BANK_IRQ_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#endif
#define MMU0_SET_ORDER 7
#define MMU1_SET_ORDER 7
#define MMU_SET_ORDER(mmu) ((mmu == 0) ? MMU0_SET_ORDER : MMU1_SET_ORDER)
#define MTK_IOMMU_SET_NR(mmu) (1<<MMU_SET_ORDER(mmu))
#define MMU_SET_LSB_OFFSET 15
#define MMU_SET_MSB_OFFSET(mmu) (MMU_SET_LSB_OFFSET+MMU_SET_ORDER(mmu)-1)
#define MMU_PFH_VA_TO_SET(mmu, va) \
F_MSK_SHIFT(va, MMU_SET_MSB_OFFSET(mmu), MMU_SET_LSB_OFFSET)
#ifdef CONFIG_FPGA_EARLY_PORTING
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {64};
#else
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {
64,
#ifdef CONFIG_MTK_APUSYS_SUPPORT
64,
#endif
};
#endif
char *smi_clk_name[MTK_IOMMU_LARB_NR] = {
"iommu_larb0", "iommu_larb1", "iommu_larb2",
"iommu_null_larb3", "iommu_larb4", "iommu_null_larb5",
"iommu_null_larb6", "iommu_larb7", "iommu_null_larb8",
"iommu_larb9", "iommu_null_larb10", "iommu_larb11",
"iommu_null_larb12", "iommu_larb13", "iommu_larb14",
"iommu_null_larb15", "iommu_larb16", "iommu_larb17",
"iommu_larb18", "iommu_larb19", "iommu_larb20",
"iommu_fake_larb21", "iommu_fake_larb22", "iommu_fake_larb23"
};
unsigned int port_size_not_aligned[] = {
M4U_PORT_L21_APU_FAKE_CODE
};
const char *smi_larb_id = "mediatek,larb-id";
#ifdef CONFIG_FPGA_EARLY_PORTING
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u",
};
#else
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u0",
#ifdef CONFIG_MTK_APUSYS_SUPPORT
"mediatek,sec_m4u1",
#endif
};
char *iommu_bank_compatible[MTK_IOMMU_M4U_COUNT][MTK_IOMMU_BANK_NODE_COUNT] = {
{"mediatek,bank1_m4u0", "mediatek,bank2_m4u0", "mediatek,bank3_m4u0"},
#ifdef CONFIG_MTK_APUSYS_SUPPORT
{"mediatek,bank1_m4u1", "mediatek,bank2_m4u1", "mediatek,bank3_m4u1"},
#endif
};
#endif
/* ================ register control ================ */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define F_MSK_SHIFT64(regval, msb, lsb) \
((((unsigned long)regval)&F_MSK(msb, lsb))>>lsb)
/* it must be open after atf driver is ready */
#define IOMMU_DESIGN_OF_BANK
/* m4u atf debug parameter */
#define IOMMU_ATF_INDEX_MASK F_MSK(3, 0)
#define IOMMU_ATF_BANK_MASK F_MSK(7, 4)
#define IOMMU_ATF_CMD_MASK F_MSK(16, 8)
#define IOMMU_ATF_SET_COMMAND(m4u, bank, cmd) \
(m4u | (bank << 4) | (cmd << 8))
enum IOMMU_ATF_CMD {
IOMMU_ATF_DUMP_SECURE_REG,
IOMMU_ATF_SECURITY_DEBUG_ENABLE,
IOMMU_ATF_SECURITY_DEBUG_DISABLE,
IOMMU_ATF_BANK_ENABLE_TF,
IOMMU_ATF_BANK_DISABLE_TF,
IOMMU_ATF_BANK_DUMP_INFO,
IOMMU_ATF_BANK_DOMAIN_CONFIG,
IOMMU_ATF_SECURITY_BACKUP,
IOMMU_ATF_SECURITY_RESTORE,
IOMMU_ATF_DUMP_SECURE_PORT_CONFIG,
IOMMU_ATF_SET_SMI_SEC_LARB,
IOMMU_ATF_DUMP_SMI_SEC_LARB,
IOMMU_ATF_CMD_COUNT
};
char *iommu_atf_cmd_name[IOMMU_ATF_CMD_COUNT] = {
"IOMMU_ATF_DUMP_SECURE_REG",
"IOMMU_ATF_SECURITY_DEBUG_ENABLE",
"IOMMU_ATF_SECURITY_DEBUG_DISABLE",
"IOMMU_ATF_BANK_ENABLE_TF",
"IOMMU_ATF_BANK_DISABLE_TF",
"IOMMU_ATF_BANK_DUMP_INFO",
"IOMMU_ATF_BANK_DOMAIN_CONFIG",
"IOMMU_ATF_SECURITY_BACKUP",
"IOMMU_ATF_SECURITY_RESTORE",
"IOMMU_ATF_DUMP_SECURE_PORT_CONFIG",
};
inline void iommu_set_field_by_mask(void __iomem *M4UBase,
unsigned int reg,
unsigned long mask,
unsigned int val)
{
unsigned int regval;
regval = readl_relaxed(M4UBase + reg);
regval = (regval & (~mask)) | val;
writel_relaxed(regval, M4UBase + reg);
}
static inline unsigned int iommu_get_field_by_mask(
void __iomem *M4UBase, unsigned int reg,
unsigned int mask)
{
return readl_relaxed(M4UBase + reg) & mask;
}
/* regiters of BANK0 */
#define REG_MMU_PT_BASE_ADDR (0x0)
#define F_MMU_PT_BASE_ADDR_MSK F_MSK(31, 7)
#define F_MMU_PT_BASE_ADDR_BIT32 F_MSK(2, 0)
#define REG_MMU_STA (0x8)
#define F_MMU_STA_INT_MASK F_MSK(18, 0)
#define REG_MMU_PROG_EN (0x10)
#define F_MMU_PROG_EN_TLB1 F_BIT_SET(1)
#define F_MMU_PROG_EN_TLB0 F_BIT_SET(0)
#define REG_MMU_PROG_VA (0x14)
#define F_MMU_PROG_VA_TBL_ID F_MSK(1, 0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_PROG_VA_BIT32 F_MSK(6, 5)
#endif
#define F_MMU_PROG_VA_SECURE F_BIT_SET(7)
#define F_MMU_PROG_VA_SIZE16X F_BIT_SET(8)
#define F_MMU_PROG_VA_LAYER F_BIT_SET(9)
#define F_MMU_PROG_VA_LOCK F_BIT_SET(11)
#define F_MMU_PROG_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_PROG_DSC (0x18)
#define REG_MMU_INVLDT (0x20)
#define F_MMU_INVLDT_RNG F_BIT_SET(0)
#define F_MMU_INVLDT_ALL F_BIT_SET(1)
#define F_MMU_INVLDT_VICT_ALL F_BIT_SET(2)
#define REG_MMU_INVLD_START_A (0x24)
#define REG_MMU_INVLD_END_A (0x28)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_INVLD_BIT32 F_MSK(1, 0)
#endif
#define F_MMU_INVLD_BIT31_12 F_MSK(31, 12)
#define REG_INVLID_SEL (0x2c)
#define F_MMU_INV_EN_L2 F_BIT_SET(1)
#define F_MMU_INV_EN_L1 F_BIT_SET(0)
#define REG_MMU_DUMMY 0x44
#define F_REG_MMU_IDLE_ENABLE F_BIT_SET(0)
#define REG_MMU_MISC_CTRL (0x48)
#define F_MMU_MISC_CTRL_COHERENCE_EN(MMU) (F_BIT_SET(0) << (MMU * 16))
#define F_MMU_MISC_CTRL_IN_ORDER_WR_EN(MMU) (F_BIT_SET(1) << (MMU * 16))
#define F_MMU_MISC_CTRL_STD_AXI_MODE(MMU) (F_BIT_SET(3) << (MMU * 16))
#define F_MMU_MISC_CTRL_BLOCKING_MODE(MMU) (F_BIT_SET(4) << (MMU * 16))
#define F_MMU_MISC_CTRL_HALF_ENTRY_MODE(MMU) (F_BIT_SET(5) << (MMU * 16))
#define REG_MMU_PRIORITY (0x4c)
#define F_MMU_PRIORITY_WALK_ULTRA F_BIT_SET(0)
#define F_MMU_PRIORITY_AUTO_PF_ULTRA F_BIT_SET(1)
#define F_MMU_PRIORITY_RS_FULL_ULTRA F_BIT_SET(2)
#define REG_MMU_DCM_DIS (0x50)
#define REG_MMU_WR_LEN_CTRL (0x54)
#define F_MMU_WR_LEN_CTRL_THROT_DIS(MMU) (F_BIT_SET(5) << (MMU * 0x10))
#define F_MMU_WR_LEN_CTRL_LEN(MMU) (F_MSK(4, 0) << (MMU * 0x10))
#define REG_MMU_HW_DEBUG (0x58)
#define F_MMU_HW_DEBUG_PFQ_BD_EN F_BIT_SET(0)
#define F_MMU_HW_DEBUG_L2_SCAN_ALL_INVLDT F_BIT_SET(1)
#define REG_MMU_DBG(index) (0x60 + index * 4)
#define REG_MMU_COH_THROT_CTRL (0x90)
#define F_MMU_COH_THROT_CTRL_REN0 F_BIT_SET(0)
#define F_MMU_COH_THROT_CTRL_RLMT0 F_MSK(3, 2)
#define F_MMU_COH_THROT_CTRL_WEN0 F_BIT_SET(4)
#define F_MMU_COH_THROT_CTRL_WLMT0 F_MSK(7, 6)
#define F_MMU_COH_THROT_CTRL_REN1 F_BIT_SET(8)
#define F_MMU_COH_THROT_CTRL_RLMT1 F_MSK(11, 10)
#define F_MMU_COH_THROT_CTRL_WEN1 F_BIT_SET(12)
#define F_MMU_COH_THROT_CTRL_WLMT1 F_MSK(15, 14)
#define REG_MMU_TBW_ID (0xA0)
#define F_MMU_TBW_ID_MISS F_MSK(15, 0)
#define F_MMU_TBW_ID_PFTH F_MSK(31, 16)
#define REG_MMU_READ_ENTRY (0x100)
#define F_READ_ENTRY_EN F_BIT_SET(31)
#define F_READ_ENTRY_VICT_TLB_SEL F_BIT_SET(13)
#define F_READ_ENTRY_MMx_MAIN(id) F_BIT_SET(27+id)
#define F_READ_ENTRY_PFH F_BIT_SET(26)
#define F_READ_ENTRY_MAIN_IDX(mmu, idx) \
F_VAL(idx, (19 + mmu * 6), (14 + mmu * 6))
#define F_READ_ENTRY_PFH_IDX(idx) F_VAL(idx, 11, 5)
#define F_READ_ENTRY_PFH_PAGE_IDX(idx) F_VAL(idx, 4, 2)
#define F_READ_ENTRY_PFH_WAY(way) F_VAL(way, 1, 0)
#define REG_MMU_DES_RDATA (0x104)
#define REG_MMU_PFH_TAG_RDATA (0x108)
#define F_PFH_TAG_VA_GET(mmu, tag) \
(F_MSK_SHIFT64(tag, 14, 3)<<(MMU_SET_MSB_OFFSET(mmu)+1))
#define F_VIC_TAG_VA_GET_L0(mmu, tag) \
(F_MSK_SHIFT(tag, 23, 17)<<(MMU_SET_MSB_OFFSET(mmu)+2))
#define F_VIC_TAG_VA_GET_L1(mmu, tag) \
(F_MSK_SHIFT(tag, 23, 17)<<(MMU_SET_MSB_OFFSET(mmu)-6))
#define F_MMU_PFH_TAG_VA_LAYER0_MSK(mmu) \
((mmu == 0)?F_MSK(31, 28):F_MSK(31, 28))
#define F_PFH_PT_BANK_BIT F_MSK(15, 16)
#define F_PFH_TAG_LAYER_BIT F_BIT_SET(2)
#define F_PFH_TAG_SEC_BIT F_BIT_SET(1)
#define F_PFH_TAG_AUTO_PFH F_BIT_SET(0)
#define REG_MMU_VICT_VLD (0x10c)
#define F_MMU_VICT_VLD_BIT(way) F_BIT_SET((way)&0xf)
#define REG_MMU_CTRL_REG (0x110)
#define F_MMU_CTRL_4GB_MODE(mode) F_BIT_VAL(mode, 17)
#define F_MMU_CTRL_RESEND_L2_EN(en) F_BIT_VAL(en, 16)
#define F_MMU_CTRL_RESEND_PFQ_EN(en) F_BIT_VAL(en, 15)
#define F_MMU_CTRL_L2TLB_EN(en) F_BIT_VAL(en, 14)
#define F_MMU_CTRL_MTLB_EN(en) F_BIT_VAL(en, 13)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_HANG_PREVENTION(en) F_BIT_VAL(en, 9)
#define F_MMU_CTRL_LAYER2_PFH_DIS(dis) F_BIT_VAL(dis, 7)
#define F_MMU_CTRL_INT_FREEZE_EN(en) F_BIT_VAL(en, 6)
#define F_MMU_CTRL_MONITOR_CLR(clr) F_BIT_VAL(clr, 2)
#define F_MMU_CTRL_MONITOR_EN(en) F_BIT_VAL(en, 1)
#define F_MMU_CTRL_PFH_DIS(dis) F_BIT_VAL(dis, 0)
#define REG_MMU_TFRP_PADDR (0x114)
#define F_RP_PA_REG_BIT31_7 F_MSK(31, 7)
#define F_RP_PA_REG_BIT32 F_MSK(2, 0)
#define F_MMU_TFRP_PA_SET(PA, EXT) (\
(((unsigned long long)PA) & F_RP_PA_REG_BIT31_7) | \
((((unsigned long long)PA) >> 32) & F_RP_PA_REG_BIT32))
#define REG_MMU_INT_CONTROL0 (0x120)
#define F_INT_L2_MULTI_HIT_FAULT F_BIT_SET(0)
#define F_INT_L2_TABLE_WALK_FAULT F_BIT_SET(1)
#define F_INT_L2_PFH_DMA_FIFO_OVERFLOW F_BIT_SET(2)
#define F_INT_L2_MISS_DMA_FIFO_OVERFLOW F_BIT_SET(3)
#define F_INT_L2_INVALID_DONE F_BIT_SET(4)
#define F_INT_L2_PFH_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_MISS_FIFO_ERR F_BIT_SET(6)
#define F_INT_CTL0_L2_CDB_SLICE_ERR BIT(7)
#define F_INT_CTL0_INT_CLR BIT(12)
#define REG_MMU_INT_MAIN_CONTROL (0x124)
#define F_INT_TRANSLATION_FAULT(MMU) F_BIT_SET(0+(MMU)*7)
#define F_INT_MAIN_MULTI_HIT_FAULT(MMU) F_BIT_SET(1+(MMU)*7)
#define F_INT_INVALID_PHYSICAL_ADDRESS_FAULT(MMU) F_BIT_SET(2+(MMU)*7)
#define F_INT_ENTRY_REPLACEMENT_FAULT(MMU) F_BIT_SET(3+(MMU)*7)
#define F_INT_TLB_MISS_FAULT(MMU) F_BIT_SET(4+(MMU)*7)
#define F_INT_MISS_FIFO_ERR(MMU) F_BIT_SET(5+(MMU)*7)
#define F_INT_PFH_FIFO_ERR(MMU) F_BIT_SET(6+(MMU)*7)
#define F_INT_MAIN_MAU_INT_EN(MMU) F_BIT_SET(14 + MMU)
#define F_INT_MMU_MAIN_MSK(MMU) F_MSK((6+(MMU)*7), ((MMU)*7))
#define REG_MMU_CPE_DONE (0x12C)
#define F_MMU_CPE_DONE_RNG_INVLADT BIT(0)
#define REG_MMU_L2_FAULT_ST (0x130)
#define F_MMU_L2_FAULT_MHIT BIT(0)
#define F_MMU_L2_FAULT_TBW BIT(1)
#define F_MMU_L2_FAULT_PFQ_FIFO_FULL BIT(2)
#define F_MMU_L2_FAULT_MQ_FIFO_FULL BIT(3)
#define F_MMU_L2_FAULT_INVLDT_DONE BIT(4)
#define F_INT_L2_PFH_OUT_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_PFH_IN_FIFO_ERROR F_BIT_SET(6)
#define F_INT_L2_MISS_OUT_FIFO_ERROR F_BIT_SET(7)
#define F_INT_L2_MISS_IN_FIFO_ERR F_BIT_SET(8)
#define F_MMU_L2_FAULT_L2_CDB_SLICE_ERR BIT(9)
#define REG_MMU_FAULT_ST1 (0x134)
//same to REG_MMU_INT_MAIN_CONTROL
#define REG_MMU_TBWALK_FAULT_VA (0x138)
#define F_MMU_TBWALK_FAULT_LAYER BIT(0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_TBWALK_FAULT_BIT32 F_MSK(10, 9)
#endif
#define F_MMU_TBWALK_FAULT_BIT31_12 F_MSK(31, 12)
#define REG_MMU_FAULT_STATUS(MMU) (0x13c+((MMU)<<3))
#define F_MMU_FAULT_VA_BIT31_12 F_MSK(31, 12)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_FAULT_VA_BIT32 F_MSK(11, 9)
#endif
#define F_MMU_FAULT_PA_BIT32 F_MSK(8, 6)
#define F_MMU_FAULT_INVPA F_BIT_SET(5)
#define F_MMU_FAULT_TF F_BIT_SET(4)
#define F_MMU_FAULT_VA_WRITE_BIT F_BIT_SET(1)
#define F_MMU_FAULT_VA_LAYER_BIT F_BIT_SET(0)
#define REG_MMU_INVLD_PA(MMU) (0x140+((MMU)<<3))
#define REG_MMU_INT_ID(MMU) (0x150+((MMU)<<2))
#define F_MMU_INT_L2_SRC F_MSK(30, 28)
#define F_MMU_INT_L1_SRC F_MSK(26, 24)
#define F_MMU_INT_TF_VAL(regval) (regval & F_MSK(11, 2))
#define REG_MMU_PERF_MON_PTLB (0x180)
#define F_MMU_PERF_MON_PTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_PTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_PTLB_ID_SEL F_BIT_SET(17)
#define F_MMU_PERF_MON_PTLB_AXI_SEL F_MSK(19, 18)
#define REG_MMU_PERF_MON_MTLB(MMU) (0x190 + mmu * 0x4)
#define F_MMU_PERF_MON_MTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_MTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_MTLB_ID_SEL F_BIT_SET(17)
#define REG_MMU_PF_L1_MSCNT (0x1A0)
#define REG_MMU_PF_L2_MSCNT (0x1A4)
#define REG_MMU_PF_L1_CNT (0x1A8)
#define REG_MMU_PF_L2_CNT (0x1AC)
#define REG_MMU_ACC_CNT(MMU) (0x1C0 + MMU * 16)
#define REG_MMU_MAIN_L1_MSCNT(MMU) (0x1C4 + MMU * 16)
#define REG_MMU_MAIN_L2_MSCNT(MMU) (0x1C8 + MMU * 16)
#define REG_MMU_RS_PERF_CNT(MMU) (0x1CC + MMU * 16)
#define REG_MMU_LOOKUP_CNT(MMU) (0x1D0 + MMU * 0x20)
#define REG_MMU_PFH_VLD(VLD, WAY) (0x200 + VLD * 0x4 + WAY * 0x10)
#define F_MMU_PFH_VLD_BIT(set, way) F_BIT_SET((set)&0x1f) /* set%32 */
#define REG_MMU_RS_VA(MMU, RS) (0x380 + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_VA_BIT32 F_MSK(2, 0)
#define F_MMU_RS_VA_TBL_ID F_MSK(5, 4)
#define F_MMU_RS_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_RS_PA(MMU, RS) (0x384 + MMU * 0x300 + RS * 0x10)
#define REG_MMU_RS_2ND_BASE(MMU, RS) (0x388 + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_2ND_BASE_MSK F_MSK(24, 0)
#define REG_MMU_RS_STA(MMU, RS) (0x38C + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_STA_IS_LTAIL BIT(0)
#define F_MMU_RS_STA_IS_LHEAD BIT(1)
#define F_MMU_RS_STA_IS_PTAIL BIT(2)
#define F_MMU_RS_STA_IS_PHEAD BIT(3)
#define F_MMU_RS_STA_PA_RDY BIT(4)
#define F_MMU_RS_STA_RDY2REQ BIT(5)
#define F_MMU_RS_STA_WRT_CMD BIT(6)
#define F_MMU_RS_STA_VLD BIT(7)
#define F_MMU_RS_STA_TO BIT(8)
#define F_MMU_RS_STA_ID F_MSK(31, 16)
#define REG_MMU_MAIN_TAG(MMU, TAG) (0x500 + MMU * 0x300 + TAG * 0x4)
#define F_MAIN_TLB_VA_MSK F_MSK(31, 12)
#define F_MAIN_TLB_VA_BIT32 F_MSK(1, 0)
#define F_MAIN_TLB_LOCK_BIT (1<<11)
#define F_MAIN_TLB_VALID_BIT (1<<10)
#define F_MAIN_TLB_LAYER_BIT F_BIT_SET(9)
#define F_MAIN_TLB_16X_BIT F_BIT_SET(8)
#define F_MAIN_TLB_SEC_BIT F_BIT_SET(7)
#define F_MAIN_TLB_INV_DES_BIT (1<<6)
#define F_MAIN_TLB_TABLE_ID_BIT(regval) F_MSK_SHIFT(regval, 5, 4)
#define REG_MMU_MAU_SA(MMU, MAU) (0x900 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_SA_EXT(MMU, MAU) (0x904 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA(MMU, MAU) (0x908 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA_EXT(MMU, MAU) (0x90C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_LARB_EN(MMU) (0x910 + MMU * 0x100)
#define REG_MMU_MAU_PORT_EN(MMU, MAU) (0x914 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ASRT_ID(MMU, MAU) (0x918 + MMU * 0x100 + MAU * 0)
#define F_MMU_MAU_ASRT_ID_LARB(regval) F_MSK_SHIFT(regval, 9, 5)
#define F_MMU_MAU_ASRT_ID_PORT(regval) F_MSK_SHIFT(regval, 4, 0)
#define F_MMU_MAU_ASRT_ID_VAL F_MSK(9, 0)
#define REG_MMU_MAU_ADDR(MMU, MAU) (0x91C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ADDR_BIT32(MMU, MAU) (0x920 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_CLR(MMU) (0x924 + MMU * 0x100)
#define REG_MMU_MAU_IO(MMU) (0x928 + MMU * 0x100)
#define F_MAU_BIT_VAL(val, mau) F_BIT_VAL(val, mau)
#define REG_MMU_MAU_RW(MMU) (0x92C + MMU * 0x100)
#define REG_MMU_MAU_VA(MMU) (0x930 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_STA(MMU) (0x934 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_C4K(MMU) (0x938 + MMU * 0x100)
#define REG_MMU_PFH_DIST(MMU, DIST) (0xB00 + MMU * 0x80 + DIST * 0x4)
// =================== IOVA Reservation ==========================
/*
* reserved IOVA Domain for IOMMU users of HW limitation.
*/
#define MTK_IOVA_REMOVE_CNT (6)
enum mtk_reserve_region_type {
// no reserved region
IOVA_REGION_UNDEFINE,
// users cannot touch the IOVA in the reserved region
IOVA_REGION_REMOVE,
// users can only touch the IOVA in the reserved region
IOVA_REGION_STAY,
};
/*
* struct mtk_iova_domain_data: domain configuration
* @min_iova: start address of IOVAD
* @max_iova: end address of IOVAD
* @resv_start: the start address of reserved region
* @resv_size: the size of reserved region
* @resv_type: the type of reserve region
* @port_mask: the user list of IOVAD
* One user can only belongs to one IOVAD, the port mask is in unit of SMI larb.
*/
struct mtk_iova_domain_data {
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
unsigned int boundary;
#endif
unsigned long min_iova;
unsigned long max_iova;
unsigned long resv_start[MTK_IOVA_REMOVE_CNT];
unsigned long resv_size[MTK_IOVA_REMOVE_CNT];
unsigned int resv_type;
unsigned int port_mask[MTK_IOMMU_LARB_NR];
int owner;
};
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#define MTK_IOVA_DOMAIN_COUNT (10) // Domain count
#define RESERVED_IOVA_ADDR_SECURE (SZ_4K)
#define RESERVED_IOVA_SIZE_SECURE (SZ_1G - SZ_4K)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define RESERVED_IOVA_ADDR_CCU0 (0x0240000000UL)
#define RESERVED_IOVA_SIZE_CCU0 (0x0004000000UL)
#define RESERVED_IOVA_ADDR_CCU1 (0x0244000000UL)
#define RESERVED_IOVA_SIZE_CCU1 (0x0004000000UL)
#define RESERVED_IOVA_ADDR_APU_CODE (0x0370000000UL)
#define RESERVED_IOVA_SIZE_APU_CODE (0x0012600000UL)
#define RESERVED_IOVA_ADDR_APU_DATA (0x0310000000UL)
#define RESERVED_IOVA_SIZE_APU_DATA (0x0010000000UL)
#define RESERVED_IOVA_ADDR_APU_VLM (0x0304000000UL)
#define RESERVED_IOVA_SIZE_APU_VLM (0x0004000000UL)
#define IOVA_ADDR_4GB (1UL << 32)
#define IOVA_ADDR_8GB (2UL << 32)
#define IOVA_ADDR_12GB (3UL << 32)
#define IOVA_ADDR_16GB (4UL << 32)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT) || \
defined(CONFIG_MTK_GZ_SUPPORT_SDSP) || \
defined(CONFIG_MTK_CAM_GENIEZONE_SUPPORT))
{ /* boundary(0~4GB) IOVA space for display(larb0,1) */
.boundary = 0,
.owner = -1,
.min_iova = SZ_1G,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x3f, 0xff, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
#else
{ /* boundary(0~4GB) IOVA space for display(larb0,1) */
.boundary = 0,
.owner = -1,
.min_iova = SZ_4K,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x3f, 0xff, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
#endif
{ /* boundary(4GB~8GB) IOVA space for video */
/* larb4,5,7,8 */
.boundary = 1,
.owner = -1,
.min_iova = IOVA_ADDR_4GB,
.max_iova = IOVA_ADDR_8GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x3fff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
{ /* boundary(8GB~12GB) IOVA space for CAM & MDP */
/* larb2, 9, 11, 13, 14, 16, 17, 18, 19, 20*/
.boundary = 2,
.owner = -1,
.min_iova = IOVA_ADDR_8GB,
.max_iova = IOVA_ADDR_12GB - 1,
.resv_start = {RESERVED_IOVA_ADDR_CCU0,
RESERVED_IOVA_ADDR_CCU1},
.resv_size = {RESERVED_IOVA_SIZE_CCU0,
RESERVED_IOVA_SIZE_CCU1},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x0, 0x0, 0x1f, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x0, 0x0, 0x0} //20~23
},
{ /* CCU0 IOVA space */
.boundary = 2,
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU0,
.max_iova = RESERVED_IOVA_ADDR_CCU0 +
RESERVED_IOVA_SIZE_CCU0 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x600, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x1, 0x0} //20~23
},
{ /* CCU1 IOVA space */
.boundary = 2,
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU1,
.max_iova = RESERVED_IOVA_ADDR_CCU1 +
RESERVED_IOVA_SIZE_CCU1 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x30, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x1} //20~23
},
{ /* boundary(12GB~16GB) IOVA space for APU DATA */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_DATA,
.min_iova = IOVA_ADDR_12GB,
.max_iova = IOVA_ADDR_16GB - 1,
.resv_start = {RESERVED_IOVA_ADDR_APU_DATA,
RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_VLM},
.resv_size = {RESERVED_IOVA_SIZE_APU_DATA,
RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_VLM},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x2, 0x0, 0x0} //20~23
},
{ /* VPU CODE IOVA space */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_CODE,
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x1, 0x0, 0x0} //20~23
},
{ /* VPU VLM IOVA space */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_VLM,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM,
.max_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x4, 0x0, 0x0} //20~23
},
};
#else
#define RESERVED_IOVA_ADDR_CCU0 (0x40000000U)
#define RESERVED_IOVA_SIZE_CCU0 (0x04000000U)
#define RESERVED_IOVA_ADDR_CCU1 (0x44000000U)
#define RESERVED_IOVA_SIZE_CCU1 (0x04000000U)
#define RESERVED_IOVA_ADDR_APU_CODE (0x70000000U)
#define RESERVED_IOVA_SIZE_APU_CODE (0x12600000U)
#define RESERVED_IOVA_ADDR_APU_DATA (0x10000000U)
#define RESERVED_IOVA_SIZE_APU_DATA (0x10000000U)
#define RESERVED_IOVA_ADDR_APU_VLM (0x48000000U)
#define RESERVED_IOVA_SIZE_APU_VLM (0x04000000U)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)) || \
defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
{ //REE IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM,
.max_iova = DMA_BIT_MASK(MTK_IOVA_ADDR_BITS),
.resv_start = {RESERVED_IOVA_ADDR_APU_CODE},
.resv_size = {RESERVED_IOVA_SIZE_APU_CODE},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x3f, 0xff, 0x1f, 0x0, //0~3
0x3fff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x2, 0x0, 0x0} //20~23
},
#else
{ //public IOVA space
.owner = -1,
.min_iova = SZ_4K,
.max_iova = DMA_BIT_MASK(MTK_IOVA_ADDR_BITS),
.resv_start = {RESERVED_IOVA_ADDR_CCU0,
RESERVED_IOVA_ADDR_CCU1,
RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_VLM,
RESERVED_IOVA_ADDR_APU_DATA},
.resv_size = {RESERVED_IOVA_SIZE_CCU0,
RESERVED_IOVA_SIZE_CCU1,
RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_VLM,
RESERVED_IOVA_SIZE_APU_DATA},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x3f, 0xff, 0x1f, 0x0, //0~3
0x3fff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x2, 0x0, 0x0} //20~23
},
#endif
{ //CCU0 IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU0,
.max_iova = RESERVED_IOVA_ADDR_CCU0 +
RESERVED_IOVA_SIZE_CCU0 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x600, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x1, 0x0} //20~23
},
{ //CCU1 IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU1,
.max_iova = RESERVED_IOVA_ADDR_CCU1 +
RESERVED_IOVA_SIZE_CCU1 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x30, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x1} //20~23
},
{ //VPU CODE IOVA space
.owner = M4U_PORT_L21_APU_FAKE_CODE,
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x1, 0x0, 0x0} //20~23
},
{ //VPU VLM IOVA space
.owner = M4U_PORT_L21_APU_FAKE_VLM,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM,
.max_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x4, 0x0, 0x0} //20~23
},
};
#endif
#define IOMMU_SECURITY_DBG_SUPPORT
/* check 17GB~32GB-1 PA for out of range */
struct mau_config_info mt6833_mau_info[MTK_IOMMU_M4U_COUNT] = {
{
.start = 0x40000000,
.end = 0xffffffff,
.port_mask = 0xffffffff,
.larb_mask = 0xffffffff,
.wr = 0x1,
.virt = 0x0,
.io = 0x1,
.start_bit32 = 0x4,
.end_bit32 = 0x7,
},
#ifdef CONFIG_MTK_APUSYS_SUPPORT
{
.start = 0x40000000,
.end = 0xffffffff,
.port_mask = 0xffffffff,
.larb_mask = 0xffffffff,
.wr = 0x1,
.virt = 0x0,
.io = 0x1,
.start_bit32 = 0x4,
.end_bit32 = 0x7,
}
#endif
};
struct mau_config_info *get_mau_info(int m4u_id)
{
if (m4u_id < MTK_IOMMU_M4U_COUNT)
return &mt6833_mau_info[m4u_id];
else
return NULL;
}
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/mt_iommu_port.h
+510
View File
@@ -0,0 +1,510 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
* this header file is only used for mtk_iomm module
* the definition of header file is platform dependency.
*/
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK
struct mtk_iommu_port {
char *name;
unsigned m4u_id: 2;
unsigned m4u_slave: 2;
unsigned larb_id: 6;
unsigned larb_port: 8;
unsigned tf_id: 14; /* 14 bits */
bool enable_tf;
mtk_iommu_fault_callback_t fault_fn;
void *fault_data;
};
#define MTK_IOMMU_PORT_INIT(name, id, slave, larb, tf_larb, port) {\
name, id, slave, larb, port, (((tf_larb)<<7)|((port)<<2)), 1\
}
#define SLAVE_L0 (0)
#define SLAVE_L1 (0)
#define SLAVE_L2 (0)
#define SLAVE_L3 (0)
#define SLAVE_L4 (0)
#define SLAVE_L5 (0)
#define SLAVE_L7 (0)
#define SLAVE_L8 (0)
#define SLAVE_L9 (0)
#define SLAVE_L11 (0)
#define SLAVE_L13 (0)
#define SLAVE_L14 (0)
#define SLAVE_L16 (0)
#define SLAVE_L17 (0)
#define SLAVE_L18 (0)
#define SLAVE_L19 (0)
#define SLAVE_L20 (0)
#define SLAVE_APU (0)
#define SLAVE_CCU0 (0)
#define SLAVE_CCU1 (0)
/* MM_IOMMU AXI_ID */
#define TF_LARB_L0 (0x0)
#define TF_LARB_L1 (0x4)
#define TF_LARB_L2 (0x10)
#define TF_LARB_L4 (0x8)
#define TF_LARB_L5 (0x9)
#define TF_LARB_L7 (0xc)
#define TF_LARB_L8 (0x5)//no use
#define TF_LARB_L9 (0x14)
#define TF_LARB_L11 (0x15)
#define TF_LARB_L13 (0x1d)
#define TF_LARB_L14 (0x19)
#define TF_LARB_L16 (0x1a)
#define TF_LARB_L17 (0x1f)
#define TF_LARB_L18 (0x1e)
#define TF_LARB_L19 (0x16)
#define TF_LARB_L20 (0x17)
#define TF_APU (0x0)
#define TF_CCU0 (0x1c)
#define TF_CCU1 (0x18)
/* avoid build error */
#define TF_CCU_DISP TF_CCU0
#define TF_CCU_MDP TF_CCU1
int mtk_iommu_larb_port_count[] = {
4, 5, 5, 0, 14,//0~4
0, 0, 13, 0, 29, //5~9
0, 29, 0, 12, 6, //10~14
0, 17, 17, 17, 4, //15~19
6, 3, 1, 1 //20~23
};
int mtk_iommu_larb_distance[] = {
0, 4, 9, -1, 14, //0~4
-1, -1, 28, -1, 41, //5~9
-1, 70, -1, 99, 111, //10~14
-1, 117, 134, 151, 168,//15~19
172, 178, 181, 182 //20~23
};
struct mtk_iommu_port iommu_port[] = {
/* Larb0 -- 4 */
MTK_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0,
SLAVE_L0, 0, TF_LARB_L0, 0),
MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0,
SLAVE_L0, 0, TF_LARB_L0, 1),
MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 2),
MTK_IOMMU_PORT_INIT("L0_DISP_RDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 3),
/* Larb1 -- 5(9) */
MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0,
SLAVE_L1, 1, TF_LARB_L1, 0),
MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 1),
MTK_IOMMU_PORT_INIT("L1_DISP_RDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 2),
MTK_IOMMU_PORT_INIT("L1_DISP_WDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 3),
MTK_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0,
SLAVE_L1, 1, TF_LARB_L1, 4),
/* Larb2 --5(14) */
MTK_IOMMU_PORT_INIT("L2_MDP_RDMA0", 0,
SLAVE_L2, 2, TF_LARB_L2, 0),
MTK_IOMMU_PORT_INIT("L2_MDP_RDMA1", 0,
SLAVE_L2, 2, TF_LARB_L2, 1),
MTK_IOMMU_PORT_INIT("L2_MDP_WROT0", 0,
SLAVE_L2, 2, TF_LARB_L2, 2),
MTK_IOMMU_PORT_INIT("L2_MDP_WROT1", 0,
SLAVE_L2, 2, TF_LARB_L2, 3),
MTK_IOMMU_PORT_INIT("L2_MDP_DISP_FAKE0", 0,
SLAVE_L2, 2, TF_LARB_L2, 4),
/* Larb4 -- 14(28) */
MTK_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 0),
MTK_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 1),
MTK_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 2),
MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 3),
MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 4),
MTK_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 5),
MTK_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 6),
MTK_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 7),
MTK_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 8),
MTK_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 9),
MTK_IOMMU_PORT_INIT("L4_VDEC_UFO_ENC_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 10),
MTK_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 11),
MTK_IOMMU_PORT_INIT("L4_MINI_MDP_R0_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 12),
MTK_IOMMU_PORT_INIT("L4_MINI_MDP_W0_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 13),
/* Larb7 --13(41) */
MTK_IOMMU_PORT_INIT("L7_VENC_RCPU", 0,
SLAVE_L7, 7, TF_LARB_L7, 0),
MTK_IOMMU_PORT_INIT("L7_VENC_REC", 0,
SLAVE_L7, 7, TF_LARB_L7, 1),
MTK_IOMMU_PORT_INIT("L7_VENC_BSDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 2),
MTK_IOMMU_PORT_INIT("L7_VENC_SV_COMV", 0,
SLAVE_L7, 7, TF_LARB_L7, 3),
MTK_IOMMU_PORT_INIT("L7_VENC_RD_COMV", 0,
SLAVE_L7, 7, TF_LARB_L7, 4),
MTK_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 5),
MTK_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 6),
MTK_IOMMU_PORT_INIT("L7_VENC_REF_LUMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 7),
MTK_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 8),
MTK_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 9),
MTK_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 10),
MTK_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE", 0,
SLAVE_L7, 7, TF_LARB_L7, 11),
MTK_IOMMU_PORT_INIT("L7_JPGENC_BSDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 12),
/*Larb9 -- 29(70) */
MTK_IOMMU_PORT_INIT("L9_IMG_IMGI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 0),
MTK_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 1),
MTK_IOMMU_PORT_INIT("L9_IMG_DMGI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 2),
MTK_IOMMU_PORT_INIT("L9_IMG_DEPI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 3),
MTK_IOMMU_PORT_INIT("L9_IMG_ICE_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 4),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 5),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D2", 0,
SLAVE_L9, 9, TF_LARB_L9, 6),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 7),
MTK_IOMMU_PORT_INIT("L9_IMG_CRZO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 8),
MTK_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 9),
MTK_IOMMU_PORT_INIT("L9_IMG_VIPI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 10),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D5", 0,
SLAVE_L9, 9, TF_LARB_L9, 11),
MTK_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 12),
MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_W0", 0,
SLAVE_L9, 9, TF_LARB_L9, 13),
MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_R0", 0,
SLAVE_L9, 9, TF_LARB_L9, 14),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 15),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 16),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA", 0,
SLAVE_L9, 9, TF_LARB_L9, 17),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 18),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 19),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2", 0,
SLAVE_L9, 9, TF_LARB_L9, 20),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3", 0,
SLAVE_L9, 9, TF_LARB_L9, 21),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4", 0,
SLAVE_L9, 9, TF_LARB_L9, 22),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5", 0,
SLAVE_L9, 9, TF_LARB_L9, 23),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 24),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 25),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE6", 0,
SLAVE_L9, 9, TF_LARB_L9, 26),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE7", 0,
SLAVE_L9, 9, TF_LARB_L9, 27),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE8", 0,
SLAVE_L9, 9, TF_LARB_L9, 28),
/*Larb11 -- 29(99) */
MTK_IOMMU_PORT_INIT("L11_IMG_IMGI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 0),
MTK_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 1),
MTK_IOMMU_PORT_INIT("L11_IMG_DMGI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 2),
MTK_IOMMU_PORT_INIT("L11_IMG_DEPI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 3),
MTK_IOMMU_PORT_INIT("L11_IMG_ICE_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 4),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 5),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D2", 0,
SLAVE_L11, 11, TF_LARB_L11, 6),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 7),
MTK_IOMMU_PORT_INIT("L11_IMG_CRZO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 8),
MTK_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 9),
MTK_IOMMU_PORT_INIT("L11_IMG_VIPI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 10),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D5", 0,
SLAVE_L11, 11, TF_LARB_L11, 11),
MTK_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 12),
MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_W0", 0,
SLAVE_L11, 11, TF_LARB_L11, 13),
MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_R0", 0,
SLAVE_L11, 11, TF_LARB_L11, 14),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 15),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 16),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA", 0,
SLAVE_L11, 11, TF_LARB_L11, 17),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 18),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 19),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2", 0,
SLAVE_L11, 11, TF_LARB_L11, 20),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3", 0,
SLAVE_L11, 11, TF_LARB_L11, 21),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4", 0,
SLAVE_L11, 11, TF_LARB_L11, 22),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5", 0,
SLAVE_L11, 11, TF_LARB_L11, 23),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 24),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 25),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE6", 0,
SLAVE_L11, 11, TF_LARB_L11, 26),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE7", 0,
SLAVE_L11, 11, TF_LARB_L11, 27),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE8", 0,
SLAVE_L11, 11, TF_LARB_L11, 28),
/*Larb13 -- 12(111) */
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWI", 0,
SLAVE_L13, 13, TF_LARB_L13, 0),
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO0", 0,
SLAVE_L13, 13, TF_LARB_L13, 1),
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO1", 0,
SLAVE_L13, 13, TF_LARB_L13, 2),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE1", 0,
SLAVE_L13, 13, TF_LARB_L13, 3),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE2", 0,
SLAVE_L13, 13, TF_LARB_L13, 4),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE3", 0,
SLAVE_L13, 13, TF_LARB_L13, 5),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV4", 0,
SLAVE_L13, 13, TF_LARB_L13, 6),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV5", 0,
SLAVE_L13, 13, TF_LARB_L13, 7),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV6", 0,
SLAVE_L13, 13, TF_LARB_L13, 8),
MTK_IOMMU_PORT_INIT("L13_CAM_CCUI", 0,
SLAVE_L13, 13, TF_LARB_L13, 9),
MTK_IOMMU_PORT_INIT("L13_CAM_CCUO", 0,
SLAVE_L13, 13, TF_LARB_L13, 10),
MTK_IOMMU_PORT_INIT("L13_CAM_FAKE", 0,
SLAVE_L13, 13, TF_LARB_L13, 11),
/*Larb14 -- 6(117) */
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE1", 0,
SLAVE_L14, 14, TF_LARB_L14, 0),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE2", 0,
SLAVE_L14, 14, TF_LARB_L14, 1),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE3", 0,
SLAVE_L14, 14, TF_LARB_L14, 2),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE4", 0,
SLAVE_L14, 14, TF_LARB_L14, 3),
MTK_IOMMU_PORT_INIT("L14_CAM_CCUI", 0,
SLAVE_L14, 14, TF_LARB_L14, 4),
MTK_IOMMU_PORT_INIT("L14_CAM_CCUO", 0,
SLAVE_L14, 14, TF_LARB_L14, 5),
/*Larb16 -- 17(134) */
MTK_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 0),
MTK_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 1),
MTK_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 2),
MTK_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 3),
MTK_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 4),
MTK_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 5),
MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 6),
MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 7),
MTK_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 8),
MTK_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 9),
MTK_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 10),
MTK_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 11),
MTK_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 12),
MTK_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 13),
MTK_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 14),
MTK_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_", 0,
SLAVE_L16, 16, TF_LARB_L16, 15),
MTK_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 16),
/*Larb17 -- 17(151) */
MTK_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 0),
MTK_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 1),
MTK_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 2),
MTK_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 3),
MTK_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 4),
MTK_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 5),
MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 6),
MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 7),
MTK_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 8),
MTK_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 9),
MTK_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 10),
MTK_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 11),
MTK_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 12),
MTK_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 13),
MTK_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 14),
MTK_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 15),
MTK_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 16),
/*Larb18 -- 17(168) */
MTK_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 0),
MTK_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 1),
MTK_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 2),
MTK_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 3),
MTK_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 4),
MTK_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 5),
MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 6),
MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 7),
MTK_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 8),
MTK_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 9),
MTK_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 10),
MTK_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 11),
MTK_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 12),
MTK_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 13),
MTK_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 14),
MTK_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 15),
MTK_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 16),
/*Larb19 -- 4(172) */
MTK_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 0),
MTK_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 1),
MTK_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 2),
MTK_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 3),
/*Larb20 -- 6(178) */
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA", 0,
SLAVE_L20, 20, TF_LARB_L20, 0),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB", 0,
SLAVE_L20, 20, TF_LARB_L20, 1),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA", 0,
SLAVE_L20, 20, TF_LARB_L20, 2),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB", 0,
SLAVE_L20, 20, TF_LARB_L20, 3),
MTK_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0", 0,
SLAVE_L20, 20, TF_LARB_L20, 4),
MTK_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA", 0,
SLAVE_L20, 20, TF_LARB_L20, 5),
/* only atf maybe need it, but kernel can't delete it,
* otherwise it affect index.
*/
/*Larb21 -- 3(181) */
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_CODE", 1,
SLAVE_APU, 21, TF_APU, 0),
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_DATA", 1,
SLAVE_APU, 21, TF_APU, 1),
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_VLM", 1,
SLAVE_APU, 21, TF_APU, 2),
/*Larb22 -- 1(182) */
MTK_IOMMU_PORT_INIT("L22_CCU0", 0,
SLAVE_CCU0, 22, TF_CCU0, 0),
/*Larb23 -- 1(183) */
MTK_IOMMU_PORT_INIT("L23_CCU1", 0,
SLAVE_CCU1, 23, TF_CCU1, 0),
/*Larb23 -- 1(184: 0~183) */
MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0, 0)
};
/* APU_IOMMU AXI_ID */
#define TF_VP6_0 (0x0)
#define TF_VP6_1 (0x1)
#define TF_UP (0x2)
#define TF_XPU (0x3)
#define MSK_VP6_0 F_MSK(10, 7)
#define MSK_VP6_1 F_MSK(10, 7)
#define MSK_UP F_MSK(10, 7)
#define MSK_XPU F_MSK(10, 7)
#define IOMMU_APU_AXI_PORT_NR (4)
static uint32_t vpu_axi_bus_id[IOMMU_APU_AXI_PORT_NR] = {
TF_VP6_0, TF_VP6_1, TF_UP, TF_XPU};
static uint32_t vpu_axi_bus_mask[IOMMU_APU_AXI_PORT_NR] = {
MSK_VP6_0, MSK_VP6_1, MSK_UP, MSK_XPU};
static char *vpu_axi_bus_name[IOMMU_APU_AXI_PORT_NR] = {
"APU_VP6_0", "APU_VP6_1", "APU_UP", "APU_XPU"};
#ifndef M4U_PORT_NR
#define M4U_PORT_NR (183)
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/mtk_cpufreq_api.h
+82
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cpu_freq(int cpu, int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void mt_cpufreq_ctrl_cci_volt(unsigned int volt);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
extern unsigned int mt_cpufreq_find_Vboot_idx(unsigned int cluster_id);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_cci_freq_idx(void);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/mtk_eem_api.h
+10
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@@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_EEM_API_H__
#define __MT_EEM_API_H__
/* DRCC */
extern void drcc_fail_composite(void);
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/pseudo_m4u.h
+336
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __PSEUDO_M4U_H__
#define __PSEUDO_M4U_H__
#include <linux/ioctl.h>
#include <linux/fs.h>
#if IS_ENABLED(CONFIG_DEBUG_FS)
#include <linux/debugfs.h>
#endif
#if IS_ENABLED(CONFIG_PROC_FS)
#include <linux/proc_fs.h>
#endif
#include <linux/seq_file.h>
#include <dt-bindings/memory/mt6781-larb-port.h>
#include <linux/list.h>
#include <linux/iova.h>
#include <linux/iommu.h>
#if (defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
defined(CONFIG_MICROTRUST_TEE_SUPPORT)) && \
defined(CONFIG_MTK_TEE_GP_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) && \
!defined(CONFIG_MTK_SVP_ON_MTEE_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#endif
#endif
#if defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
#define M4U_MTEE_SERVICE_ENABLE
#endif
#endif
#if defined(CONFIG_MTK_CAM_GENIEZONE_SUPPORT) || \
defined(CONFIG_MTK_SVP_ON_MTEE_SUPPORT)
#define M4U_GZ_SERVICE_ENABLE
#endif
#define M4U_PAGE_SIZE (0x1000)
#define M4U_DEVNAME "m4u"
#define TOTAL_M4U_NUM (2)
#define M4U_REG_SIZE (0x5e0)
#ifndef SMI_LARB_NR
#define SMI_LARB_NR (21)
#endif
#define ONE_SMI_PORT_NR (32)
#define M4U_PAGE_MASK (0xfff)
/* public flags */
/* engine access this buffer in sequncial way. */
#define M4U_FLAGS_SEQ_ACCESS (1<<0)
/* fix allocation, we will use mva user specified. */
#define M4U_FLAGS_FIX_MVA (1<<1)
/* the mva will share in SWd */
#define M4U_FLAGS_SEC_SHAREABLE (1<<2)
/* the allocator will search free mva from user specified. */
#define M4U_FLAGS_START_FROM (1<<3)
#define M4U_FLAGS_SG_READY (1<<4)
#ifdef CONFIG_MTK_IOMMU_V2
#define M4U_FLAGS_TO_ACP (1<<5)
#endif
/* port related: virtuality, security, distance */
struct M4U_PORT_STRUCT {
int ePortID;
unsigned int Virtuality;
unsigned int Security;
unsigned int domain; /*domain : 0 1 2 3*/
unsigned int Distance;
unsigned int Direction; /* 0:- 1:+*/
char name[128];
};
/* module related: alloc/dealloc MVA buffer */
struct M4U_MOUDLE_STRUCT {
int port;
unsigned long BufAddr;
unsigned long BufSize;
unsigned int prot;
unsigned long MVAStart;
unsigned long MVAEnd;
unsigned int flags;
};
struct mva_info_t {
struct list_head link;
unsigned long bufAddr;
unsigned long mvaStart;
unsigned long size;
int eModuleId;
unsigned int flags;
int security;
int cache_coherent;
unsigned int mapped_kernel_va_for_debug;
};
struct m4u_buf_info_t {
struct list_head link;
unsigned long va;
unsigned long mva;
unsigned long size;
int port;
unsigned int prot;
unsigned int flags;
struct sg_table *sg_table;
unsigned long mva_align;
unsigned long size_align;
int seq_id;
unsigned long mapped_kernel_va_for_debug;
unsigned long long timestamp;
char task_comm[TASK_COMM_LEN];
pid_t pid;
};
struct m4u_client_t {
/* mutex to protect mvaList */
/* should get this mutex whenever add/delete/interate mvaList */
struct mutex dataMutex;
pid_t open_pid;
pid_t open_tgid;
struct list_head mvaList;
unsigned long count;
};
struct port_mva_info_t {
int emoduleid;
unsigned long va;
unsigned long buf_size;
int security;
int cache_coherent;
unsigned int flags;
unsigned int iova_start;
unsigned int iova_end;
unsigned long mva;
};
#if IS_ENABLED(CONFIG_PROC_FS)
#define DEFINE_PROC_ATTRIBUTE(__fops, __get, __set, __fmt) \
static int __fops ## _open(struct inode *inode, struct file *file) \
{ \
struct inode local_inode = *inode; \
\
local_inode.i_private = PDE_DATA(inode); \
__simple_attr_check_format(__fmt, 0ull); \
return simple_attr_open(&local_inode, file, __get, __set, __fmt); \
} \
static const struct file_operations __fops = { \
.owner = THIS_MODULE, \
.open = __fops ## _open, \
.release = simple_attr_release, \
.read = simple_attr_read, \
.write = simple_attr_write, \
.llseek = generic_file_llseek, \
}
#endif
struct m4u_device {
struct proc_dir_entry *m4u_dev_proc_entry;
#if IS_ENABLED(CONFIG_DEBUG_FS)
struct dentry *debug_root;
#endif
#if IS_ENABLED(CONFIG_PROC_FS)
struct proc_dir_entry *proc_root;
#endif
};
/* we use this for trace the mva<-->sg_table relation ship */
struct mva_sglist {
struct list_head list;
unsigned long mva;
struct sg_table *table;
};
struct m4u_port_array {
#define M4U_PORT_ATTR_EN (1<<0)
#define M4U_PORT_ATTR_VIRTUAL (1<<1)
#define M4U_PORT_ATTR_SEC (1<<2)
unsigned char ports[M4U_PORT_NR];
};
extern unsigned long max_pfn;
extern unsigned char *pMlock_cnt;
extern unsigned int mlock_cnt_size;
extern unsigned long pagetable_pa;
struct sg_table *m4u_create_sgtable(unsigned long va, unsigned long size);
int m4u_dealloc_mva_sg(int eModuleID,
struct sg_table *sg_table,
const unsigned long BufSize,
const unsigned long MVA);
int m4u_alloc_mva_sg(struct port_mva_info_t *port_info,
struct sg_table *sg_table);
int m4u_mva_map_kernel(unsigned long mva,
unsigned long size, unsigned long *map_va,
unsigned long *map_size, struct sg_table *table);
int m4u_mva_unmap_kernel(unsigned long mva, unsigned long size,
unsigned long va);
#ifndef IOVA_PFN
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
#endif
int pseudo_get_reg_of_path(unsigned int port, bool is_va,
unsigned int *reg, unsigned int *mask,
unsigned int *value);
int m4u_config_port(struct M4U_PORT_STRUCT *pM4uPort);
int m4u_get_boundary(int port);
int pseudo_config_port_tee(int kernelport);
int m4u_switch_acp(unsigned int port,
unsigned long iova, size_t size, bool is_acp);
void pseudo_m4u_db_debug(unsigned int m4uid,
struct seq_file *s);
int m4u_get_dma_buf_port(struct device *dev);
static inline bool m4u_enable_4G(void)
{
return (max_pfn > (0xffffffffUL >> PAGE_SHIFT));
}
struct iova *__alloc_iova(struct iova_domain *iovad, size_t size,
dma_addr_t dma_limit);
void __free_iova(struct iova_domain *iovad, struct iova *iova);
void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr);
int pseudo_m4u_sec_init(int mtk_iommu_sec_id);
/* IOCTL commnad */
#define MTK_M4U_MAGICNO 'g'
#define MTK_M4U_T_POWER_ON _IOW(MTK_M4U_MAGICNO, 0, int)
#define MTK_M4U_T_POWER_OFF _IOW(MTK_M4U_MAGICNO, 1, int)
#define MTK_M4U_T_DUMP_REG _IOW(MTK_M4U_MAGICNO, 2, int)
#define MTK_M4U_T_DUMP_INFO _IOW(MTK_M4U_MAGICNO, 3, int)
#define MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define MTK_M4U_T_INSERT_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 6, int)
#define MTK_M4U_T_INVALID_TLB_RANGE _IOW(MTK_M4U_MAGICNO, 7, int)
#define MTK_M4U_T_INVALID_TLB_ALL _IOW(MTK_M4U_MAGICNO, 8, int)
#define MTK_M4U_T_MANUAL_INSERT_ENTRY _IOW(MTK_M4U_MAGICNO, 9, int)
#define MTK_M4U_T_CACHE_SYNC _IOW(MTK_M4U_MAGICNO, 10, int)
#define MTK_M4U_T_CONFIG_PORT _IOW(MTK_M4U_MAGICNO, 11, int)
#define MTK_M4U_T_CONFIG_ASSERT _IOW(MTK_M4U_MAGICNO, 12, int)
#define MTK_M4U_T_INSERT_WRAP_RANGE _IOW(MTK_M4U_MAGICNO, 13, int)
#define MTK_M4U_T_MONITOR_START _IOW(MTK_M4U_MAGICNO, 14, int)
#define MTK_M4U_T_MONITOR_STOP _IOW(MTK_M4U_MAGICNO, 15, int)
#define MTK_M4U_T_RESET_MVA_RELEASE_TLB _IOW(MTK_M4U_MAGICNO, 16, int)
#define MTK_M4U_T_CONFIG_PORT_ROTATOR _IOW(MTK_M4U_MAGICNO, 17, int)
#define MTK_M4U_T_QUERY_MVA _IOW(MTK_M4U_MAGICNO, 18, int)
#define MTK_M4U_T_M4UDrv_CONSTRUCT _IOW(MTK_M4U_MAGICNO, 19, int)
#define MTK_M4U_T_M4UDrv_DECONSTRUCT _IOW(MTK_M4U_MAGICNO, 20, int)
#define MTK_M4U_T_DUMP_PAGETABLE _IOW(MTK_M4U_MAGICNO, 21, int)
#define MTK_M4U_T_REGISTER_BUFFER _IOW(MTK_M4U_MAGICNO, 22, int)
#define MTK_M4U_T_CACHE_FLUSH_ALL _IOW(MTK_M4U_MAGICNO, 23, int)
#define MTK_M4U_T_CONFIG_PORT_ARRAY _IOW(MTK_M4U_MAGICNO, 26, int)
#define MTK_M4U_T_CONFIG_MAU _IOW(MTK_M4U_MAGICNO, 27, int)
#define MTK_M4U_T_CONFIG_TF _IOW(MTK_M4U_MAGICNO, 28, int)
#define MTK_M4U_T_DMA_OP _IOW(MTK_M4U_MAGICNO, 29, int)
#define MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#define MTK_M4U_GZ_SEC_INIT _IOW(MTK_M4U_MAGICNO, 60, int)
#if IS_ENABLED(CONFIG_COMPAT)
struct COMPAT_M4U_MOUDLE_STRUCT {
compat_uint_t port;
compat_ulong_t BufAddr;
compat_ulong_t BufSize;
compat_uint_t prot;
compat_ulong_t MVAStart;
compat_ulong_t MVAEnd;
compat_uint_t flags;
};
#define COMPAT_MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define COMPAT_MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define COMPAT_MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#endif
#ifdef M4U_MTEE_SERVICE_ENABLE
extern bool m4u_tee_en;
int smi_reg_restore_sec(void);
int smi_reg_backup_sec(void);
/*int m4u_config_port_array_tee(unsigned char* port_array);*/
int m4u_dump_secpgd(unsigned int port, unsigned long faultmva);
#endif
int pseudo_debug_init(struct m4u_device *data);
int pseudo_get_iova_space(int port,
unsigned long *base, unsigned long *max,
struct list_head *list);
void pseudo_put_iova_space(int port,
struct list_head *list);
void m4u_dump_pgtable(unsigned int level, unsigned long target);
void __m4u_dump_pgtable(struct seq_file *s, unsigned int level,
bool lock, unsigned long target);
int pseudo_dump_port(int port, bool ignore_power);
int pseudo_dump_all_port_status(struct seq_file *s);
int pseudo_dump_iova_reserved_region(struct seq_file *s);
/* =========== register defination =========== */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define SMI_LARB_NON_SEC_CONx(larb_port)(0x380 + ((larb_port)<<2))
#define F_SMI_NON_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_MMU_EN F_BIT_SET(0)
#define F_SMI_ADDR_BIT32 F_MSK(15, 8)
#define F_SMI_ADDR_BIT32_VAL(regval) F_MSK_SHIFT(regval, 15, 8)
#define SMI_LARB_SEC_CONx(larb_port) (0xf80 + ((larb_port)<<2))
#define F_SMI_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_SEC_EN(sec) F_BIT_VAL(sec, 1)
#define F_SMI_DOMN(domain) F_VAL(domain, 8, 4)
#define F_SMI_DOMN_VAL(regval) F_MSK_SHIFT(regval, 8, 4)
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/pseudo_m4u_plat.h
+94
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@@ -0,0 +1,94 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __PSEUDO_M4U_PLAT_H__
#define __PSEUDO_M4U_PLAT_H__
struct pseudo_device {
struct device *dev; /* record the device for config mmu use. */
int larbid; /* the larb id of this device*/
bool mmuen; /* whether this larb have been configed. */
const char *name;
int port[32];
};
struct pseudo_device pseudo_dev_larb[SMI_LARB_NR];
struct pseudo_device pseudo_dev_larb_fake[] = {
{
.larbid = MISC_PSEUDO_LARBID,
.port = {
M4U_PORT_L0_DISP_FAKE0, -1},
.name = "misc",
},
{
.larbid = CCU0_PSEUDO_LARBID,
.port = {
M4U_PORT_L13_CAM_CCUI,
M4U_PORT_L13_CAM_CCUO,
M4U_PORT_L22_CCU0, -1},
.name = "ccu0",
},
{
.larbid = CCU1_PSEUDO_LARBID,
.port = {
M4U_PORT_L14_CAM_CCUI,
M4U_PORT_L14_CAM_CCUO,
M4U_PORT_L23_CCU1, -1},
.name = "ccu1",
},
{
.larbid = APU_PSEUDO_LARBID_CODE,
.port = {
M4U_PORT_L21_APU_FAKE_CODE, -1},
.name = "apu_code",
},
{
.larbid = APU_PSEUDO_LARBID_DATA,
.port = {
M4U_PORT_L21_APU_FAKE_DATA, -1},
.name = "apu_data",
},
{
.larbid = APU_PSEUDO_LARBID_VLM,
.port = {
M4U_PORT_L21_APU_FAKE_VLM, -1},
.name = "apu_vlm",
},
};
unsigned int pseudo_acp_port_array[] = {
M4U_PORT_L21_APU_FAKE_CODE,
M4U_PORT_L21_APU_FAKE_DATA,
M4U_PORT_L21_APU_FAKE_VLM,
};
static char *pseudo_larbname[] = {
"mediatek,smi_larb0", "mediatek,smi_larb1", "mediatek,smi_larb2",
"m4u_none", "mediatek,smi_larb4", "m4u_none",
"m4u_none", "mediatek,smi_larb7", "m4u_none",
"mediatek,smi_larb9", "m4u_none", "mediatek,smi_larb11",
"m4u_none", "mediatek,smi_larb13", "mediatek,smi_larb14",
"m4u_none", "mediatek,smi_larb16", "mediatek,smi_larb17",
"mediatek,smi_larb18", "mediatek,smi_larb19", "mediatek,smi_larb20"
};
char *pseudo_larb_clk_name[] = {
"m4u_smi_larb0", "m4u_smi_larb1", "m4u_smi_larb2", "m4u_none",
"m4u_smi_larb4", "m4u_smi_larb5", "m4u_none", "m4u_smi_larb7",
"m4u_none", "m4u_smi_larb9", "m4u_none", "m4u_smi_larb11",
"m4u_none", "m4u_smi_larb13", "m4u_smi_larb14", "m4u_none",
"m4u_smi_larb16", "m4u_smi_larb17", "m4u_smi_larb18", "m4u_smi_larb19",
"m4u_smi_larb20"
};
static inline int m4u_port_id_of_mdp(
unsigned int larb, unsigned int port)
{
if (larb == 2 && port <= 4)
return 1;
else
return 0;
}
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/upmu_hw.h
+24302
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drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/upmu_sw.h
+11
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MT_PMIC_UPMU_SW_H_
#define _MT_PMIC_UPMU_SW_H_
#include "../../../mt6785/include/mach/upmu_sw.h"
#endif /* _MT_PMIC_UPMU_SW_H_ */
drivers/misc/mediatek/include/mt-plat/mt6781/include/mach/wd_api.h
+12
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if defined(CONFIG_MTK_WATCHDOG_COMMON)
/* use common wd api */
#include <mt-plat/mtk_wd_api.h>
#else
#error "watchdog: common wd_api.h shall be used."
#endif
drivers/misc/mediatek/include/mt-plat/mt6781/include/trustzone/m4u/tz_m4u.h
+207
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __TZ_M4U_H__
#define __TZ_M4U_H__
/* #include "drStd.h" */
#ifdef CONFIG_MTK_PSEUDO_M4U
#include "mach/mt_iommu.h"
#else
#include "m4u_port.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/* #define __M4U_SECURE_SYSTRACE_ENABLE__ */
#define M4U_NONSEC_MVA_START (0x40000000)
#define CMD_M4U_MAGIC (0x77880000)
enum m4u_cmd {
CMD_M4U_ADD = CMD_M4U_MAGIC,
CMD_M4U_CFG_PORT,
CMD_M4U_MAP_NONSEC_BUFFER,
CMD_M4U_SEC_INIT,
CMD_M4U_ALLOC_MVA,
CMD_M4U_DEALLOC_MVA,
CMD_M4U_REG_BACKUP,
CMD_M4U_REG_RESTORE,
CMD_M4U_PRINT_PORT,
CMD_M4U_DUMP_SEC_PGTABLE,
CMD_M4UTL_INIT,
CMD_M4U_OPEN_SESSION,
CMD_M4U_CLOSE_SESSION,
CMD_M4U_CFG_PORT_ARRAY,
CMD_M4U_SYSTRACE_MAP,
CMD_M4U_SYSTRACE_UNMAP,
CMD_M4U_SYSTRACE_TRANSACT,
CMD_M4U_LARB_BACKUP,
CMD_M4U_LARB_RESTORE,
CMD_M4U_UNMAP_NONSEC_BUFFER,
CMD_M4U_GET_RESERVED_MEMORY,
CMD_M4U_GET_SEC_MEM,
CMD_M4U_NUM,
/* Add for m4u in MTEE*/
CMD_M4UTY_INIT,
CMD_M4UTY_CFG_PORT_SEC,
CMD_M4UTY_CFG_PORT_ARRAY,
CMD_M4UTY_MAP_NONSEC_BUFFER,
CMD_M4UTY_UNMAP_NONSEC_BUFFER,
CMD_M4UTY_ALLOC_MVA_SEC_NOIPC,
CMD_M4UTY_DEALLOC_MVA_SEC_NOIPC,
CMD_M4UTY_ALLOC_MVA_SEC,
CMD_M4UTY_DEALLOC_MVA_SEC,
CMD_M4UTY_GET_SEC_MEM,
};
#define M4U_RET_OK 0
#define M4U_RET_UNKNOWN_CMD -1
#define M4U_RET_NO_PERM -2
#define EXIT_ERROR ((uint32_t)(-1))
struct m4u_add_param {
int a;
int b;
int result;
};
#define M4U_SIN_NAME_LEN 12
struct m4u_session_param {
int sid;
char name[M4U_SIN_NAME_LEN];
};
struct m4u_cfg_port_param {
int port;
int virt;
int sec;
int distance;
int direction;
};
struct m4u_buf_param {
int port;
unsigned int mva;
unsigned int size;
unsigned long long pa;
};
#define TZ_M4U_MAX_MEM_CHUNK_NR 2
struct m4u_sec_mem_param {
uint64_t pa[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t sz[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t mva[TZ_M4U_MAX_MEM_CHUNK_NR];
unsigned int nr;
};
struct m4u_init_param {
unsigned long long nonsec_pt_pa;
int l2_en;
unsigned int sec_pt_pa;
struct m4u_sec_mem_param sec_mem;
unsigned int chunk_nr;
int reinit;
};
struct m4u_systrace_param {
unsigned long pa;
unsigned long size;
};
struct m4u_cfg_port_array_param {
unsigned char m4u_port_array[M4U_PORT_NR];
};
struct m4u_larb_restore_param {
unsigned int larb_idx;
};
struct m4u_reserved_memory_param {
unsigned int reserved_mem_start;
unsigned int reserved_mem_size;
};
enum mtk_iommu_sec_id {
SEC_ID_SEC_CAM = 0,
SEC_ID_SVP,
SEC_ID_SDSP,
SEC_ID_WFD,
SEC_ID_COUNT
};
struct m4u_msg {
unsigned int cmd;
unsigned int retval_for_tbase; /* it must be 0 */
unsigned int rsp;
union {
struct m4u_session_param session_param;
struct m4u_cfg_port_param port_param;
struct m4u_buf_param buf_param;
struct m4u_init_param init_param;
struct m4u_cfg_port_array_param port_array_param;
#ifdef __M4U_SECURE_SYSTRACE_ENABLE__
struct m4u_systrace_param systrace_param;
#endif
struct m4u_larb_restore_param larb_param;
struct m4u_reserved_memory_param reserved_memory_param;
struct m4u_sec_mem_param sec_mem_param;
};
};
struct gz_m4u_msg {
unsigned int cmd;
unsigned int retval_for_tbase; /* it must be 0 */
unsigned int rsp;
unsigned int iommu_type;
unsigned int iommu_sec_id;
union {
struct m4u_session_param session_param;
struct m4u_cfg_port_param port_param;
struct m4u_buf_param buf_param;
struct m4u_init_param init_param;
struct m4u_cfg_port_array_param port_array_param;
#ifdef __M4U_SECURE_SYSTRACE_ENABLE__
struct m4u_systrace_param systrace_param;
#endif
struct m4u_larb_restore_param larb_param;
struct m4u_reserved_memory_param reserved_memory_param;
struct m4u_sec_mem_param sec_mem_param;
};
};
/* logs */
#define M4U_U64_FMT "0x%08x_%08x"
#define M4U_U64_PR(u64) ((uint32_t)((u64) >> 32), (uint32_t)(u64))
/* should be removed before MP */
#define TZ_M4U_DBG
#if defined(__cplusplus)
}
#endif
#endif /* TLFOO_H_ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/memory_layout.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _H_MEMORY_LAYOUT_H_
#define _H_MEMORY_LAYOUT_H_
#define LK_KERNEL_32_BASE (0x40008000)
#define LK_KERNEL_32_MAX_SIZE (0x7C00000)
#define LK_KERNEL_64_BASE (0x40080000)
#define LK_KERNEL_64_MAX_SIZE (0x7C00000)
#define KERN_RAMCONSOLE_BASE (0x4D000000)
#define KERN_RAMCONSOLE_MAX_SIZE (0x10000)
#define KERN_PSTORE_BASE (0x4D010000)
#define KERN_PSTORE_MAX_SIZE (0xE0000)
#define KERN_MINIDUMP_BASE (0x4D0F0000)
#define KERN_MINIDUMP_MAX_SIZE (0x10000)
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mt_iommu.h
+18
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_IOMMU_H__
#define __MT_IOMMU_H__
#if IS_ENABLED(CONFIG_MACH_MT6781)
#include <dt-bindings/memory/mt6781-larb-port.h>
#else
#include <dt-bindings/memory/mt6785-larb-port.h>
#endif
#include "mtk_iommu_ext.h"
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mt_iommu_plat.h
+565
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if IS_ENABLED(CONFIG_MACH_MT6781)
#include "../../../mt6781/include/mach/mt_iommu_plat.h"
#else
#ifndef __MT_IOMMU_PLAT_H__
#define __MT_IOMMU_PLAT_H__
#define MMU0_SET_ORDER 7
#define MMU1_SET_ORDER 7
#define MMU_SET_ORDER(mmu) ((mmu == 0) ? MMU0_SET_ORDER : MMU1_SET_ORDER)
#define MTK_IOMMU_SET_NR(mmu) (1<<MMU_SET_ORDER(mmu))
#define MMU_SET_LSB_OFFSET 15
#define MMU_SET_MSB_OFFSET(mmu) (MMU_SET_LSB_OFFSET+MMU_SET_ORDER(mmu)-1)
#define MMU_PFH_VA_TO_SET(mmu, va) \
F_MSK_SHIFT(va, MMU_SET_MSB_OFFSET(mmu), MMU_SET_LSB_OFFSET)
#ifdef CONFIG_FPGA_EARLY_PORTING
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {64};
#else
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {64, 64};
#endif
char *smi_clk_name[MTK_IOMMU_LARB_NR] = {
"iommu_disp_larb0", "iommu_disp_larb1", "iommu_disp_larb2",
"iommu_disp_larb3", "iommu_null_larb4", "iommu_disp_larb5",
"iommu_disp_larb6", "iommu_null_larb7", "iommu_null_larb8",
};
unsigned int port_size_not_aligned[] = {
M4U_PORT_VPU,
};
const char *smi_larb_id = "mediatek,smi-id";
#ifdef CONFIG_FPGA_EARLY_PORTING
unsigned int iommu_power_id[MTK_IOMMU_M4U_COUNT] = {
0
};
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u0"
};
#else
unsigned int iommu_power_id[MTK_IOMMU_M4U_COUNT] = {
};
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u0", "mediatek,sec_m4u1",
};
#endif
/* ================ register control ================ */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define IOMMU_DESIGN_OF_BANK
#ifdef IOMMU_DESIGN_OF_BANK
/* m4u atf debug parameter */
#define IOMMU_ATF_INDEX_MASK F_MSK(3, 0)
#define IOMMU_ATF_BANK_MASK F_MSK(7, 4)
#define IOMMU_ATF_CMD_MASK F_MSK(16, 8)
#define IOMMU_ATF_SET_COMMAND(m4u, bank, cmd) \
(m4u | (bank << 4) | (cmd << 8))
enum IOMMU_ATF_CMD {
IOMMU_ATF_DUMP_SECURE_REG,
IOMMU_ATF_SECURITY_DEBUG_ENABLE,
IOMMU_ATF_SECURITY_DEBUG_DISABLE,
IOMMU_ATF_BANK_ENABLE_TF,
IOMMU_ATF_BANK_DISABLE_TF,
IOMMU_ATF_BANK_DUMP_INFO,
IOMMU_ATF_BANK_DOMAIN_CONFIG,
IOMMU_ATF_SECURITY_BACKUP,
IOMMU_ATF_SECURITY_RESTORE,
IOMMU_ATF_DUMP_SECURE_PORT_CONFIG,
IOMMU_ATF_CMD_COUNT
};
char *iommu_atf_cmd_name[IOMMU_ATF_CMD_COUNT] = {
"IOMMU_ATF_DUMP_SECURE_REG",
"IOMMU_ATF_SECURITY_DEBUG_ENABLE",
"IOMMU_ATF_SECURITY_DEBUG_DISABLE",
"IOMMU_ATF_BANK_ENABLE_TF",
"IOMMU_ATF_BANK_DISABLE_TF",
"IOMMU_ATF_BANK_DUMP_INFO",
"IOMMU_ATF_BANK_DOMAIN_CONFIG",
"IOMMU_ATF_SECURITY_BACKUP",
"IOMMU_ATF_SECURITY_RESTORE",
"IOMMU_ATF_DUMP_SECURE_PORT_CONFIG",
};
#endif
inline void iommu_set_field_by_mask(void __iomem *M4UBase,
unsigned int reg,
unsigned long mask,
unsigned int val)
{
unsigned int regval;
regval = readl_relaxed(M4UBase + reg);
regval = (regval & (~mask)) | val;
writel_relaxed(regval, M4UBase + reg);
}
static inline unsigned int iommu_get_field_by_mask(
void __iomem *M4UBase, unsigned int reg,
unsigned int mask)
{
return readl_relaxed(M4UBase + reg) & mask;
}
/* regiters of BANK0 */
#define REG_MMU_PT_BASE_ADDR (0x0)
#define F_MMU_PT_BASE_ADDR_MSK F_MSK(31, 7)
#define F_MMU_PT_BASE_ADDR_BIT32 F_MSK(1, 0)
#define REG_MMU_STA (0x8)
#define F_MMU_STA_INT_MASK F_MSK(18, 0)
#define REG_MMU_PROG_EN (0x10)
#define F_MMU_PROG_EN_TLB1 F_BIT_SET(1)
#define F_MMU_PROG_EN_TLB0 F_BIT_SET(0)
#define REG_MMU_PROG_VA (0x14)
#define F_MMU_PROG_VA_TBL_ID F_MSK(1, 0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_PROG_VA_BIT32 F_MSK(6, 5)
#endif
#define F_MMU_PROG_VA_SECURE F_BIT_SET(7)
#define F_MMU_PROG_VA_SIZE16X F_BIT_SET(8)
#define F_MMU_PROG_VA_LAYER F_BIT_SET(9)
#define F_MMU_PROG_VA_LOCK F_BIT_SET(11)
#define F_MMU_PROG_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_PROG_DSC (0x18)
#define REG_MMU_INVLDT (0x20)
#define F_MMU_INVLDT_RNG F_BIT_SET(0)
#define F_MMU_INVLDT_ALL F_BIT_SET(1)
#define F_MMU_INVLDT_VICT_ALL F_BIT_SET(2)
#define REG_MMU_INVLD_START_A (0x24)
#define REG_MMU_INVLD_END_A (0x28)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_INVLD_BIT32 F_MSK(1, 0)
#endif
#define F_MMU_INVLD_BIT31_12 F_MSK(31, 12)
#define REG_INVLID_SEL (0x2c)
#define F_MMU_INV_EN_L2 F_BIT_SET(1)
#define F_MMU_INV_EN_L1 F_BIT_SET(0)
#define REG_MMU_DUMMY 0x44
#define F_REG_MMU_IDLE_ENABLE F_BIT_SET(0)
#define REG_MMU_MISC_CTRL (0x48)
#define F_MMU_MISC_CTRL_COHERENCE_EN(MMU) (F_BIT_SET(0) << (MMU * 16))
#define F_MMU_MISC_CTRL_IN_ORDER_WR_EN(MMU) (F_BIT_SET(1) << (MMU * 16))
#define F_MMU_MISC_CTRL_STD_AXI_MODE(MMU) (F_BIT_SET(3) << (MMU * 16))
#define F_MMU_MISC_CTRL_BLOCKING_MODE(MMU) (F_BIT_SET(4) << (MMU * 16))
#define F_MMU_MISC_CTRL_HALF_ENTRY_MODE(MMU) (F_BIT_SET(5) << (MMU * 16))
#define REG_MMU_PRIORITY (0x4c)
#define F_MMU_PRIORITY_WALK_ULTRA F_BIT_SET(0)
#define F_MMU_PRIORITY_AUTO_PF_ULTRA F_BIT_SET(1)
#define F_MMU_PRIORITY_RS_FULL_ULTRA F_BIT_SET(2)
#define REG_MMU_DCM_DIS (0x50)
#define REG_MMU_WR_LEN_CTRL (0x54)
#define F_MMU_WR_LEN_CTRL_THROT_DIS(MMU) (F_BIT_SET(5) << (MMU * 0x10))
#define F_MMU_WR_LEN_CTRL_LEN(MMU) (F_MSK(4, 0) << (MMU * 0x10))
#define REG_MMU_HW_DEBUG (0x58)
#define F_MMU_HW_DEBUG_PFQ_BD_EN F_BIT_SET(0)
#define F_MMU_HW_DEBUG_L2_SCAN_ALL_INVLDT F_BIT_SET(1)
#define REG_MMU_DBG(index) (0x60 + index * 4)
#define REG_MMU_COH_THROT_CTRL (0x90)
#define F_MMU_COH_THROT_CTRL_REN0 F_BIT_SET(0)
#define F_MMU_COH_THROT_CTRL_RLMT0 F_MSK(3, 2)
#define F_MMU_COH_THROT_CTRL_WEN0 F_BIT_SET(4)
#define F_MMU_COH_THROT_CTRL_WLMT0 F_MSK(7, 6)
#define F_MMU_COH_THROT_CTRL_REN1 F_BIT_SET(8)
#define F_MMU_COH_THROT_CTRL_RLMT1 F_MSK(11, 10)
#define F_MMU_COH_THROT_CTRL_WEN1 F_BIT_SET(12)
#define F_MMU_COH_THROT_CTRL_WLMT1 F_MSK(15, 14)
#define REG_MMU_TBW_ID (0xA0)
#define F_MMU_TBW_ID_MISS F_MSK(15, 0)
#define F_MMU_TBW_ID_PFTH F_MSK(31, 16)
#define REG_MMU_READ_ENTRY (0x100)
#define F_READ_ENTRY_EN F_BIT_SET(31)
#define F_READ_ENTRY_VICT_TLB_SEL F_BIT_SET(13)
#define F_READ_ENTRY_MM0_MAIN F_BIT_SET(27)
#define F_READ_ENTRY_MMx_MAIN(id) F_BIT_SET(27+id)
#define F_READ_ENTRY_PFH F_BIT_SET(26)
#define F_READ_ENTRY_MMU1_IDX(idx) F_VAL(idx, 25, 20)
#define F_READ_ENTRY_MAIN_IDX(idx) F_VAL(idx, 19, 14)
#define F_READ_ENTRY_PFH_IDX(idx) F_VAL(idx, 11, 5)
#define F_READ_ENTRY_PFH_PAGE_IDX(idx) F_VAL(idx, 4, 2)
#define F_READ_ENTRY_PFH_WAY(way) F_VAL(way, 1, 0)
#define REG_MMU_DES_RDATA (0x104)
#define REG_MMU_PFH_TAG_RDATA 0x108
#define F_PFH_TAG_VA_GET(mmu, tag) \
((mmu == 0)?F_MMU0_PFH_TAG_VA_GET(tag) : F_MMU1_PFH_TAG_VA_GET(tag))
#define F_MMU0_PFH_TAG_VA_GET(tag) \
(F_MSK_SHIFT(tag, 13, 4)<<(MMU_SET_MSB_OFFSET(0)+1))
#define F_MMU1_PFH_TAG_VA_GET(tag) \
(F_MSK_SHIFT(tag, 13, 4)<<(MMU_SET_MSB_OFFSET(1)+1))
#define F_MMU_PFH_TAG_VA_LAYER0_MSK(mmu) \
((mmu == 0)?F_MSK(31, 28):F_MSK(31, 28))
#define F_PFH_TAG_LAYER_BIT F_BIT_SET(3)
#define F_PFH_TAG_16X_BIT \
F_BIT_SET(2) /* this bit is always 0 -- cost down. */
#define F_PFH_TAG_SEC_BIT F_BIT_SET(1)
#define F_PFH_TAG_AUTO_PFH F_BIT_SET(0)
#define REG_MMU_VICT_VLD (0x10c)
#define F_MMU_VICT_VLD_BIT(way) F_BIT_SET((way)&0xf)
#define REG_MMU_CTRL_REG (0x110)
#define F_MMU_CTRL_4GB_MODE(mode) F_BIT_VAL(mode, 17)
#define F_MMU_CTRL_RESEND_L2_EN(en) F_BIT_VAL(en, 16)
#define F_MMU_CTRL_RESEND_PFQ_EN(en) F_BIT_VAL(en, 15)
#define F_MMU_CTRL_L2TLB_EN(en) F_BIT_VAL(en, 14)
#define F_MMU_CTRL_MTLB_EN(en) F_BIT_VAL(en, 13)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_HANG_PREVENTION(en) F_BIT_VAL(en, 9)
#define F_MMU_CTRL_LAYER2_PFH_DIS(dis) F_BIT_VAL(dis, 7)
#define F_MMU_CTRL_INT_FREEZE_EN(en) F_BIT_VAL(en, 6)
#define F_MMU_CTRL_MONITOR_CLR(clr) F_BIT_VAL(clr, 2)
#define F_MMU_CTRL_MONITOR_EN(en) F_BIT_VAL(en, 1)
#define F_MMU_CTRL_PFH_DIS(dis) F_BIT_VAL(dis, 0)
#define REG_MMU_TFRP_PADDR (0x114)
#define F_RP_PA_REG_BIT31_7 F_MSK(31, 7)
#define F_RP_PA_REG_BIT32 F_MSK(1, 0)
#define F_MMU_TFRP_PA_SET(PA, EXT) (\
(((unsigned long long)PA) & F_RP_PA_REG_BIT31_7) | \
((((unsigned long long)PA) >> 32) & F_RP_PA_REG_BIT32))
#define REG_MMU_INT_CONTROL0 (0x120)
#define F_INT_L2_MULTI_HIT_FAULT F_BIT_SET(0)
#define F_INT_L2_TABLE_WALK_FAULT F_BIT_SET(1)
#define F_INT_L2_PFH_DMA_FIFO_OVERFLOW F_BIT_SET(2)
#define F_INT_L2_MISS_DMA_FIFO_OVERFLOW F_BIT_SET(3)
#define F_INT_L2_INVALID_DONE F_BIT_SET(4)
#define F_INT_L2_PFH_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_MISS_FIFO_ERR F_BIT_SET(6)
#define F_INT_CTL0_L2_CDB_SLICE_ERR BIT(7)
#define F_INT_CTL0_INT_CLR BIT(12)
#define REG_MMU_INT_MAIN_CONTROL (0x124)
#define F_INT_TRANSLATION_FAULT(MMU) F_BIT_SET(0+(MMU)*7)
#define F_INT_MAIN_MULTI_HIT_FAULT(MMU) F_BIT_SET(1+(MMU)*7)
#define F_INT_INVALID_PHYSICAL_ADDRESS_FAULT(MMU) F_BIT_SET(2+(MMU)*7)
#define F_INT_ENTRY_REPLACEMENT_FAULT(MMU) F_BIT_SET(3+(MMU)*7)
#define F_INT_TLB_MISS_FAULT(MMU) F_BIT_SET(4+(MMU)*7)
#define F_INT_MISS_FIFO_ERR(MMU) F_BIT_SET(5+(MMU)*7)
#define F_INT_PFH_FIFO_ERR(MMU) F_BIT_SET(6+(MMU)*7)
#define F_INT_MAIN_MAU_INT_EN(MMU) F_BIT_SET(14 + MMU)
#define F_INT_MMU_MAIN_MSK(MMU) F_MSK((6+(MMU)*7), ((MMU)*7))
#define REG_MMU_CPE_DONE (0x12C)
#define F_MMU_CPE_DONE_RNG_INVLADT BIT(0)
#define REG_MMU_L2_FAULT_ST (0x130)
#define F_MMU_L2_FAULT_MHIT BIT(0)
#define F_MMU_L2_FAULT_TBW BIT(1)
#define F_MMU_L2_FAULT_PFQ_FIFO_FULL BIT(2)
#define F_MMU_L2_FAULT_MQ_FIFO_FULL BIT(3)
#define F_MMU_L2_FAULT_INVLDT_DONE BIT(4)
#define F_INT_L2_PFH_OUT_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_PFH_IN_FIFO_ERROR F_BIT_SET(6)
#define F_INT_L2_MISS_OUT_FIFO_ERROR F_BIT_SET(7)
#define F_INT_L2_MISS_IN_FIFO_ERR F_BIT_SET(8)
#define F_MMU_L2_FAULT_L2_CDB_SLICE_ERR BIT(9)
#define REG_MMU_FAULT_ST1 (0x134)
//same to REG_MMU_INT_MAIN_CONTROL
#define REG_MMU_TBWALK_FAULT_VA (0x138)
#define F_MMU_TBWALK_FAULT_LAYER BIT(0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_TBWALK_FAULT_BIT32 F_MSK(10, 9)
#endif
#define F_MMU_TBWALK_FAULT_BIT31_12 F_MSK(31, 12)
#define REG_MMU_FAULT_STATUS(MMU) (0x13c+((MMU)<<3))
#define F_MMU_FAULT_VA_BIT31_12 F_MSK(31, 12)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_FAULT_VA_BIT32 F_MSK(11, 9)
#endif
#define F_MMU_FAULT_PA_BIT32 F_MSK(7, 6)
#define F_MMU_FAULT_INVPA F_BIT_SET(5)
#define F_MMU_FAULT_TF F_BIT_SET(4)
#define F_MMU_FAULT_VA_WRITE_BIT F_BIT_SET(1)
#define F_MMU_FAULT_VA_LAYER_BIT F_BIT_SET(0)
#define REG_MMU_INVLD_PA(MMU) (0x140+((MMU)<<3))
#define REG_MMU_INT_ID(MMU) (0x150+((MMU)<<2))
#define F_MMU_INT_L2_SRC F_MSK(30, 28)
#define F_MMU_INT_L1_SRC F_MSK(26, 24)
#define F_MMU_INT_TF_VAL(regval) (regval & F_MSK(11, 2))
#define REG_MMU_PERF_MON_PTLB (0x180)
#define F_MMU_PERF_MON_PTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_PTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_PTLB_ID_SEL F_BIT_SET(17)
#define F_MMU_PERF_MON_PTLB_AXI_SEL F_MSK(19, 18)
#define REG_MMU_PERF_MON_MTLB(MMU) (0x190 + mmu * 0x4)
#define F_MMU_PERF_MON_MTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_MTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_MTLB_ID_SEL F_BIT_SET(17)
#define REG_MMU_PF_L1_MSCNT (0x1A0)
#define REG_MMU_PF_L2_MSCNT (0x1A4)
#define REG_MMU_PF_L1_CNT (0x1A8)
#define REG_MMU_PF_L2_CNT (0x1AC)
#define REG_MMU_ACC_CNT(MMU) (0x1C0 + MMU * 16)
#define REG_MMU_MAIN_L1_MSCNT(MMU) (0x1C4 + MMU * 16)
#define REG_MMU_MAIN_L2_MSCNT(MMU) (0x1C8 + MMU * 16)
#define REG_MMU_RS_PERF_CNT(MMU) (0x1CC + MMU * 16)
#define REG_MMU_LOOKUP_CNT(MMU) (0x1D0 + MMU * 0x20)
#define REG_MMU_PFH_VLD(VLD, WAY) (0x200 + VLD * 0x4 + WAY * 0x10)
#define F_MMU_PFH_VLD_BIT(set, way) F_BIT_SET((set)&0x1f) /* set%32 */
#define REG_MMU_RS_VA(MMU, RS) (0x380 + MMU * 0x300 + RS * 0x10)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_RS_VA_BIT32 F_MSK(1, 0)
#endif
#define F_MMU_RS_VA_TBL_ID F_MSK(5, 4)
#define F_MMU_RS_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_RS_PA(MMU, RS) (0x384 + MMU * 0x300 + RS * 0x10)
#define REG_MMU_RS_2ND_BASE(MMU, RS) (0x388 + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_2ND_BASE_MSK F_MSK(24, 0)
#define REG_MMU_RS_STA(MMU, RS) (0x38C + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_STA_IS_LTAIL BIT(0)
#define F_MMU_RS_STA_IS_LHEAD BIT(1)
#define F_MMU_RS_STA_IS_PTAIL BIT(2)
#define F_MMU_RS_STA_IS_PHEAD BIT(3)
#define F_MMU_RS_STA_PA_RDY BIT(4)
#define F_MMU_RS_STA_RDY2REQ BIT(5)
#define F_MMU_RS_STA_WRT_CMD BIT(6)
#define F_MMU_RS_STA_VLD BIT(7)
#define F_MMU_RS_STA_TO BIT(8)
#define F_MMU_RS_STA_ID F_MSK(31, 16)
#define REG_MMU_MAIN_TAG(MMU, TAG) (0x500 + MMU * 300 + TAG * 0x4)
#define F_MAIN_TLB_VA_MSK F_MSK(31, 12)
#define F_MAIN_TLB_LOCK_BIT (1<<11)
#define F_MAIN_TLB_VALID_BIT (1<<10)
#define F_MAIN_TLB_LAYER_BIT F_BIT_SET(9)
#define F_MAIN_TLB_16X_BIT F_BIT_SET(8)
#define F_MAIN_TLB_SEC_BIT F_BIT_SET(7)
#define F_MAIN_TLB_INV_DES_BIT (1<<6)
#define F_MAIN_TLB_TABLE_ID_BIT(regval) F_MSK_SHIFT(regval, 5, 4)
#define REG_MMU_MAU_SA(MMU, MAU) (0x900 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_SA_EXT(MMU, MAU) (0x904 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA(MMU, MAU) (0x908 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA_EXT(MMU, MAU) (0x90C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_LARB_EN(MMU) (0x910 + MMU * 0x100)
#define REG_MMU_MAU_PORT_EN(MMU, MAU) (0x914 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ASRT_ID(MMU, MAU) (0x918 + MMU * 0x100 + MAU * 0)
#define F_MMU_MAU_ASRT_ID_LARB(regval) F_MSK_SHIFT(regval, 9, 5)
#define F_MMU_MAU_ASRT_ID_PORT(regval) F_MSK_SHIFT(regval, 4, 0)
#define F_MMU_MAU_ASRT_ID_VAL F_MSK(9, 0)
#define REG_MMU_MAU_ADDR(MMU, MAU) (0x91C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ADDR_BIT32(MMU, MAU) (0x920 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_CLR(MMU) (0x924 + MMU * 0x100)
#define REG_MMU_MAU_IO(MMU) (0x928 + MMU * 0x100)
#define F_MAU_BIT_VAL(val, mau) F_BIT_VAL(val, mau)
#define REG_MMU_MAU_RW(MMU) (0x92C + MMU * 0x100)
#define REG_MMU_MAU_VA(MMU) (0x930 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_STA(MMU) (0x934 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_C4K(MMU) (0x938 + MMU * 0x100)
#define REG_MMU_PFH_DIST(MMU, DIST) (0xB00 + MMU * 0x80 + DIST * 0x4)
// =================== IOVA Reservation ==========================
/*
* reserved IOVA Domain for IOMMU users of HW limitation.
*/
#define MTK_IOVA_REMOVE_CNT (6)
enum mtk_reserve_region_type {
// no reserved region
IOVA_REGION_UNDEFINE,
// users cannot touch the IOVA in the reserved region
IOVA_REGION_REMOVE,
// users can only touch the IOVA in the reserved region
IOVA_REGION_STAY,
};
/*
* struct mtk_iova_domain_data: domain configuration
* @min_iova: start address of IOVAD
* @max_iova: end address of IOVAD
* @resv_start: the start address of reserved region
* @resv_size: the size of reserved region
* @resv_type: the type of reserve region
* @port_mask: the user list of IOVAD
* One user can only belongs to one IOVAD, the port mask is in unit of SMI larb.
*/
struct mtk_iova_domain_data {
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
unsigned int boundary;
#endif
unsigned long min_iova;
unsigned long max_iova;
unsigned long resv_start[MTK_IOVA_REMOVE_CNT];
unsigned long resv_size[MTK_IOVA_REMOVE_CNT];
unsigned int resv_type;
unsigned int port_mask[MTK_IOMMU_LARB_NR];
};
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#define MTK_IOVA_DOMAIN_COUNT (10) // Domain count
#define RESERVED_IOVA_ADDR_SECURE SZ_4K
#define RESERVED_IOVA_SIZE_SECURE (SZ_1G - SZ_4K)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define RESERVED_IOVA_ADDR_CCU (0x0240000000UL)
#define RESERVED_IOVA_SIZE_CCU (0x0008000000UL)
#define RESERVED_IOVA_ADDR_APU_CODE (0x0370000000UL)
#define RESERVED_IOVA_SIZE_APU_CODE (0x0010000000UL)
#define RESERVED_IOVA_ADDR_APU_DATA (0x0310000000UL)
#define RESERVED_IOVA_SIZE_APU_DATA (0x0010000000UL)
#define IOVA_ADDR_4GB (1UL << 32)
#define IOVA_ADDR_8GB (2UL << 32)
#define IOVA_ADDR_12GB (3UL << 32)
#define IOVA_ADDR_16GB (4UL << 32)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT))
{ // boundary(0~4GB) IOVA space for OVL
.boundary = 0,
.min_iova = SZ_1G,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x1ff, 0x3fff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
#else
{ // boundary(0~4GB) IOVA space for display
.boundary = 0,
.min_iova = SZ_4K,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x1ff, 0x3fff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
#endif
{ // boundary(4GB~8GB) IOVA space for CODEC
.boundary = 1,
.min_iova = IOVA_ADDR_4GB,
.max_iova = IOVA_ADDR_8GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0xfff, 0x7ffff,
0x0, 0x3ffffff, 0x7fee7fff, 0x8},
},
{ // boundary(8GB~12GB) IOVA space for CMA MDP
.boundary = 2,
.min_iova = IOVA_ADDR_8GB,
.max_iova = IOVA_ADDR_12GB - 1,
.resv_start = {RESERVED_IOVA_ADDR_CCU},
.resv_size = {RESERVED_IOVA_SIZE_CCU},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x0, 0x0, 0x3f, 0x3f, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x7fff, 0x7fff, 0x7fff, 0xf, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
{ //CCU IOVA space
.boundary = 2,
.min_iova = RESERVED_IOVA_ADDR_CCU,
.max_iova = RESERVED_IOVA_ADDR_CCU +
RESERVED_IOVA_SIZE_CCU - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x118000, 0x3},
},
{ //VPU CODE IOVA space
.boundary = 3,
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4},
},
};
#else
#define RESERVED_IOVA_ADDR_CCU (0x40000000U)
#define RESERVED_IOVA_SIZE_CCU (0x8000000U)
#define RESERVED_IOVA_ADDR_APU_CODE (0x7da00000U)
#define RESERVED_IOVA_SIZE_APU_CODE (0x4c00000U)
#define RESERVED_IOVA_ADDR_APU_DATA (0x7fc00000U)
#define RESERVED_IOVA_SIZE_APU_DATA (0x500000U)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT))
{
.min_iova = RESERVED_IOVA_ADDR_CCU +
RESERVED_IOVA_SIZE_CCU,
.max_iova = DMA_BIT_MASK(32),
.resv_start = {RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_DATA},
.resv_size = {RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_DATA},
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x1ff, 0x3fff, 0xfff, 0x7ffff,
0x0, 0x3ffffff, 0x7fee7fff, 0x0, 0x2},
},
#else
{
.min_iova = SZ_4K,
.max_iova = DMA_BIT_MASK(32),
.resv_start = {RESERVED_IOVA_ADDR_CCU,
RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_DATA},
.resv_size = {RESERVED_IOVA_SIZE_CCU,
RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_DATA},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x1ff, 0x3fff, 0xfff, 0x7ffff,
0x0, 0x3ffffff, 0x7fee7fff, 0x0, 0x2},
},
#endif
{
.min_iova = RESERVED_IOVA_ADDR_CCU,
.max_iova = RESERVED_IOVA_ADDR_CCU +
RESERVED_IOVA_SIZE_CCU - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x118000, 0x3, 0x0},
},
{
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1},
}
};
#endif
#define MTK_IOMMU_PAGE_TABLE_SHARE (1)
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mt_iommu_port.h
+353
View File
@@ -0,0 +1,353 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if IS_ENABLED(CONFIG_MACH_MT6781)
#include "../../../mt6781/include/mach/mt_iommu_port.h"
#else
#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
* this header file is only used for mtk_iomm module
* the definition of header file is platform dependency.
*/
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK
struct mtk_iommu_port {
char *name;
unsigned m4u_id: 2;
unsigned m4u_slave: 2;
unsigned larb_id: 6;
unsigned larb_port: 8;
unsigned tf_id: 14; /* 14 bits */
bool enable_tf;
mtk_iommu_fault_callback_t fault_fn;
void *fault_data;
};
#define MTK_IOMMU_PORT_INIT(name, id, slave, larb, tf_larb, port) {\
name, id, slave, larb, port, (((tf_larb)<<7)|((port)<<2)), 1\
}
#define SLAVE_L0 (0)
#define SLAVE_L1 (0)
#define SLAVE_L2 (0)
#define SLAVE_L3 (0)
#define SLAVE_L4 (0)
#define SLAVE_L5 (0)
#define SLAVE_L6 (0)
/* MM_IOMMU AXI_ID */
#define TF_LARB_L0 (0)
#define TF_LARB_L1 (4)
#define TF_LARB_L2 (8)
#define TF_LARB_L3 (12)
#define TF_LARB_L4 (0)
#define TF_LARB_L5 (16)
#define TF_LARB_L6 (28)
#define TF_LARB_CCU (24)
int mtk_iommu_larb_port_count[] = {
9, 14, 12, 19, 0,//0~4
26, 31, 2, 2 //5~8
};
int mtk_iommu_larb_distance[] = {
0, 9, 23, 35, -1, //0~4
54, 80, 111, 113, //5~8
};
struct mtk_iommu_port iommu_port[] = {
/* larb0 -MMSYS-9 */
MTK_IOMMU_PORT_INIT("DISP_POSTMASK0", 0,
SLAVE_L0, 0, TF_LARB_L0, 0),
MTK_IOMMU_PORT_INIT("DISP_OVL0_HDR", 0,
SLAVE_L0, 0, TF_LARB_L0, 1),
MTK_IOMMU_PORT_INIT("DISP_OVL1_HDR", 0,
SLAVE_L0, 0, TF_LARB_L0, 2),
MTK_IOMMU_PORT_INIT("DISP_OVL0", 0,
SLAVE_L0, 0, TF_LARB_L0, 3),
MTK_IOMMU_PORT_INIT("DISP_OVL1", 0,
SLAVE_L0, 0, TF_LARB_L0, 4),
MTK_IOMMU_PORT_INIT("DISP_PVRIC0", 0,
SLAVE_L0, 0, TF_LARB_L0, 5),
MTK_IOMMU_PORT_INIT("DISP_RDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 6),
MTK_IOMMU_PORT_INIT("DISP_WDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 7),
MTK_IOMMU_PORT_INIT("DISP_FAKE0", 0,
SLAVE_L0, 0, TF_LARB_L0, 8),
/*larb1-MMSYS-14*/
MTK_IOMMU_PORT_INIT("DISP_OVL0_2L_HDR", 0,
SLAVE_L1, 1, TF_LARB_L1, 0),
MTK_IOMMU_PORT_INIT("DISP_OVL1_2L_HDR", 0,
SLAVE_L1, 1, TF_LARB_L1, 1),
MTK_IOMMU_PORT_INIT("DISP_OVL0_2L", 0,
SLAVE_L1, 1, TF_LARB_L1, 2),
MTK_IOMMU_PORT_INIT("DISP_OVL1_2L", 0,
SLAVE_L1, 1, TF_LARB_L1, 3),
MTK_IOMMU_PORT_INIT("DISP_RDMA1", 0,
SLAVE_L1, 1, TF_LARB_L1, 4),
MTK_IOMMU_PORT_INIT("MDP_PVRIC0", 0,
SLAVE_L1, 1, TF_LARB_L1, 5),
MTK_IOMMU_PORT_INIT("MDP_PVRIC1", 0,
SLAVE_L1, 1, TF_LARB_L1, 6),
MTK_IOMMU_PORT_INIT("MDP_RDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 7),
MTK_IOMMU_PORT_INIT("MDP_RDMA1", 0,
SLAVE_L1, 1, TF_LARB_L1, 8),
MTK_IOMMU_PORT_INIT("MDP_WROT0_R", 0,
SLAVE_L1, 1, TF_LARB_L1, 9),
MTK_IOMMU_PORT_INIT("MDP_WROT0_W", 0,
SLAVE_L1, 1, TF_LARB_L1, 10),
MTK_IOMMU_PORT_INIT("MDP_WROT1_R", 0,
SLAVE_L1, 1, TF_LARB_L1, 11),
MTK_IOMMU_PORT_INIT("MDP_WROT1_W", 0,
SLAVE_L1, 1, TF_LARB_L1, 12),
MTK_IOMMU_PORT_INIT("DISP_FAKE1", 0,
SLAVE_L1, 1, TF_LARB_L1, 13),
/*larb2-VDEC-12*/
MTK_IOMMU_PORT_INIT("VDEC_MC_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 0),
MTK_IOMMU_PORT_INIT("VDEC_UFO_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 1),
MTK_IOMMU_PORT_INIT("VDEC_PP_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 2),
MTK_IOMMU_PORT_INIT("VDEC_PRED_RD_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 3),
MTK_IOMMU_PORT_INIT("VDEC_PRED_WR_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 4),
MTK_IOMMU_PORT_INIT("VDEC_PPWRAP_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 5),
MTK_IOMMU_PORT_INIT("VDEC_TILE_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 6),
MTK_IOMMU_PORT_INIT("VDEC_VLD_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 7),
MTK_IOMMU_PORT_INIT("VDEC_VLD2_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 8),
MTK_IOMMU_PORT_INIT("VDEC_AVC_MV_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 9),
MTK_IOMMU_PORT_INIT("VDEC_UFO_ENC_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 10),
MTK_IOMMU_PORT_INIT("VDEC_RG_CTRL_DMA_EXT", 0,
SLAVE_L2, 2, TF_LARB_L2, 11),
/*larb3-VENC-19*/
MTK_IOMMU_PORT_INIT("VENC_RCPU", 0,
SLAVE_L3, 3, TF_LARB_L3, 0),
MTK_IOMMU_PORT_INIT("VENC_REC", 0,
SLAVE_L3, 3, TF_LARB_L3, 1),
MTK_IOMMU_PORT_INIT("VENC_BSDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 2),
MTK_IOMMU_PORT_INIT("VENC_SV_COMV", 0,
SLAVE_L3, 3, TF_LARB_L3, 3),
MTK_IOMMU_PORT_INIT("VENC_RD_COMV", 0,
SLAVE_L3, 3, TF_LARB_L3, 4),
MTK_IOMMU_PORT_INIT("VENC_NBM_RDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 5),
MTK_IOMMU_PORT_INIT("VENC_NBM_RDMA_LITE", 0,
SLAVE_L3, 3, TF_LARB_L3, 6),
MTK_IOMMU_PORT_INIT("JPGENC_Y_RDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 7),
MTK_IOMMU_PORT_INIT("JPGENC_C_RDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 8),
MTK_IOMMU_PORT_INIT("JPGENC_Q_TABLE", 0,
SLAVE_L3, 3, TF_LARB_L3, 9),
MTK_IOMMU_PORT_INIT("JPGENC_BSDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 10),
MTK_IOMMU_PORT_INIT("JPGDEC_WDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 11),
MTK_IOMMU_PORT_INIT("JPGDEC_BSDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 12),
MTK_IOMMU_PORT_INIT("VENC_NBM_WDMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 13),
MTK_IOMMU_PORT_INIT("VENC_NBM_WDMA_LITE", 0,
SLAVE_L3, 3, TF_LARB_L3, 14),
MTK_IOMMU_PORT_INIT("VENC_CUR_LUMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 15),
MTK_IOMMU_PORT_INIT("VENC_CUR_CHROMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 16),
MTK_IOMMU_PORT_INIT("VENC_REF_LUMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 17),
MTK_IOMMU_PORT_INIT("VENC_REF_CHROMA", 0,
SLAVE_L3, 3, TF_LARB_L3, 18),
/*larb4-dummy*/
/*larb5-IMG-26*/
MTK_IOMMU_PORT_INIT("IMGI", 0,
SLAVE_L5, 5, TF_LARB_L5, 0),
MTK_IOMMU_PORT_INIT("IMG2O", 0,
SLAVE_L5, 5, TF_LARB_L5, 1),
MTK_IOMMU_PORT_INIT("IMG3O", 0,
SLAVE_L5, 5, TF_LARB_L5, 2),
MTK_IOMMU_PORT_INIT("VIPI", 0,
SLAVE_L5, 5, TF_LARB_L5, 3),
MTK_IOMMU_PORT_INIT("LCEI", 0,
SLAVE_L5, 5, TF_LARB_L5, 4),
MTK_IOMMU_PORT_INIT("SMXI", 0,
SLAVE_L5, 5, TF_LARB_L5, 5),
MTK_IOMMU_PORT_INIT("SMXO", 0,
SLAVE_L5, 5, TF_LARB_L5, 6),
MTK_IOMMU_PORT_INIT("WPE0_RDMA1", 0,
SLAVE_L5, 5, TF_LARB_L5, 7),
MTK_IOMMU_PORT_INIT("WPE0_RDMA0", 0,
SLAVE_L5, 5, TF_LARB_L5, 8),
MTK_IOMMU_PORT_INIT("WPE0_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 9),
MTK_IOMMU_PORT_INIT("FDVT_RDB", 0,
SLAVE_L5, 5, TF_LARB_L5, 10),
MTK_IOMMU_PORT_INIT("FDVT_WRA", 0,
SLAVE_L5, 5, TF_LARB_L5, 11),
MTK_IOMMU_PORT_INIT("FDVT_RDA", 0,
SLAVE_L5, 5, TF_LARB_L5, 12),
MTK_IOMMU_PORT_INIT("WPE1_RDMA0", 0,
SLAVE_L5, 5, TF_LARB_L5, 13),
MTK_IOMMU_PORT_INIT("WPE1_RDMA1", 0,
SLAVE_L5, 5, TF_LARB_L5, 14),
MTK_IOMMU_PORT_INIT("WPE1_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 15),
MTK_IOMMU_PORT_INIT("DPE_RDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 16),
MTK_IOMMU_PORT_INIT("DPE_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 17),
MTK_IOMMU_PORT_INIT("MFB_RDMA0", 0,
SLAVE_L5, 5, TF_LARB_L5, 18),
MTK_IOMMU_PORT_INIT("MFB_RDMA1", 0,
SLAVE_L5, 5, TF_LARB_L5, 19),
MTK_IOMMU_PORT_INIT("MFB_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 20),
MTK_IOMMU_PORT_INIT("RSC_RDMA0", 0,
SLAVE_L5, 5, TF_LARB_L5, 21),
MTK_IOMMU_PORT_INIT("RSC_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 22),
MTK_IOMMU_PORT_INIT("OWE_RDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 23),
MTK_IOMMU_PORT_INIT("OWE_WDMA", 0,
SLAVE_L5, 5, TF_LARB_L5, 24),
MTK_IOMMU_PORT_INIT("FDVT_WRB", 0,
SLAVE_L5, 5, TF_LARB_L5, 25),
/*larb6-IMG-31 */
MTK_IOMMU_PORT_INIT("IMGO", 0,
SLAVE_L6, 6, TF_LARB_L6, 0),
MTK_IOMMU_PORT_INIT("RRZO", 0,
SLAVE_L6, 6, TF_LARB_L6, 1),
MTK_IOMMU_PORT_INIT("AAO,", 0,
SLAVE_L6, 6, TF_LARB_L6, 2),
MTK_IOMMU_PORT_INIT("AFO,", 0,
SLAVE_L6, 6, TF_LARB_L6, 3),
MTK_IOMMU_PORT_INIT("LSCI_0", 0,
SLAVE_L6, 6, TF_LARB_L6, 4),
MTK_IOMMU_PORT_INIT("LSCI_1", 0,
SLAVE_L6, 6, TF_LARB_L6, 5),
MTK_IOMMU_PORT_INIT("PDO", 0,
SLAVE_L6, 6, TF_LARB_L6, 6),
MTK_IOMMU_PORT_INIT("BPCI", 0,
SLAVE_L6, 6, TF_LARB_L6, 7),
MTK_IOMMU_PORT_INIT("LSCO", 0,
SLAVE_L6, 6, TF_LARB_L6, 8),
MTK_IOMMU_PORT_INIT("RSSO_A", 0,
SLAVE_L6, 6, TF_LARB_L6, 9),
MTK_IOMMU_PORT_INIT("UFEO", 0,
SLAVE_L6, 6, TF_LARB_L6, 10),
MTK_IOMMU_PORT_INIT("SOCO", 0,
SLAVE_L6, 6, TF_LARB_L6, 11),
MTK_IOMMU_PORT_INIT("SOC1", 0,
SLAVE_L6, 6, TF_LARB_L6, 12),
MTK_IOMMU_PORT_INIT("SOC2", 0,
SLAVE_L6, 6, TF_LARB_L6, 13),
MTK_IOMMU_PORT_INIT("CCUI", 0,
SLAVE_L6, 6, TF_LARB_L6, 14),
MTK_IOMMU_PORT_INIT("CCUO", 0,
SLAVE_L6, 6, TF_LARB_L6, 15),
MTK_IOMMU_PORT_INIT("RAWI_A", 0,
SLAVE_L6, 6, TF_LARB_L6, 16),
MTK_IOMMU_PORT_INIT("CCUG", 0,
SLAVE_L6, 6, TF_LARB_L6, 17),
MTK_IOMMU_PORT_INIT("PS0", 0,
SLAVE_L6, 6, TF_LARB_L6, 18),
MTK_IOMMU_PORT_INIT("AFO_1", 0,
SLAVE_L6, 6, TF_LARB_L6, 19),
MTK_IOMMU_PORT_INIT("LSCI_2", 0,
SLAVE_L6, 6, TF_LARB_L6, 20),
MTK_IOMMU_PORT_INIT("PDI", 0,
SLAVE_L6, 6, TF_LARB_L6, 21),
MTK_IOMMU_PORT_INIT("FLKO", 0,
SLAVE_L6, 6, TF_LARB_L6, 22),
MTK_IOMMU_PORT_INIT("LMVO", 0,
SLAVE_L6, 6, TF_LARB_L6, 23),
MTK_IOMMU_PORT_INIT("UFGO", 0,
SLAVE_L6, 6, TF_LARB_L6, 24),
MTK_IOMMU_PORT_INIT("SPARE", 0,
SLAVE_L6, 6, TF_LARB_L6, 25),
MTK_IOMMU_PORT_INIT("SPARE2", 0,
SLAVE_L6, 6, TF_LARB_L6, 26),
MTK_IOMMU_PORT_INIT("SPARE3", 0,
SLAVE_L6, 6, TF_LARB_L6, 27),
MTK_IOMMU_PORT_INIT("SPARE4", 0,
SLAVE_L6, 6, TF_LARB_L6, 28),
MTK_IOMMU_PORT_INIT("SPARE5", 0,
SLAVE_L6, 6, TF_LARB_L6, 29),
MTK_IOMMU_PORT_INIT("FAKE_ENGINE", 0,
SLAVE_L6, 6, TF_LARB_L6, 30),
/*SMI COMMON*/
MTK_IOMMU_PORT_INIT("CCU0", 0, 0, 7, TF_LARB_CCU, 0),
MTK_IOMMU_PORT_INIT("CCU1", 0, 0, 7, TF_LARB_CCU, 1),
MTK_IOMMU_PORT_INIT("VPU_CODE", 1, 0, 8, 0, 0),
MTK_IOMMU_PORT_INIT("VPU_DATA", 1, 0, 8, 0, 1),
MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0, 0)
};
/* APU_IOMMU AXI_ID */
#define TF_IDMA_0 0x9
#define TF_CORE_0 0x1
#define TF_EDMA 0x5
#define TF_IDMA_1 0xB
#define TF_CORE_1 0x3
#define TF_EDMB 0x7
#define TF_CORE_2 0x0
#define TF_EDMC 0x2
#define MSK_IDMA_0 F_MSK(3, 0)
#define MSK_CORE_0 (F_MSK(3, 0) | F_MSK(9, 8))
#define MSK_EDMA (F_MSK(2, 0) | F_BIT_SET(9))
#define MSK_IDMA_1 F_MSK(3, 0)
#define MSK_CORE_1 (F_MSK(3, 0) | F_MSK(9, 8))
#define MSK_EDMB (F_MSK(2, 0) | F_BIT_SET(9))
#define MSK_CORE_2 (F_MSK(1, 0) | F_BIT_SET(9))
#define MSK_EDMC (F_MSK(1, 0) | F_MSK(9, 8))
#define IOMMU_APU_AXI_PORT_NR (8)
static uint32_t vpu_axi_bus_id[IOMMU_APU_AXI_PORT_NR] = {
TF_IDMA_0, TF_CORE_0, TF_EDMA, TF_IDMA_1,
TF_CORE_1, TF_EDMB, TF_CORE_2, TF_EDMC};
static uint32_t vpu_axi_bus_mask[IOMMU_APU_AXI_PORT_NR] = {
MSK_IDMA_0, MSK_CORE_0, MSK_EDMA, MSK_IDMA_1,
MSK_CORE_1, MSK_EDMB, MSK_CORE_2, MSK_EDMC};
static char *vpu_axi_bus_name[IOMMU_APU_AXI_PORT_NR] = {
"APU_IDMA0", "APU_CORE_0", "APU_EDMA",
"APU_IDMA_1", "APU_CORE_1", "APU_EDMB",
"APU_CORE_2", "APU_EDMC"};
#ifndef M4U_PORT_NR
#define M4U_PORT_NR (115)
#endif
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_battery_property.h
+278
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@@ -0,0 +1,278 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MTK_BATTERY_PROPERTY_H
#define _MTK_BATTERY_PROPERTY_H
/* customize */
#define DIFFERENCE_FULLOCV_ITH 200 /* mA */
#define MTK_CHR_EXIST 1
#define KEEP_100_PERCENT 1
#define R_FG_VALUE 5 /* mOhm */
#define EMBEDDED_SEL 0
#define PMIC_SHUTDOWN_CURRENT 20 /* 0.01 mA */
#define FG_METER_RESISTANCE 100
#define CAR_TUNE_VALUE 100 /*1.00 */
#define NO_BAT_TEMP_COMPENSATE 0
/* NO_BAT_TEMP_COMPENSATE 1 = don't need bat_temper compensate, */
/* but fg_meter_resistance still use for SWOCV */
/* enable that soc = 0 , shutdown */
#define SHUTDOWN_GAUGE0 1
/* enable that uisoc = 1 and wait xmins then shutdown */
#define SHUTDOWN_GAUGE1_XMINS 1
/* define Xmins to shutdown*/
#define SHUTDOWN_1_TIME 5
#define SHUTDOWN_GAUGE1_VBAT_EN 0
#define SHUTDOWN_GAUGE1_VBAT 34000
#define SHUTDOWN_GAUGE0_VOLTAGE 34000
#define POWERON_SYSTEM_IBOOT 500 /* mA */
/*
* LOW_TEMP_MODE = 0
* disable LOW_TEMP_MODE
* LOW_TEMP_MODE = 1
* if battery temperautre < LOW_TEMP_MODE_TEMP
* when bootup , force C mode
* LOW_TEMP_MODE = 2
* if battery temperautre < LOW_TEMP_MODE_TEMP
* force C mode
*/
#define LOW_TEMP_MODE 0
#define LOW_TEMP_MODE_TEMP 0
#define D0_SEL 0 /* not implement */
#define AGING_SEL 0 /* not implement */
#define DLPT_UI_REMAP_EN 0
/* ADC resistor */
#define R_BAT_SENSE 4
#define R_I_SENSE 4
#define R_CHARGER_1 330
#define R_CHARGER_2 39
#define QMAX_SEL 1
#define IBOOT_SEL 0
#define SHUTDOWN_SYSTEM_IBOOT 15000 /* 0.1mA */
#define PMIC_MIN_VOL 33500
/*ui_soc related */
#define DIFFERENCE_FULL_CV 1000 /*0.01%*/
#define PSEUDO1_EN 1
#define PSEUDO100_EN 1
#define PSEUDO100_EN_DIS 1
#define DIFF_SOC_SETTING 50 /* 0.01% */
#define DIFF_BAT_TEMP_SETTING 1
#define DIFF_BAT_TEMP_SETTING_C 10
#define DISCHARGE_TRACKING_TIME 10
#define CHARGE_TRACKING_TIME 60
#define DIFFERENCE_FULLOCV_VTH 1000 /* 0.1mV */
#define CHARGE_PSEUDO_FULL_LEVEL 8000
#define FULL_TRACKING_BAT_INT2_MULTIPLY 6
/* pre tracking */
#define FG_PRE_TRACKING_EN 1
#define VBAT2_DET_TIME 5
#define VBAT2_DET_COUNTER 6
#define VBAT2_DET_VOLTAGE1 34500
#define VBAT2_DET_VOLTAGE2 32000
#define VBAT2_DET_VOLTAGE3 35000
/* PCB setting */
#define CALIBRATE_CAR_TUNE_VALUE_BY_META_TOOL
#define CALI_CAR_TUNE_AVG_NUM 60
/* Aging Compensation 1*/
#define AGING_FACTOR_MIN 90
#define AGING_FACTOR_DIFF 10
#define DIFFERENCE_VOLTAGE_UPDATE 50
#define AGING_ONE_EN 1
#define AGING1_UPDATE_SOC 30
#define AGING1_LOAD_SOC 70
#define AGING_TEMP_DIFF 10
#define AGING_TEMP_LOW_LIMIT 15
#define AGING_TEMP_HIGH_LIMIT 50
#define AGING_100_EN 1
/* Aging Compensation 2*/
#define AGING_TWO_EN 1
/* Aging Compensation 3*/
#define AGING_THIRD_EN 1
#define AGING_4_EN 1
#define AGING_5_EN 1
#define AGING_6_EN 1
#define AGING4_UPDATE_SOC 40
#define AGING4_LOAD_SOC 70
#define AGING5_UPDATE_SOC 30
#define AGING5_LOAD_SOC 70
#define AGING6_UPDATE_SOC 30
#define AGING6_LOAD_SOC 70
/* threshold */
#define HWOCV_SWOCV_DIFF 300
#define HWOCV_SWOCV_DIFF_LT 1500
#define HWOCV_SWOCV_DIFF_LT_TEMP 5
#define HWOCV_OLDOCV_DIFF 300
#define HWOCV_OLDOCV_DIFF_CHR 800
#define SWOCV_OLDOCV_DIFF 300
#define SWOCV_OLDOCV_DIFF_CHR 800
#define VBAT_OLDOCV_DIFF 1000
#define SWOCV_OLDOCV_DIFF_EMB 1000 /* 100mV */
#define VIR_OLDOCV_DIFF_EMB 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_LT 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_TMP 5
#define TNEW_TOLD_PON_DIFF 5
#define TNEW_TOLD_PON_DIFF2 15
#define PMIC_SHUTDOWN_TIME 30
#define BAT_PLUG_OUT_TIME 32
#define EXT_HWOCV_SWOCV 300
#define EXT_HWOCV_SWOCV_LT 1500
#define EXT_HWOCV_SWOCV_LT_TEMP 5
/* fgc & fgv threshold */
#define DIFFERENCE_FGC_FGV_TH1 300
#define DIFFERENCE_FGC_FGV_TH2 500
#define DIFFERENCE_FGC_FGV_TH3 300
#define DIFFERENCE_FGC_FGV_TH_SOC1 7000
#define DIFFERENCE_FGC_FGV_TH_SOC2 3000
#define NAFG_TIME_SETTING 10
#define NAFG_RATIO 100
#define NAFG_RATIO_EN 0
#define NAFG_RATIO_TMP_THR 1
#define NAFG_RESISTANCE 1500
#define PMIC_SHUTDOWN_SW_EN 1
#define FORCE_VC_MODE 0 /* 0: mix, 1:Coulomb, 2:voltage */
#define LOADING_1_EN 0
#define LOADING_2_EN 2
#define DIFF_IAVG_TH 3000
/* ZCV INTR */
#define ZCV_SUSPEND_TIME 3
#define SLEEP_CURRENT_AVG 200 /*0.1mA*/
#define ZCV_COM_VOL_LIMIT 50 /* 50mv */
#define ZCV_CAR_GAP_PERCENTAGE 5
/* Additional battery table */
#define ADDITIONAL_BATTERY_TABLE_EN 1
#define DC_RATIO_SEL 5
#define DC_R_CNT 1000 /* if set 0, dcr_start will not be 1*/
#define BAT_PAR_I 4000 /* not implement */
#define PSEUDO1_SEL 2
#define FG_TRACKING_CURRENT 30000 /* not implement */
#define FG_TRACKING_CURRENT_IBOOT_EN 0 /* not implement */
#define UI_FAST_TRACKING_EN 0
#define UI_FAST_TRACKING_GAP 300
#define KEEP_100_PERCENT_MINSOC 9000
#define SHUTDOWN_CONDITION_LOW_BAT_VOLT
#define LOW_TEMP_DISABLE_LOW_BAT_SHUTDOWN 1
#define LOW_TEMP_THRESHOLD 5
#define BATTERY_TMP_TO_DISABLE_GM30 -50
#define BATTERY_TMP_TO_DISABLE_NAFG -35
#define DEFAULT_BATTERY_TMP_WHEN_DISABLE_NAFG 25
#define BATTERY_TMP_TO_ENABLE_NAFG -20
/* #define GM30_DISABLE_NAFG */
#define POWER_ON_CAR_CHR 5
#define POWER_ON_CAR_NOCHR -35
#define SHUTDOWN_CAR_RATIO 1
#define MULTI_TEMP_GAUGE0 1 /* different temp using different gauge 0% */
#define OVER_DISCHARGE_LEVEL -1500
#define UISOC_UPDATE_TYPE 0
/*
* uisoc_update_type:
* 0: only ui_soc interrupt update ui_soc
* 1: coulomb/nafg will update ui_soc if delta car > ht/lt_gap /2
* 2: coulomb/nafg will update ui_soc
*/
/* using current to limit uisoc in 100% case*/
/* UI_FULL_LIMIT_ITH0 3000 means 300ma */
#define UI_FULL_LIMIT_EN 0
#define UI_FULL_LIMIT_SOC0 9900
#define UI_FULL_LIMIT_ITH0 2200
#define UI_FULL_LIMIT_SOC1 9900
#define UI_FULL_LIMIT_ITH1 2200
#define UI_FULL_LIMIT_SOC2 9900
#define UI_FULL_LIMIT_ITH2 2200
#define UI_FULL_LIMIT_SOC3 9900
#define UI_FULL_LIMIT_ITH3 2200
#define UI_FULL_LIMIT_SOC4 9900
#define UI_FULL_LIMIT_ITH4 2200
#define UI_FULL_LIMIT_TIME 99999
#define UI_FULL_LIMIT_FC_SOC0 9900
#define UI_FULL_LIMIT_FC_ITH0 3000
#define UI_FULL_LIMIT_FC_SOC1 9900
#define UI_FULL_LIMIT_FC_ITH1 3100
#define UI_FULL_LIMIT_FC_SOC2 9900
#define UI_FULL_LIMIT_FC_ITH2 3200
#define UI_FULL_LIMIT_FC_SOC3 9900
#define UI_FULL_LIMIT_FC_ITH3 3300
#define UI_FULL_LIMIT_FC_SOC4 9900
#define UI_FULL_LIMIT_FC_ITH4 3400
/* using voltage to limit uisoc in 1% case */
/* UI_LOW_LIMIT_VTH0=36000 means 3.6v */
#define UI_LOW_LIMIT_EN 0
#define UI_LOW_LIMIT_SOC0 200
#define UI_LOW_LIMIT_VTH0 34500
#define UI_LOW_LIMIT_SOC1 200
#define UI_LOW_LIMIT_VTH1 34500
#define UI_LOW_LIMIT_SOC2 200
#define UI_LOW_LIMIT_VTH2 34500
#define UI_LOW_LIMIT_SOC3 200
#define UI_LOW_LIMIT_VTH3 34500
#define UI_LOW_LIMIT_SOC4 200
#define UI_LOW_LIMIT_VTH4 34500
#define UI_LOW_LIMIT_TIME 99999
#define MOVING_BATTEMP_EN 1
#define MOVING_BATTEMP_THR 20
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_battery_table.h
+4204
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File diff suppressed because it is too large. Load diff
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_clkmgr.h
+12
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MT_CLKMGR_H
#define _MT_CLKMGR_H
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_cpufreq_api.h
+83
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@@ -0,0 +1,83 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cpu_freq(int cpu, int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void mt_cpufreq_ctrl_cci_volt(unsigned int volt);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
extern unsigned int mt_cpufreq_find_Vboot_idx(unsigned int cluster_id);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_cci_freq_idx(void);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
extern void mt_cpufreq_update_cci_mode(unsigned int mode, unsigned int use_id);
#endif /* __MTK_CPUFREQ_API_H__ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_eem_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_EEM_API_H__
#define __MT_EEM_API_H__
/* DRCC */
extern void drcc_fail_composite(void);
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_fhreg.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_FHREG_H__
#define __MT_FHREG_H__
#include <linux/bitops.h>
/* #include <mach/mt_reg_base.h> */
/* **************************************************** */
/* IP base address */
/* **************************************************** */
#ifdef CONFIG_ARM64
#define REG_ADDR(x) ((unsigned long)g_fhctl_base + (x))
#define REG_MCU_FHCTL_ADDR(x) ((unsigned long)g_mcu_fhctl_base + (x))
#define REG_APMIX_ADDR(x) ((unsigned long)g_apmixed_base + (x))
#define REG_MCUMIX_ADDR(x) ((unsigned long)g_mcumixed_base + (x))
#else
#define REG_ADDR(x) ((unsigned int)g_fhctl_base + (x))
#define REG_MCU_FHCTL_ADDR(x) ((unsigned int)g_mcu_fhctl_base + (x))
#define REG_APMIX_ADDR(x) ((unsigned int)g_apmixed_base + (x))
#define REG_MCUMIX_ADDR(x) ((unsigned int)g_mcumixed_base + (x))
#endif
/* **************************************************** */
/* FHCTL register */
/* **************************************************** */
#define REG_FHCTL_HP_EN REG_ADDR(0x0000)
#define REG_FHCTL_CLK_CON REG_ADDR(0x0004)
#define REG_FHCTL_RST_CON REG_ADDR(0x0008)
#define REG_FHCTL_SLOPE0 REG_ADDR(0x000C)
#define REG_FHCTL_SLOPE1 REG_ADDR(0x0010)
#define REG_FHCTL_DSSC_CFG REG_ADDR(0x0014)
#define REG_FHCTL_DSSC0_CON REG_ADDR(0x0018)
#define REG_FHCTL_DSSC1_CON REG_ADDR(0x001C)
#define REG_FHCTL_DSSC2_CON REG_ADDR(0x0020)
#define REG_FHCTL_DSSC3_CON REG_ADDR(0x0024)
#define REG_FHCTL_DSSC4_CON REG_ADDR(0x0028)
#define REG_FHCTL_DSSC5_CON REG_ADDR(0x002C)
#define REG_FHCTL_DSSC6_CON REG_ADDR(0x0030)
#define REG_FHCTL_DSSC7_CON REG_ADDR(0x0034)
#define REG_FHCTL0_CFG REG_ADDR(0x0038)
#define REG_FHCTL0_UPDNLMT REG_ADDR(0x003C)
#define REG_FHCTL0_DDS REG_ADDR(0x0040)
#define REG_FHCTL0_DVFS REG_ADDR(0x0044)
#define REG_FHCTL0_MON REG_ADDR(0x0048)
#define REG_FHCTL1_CFG REG_ADDR(0x004C)
#define REG_FHCTL1_UPDNLMT REG_ADDR(0x0050)
#define REG_FHCTL1_DDS REG_ADDR(0x0054)
#define REG_FHCTL1_DVFS REG_ADDR(0x0058)
#define REG_FHCTL1_MON REG_ADDR(0x005C)
#define REG_FHCTL2_CFG REG_ADDR(0x0060)
#define REG_FHCTL2_UPDNLMT REG_ADDR(0x0064)
#define REG_FHCTL2_DDS REG_ADDR(0x0068)
#define REG_FHCTL2_DVFS REG_ADDR(0x006C)
#define REG_FHCTL2_MON REG_ADDR(0x0070)
#define REG_FHCTL3_CFG REG_ADDR(0x0074)
#define REG_FHCTL3_UPDNLMT REG_ADDR(0x0078)
#define REG_FHCTL3_DDS REG_ADDR(0x007C)
#define REG_FHCTL3_DVFS REG_ADDR(0x0080)
#define REG_FHCTL3_MON REG_ADDR(0x0084)
#define REG_FHCTL4_CFG REG_ADDR(0x0088)
#define REG_FHCTL4_UPDNLMT REG_ADDR(0x008C)
#define REG_FHCTL4_DDS REG_ADDR(0x0090)
#define REG_FHCTL4_DVFS REG_ADDR(0x0094)
#define REG_FHCTL4_MON REG_ADDR(0x0098)
#define REG_FHCTL5_CFG REG_ADDR(0x009C)
#define REG_FHCTL5_UPDNLMT REG_ADDR(0x00A0)
#define REG_FHCTL5_DDS REG_ADDR(0x00A4)
#define REG_FHCTL5_DVFS REG_ADDR(0x00A8)
#define REG_FHCTL5_MON REG_ADDR(0x00AC)
#define REG_FHCTL6_CFG REG_ADDR(0x00B0)
#define REG_FHCTL6_UPDNLMT REG_ADDR(0x00B4)
#define REG_FHCTL6_DDS REG_ADDR(0x00B8)
#define REG_FHCTL6_DVFS REG_ADDR(0x00BC)
#define REG_FHCTL6_MON REG_ADDR(0x00C0)
#define REG_FHCTL7_CFG REG_ADDR(0x00C4)
#define REG_FHCTL7_UPDNLMT REG_ADDR(0x00C8)
#define REG_FHCTL7_DDS REG_ADDR(0x00CC)
#define REG_FHCTL7_DVFS REG_ADDR(0x00D0)
#define REG_FHCTL7_MON REG_ADDR(0x00D4)
#define REG_FHCTL8_CFG REG_ADDR(0x00D8)
#define REG_FHCTL8_UPDNLMT REG_ADDR(0x00DC)
#define REG_FHCTL8_DDS REG_ADDR(0x00E0)
#define REG_FHCTL8_DVFS REG_ADDR(0x00E4)
#define REG_FHCTL8_MON REG_ADDR(0x00E8)
#define REG_FHCTL9_CFG REG_ADDR(0x00EC)
#define REG_FHCTL9_UPDNLMT REG_ADDR(0x00F0)
#define REG_FHCTL9_DDS REG_ADDR(0x00F4)
#define REG_FHCTL9_DVFS REG_ADDR(0x00F8)
#define REG_FHCTL9_MON REG_ADDR(0x00FC)
#define REG_FHCTL10_CFG REG_ADDR(0x0100)
#define REG_FHCTL10_UPDNLMT REG_ADDR(0x0104)
#define REG_FHCTL10_DDS REG_ADDR(0x0108)
#define REG_FHCTL10_DVFS REG_ADDR(0x010C)
#define REG_FHCTL10_MON REG_ADDR(0x0110)
#define REG_FHCTL11_CFG REG_ADDR(0x0114)
#define REG_FHCTL11_UPDNLMT REG_ADDR(0x0118)
#define REG_FHCTL11_DDS REG_ADDR(0x011C)
#define REG_FHCTL11_DVFS REG_ADDR(0x0120)
#define REG_FHCTL11_MON REG_ADDR(0x0124)
/* **************************************************** */
/* APMIXED CON0/CON1 Register */
/* **************************************************** */
#define REG_PLL_NOT_SUPPORT 0xdeadbeef
/*CON0, PLL enable status */
#define REG_ARMPLL1_CON0 REG_APMIX_ADDR(0x0200)
#define REG_ARMPLL2_CON0 REG_APMIX_ADDR(0x0210)
#define REG_ARMPLL3_CON0 REG_PLL_NOT_SUPPORT /* not support in 63 */
#define REG_CCIPLL_CON0 REG_APMIX_ADDR(0x0290)
/* change name to MFGPLL in 63*/
#define REG_GPUPLL_CON0 REG_APMIX_ADDR(0x0240)
#define REG_MPLL_CON0 REG_APMIX_ADDR(0x0280)
#define REG_MEMPLL_CON0 REG_PLL_NOT_SUPPORT /* dram use MPLL */
#define REG_MAINPLL_CON0 REG_APMIX_ADDR(0x0220)
#define REG_MSDCPLL_CON0 REG_APMIX_ADDR(0x0250)
#define REG_MMPLL_CON0 REG_APMIX_ADDR(0x0270)
#define REG_VDECPLL_CON0 REG_PLL_NOT_SUPPORT /* not support in 63 */
#define REG_TVDPLL_CON0 REG_APMIX_ADDR(0x0260)
/*CON1, DDS value */
#define REG_ARMPLL1_CON1 REG_APMIX_ADDR(0x0204)
#define REG_ARMPLL2_CON1 REG_APMIX_ADDR(0x0214)
#define REG_ARMPLL3_CON1 REG_PLL_NOT_SUPPORT /* not support in 63 */
#define REG_CCIPLL_CON1 REG_APMIX_ADDR(0x0294)
/* change name to MFGPLL in 63*/
#define REG_GPUPLL_CON1 REG_APMIX_ADDR(0x0244)
#define REG_MPLL_CON1 REG_APMIX_ADDR(0x0284)
#define REG_MEMPLL_CON1 REG_PLL_NOT_SUPPORT /* dram use MPLL */
#define REG_MAINPLL_CON1 REG_APMIX_ADDR(0x0224)
#define REG_MSDCPLL_CON1 REG_APMIX_ADDR(0x0254)
#define REG_MMPLL_CON1 REG_APMIX_ADDR(0x0274)
#define REG_VDECPLL_CON1 REG_PLL_NOT_SUPPORT /* not support in 63 */
#define REG_TVDPLL_CON1 REG_APMIX_ADDR(0x0264)
#define REG_FH_PLL0_CON0 REG_ARMPLL1_CON0
#define REG_FH_PLL1_CON0 REG_ARMPLL2_CON0
#define REG_FH_PLL2_CON0 REG_ARMPLL3_CON0
#define REG_FH_PLL3_CON0 REG_CCIPLL_CON0
#define REG_FH_PLL4_CON0 REG_GPUPLL_CON0
#define REG_FH_PLL5_CON0 REG_MPLL_CON0
#define REG_FH_PLL6_CON0 REG_MEMPLL_CON0
#define REG_FH_PLL7_CON0 REG_MAINPLL_CON0
#define REG_FH_PLL8_CON0 REG_MSDCPLL_CON0
#define REG_FH_PLL9_CON0 REG_MMPLL_CON0
#define REG_FH_PLL10_CON0 REG_VDECPLL_CON0
#define REG_FH_PLL11_CON0 REG_TVDPLL_CON0
#define REG_FH_PLL0_CON1 REG_ARMPLL1_CON1
#define REG_FH_PLL1_CON1 REG_ARMPLL2_CON1
#define REG_FH_PLL2_CON1 REG_ARMPLL3_CON1
#define REG_FH_PLL3_CON1 REG_CCIPLL_CON1
#define REG_FH_PLL4_CON1 REG_GPUPLL_CON1
#define REG_FH_PLL5_CON1 REG_MPLL_CON1
#define REG_FH_PLL6_CON1 REG_MEMPLL_CON1
#define REG_FH_PLL7_CON1 REG_MAINPLL_CON1
#define REG_FH_PLL8_CON1 REG_MSDCPLL_CON1
#define REG_FH_PLL9_CON1 REG_MMPLL_CON1
#define REG_FH_PLL10_CON1 REG_VDECPLL_CON1
#define REG_FH_PLL11_CON1 REG_TVDPLL_CON1
/***************************************************** */
/* **************************************************** */
/* FHCTL Register mask */
/* **************************************************** */
#define MASK_FRDDSX_DYS (0xFU<<20)
#define MASK_FRDDSX_DTS (0xFU<<16)
#define FH_FHCTLX_MON_SEL (0x1U<<5)
#define FH_FHCTLX_PAUSE (0x1U<<4)
#define FH_FHCTLX_CFG_PAUSE (0x1U<<4)
#define FH_DYSSCX_EN (0x1U<<3)
#define FH_SFSTRX_EN (0x1U<<2)
#define FH_FRDDSX_EN (0x1U<<1)
#define FH_FHCTLX_EN (0x1U<<0)
#define FH_FRDDSX_DNLMT (0xFFU<<16)
#define FH_FRDDSX_UPLMT (0xFFU)
#define FH_FHCTLX_PLL_TGL_ORG (0x1U<<31)
#define FH_FHCTLX_PLL_ORG (0xFFFFFU)
#define FH_MON_FHCTLX_PAUSE (0x1U<<31)
#define FH_MON_FHCTLX_PRD (0x1U<<30)
#define FH_MON_SFSTRX_PRD (0x1U<<29)
#define FH_MON_FRDDSX_PRD (0x1U<<28)
#define FH_FHCTLX_STATE (0xFU<<24)
#define FH_FHCTLX_PLL_DDS (0xFFFFFFU)
/* **************************************************** */
/* Macro */
/* **************************************************** */
static inline unsigned int uffs(unsigned int x)
{
unsigned int r = 1;
if (!x)
return 0;
if (!(x & 0xffff)) {
x >>= 16;
r += 16;
}
if (!(x & 0xff)) {
x >>= 8;
r += 8;
}
if (!(x & 0xf)) {
x >>= 4;
r += 4;
}
if (!(x & 3)) {
x >>= 2;
r += 2;
}
if (!(x & 1)) {
x >>= 1;
r += 1;
}
return r;
}
#define fh_read8(reg) readb(reg)
#define fh_read16(reg) readw(reg)
#define fh_read32(reg) readl((void __iomem *)reg)
#define fh_write8(reg, val) mt_reg_sync_writeb((val), (reg))
#define fh_write16(reg, val) mt_reg_sync_writew((val), (reg))
#define fh_write32(reg, val) mt_reg_sync_writel((val), (reg))
#define fh_set_field(reg, field, val) \
do { \
unsigned int tv = fh_read32(reg); \
tv &= ~(field); \
tv |= ((val) << (uffs((unsigned int)field) - 1)); \
fh_write32(reg, tv); \
} while (0)
#define fh_get_field(reg, field, val) \
do { \
unsigned int tv = fh_read32(reg); \
val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
} while (0)
#endif /* #ifndef __MT_FHREG_H__ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_mdpm_api.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MTK_MDPM_API_H_
#define _MTK_MDPM_API_H_
#include <mach/mtk_pmic.h>
#include <mach/mtk_pbm.h>
enum mdpm_power_type {
MAX_POWER = 0,
AVG_POWER,
POWER_TYPE_NUM
};
enum pbm_kicker {
KR_DLPT, /* 0 */
KR_MD1, /* 1 */
KR_MD3, /* 2 */
KR_CPU, /* 3 */
KR_GPU, /* 4 */
KR_FLASH /* 5 */
};
extern void init_md_section_level(enum pbm_kicker kicker);
extern int get_md1_power(enum mdpm_power_type power_type, bool need_update);
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_pbm.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MT_PBM_
#define _MT_PBM_
/* #include <cust_pmic.h> */
#include <mach/mtk_pmic.h>
#include <mach/mtk_mdpm_api.h>
#ifdef DISABLE_DLPT_FEATURE
#define DISABLE_PBM_FEATURE
#endif
extern void kicker_pbm_by_dlpt(unsigned int i_max);
extern void kicker_pbm_by_md(enum pbm_kicker kicker, bool status);
extern void kicker_pbm_by_cpu(unsigned int loading, int core, int voltage);
extern void kicker_pbm_by_gpu(bool status, unsigned int loading, int voltage);
extern void kicker_pbm_by_flash(bool status);
#ifndef DISABLE_PBM_FEATURE
extern int g_dlpt_stop;
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_pmic.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _CUST_PMIC_H_
#define _CUST_PMIC_H_
/*#define PMIC_VDVFS_CUST_ENABLE*/
#define LOW_POWER_LIMIT_LEVEL_1 15
#define PT_DLPT_BRINGUP 0
#if defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP
/* Define for disable low battery protect feature,
* default no define for enable low battery protect.
*/
#define DISABLE_LOW_BATTERY_PROTECT
/*Define for disable battery OC protect*/
#define DISABLE_BATTERY_OC_PROTECT
/*Define for disable battery 15% protect*/
#define DISABLE_BATTERY_PERCENT_PROTECT
/*Define for DLPT*/
#define DISABLE_DLPT_FEATURE
#endif /* defined(CONFIG_FPGA_EARLY_PORTING) || PT_DLPT_BRINGUP */
/* if not support GM3, disable DLPT */
#if defined(CONFIG_MTK_DISABLE_GAUGE)
#define DISABLE_DLPT_FEATURE
#endif /* defined(CONFIG_MTK_DISABLE_GAUGE) */
#ifndef DISABLE_LOW_BATTERY_PROTECT
#if defined(CONFIG_MACH_MT6781)
#define LBAT_LIMIT_BCPU_OPP
#endif
#endif
#define POWER_UVLO_VOLT_LEVEL 2600
#define IMAX_MAX_VALUE 5500
#define POWER_INT0_VOLT 3400
#define POWER_INT1_VOLT 3250
#define POWER_INT2_VOLT 3100
#define POWER_INT0_VOLT_EXT 3700
#define POWER_INT1_VOLT_EXT 3550
#define POWER_INT2_VOLT_EXT 1000
#define POWER_BAT_OC_CURRENT_H 5800
#define POWER_BAT_OC_CURRENT_L 6300
#define DLPT_POWER_OFF_EN
#define POWEROFF_BAT_CURRENT 3000
#define DLPT_POWER_OFF_THD 100
#define DLPT_VOLT_MIN 3100
#define BATTERY_MODULE_INIT
/* ADC Channel Number, not uesed and removed */
extern const char *pmic_auxadc_channel_name[];
/* Legacy pmic auxadc interface */
#if defined(CONFIG_MTK_PMIC_CHIP_MT6358)
/* for CONFIG_MACH_MT6781 */
enum {
AUXADC_LIST_BATADC,
AUXADC_LIST_START = AUXADC_LIST_BATADC,
AUXADC_LIST_VCDT,
AUXADC_LIST_BATTEMP,
AUXADC_LIST_VBIF,
AUXADC_LIST_CHIP_TEMP,
AUXADC_LIST_DCXO,
AUXADC_LIST_ACCDET,
AUXADC_LIST_TSX,
AUXADC_LIST_HPOFS_CAL,
AUXADC_LIST_VCORE_TEMP,
AUXADC_LIST_VPROC_TEMP,
AUXADC_LIST_VGPU_TEMP,
AUXADC_LIST_DCXO_VOLT,
AUXADC_LIST_END = AUXADC_LIST_DCXO_VOLT,
AUXADC_LIST_ISENSE,
};
#else
enum {
AUXADC_LIST_BATADC,
AUXADC_LIST_START = AUXADC_LIST_BATADC,
AUXADC_LIST_VCDT,
AUXADC_LIST_BATTEMP,
AUXADC_LIST_CHIP_TEMP,
AUXADC_LIST_VCORE_TEMP,
AUXADC_LIST_VPROC_TEMP,
AUXADC_LIST_VGPU_TEMP,
AUXADC_LIST_ACCDET,
AUXADC_LIST_VDCXO,
AUXADC_LIST_TSX_TEMP,
AUXADC_LIST_HPOFS_CAL,
AUXADC_LIST_DCXO_TEMP,
AUXADC_LIST_VBIF,
AUXADC_LIST_END = AUXADC_LIST_VBIF,
AUXADC_LIST_ISENSE,
};
#endif
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_dump_regs(char *buf);
extern int pmic_get_auxadc_channel_max(void);
extern int mt_get_auxadc_value(u8 channel);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
#endif /* _CUST_PMIC_H_ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_pmic_ipi.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MT_PMIC_IPI_H_
#define _MT_PMIC_IPI_H_
#if defined(CONFIG_MACH_MT6781)
/* SSPM V2 */
unsigned int pmic_ipi_config_interface(unsigned int RegNum, unsigned int val,
unsigned int MASK, unsigned int SHIFT,
unsigned char _unused);
#else
void pmic_ipi_write_test(void);
#ifdef CONFIG_MTK_EXTBUCK
enum { /* must compatible with sspm EXTBUCK ID */
EXTBUCK_ID_GPU,
EXTBUCK_ID_PROC2,
EXTBUCK_ID_PROC1,
};
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en);
#else
int extbuck_ipi_enable(unsigned char buck_id, unsigned char en)
{
return -1;
}
#endif /* CONFIG_MTK_EXTBUCK */
unsigned int pmic_ipi_read_interface(unsigned int RegNum,
unsigned int *val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_ipi_config_interface(unsigned int RegNum,
unsigned int val,
unsigned int MASK,
unsigned int SHIFT,
unsigned char lock);
unsigned int pmic_regulator_profiling(unsigned char type);
unsigned int sub_pmic_ipi_interface(unsigned int type, unsigned int ctrl);
unsigned int mt6311_ipi_set_mode(unsigned char mode);
#endif /* CONFIG_MACH_MT6781 */
#endif /* _MT_PMIC_IPI_H_*/
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_pmic_wrap.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_PMIC_WRAP_H__
#define __MT_PMIC_WRAP_H__
/* #include <mach/typedefs.h> */
/* #include <linux/smp.h> */
#include <linux/types.h>
#include <linux/device.h>
#include <mach/upmu_hw.h>
struct mt_pmic_wrap_driver {
struct device_driver driver;
s32 (*wacs2_hal)(u32 write, u32 adr, u32 wdata, u32 *rdata);
s32 (*show_hal)(char *buf);
s32 (*store_hal)(const char *buf, size_t count);
s32 (*suspend)(void);
void (*resume)(void);
};
#define PWRAP_READ 0
#define PWRAP_WRITE 1
/* ------external API for pmic_wrap user------------------------ */
s32 pwrap_read(u32 adr, u32 *rdata);
s32 pwrap_write(u32 adr, u32 wdata);
s32 pwrap_wacs2(u32 write, u32 adr, u32 wdata, u32 *rdata);
/*_____________ROME only_____________________________________________*/
/********************************************************************/
#define PWRAP_TRACE
#ifdef CONFIG_FPGA_EARLY_PORTING
#define tracepwrap(addr, wdata)
#else /*--!CONFIG_FPGA_EARLY_PORTING --*/
extern unsigned int gPWRAPHCK;
extern unsigned int gPWRAPDBGADDR;
#define PWRAP_HCK_LEVEL 4
#define tracepwrap(addr, wdata) do { \
if (gPWRAPHCK >= PWRAP_HCK_LEVEL) \
if (addr == gPWRAPDBGADDR) { \
unsigned int rdata; \
pwrap_read(addr, &rdata); \
pr_notice("addr = 0x%x, wdata = 0x%x, rdata = 0x%x\n", \
addr, wdata, rdata); \
WARN_ON(1); \
} \
} while (0)
#endif /*--End of CONFIG_FPGA_EARLY_PORTING --*/
/********************************************************************/
/********************************************************************/
/* return value : EINT_STA: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/********************************************************************/
u32 pmic_wrap_eint_status(void);
/********************************************************************/
/* set value(W1C) : EINT_CLR: [0]: CPU IRQ status in MT6331 */
/* [1]: MD32 IRQ status in MT6331 */
/* [2]: CPU IRQ status in MT6332 */
/* [3]: RESERVED */
/* para: offset is shift of clear bit which needs to clear */
/********************************************************************/
void pmic_wrap_eint_clr(int offset);
/*--------------------------------------------------------------------*/
u32 mt_pmic_wrap_eint_status(void);
void mt_pmic_wrap_eint_clr(int offset);
s32 pwrap_init(void);
struct mt_pmic_wrap_driver *get_mt_pmic_wrap_drv(void);
/* MTS debug only */
void pwrap_dump_all_register(void);
/* dump ap/pmic register and recovery WACS2 */
void pwrap_dump_and_recovery(void);
#endif /* __MT_PMIC_WRAP_H__ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/mtk_pwm_hal.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __MT_PWM_HAL_H__
#define __MT_PWM_HAL_H__
#include <linux/types.h>
#include <mt-plat/sync_write.h>
/**********************************
* Global enum data
*/
/******************* Register Manipulations*****************/
#define INREG32(reg) __raw_readl((void *)reg)
#define OUTREG32(reg, val) mt_reg_sync_writel(val, (void *)reg)
#define OUTREG32_DMA(reg, val) ((*(long *)(reg)) = (long)(val))
#define SETREG32(reg, val) OUTREG32(reg, INREG32(reg)|(val))
#define CLRREG32(reg, val) OUTREG32(reg, INREG32(reg)&~(val))
#define MASKREG32(x, y, z) OUTREG32(x, (INREG32(x)&~(y))|(z))
enum PWN_NO {
PWM_MIN,
PWM1 = PWM_MIN,
PWM2,
PWM3,
PWM4,
PWM_NUM,
PWM_MAX = PWM_NUM
};
enum TEST_SEL_BIT {
TEST_SEL_FALSE,
TEST_SEL_TRUE
};
enum PWM_CON_MODE_BIT {
PERIOD,
RAND
};
enum PWM_CON_SRCSEL_BIT {
PWM_FIFO,
MEMORY
};
enum PWM_CON_IDLE_BIT {
IDLE_FALSE,
IDLE_TRUE,
IDLE_MAX
};
enum PWM_CON_GUARD_BIT {
GUARD_FALSE,
GUARD_TRUE,
GUARD_MAX
};
enum OLD_MODE_BIT {
OLDMODE_DISABLE,
OLDMODE_ENABLE
};
enum PWM_BUF_VALID_BIT {
BUF0_VALID,
BUF0_EN_VALID,
BUF1_VALID,
BUF1_EN_VALID,
BUF_EN_MAX
};
enum CLOCK_SRC {
CLK_BLOCK,
CLK_BLOCK_BY_1625_OR_32K
};
enum PWM_CLK_DIV {
CLK_DIV_MIN,
CLK_DIV1 = CLK_DIV_MIN,
CLK_DIV2,
CLK_DIV4,
CLK_DIV8,
CLK_DIV16,
CLK_DIV32,
CLK_DIV64,
CLK_DIV128,
CLK_DIV_MAX
};
enum PWM_INT_ENABLE_BITS {
PWM1_INT_FINISH_EN,
PWM1_INT_UNDERFLOW_EN,
PWM2_INT_FINISH_EN,
PWM2_INT_UNDERFLOW_EN,
PWM3_INT_FINISH_EN,
PWM3_INT_UNDERFLOW_EN,
PWM4_INT_FINISH_EN,
PWM4_INT_UNDERFLOW_EN,
PWM_INT_ENABLE_BITS_MAX,
};
enum PWM_INT_STATUS_BITS {
PWM1_INT_FINISH_ST,
PWM1_INT_UNDERFLOW_ST,
PWM2_INT_FINISH_ST,
PWM2_INT_UNDERFLOW_ST,
PWM3_INT_FINISH_ST,
PWM3_INT_UNDERFLOW_ST,
PWM4_INT_FINISH_ST,
PWM4_INT_UNDERFLOW_ST,
PWM_INT_STATUS_BITS_MAX,
};
enum PWM_INT_ACK_BITS {
PWM1_INT_FINISH_ACK,
PWM1_INT_UNDERFLOW_ACK,
PWM2_INT_FINISH_ACK,
PWM2_INT_UNDERFLOW_ACK,
PWM3_INT_FINISH_ACK,
PWM3_INT_UNDERFLOW_ACK,
PWM4_INT_FINISH_ACK,
PWM4_INT_UNDERFLOW_ACK,
PWM_INT_ACK_BITS_MAX,
};
enum PWM_CLOCK_SRC_ENUM {
PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_BLOCK = PWM_CLK_SRC_MIN,
PWM_CLK_OLD_MODE_32K,
PWM_CLK_NEW_MODE_BLOCK,
PWM_CLK_NEW_MODE_BLOCK_DIV_BY_1625,
PWM_CLK_SRC_NUM,
PWM_CLK_SRC_INVALID,
};
enum PWM_MODE_ENUM {
PWM_MODE_MIN,
PWM_MODE_OLD = PWM_MODE_MIN,
PWM_MODE_FIFO,
PWM_MODE_MEMORY,
PWM_MODE_RANDOM,
PWM_MODE_DELAY,
PWM_MODE_INVALID,
};
enum INFRA_CLK_SRC_CTRL {
CLK_32K = 0x00,
CLK_26M = 0x01,
CLK_78M = 0x2,
CLK_SEL_TOPCKGEN = 0x3,
};
#define PWM_NEW_MODE_DUTY_TOTAL_BITS 64
void mt_set_pwm_3dlcm_enable_hal(u8 enable);
void mt_set_pwm_3dlcm_inv_hal(u32 pwm_no, u8 inv);
void mt_set_pwm_3dlcm_base_hal(u32 pwm_no);
void mt_pwm_26M_clk_enable_hal(u32 enable);
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/pseudo_m4u.h
+306
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if IS_ENABLED(CONFIG_MACH_MT6781)
#include "../../../mt6781/include/mach/pseudo_m4u.h"
#else
#ifndef __PSEUDO_M4U_H__
#define __PSEUDO_M4U_H__
#include <linux/ioctl.h>
#include <linux/fs.h>
#if IS_ENABLED(CONFIG_DEBUG_FS)
#include <linux/debugfs.h>
#endif
#if IS_ENABLED(CONFIG_PROC_FS)
#include <linux/proc_fs.h>
#endif
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/iova.h>
#include <linux/iommu.h>
#include <dt-bindings/memory/mt6785-larb-port.h>
#if (defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
defined(CONFIG_MICROTRUST_TEE_SUPPORT)) && \
defined(CONFIG_MTK_TEE_GP_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define PSEUDO_M4U_TEE_SERVICE_ENABLE
#endif
#endif
#if defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define M4U_MTEE_SERVICE_ENABLE
#endif
#endif
#define M4U_PAGE_SIZE 0x1000
#define M4U_DEVNAME "m4u"
#define TOTAL_M4U_NUM 2
#define M4U_REG_SIZE 0x5e0
#ifndef SMI_LARB_NR
#define SMI_LARB_NR (7)
#endif
#define M4U_PAGE_MASK 0xfff
/* public flags */
/* engine access this buffer in sequncial way. */
#define M4U_FLAGS_SEQ_ACCESS (1<<0)
/* fix allocation, we will use mva user specified. */
#define M4U_FLAGS_FIX_MVA (1<<1)
/* the mva will share in SWd */
#define M4U_FLAGS_SEC_SHAREABLE (1<<2)
/* the allocator will search free mva from user specified. */
#define M4U_FLAGS_START_FROM (1<<3)
#define M4U_FLAGS_SG_READY (1<<4)
#ifdef CONFIG_MTK_IOMMU_V2
#define M4U_FLAGS_TO_ACP (1<<5)
#endif
/* port related: virtuality, security, distance */
struct M4U_PORT_STRUCT {
int ePortID;
unsigned int Virtuality;
unsigned int Security;
unsigned int domain; /*domain : 0 1 2 3*/
unsigned int Distance;
unsigned int Direction; /* 0:- 1:+*/
char *name;
};
/* module related: alloc/dealloc MVA buffer */
struct M4U_MOUDLE_STRUCT {
int port;
unsigned long BufAddr;
unsigned long BufSize;
unsigned int prot;
unsigned long MVAStart;
unsigned long MVAEnd;
unsigned int flags;
};
struct mva_info_t {
struct list_head link;
unsigned long bufAddr;
unsigned long mvaStart;
unsigned long size;
int eModuleId;
unsigned int flags;
int security;
int cache_coherent;
unsigned int mapped_kernel_va_for_debug;
};
struct m4u_buf_info_t {
struct list_head link;
unsigned long va;
unsigned long mva;
unsigned long size;
int port;
unsigned int prot;
unsigned int flags;
struct sg_table *sg_table;
unsigned long mva_align;
unsigned long size_align;
int seq_id;
unsigned long mapped_kernel_va_for_debug;
unsigned long long timestamp;
char task_comm[TASK_COMM_LEN];
pid_t pid;
};
struct m4u_client_t {
/* mutex to protect mvaList */
/* should get this mutex whenever add/delete/interate mvaList */
struct mutex dataMutex;
pid_t open_pid;
pid_t open_tgid;
struct list_head mvaList;
};
struct port_mva_info_t {
int module_id;
unsigned long va;
unsigned long buf_size;
int security;
int cache_coherent;
unsigned int flags;
unsigned int iova_start;
unsigned int iova_end;
unsigned long mva;
};
#if IS_ENABLED(CONFIG_PROC_FS)
#define DEFINE_PROC_ATTRIBUTE(__fops, __get, __set, __fmt) \
static int __fops ## _open(struct inode *inode, struct file *file) \
{ \
struct inode local_inode = *inode; \
\
local_inode.i_private = PDE_DATA(inode); \
__simple_attr_check_format(__fmt, 0ull); \
return simple_attr_open(&local_inode, file, __get, __set, __fmt); \
} \
static const struct file_operations __fops = { \
.owner = THIS_MODULE, \
.open = __fops ## _open, \
.release = simple_attr_release, \
.read = simple_attr_read, \
.write = simple_attr_write, \
.llseek = generic_file_llseek, \
}
#endif
struct m4u_device {
struct proc_dir_entry *m4u_dev_proc_entry;
#if IS_ENABLED(CONFIG_DEBUG_FS)
struct dentry *debug_root;
#endif
#if IS_ENABLED(CONFIG_PROC_FS)
struct proc_dir_entry *proc_root;
#endif
};
/* we use this for trace the mva<-->sg_table relation ship */
struct mva_sglist {
struct list_head list;
unsigned long mva;
struct sg_table *table;
};
struct m4u_port_array {
#define M4U_PORT_ATTR_EN (1<<0)
#define M4U_PORT_ATTR_VIRTUAL (1<<1)
#define M4U_PORT_ATTR_SEC (1<<2)
unsigned char ports[M4U_PORT_NR];
};
extern unsigned long max_pfn;
extern unsigned char *pMlock_cnt;
extern unsigned int mlock_cnt_size;
extern unsigned long pagetable_pa;
struct sg_table *m4u_create_sgtable(unsigned long va, unsigned long size);
int m4u_dealloc_mva_sg(int eModuleID,
struct sg_table *sg_table,
const unsigned long BufSize,
const unsigned long MVA);
int m4u_alloc_mva_sg(struct port_mva_info_t *port_info,
struct sg_table *sg_table);
int m4u_mva_map_kernel(unsigned long mva, unsigned long size,
unsigned long *map_va, unsigned long *map_size);
int m4u_mva_unmap_kernel(unsigned long mva, unsigned long size,
unsigned long va);
#ifndef IOVA_PFN
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
#endif
int pseudo_get_reg_of_path(unsigned int port, bool is_va,
unsigned int *reg, unsigned int *mask,
unsigned int *value);
int m4u_config_port(struct M4U_PORT_STRUCT *pM4uPort);
int m4u_get_boundary(int port);
int pseudo_config_port_tee(int kernelport);
int m4u_switch_acp(unsigned int port,
unsigned long iova, size_t size, bool is_acp);
static inline bool m4u_enable_4G(void)
{
return (max_pfn > (0xffffffffUL >> PAGE_SHIFT));
}
struct iova *__alloc_iova(struct iova_domain *iovad, size_t size,
dma_addr_t dma_limit);
void __free_iova(struct iova_domain *iovad, struct iova *iova);
void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr);
int pseudo_m4u_sec_init(int mtk_iommu_sec_id);
/* IOCTL commnad */
#define MTK_M4U_MAGICNO 'g'
#define MTK_M4U_T_POWER_ON _IOW(MTK_M4U_MAGICNO, 0, int)
#define MTK_M4U_T_POWER_OFF _IOW(MTK_M4U_MAGICNO, 1, int)
#define MTK_M4U_T_DUMP_REG _IOW(MTK_M4U_MAGICNO, 2, int)
#define MTK_M4U_T_DUMP_INFO _IOW(MTK_M4U_MAGICNO, 3, int)
#define MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define MTK_M4U_T_CONFIG_PORT _IOW(MTK_M4U_MAGICNO, 6, int)
#define MTK_M4U_T_MONITOR_START _IOW(MTK_M4U_MAGICNO, 7, int)
#define MTK_M4U_T_MONITOR_STOP _IOW(MTK_M4U_MAGICNO, 8, int)
#define MTK_M4U_T_DUMP_PAGETABLE _IOW(MTK_M4U_MAGICNO, 9, int)
#define MTK_M4U_T_CONFIG_PORT_ARRAY _IOW(MTK_M4U_MAGICNO, 10, int)
#define MTK_M4U_T_CONFIG_MAU _IOW(MTK_M4U_MAGICNO, 11, int)
#define MTK_M4U_T_CONFIG_TF _IOW(MTK_M4U_MAGICNO, 12, int)
#define MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#if IS_ENABLED(CONFIG_COMPAT)
struct COMPAT_M4U_MOUDLE_STRUCT {
compat_uint_t port;
compat_ulong_t BufAddr;
compat_ulong_t BufSize;
compat_uint_t prot;
compat_ulong_t MVAStart;
compat_ulong_t MVAEnd;
compat_uint_t flags;
};
#define COMPAT_MTK_M4U_T_ALLOC_MVA _IOWR(MTK_M4U_MAGICNO, 4, int)
#define COMPAT_MTK_M4U_T_DEALLOC_MVA _IOW(MTK_M4U_MAGICNO, 5, int)
#define COMPAT_MTK_M4U_T_SEC_INIT _IOW(MTK_M4U_MAGICNO, 50, int)
#endif
#ifdef M4U_MTEE_SERVICE_ENABLE
extern bool m4u_tee_en;
int smi_reg_restore_sec(void);
int smi_reg_backup_sec(void);
/*int m4u_config_port_array_tee(unsigned char* port_array);*/
int m4u_dump_secpgd(unsigned int port, unsigned long faultmva);
#endif
int pseudo_debug_init(struct m4u_device *data);
int pseudo_get_iova_space(int port,
unsigned long *base, unsigned long *max,
struct list_head *list);
void pseudo_put_iova_space(int port,
struct list_head *list);
void m4u_dump_pgtable(unsigned int level);
void __m4u_dump_pgtable(struct seq_file *s, unsigned int level,
bool lock);
int pseudo_dump_port(int port);
int pseudo_dump_all_port_status(struct seq_file *s);
int pseudo_dump_iova_reserved_region(struct seq_file *s);
/* =========== register defination =========== */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define SMI_LARB_NON_SEC_CONx(larb_port) (0x380 + ((larb_port)<<2))
#define F_SMI_NON_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_MMU_EN F_BIT_SET(0)
#define F_SMI_ADDR_BIT32 F_MSK(15, 8)
#define F_SMI_ADDR_BIT32_VAL(regval) F_MSK_SHIFT(regval, 15, 8)
#define SMI_LARB_SEC_CONx(larb_port) (0xf80 + ((larb_port)<<2))
#define F_SMI_SEC_MMU_EN(en) F_BIT_VAL(en, 0)
#define F_SMI_SEC_EN(sec) F_BIT_VAL(sec, 1)
#define F_SMI_DOMN(domain) F_VAL(domain, 8, 4)
#define F_SMI_DOMN_VAL(regval) F_MSK_SHIFT(regval, 8, 4)
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/pseudo_m4u_plat.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if IS_ENABLED(CONFIG_MACH_MT6781)
#include "../../../mt6781/include/mach/pseudo_m4u_plat.h"
#else
#ifndef __PSEUDO_M4U_PLAT_H__
#define __PSEUDO_M4U_PLAT_H__
struct pseudo_device {
struct device *dev; /* record the device for config mmu use. */
int larbid; /* the larb id of this device*/
bool mmuen; /* whether this larb have been configed. */
const char *name;
int port[32];
};
struct pseudo_device pseudo_dev_larb[SMI_LARB_NR];
struct pseudo_device pseudo_dev_larb_fake[] = {
{
.larbid = MISC_PSEUDO_LARBID_DISP,
.port = {
M4U_PORT_DISP_FAKE0, -1},
.name = "misc",
},
{
.larbid = M4U_LARB_CCU,
.port = {
M4U_PORT_CCU0,
M4U_PORT_CCU1, -1},
.name = "ccu_disp",
},
{
.larbid = M4U_LARB_APU,
.port = {
M4U_PORT_VPU, -1},
.name = "apu_code",
},
{
.larbid = APU_PSEUDO_LARBID_DATA,
.port = {
M4U_PORT_VPU_DATA, -1},
.name = "apu_data",
},
};
static char *pseudo_larbname[] = {
"mediatek,smi_larb0", "mediatek,smi_larb1", "mediatek,smi_larb2",
"mediatek,smi_larb3", "m4u_none", "mediatek,smi_larb5",
"mediatek,smi_larb6",
};
char *pseudo_larb_clk_name[] = {
"m4u_smi_larb0", "m4u_smi_larb1", "m4u_smi_larb2", "m4u_smi_larb3",
"m4u_none", "m4u_smi_larb5", "m4u_smi_larb6",
};
unsigned int pseudo_acp_port_array[] = {M4U_PORT_APU};
static inline int m4u_port_id_of_mdp(
unsigned int larb, unsigned int port)
{
if (larb == 1 &&
port >= 5 &&
port <= 12)
return 1;
else
return 0;
}
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/upmu_hw.h
+39352
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drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/upmu_sw.h
+557
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef _MT_PMIC_UPMU_SW_H_
#define _MT_PMIC_UPMU_SW_H_
#include <mach/upmu_hw.h>
#define AUXADC_SUPPORT_IMM_CURRENT_MODE
#define BATTERY_SW_INIT
#define RBAT_PULL_UP_VOLT_BY_BIF
/* #define INIT_BAT_CUR_FROM_PTIM */
#define FG_RG_INT_EN_CHRDET INT_CHRDET
#define FG_RG_INT_EN_BAT2_H INT_BAT2_H
#define FG_RG_INT_EN_BAT2_L INT_BAT2_L
#define FG_RG_INT_EN_BAT_TEMP_H INT_BAT_TEMP_H
#define FG_RG_INT_EN_BAT_TEMP_L INT_BAT_TEMP_L
#define FG_RG_INT_EN_NAG_C_DLTV INT_NAG_C_DLTV
#if defined(CONFIG_MTK_PMIC_CHIP_MT6358)
/* for CONFIG_MACH_MT6781 */
#define FG_BAT0_INT_H_NO INT_FG_BAT0_H
#define FG_BAT0_INT_L_NO INT_FG_BAT0_L
#define FG_BAT_INT_H_NO INT_FG_BAT0_H
#define FG_BAT_INT_L_NO INT_FG_BAT0_L
#define FG_BAT1_INT_H_NO INT_FG_BAT1_H
#define FG_BAT1_INT_L_NO INT_FG_BAT1_L
#else
#define FG_BAT0_INT_H_NO INT_FG_BAT_H
#define FG_BAT0_INT_L_NO INT_FG_BAT_L
#define FG_BAT_INT_H_NO INT_FG_BAT_H
#define FG_BAT_INT_L_NO INT_FG_BAT_L
#define FG_BAT1_INT_H_NO INT_FG_BAT_H
#define FG_BAT1_INT_L_NO INT_FG_BAT_L
#endif
#define FG_CUR_H_NO INT_FG_CUR_H
#define FG_CUR_L_NO INT_FG_CUR_L
#define FG_ZCV_NO INT_FG_ZCV
#define FG_N_CHARGE_L_NO INT_FG_N_CHARGE_L
#define FG_IAVG_H_NO INT_FG_IAVG_H
#define FG_IAVG_L_NO INT_FG_IAVG_L
#if defined(CONFIG_MTK_PMIC_CHIP_MT6358)
/* for CONFIG_MACH_MT6781 */
#define FG_TIME_NO INT_FG_TIME_H
#else
#define FG_TIME_NO INT_ENUM_MAX
#endif
#define FG_BAT_PLUGOUT_NO INT_BATON_BAT_OUT
/* =============================================================================
* Low battery level define
* =============================================================================
*/
#define LOW_BATTERY_LEVEL enum LOW_BATTERY_LEVEL_TAG
#define LOW_BATTERY_PRIO enum LOW_BATTERY_PRIO_TAG
enum LOW_BATTERY_LEVEL_TAG {
LOW_BATTERY_LEVEL_0 = 0,
LOW_BATTERY_LEVEL_1 = 1,
LOW_BATTERY_LEVEL_2 = 2
};
enum LOW_BATTERY_PRIO_TAG {
LOW_BATTERY_PRIO_CPU_B = 0,
LOW_BATTERY_PRIO_CPU_L = 1,
LOW_BATTERY_PRIO_GPU = 2,
LOW_BATTERY_PRIO_MD = 3,
LOW_BATTERY_PRIO_MD5 = 4,
LOW_BATTERY_PRIO_FLASHLIGHT = 5,
LOW_BATTERY_PRIO_VIDEO = 6,
LOW_BATTERY_PRIO_WIFI = 7,
LOW_BATTERY_PRIO_BACKLIGHT = 8
};
extern void (*low_battery_callback)(LOW_BATTERY_LEVEL tag);
extern void register_low_battery_notify(
void (*low_battery_callback)(LOW_BATTERY_LEVEL tag),
LOW_BATTERY_PRIO prio_val);
extern void register_low_battery_notify_ext(
void (*low_battery_callback)(LOW_BATTERY_LEVEL tag),
LOW_BATTERY_PRIO prio_val);
/* =============================================================================
* Battery OC level define
* =============================================================================
*/
#define BATTERY_OC_LEVEL enum BATTERY_OC_LEVEL_TAG
#define BATTERY_OC_PRIO enum BATTERY_OC_PRIO_TAG
enum BATTERY_OC_LEVEL_TAG {
BATTERY_OC_LEVEL_0 = 0,
BATTERY_OC_LEVEL_1 = 1
};
enum BATTERY_OC_PRIO_TAG {
BATTERY_OC_PRIO_CPU_B = 0,
BATTERY_OC_PRIO_CPU_L = 1,
BATTERY_OC_PRIO_GPU = 2,
BATTERY_OC_PRIO_MD = 3,
BATTERY_OC_PRIO_MD5 = 4,
BATTERY_OC_PRIO_FLASHLIGHT = 5,
BATTERY_OC_PRIO_CHARGER = 6
};
extern void (*battery_oc_callback)(BATTERY_OC_LEVEL tag);
extern void register_battery_oc_notify(
void (*battery_oc_callback)(BATTERY_OC_LEVEL tag),
BATTERY_OC_PRIO prio_val);
/* =============================================================================
* Battery percent define
* =============================================================================
*/
#define BATTERY_PERCENT_LEVEL enum BATTERY_PERCENT_LEVEL_TAG
#define BATTERY_PERCENT_PRIO enum BATTERY_PERCENT_PRIO_TAG
enum BATTERY_PERCENT_LEVEL_TAG {
BATTERY_PERCENT_LEVEL_0 = 0,
BATTERY_PERCENT_LEVEL_1 = 1
};
enum BATTERY_PERCENT_PRIO_TAG {
BATTERY_PERCENT_PRIO_CPU_B = 0,
BATTERY_PERCENT_PRIO_CPU_L = 1,
BATTERY_PERCENT_PRIO_GPU = 2,
BATTERY_PERCENT_PRIO_MD = 3,
BATTERY_PERCENT_PRIO_MD5 = 4,
BATTERY_PERCENT_PRIO_FLASHLIGHT = 5,
BATTERY_PERCENT_PRIO_VIDEO = 6,
BATTERY_PERCENT_PRIO_WIFI = 7,
BATTERY_PERCENT_PRIO_BACKLIGHT = 8
};
extern void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL tag);
extern void
register_battery_percent_notify(
void (*battery_percent_callback)(BATTERY_PERCENT_LEVEL tag),
BATTERY_PERCENT_PRIO prio_val);
/*=============================================================================
* DLPT define
*=============================================================================
*/
#define DLPT_PRIO enum DLPT_PRIO_TAG
enum DLPT_PRIO_TAG {
DLPT_PRIO_PBM = 0,
DLPT_PRIO_CPU_B = 1,
DLPT_PRIO_CPU_L = 2,
DLPT_PRIO_GPU = 3,
DLPT_PRIO_MD = 4,
DLPT_PRIO_MD5 = 5,
DLPT_PRIO_FLASHLIGHT = 6,
DLPT_PRIO_VIDEO = 7,
DLPT_PRIO_WIFI = 8,
DLPT_PRIO_BACKLIGHT = 9
};
extern void (*dlpt_callback)(unsigned int val);
extern void register_dlpt_notify(
void (*dlpt_callback)(unsigned int val), DLPT_PRIO prio_val);
extern const PMU_FLAG_TABLE_ENTRY pmu_flags_table[];
extern unsigned short is_battery_remove;
extern unsigned short is_wdt_reboot_pmic;
extern unsigned short is_wdt_reboot_pmic_chk;
/*=============================================================================
* PMIC IRQ ENUM define
*=============================================================================
*/
#if defined(CONFIG_MTK_PMIC_CHIP_MT6358) && defined(CONFIG_MACH_MT6781)
enum PMIC_IRQ_ENUM {
INT_VPROC11_OC,
SP_BUCK_TOP_START = INT_VPROC11_OC,
INT_VPROC12_OC,
INT_VCORE_OC,
INT_VGPU_OC,
INT_VMODEM_OC,
INT_VDRAM1_OC,
INT_VS1_OC,
INT_VS2_OC,
INT_VPA_OC,
INT_VCORE_PREOC,
NO_USE_0_10,
NO_USE_0_11,
NO_USE_0_12,
NO_USE_0_13,
NO_USE_0_14,
NO_USE_0_15,
INT_VFE28_OC,
SP_LDO_TOP_START = INT_VFE28_OC,
INT_VXO22_OC,
INT_VRF18_OC,
INT_VRF12_OC,
INT_VEFUSE_OC,
INT_VCN33_OC,
INT_VCN28_OC,
INT_VCN18_OC,
INT_VM18_OC,
INT_VMDDR_OC,
INT_VSRAM_CORE_OC,
NO_USE_1_11,
NO_USE_1_12,
INT_VA12_OC,
INT_VAUX18_OC,
INT_VAUD28_OC,
INT_VIO28_OC,
INT_VIO18_OC,
INT_VSRAM_PROC11_OC,
INT_VSRAM_PROC12_OC,
INT_VSRAM_OTHERS_OC,
INT_VSRAM_GPU_OC,
INT_VDRAM2_OC,
INT_VMC_OC,
INT_VMCH_OC,
INT_VEMC_OC,
INT_VSIM1_OC,
INT_VSIM2_OC,
INT_VIBR_OC,
INT_VUSB_OC,
INT_VBIF28_OC,
NO_USE_2_15,
INT_PWRKEY,
SP_PSC_TOP_START = INT_PWRKEY,
INT_HOMEKEY,
INT_PWRKEY_R,
INT_HOMEKEY_R,
INT_NI_LBAT_INT,
INT_CHRDET,
INT_CHRDET_EDGE,
INT_VCDT_HV_DET,
NO_USE_3_8,
NO_USE_3_9,
NO_USE_3_10,
NO_USE_3_11,
NO_USE_3_12,
NO_USE_3_13,
NO_USE_3_14,
NO_USE_3_15,
INT_RTC,
SP_SCK_TOP_START = INT_RTC,
NO_USE_4_1,
NO_USE_4_2,
NO_USE_4_3,
NO_USE_4_4,
NO_USE_4_5,
NO_USE_4_6,
NO_USE_4_7,
NO_USE_4_8,
NO_USE_4_9,
NO_USE_4_10,
NO_USE_4_11,
NO_USE_4_12,
NO_USE_4_13,
NO_USE_4_14,
NO_USE_4_15,
INT_FG_BAT0_H,
SP_BM_TOP_START = INT_FG_BAT0_H,
INT_FG_BAT0_L,
INT_FG_CUR_H,
INT_FG_CUR_L,
INT_FG_ZCV,
INT_FG_BAT1_H,
INT_FG_BAT1_L,
INT_FG_N_CHARGE_L,
INT_FG_IAVG_H,
INT_FG_IAVG_L,
INT_FG_TIME_H,
INT_FG_DISCHARGE,
INT_FG_CHARGE,
NO_USE_5_13,
NO_USE_5_14,
NO_USE_5_15,
INT_BATON_LV,
INT_BATON_HT,
INT_BATON_BAT_IN,
INT_BATON_BAT_OUT,
INT_BIF,
NO_USE_6_5,
NO_USE_6_6,
NO_USE_6_7,
NO_USE_6_8,
NO_USE_6_9,
NO_USE_6_10,
NO_USE_6_11,
NO_USE_6_12,
NO_USE_6_13,
NO_USE_6_14,
NO_USE_6_15,
INT_BAT_H,
SP_HK_TOP_START = INT_BAT_H,
INT_BAT_L,
INT_BAT2_H,
INT_BAT2_L,
INT_BAT_TEMP_H,
INT_BAT_TEMP_L,
INT_AUXADC_IMP,
INT_NAG_C_DLTV,
NO_USE_7_8,
NO_USE_7_9,
NO_USE_7_10,
NO_USE_7_11,
NO_USE_7_12,
NO_USE_7_13,
NO_USE_7_14,
NO_USE_7_15,
INT_AUDIO,
SP_AUD_TOP_START = INT_AUDIO,
NO_USE_8_1,
NO_USE_8_2,
NO_USE_8_3,
NO_USE_8_4,
INT_ACCDET,
INT_ACCDET_EINT0,
INT_ACCDET_EINT1,
NO_USE_8_8,
NO_USE_8_9,
NO_USE_8_10,
NO_USE_8_11,
NO_USE_8_12,
NO_USE_8_13,
NO_USE_8_14,
NO_USE_8_15,
INT_SPI_CMD_ALERT,
SP_MISC_TOP_START = INT_SPI_CMD_ALERT,
NO_USE_9_1,
NO_USE_9_2,
NO_USE_9_3,
NO_USE_9_4,
NO_USE_9_5,
NO_USE_9_6,
NO_USE_9_7,
NO_USE_9_8,
NO_USE_9_9,
NO_USE_9_10,
NO_USE_9_11,
NO_USE_9_12,
NO_USE_9_13,
NO_USE_9_14,
NO_USE_9_15,
INT_ENUM_MAX,
};
#else
enum PMIC_IRQ_ENUM {
INT_VPU_OC,
SP_BUCK_TOP_START = INT_VPU_OC,
INT_VCORE_OC,
INT_VGPU11_OC,
INT_VGPU12_OC,
INT_VMODEM_OC,
INT_VPROC1_OC,
INT_VPROC2_OC,
INT_VS1_OC,
INT_VS2_OC,
INT_VPA_OC,
NO_USE_0_10,
NO_USE_0_11,
NO_USE_0_12,
NO_USE_0_13,
NO_USE_0_14,
NO_USE_0_15,
INT_VFE28_OC,
SP_LDO_TOP_START = INT_VFE28_OC,
INT_VXO22_OC,
INT_VRF18_OC,
INT_VRF12_OC,
INT_VEFUSE_OC,
INT_VCN33_1_OC,
INT_VCN33_2_OC,
INT_VCN13_OC,
INT_VCN18_OC,
INT_VA09_OC,
INT_VCAMIO_OC,
INT_VA12_OC,
INT_VAUX18_OC,
INT_VAUD18_OC,
INT_VIO18_OC,
INT_VSRAM_PROC1_OC,
INT_VSRAM_PROC2_OC,
INT_VSRAM_OTHERS_OC,
INT_VSRAM_MD_OC,
INT_VEMC_OC,
INT_VSIM1_OC,
INT_VSIM2_OC,
INT_VUSB_OC,
INT_VRFCK_OC,
INT_VBBCK_OC,
INT_VBIF28_OC,
INT_VIBR_OC,
INT_VIO28_OC,
INT_VM18_OC,
INT_VUFS_OC,
NO_USE_2_14,
NO_USE_2_15,
INT_PWRKEY,
SP_PSC_TOP_START = INT_PWRKEY,
INT_HOMEKEY,
INT_PWRKEY_R,
INT_HOMEKEY_R,
INT_NI_LBAT_INT,
INT_CHRDET_EDGE,
NO_USE_3_6,
NO_USE_3_7,
NO_USE_3_8,
NO_USE_3_9,
NO_USE_3_10,
NO_USE_3_11,
NO_USE_3_12,
NO_USE_3_13,
NO_USE_3_14,
NO_USE_3_15,
INT_RTC,
SP_SCK_TOP_START = INT_RTC,
NO_USE_4_1,
NO_USE_4_2,
NO_USE_4_3,
NO_USE_4_4,
NO_USE_4_5,
NO_USE_4_6,
NO_USE_4_7,
NO_USE_4_8,
NO_USE_4_9,
NO_USE_4_10,
NO_USE_4_11,
NO_USE_4_12,
NO_USE_4_13,
NO_USE_4_14,
NO_USE_4_15,
INT_FG_BAT_H,
SP_BM_TOP_START = INT_FG_BAT_H,
INT_FG_BAT_L,
INT_FG_CUR_H,
INT_FG_CUR_L,
INT_FG_ZCV,
NO_USE_5_5,
NO_USE_5_6,
INT_FG_N_CHARGE_L,
INT_FG_IAVG_H,
INT_FG_IAVG_L,
NO_USE_5_10,
INT_FG_DISCHARGE,
INT_FG_CHARGE,
NO_USE_5_13,
NO_USE_5_14,
NO_USE_5_15,
INT_BATON_LV,
NO_USE_6_1,
INT_BATON_BAT_IN,
INT_BATON_BAT_OUT,
INT_BIF,
NO_USE_6_5,
NO_USE_6_6,
NO_USE_6_7,
NO_USE_6_8,
NO_USE_6_9,
NO_USE_6_10,
NO_USE_6_11,
NO_USE_6_12,
NO_USE_6_13,
NO_USE_6_14,
NO_USE_6_15,
INT_BAT_H,
SP_HK_TOP_START = INT_BAT_H,
INT_BAT_L,
INT_BAT2_H,
INT_BAT2_L,
INT_BAT_TEMP_H,
INT_BAT_TEMP_L,
INT_THR_H,
INT_THR_L,
INT_AUXADC_IMP,
INT_NAG_C_DLTV,
NO_USE_7_10,
NO_USE_7_11,
NO_USE_7_12,
NO_USE_7_13,
NO_USE_7_14,
NO_USE_7_15,
INT_AUDIO,
SP_AUD_TOP_START = INT_AUDIO,
NO_USE_8_1,
NO_USE_8_2,
NO_USE_8_3,
NO_USE_8_4,
INT_ACCDET,
INT_ACCDET_EINT0,
INT_ACCDET_EINT1,
NO_USE_8_8,
NO_USE_8_9,
NO_USE_8_10,
NO_USE_8_11,
NO_USE_8_12,
NO_USE_8_13,
NO_USE_8_14,
NO_USE_8_15,
INT_SPI_CMD_ALERT,
SP_MISC_TOP_START = INT_SPI_CMD_ALERT,
NO_USE_9_1,
NO_USE_9_2,
NO_USE_9_3,
NO_USE_9_4,
NO_USE_9_5,
NO_USE_9_6,
NO_USE_9_7,
NO_USE_9_8,
NO_USE_9_9,
NO_USE_9_10,
NO_USE_9_11,
NO_USE_9_12,
NO_USE_9_13,
NO_USE_9_14,
NO_USE_9_15,
INT_ENUM_MAX,
};
#endif
/*=============================================================================
* PMIC auxadc define
*=============================================================================
*/
extern signed int g_I_SENSE_offset;
extern void pmic_auxadc_init(void);
extern void pmic_auxadc_lock(void);
extern void pmic_auxadc_unlock(void);
extern void mt_power_off(void);
/*=============================================================================
* PMIC fg define
*=============================================================================
*/
extern unsigned int bat_get_ui_percentage(void);
extern signed int fgauge_read_v_by_d(int d_val);
extern signed int fgauge_read_r_bat_by_v(signed int voltage);
extern signed int fgauge_read_IM_current(void *data);
extern void kpd_pwrkey_pmic_handler(unsigned long pressed);
extern void kpd_pmic_rstkey_handler(unsigned long pressed);
extern int is_mt6311_sw_ready(void);
extern int is_mt6311_exist(void);
extern int get_mt6311_i2c_ch_num(void);
/*extern bool crystal_exist_status(void);*/
#if defined CONFIG_MTK_LEGACY
extern void pmu_drv_tool_customization_init(void);
#endif
extern int batt_init_cust_data(void);
extern void PMIC_INIT_SETTING_V1(void);
extern int do_ptim_ex(bool isSuspend, unsigned int *bat, signed int *cur);
#endif /* _MT_PMIC_UPMU_SW_H_ */
drivers/misc/mediatek/include/mt-plat/mt6785/include/mach/wd_api.h
+12
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#if defined(CONFIG_MTK_WATCHDOG_COMMON)
/* use common wd api */
#include <mt-plat/mtk_wd_api.h>
#else
#error "watchdog: common wd_api.h shall be used."
#endif
drivers/misc/mediatek/include/mt-plat/mt6785/include/trustzone/m4u/tz_m4u.h
+207
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@@ -0,0 +1,207 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016 MediaTek Inc.
*/
#ifndef __TZ_M4U_H__
#define __TZ_M4U_H__
/* #include "drStd.h" */
#ifdef CONFIG_MTK_PSEUDO_M4U
#include "mach/mt_iommu.h"
#else
#include "m4u_port.h"
#endif
#if defined(__cplusplus)
extern "C" {
#endif
/* #define __M4U_SECURE_SYSTRACE_ENABLE__ */
#define M4U_NONSEC_MVA_START (0x40000000)
#define CMD_M4U_MAGIC (0x77880000)
enum m4u_cmd {
CMD_M4U_ADD = CMD_M4U_MAGIC,
CMD_M4U_CFG_PORT,
CMD_M4U_MAP_NONSEC_BUFFER,
CMD_M4U_SEC_INIT,
CMD_M4U_ALLOC_MVA,
CMD_M4U_DEALLOC_MVA,
CMD_M4U_REG_BACKUP,
CMD_M4U_REG_RESTORE,
CMD_M4U_PRINT_PORT,
CMD_M4U_DUMP_SEC_PGTABLE,
CMD_M4UTL_INIT,
CMD_M4U_OPEN_SESSION,
CMD_M4U_CLOSE_SESSION,
CMD_M4U_CFG_PORT_ARRAY,
CMD_M4U_SYSTRACE_MAP,
CMD_M4U_SYSTRACE_UNMAP,
CMD_M4U_SYSTRACE_TRANSACT,
CMD_M4U_LARB_BACKUP,
CMD_M4U_LARB_RESTORE,
CMD_M4U_UNMAP_NONSEC_BUFFER,
CMD_M4U_GET_RESERVED_MEMORY,
CMD_M4U_GET_SEC_MEM,
CMD_M4U_NUM,
/* Add for m4u in MTEE*/
CMD_M4UTY_INIT,
CMD_M4UTY_CFG_PORT_SEC,
CMD_M4UTY_CFG_PORT_ARRAY,
CMD_M4UTY_MAP_NONSEC_BUFFER,
CMD_M4UTY_UNMAP_NONSEC_BUFFER,
CMD_M4UTY_ALLOC_MVA_SEC_NOIPC,
CMD_M4UTY_DEALLOC_MVA_SEC_NOIPC,
CMD_M4UTY_ALLOC_MVA_SEC,
CMD_M4UTY_DEALLOC_MVA_SEC,
CMD_M4UTY_GET_SEC_MEM,
};
#define M4U_RET_OK 0
#define M4U_RET_UNKNOWN_CMD -1
#define M4U_RET_NO_PERM -2
#define EXIT_ERROR ((uint32_t)(-1))
struct m4u_add_param {
int a;
int b;
int result;
};
#define M4U_SIN_NAME_LEN 12
struct m4u_session_param {
int sid;
char name[M4U_SIN_NAME_LEN];
};
struct m4u_cfg_port_param {
int port;
int virt;
int sec;
int distance;
int direction;
};
struct m4u_buf_param {
int port;
unsigned int mva;
unsigned int size;
unsigned long long pa;
};
#define TZ_M4U_MAX_MEM_CHUNK_NR 2
struct m4u_sec_mem_param {
uint64_t pa[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t sz[TZ_M4U_MAX_MEM_CHUNK_NR];
uint64_t mva[TZ_M4U_MAX_MEM_CHUNK_NR];
unsigned int nr;
};
struct m4u_init_param {
unsigned long long nonsec_pt_pa;
int l2_en;
unsigned int sec_pt_pa;
struct m4u_sec_mem_param sec_mem;
unsigned int chunk_nr;
int reinit;
};
struct m4u_systrace_param {
unsigned long pa;
unsigned long size;
};
struct m4u_cfg_port_array_param {
unsigned char m4u_port_array[M4U_PORT_NR];
};
struct m4u_larb_restore_param {
unsigned int larb_idx;
};
struct m4u_reserved_memory_param {
unsigned int reserved_mem_start;
unsigned int reserved_mem_size;
};
enum mtk_iommu_sec_id {
SEC_ID_SEC_CAM = 0,
SEC_ID_SVP,
SEC_ID_SDSP,
SEC_ID_WFD,
SEC_ID_COUNT
};
struct m4u_msg {
unsigned int cmd;
unsigned int retval_for_tbase; /* it must be 0 */
unsigned int rsp;
union {
struct m4u_session_param session_param;
struct m4u_cfg_port_param port_param;
struct m4u_buf_param buf_param;
struct m4u_init_param init_param;
struct m4u_cfg_port_array_param port_array_param;
#ifdef __M4U_SECURE_SYSTRACE_ENABLE__
struct m4u_systrace_param systrace_param;
#endif
struct m4u_larb_restore_param larb_param;
struct m4u_reserved_memory_param reserved_memory_param;
struct m4u_sec_mem_param sec_mem_param;
};
};
struct gz_m4u_msg {
unsigned int cmd;
unsigned int retval_for_tbase; /* it must be 0 */
unsigned int rsp;
unsigned int iommu_type;
unsigned int iommu_sec_id;
union {
struct m4u_session_param session_param;
struct m4u_cfg_port_param port_param;
struct m4u_buf_param buf_param;
struct m4u_init_param init_param;
struct m4u_cfg_port_array_param port_array_param;
#ifdef __M4U_SECURE_SYSTRACE_ENABLE__
struct m4u_systrace_param systrace_param;
#endif
struct m4u_larb_restore_param larb_param;
struct m4u_reserved_memory_param reserved_memory_param;
struct m4u_sec_mem_param sec_mem_param;
};
};
/* logs */
#define M4U_U64_FMT "0x%08x_%08x"
#define M4U_U64_PR(u64) ((uint32_t)((u64) >> 32), (uint32_t)(u64))
/* should be removed before MP */
#define TZ_M4U_DBG
#if defined(__cplusplus)
}
#endif
#endif /* TLFOO_H_ */
drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mt_iommu.h
+12
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@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_H__
#define __MT_IOMMU_H__
#include <dt-bindings/memory/mt6833-larb-port.h>
#include "mtk_iommu_ext.h"
#endif
drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mt_iommu_plat.h
+792
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@@ -0,0 +1,792 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PLAT_H__
#define __MT_IOMMU_PLAT_H__
#define MTK_IOMMU_PAGE_TABLE_SHARE (1)
//#define MTK_APU_TFRP_SUPPORT no need for mt6833
#define MTK_IOMMU_SIZE_NOT_ALIGNMENT
#ifndef CONFIG_FPGA_EARLY_PORTING
#define IOMMU_POWER_CLK_SUPPORT
#define MTK_IOMMU_BANK_IRQ_SUPPORT
#ifdef IOMMU_POWER_CLK_SUPPORT
#define MTK_IOMMU_LOW_POWER_SUPPORT
#define MTK_WARN_PSEDUO_FIND_SG
#include "clk-mt6833-pg.h"
enum subsys_id iommu_mtcmos_subsys[MTK_IOMMU_M4U_COUNT] = {
SYS_DIS,
#ifdef CONFIG_MTK_APUSYS_SUPPORT
SYS_VPU
#endif
};
#endif
#endif
#if (defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
defined(CONFIG_MICROTRUST_TEE_SUPPORT)) && \
defined(CONFIG_MTK_TEE_GP_SUPPORT)
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) && \
!defined(CONFIG_MTK_SVP_ON_MTEE_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#elif defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#elif defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#endif
#elif defined(MTK_IOMMU_BANK_IRQ_SUPPORT)
#define MTK_M4U_SECURE_IRQ_SUPPORT
#endif
#define MMU0_SET_ORDER 7
#define MMU1_SET_ORDER 7
#define MMU_SET_ORDER(mmu) ((mmu == 0) ? MMU0_SET_ORDER : MMU1_SET_ORDER)
#define MTK_IOMMU_SET_NR(mmu) (1<<MMU_SET_ORDER(mmu))
#define MMU_SET_LSB_OFFSET 15
#define MMU_SET_MSB_OFFSET(mmu) (MMU_SET_LSB_OFFSET+MMU_SET_ORDER(mmu)-1)
#define MMU_PFH_VA_TO_SET(mmu, va) \
F_MSK_SHIFT(va, MMU_SET_MSB_OFFSET(mmu), MMU_SET_LSB_OFFSET)
#ifdef CONFIG_FPGA_EARLY_PORTING
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {64};
#else
static unsigned int g_tag_count[MTK_IOMMU_M4U_COUNT] = {
64,
#ifdef CONFIG_MTK_APUSYS_SUPPORT
64,
#endif
};
#endif
char *smi_clk_name[MTK_IOMMU_LARB_NR] = {
"iommu_larb0", "iommu_larb1", "iommu_larb2",
"iommu_null_larb3", "iommu_larb4", "iommu_null_larb5",
"iommu_null_larb6", "iommu_larb7", "iommu_null_larb8",
"iommu_larb9", "iommu_null_larb10", "iommu_larb11",
"iommu_null_larb12", "iommu_larb13", "iommu_larb14",
"iommu_null_larb15", "iommu_larb16", "iommu_larb17",
"iommu_larb18", "iommu_larb19", "iommu_larb20",
"iommu_fake_larb21", "iommu_fake_larb22", "iommu_fake_larb23"
};
unsigned int port_size_not_aligned[] = {
M4U_PORT_L21_APU_FAKE_CODE
};
const char *smi_larb_id = "mediatek,larb-id";
#ifdef CONFIG_FPGA_EARLY_PORTING
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u",
};
#else
char *iommu_secure_compatible[MTK_IOMMU_M4U_COUNT] = {
"mediatek,sec_m4u0",
#ifdef CONFIG_MTK_APUSYS_SUPPORT
"mediatek,sec_m4u1",
#endif
};
char *iommu_bank_compatible[MTK_IOMMU_M4U_COUNT][MTK_IOMMU_BANK_NODE_COUNT] = {
{"mediatek,bank1_m4u0", "mediatek,bank2_m4u0", "mediatek,bank3_m4u0"},
#ifdef CONFIG_MTK_APUSYS_SUPPORT
{"mediatek,bank1_m4u1", "mediatek,bank2_m4u1", "mediatek,bank3_m4u1"},
#endif
};
#endif
/* ================ register control ================ */
#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
#define F_VAL_L(val, msb, lsb) (((val)&((1L<<(msb-lsb+1))-1))<<lsb)
#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
#define F_MSK_L(msb, lsb) F_VAL_L(0xffffffffffffffff, msb, lsb)
#define F_BIT_SET(bit) (1<<(bit))
#define F_BIT_VAL(val, bit) ((!!(val))<<(bit))
#define F_MSK_SHIFT(regval, msb, lsb) (((regval)&F_MSK(msb, lsb))>>lsb)
#define F_MSK_SHIFT64(regval, msb, lsb) \
((((unsigned long)regval)&F_MSK(msb, lsb))>>lsb)
/* it must be open after atf driver is ready */
#define IOMMU_DESIGN_OF_BANK
/* m4u atf debug parameter */
#define IOMMU_ATF_INDEX_MASK F_MSK(3, 0)
#define IOMMU_ATF_BANK_MASK F_MSK(7, 4)
#define IOMMU_ATF_CMD_MASK F_MSK(16, 8)
#define IOMMU_ATF_SET_COMMAND(m4u, bank, cmd) \
(m4u | (bank << 4) | (cmd << 8))
enum IOMMU_ATF_CMD {
IOMMU_ATF_DUMP_SECURE_REG,
IOMMU_ATF_SECURITY_DEBUG_ENABLE,
IOMMU_ATF_SECURITY_DEBUG_DISABLE,
IOMMU_ATF_BANK_ENABLE_TF,
IOMMU_ATF_BANK_DISABLE_TF,
IOMMU_ATF_BANK_DUMP_INFO,
IOMMU_ATF_BANK_DOMAIN_CONFIG,
IOMMU_ATF_SECURITY_BACKUP,
IOMMU_ATF_SECURITY_RESTORE,
IOMMU_ATF_DUMP_SECURE_PORT_CONFIG,
IOMMU_ATF_SET_SMI_SEC_LARB,
IOMMU_ATF_DUMP_SMI_SEC_LARB,
IOMMU_ATF_CMD_COUNT
};
char *iommu_atf_cmd_name[IOMMU_ATF_CMD_COUNT] = {
"IOMMU_ATF_DUMP_SECURE_REG",
"IOMMU_ATF_SECURITY_DEBUG_ENABLE",
"IOMMU_ATF_SECURITY_DEBUG_DISABLE",
"IOMMU_ATF_BANK_ENABLE_TF",
"IOMMU_ATF_BANK_DISABLE_TF",
"IOMMU_ATF_BANK_DUMP_INFO",
"IOMMU_ATF_BANK_DOMAIN_CONFIG",
"IOMMU_ATF_SECURITY_BACKUP",
"IOMMU_ATF_SECURITY_RESTORE",
"IOMMU_ATF_DUMP_SECURE_PORT_CONFIG",
};
inline void iommu_set_field_by_mask(void __iomem *M4UBase,
unsigned int reg,
unsigned long mask,
unsigned int val)
{
unsigned int regval;
regval = readl_relaxed(M4UBase + reg);
regval = (regval & (~mask)) | val;
writel_relaxed(regval, M4UBase + reg);
}
static inline unsigned int iommu_get_field_by_mask(
void __iomem *M4UBase, unsigned int reg,
unsigned int mask)
{
return readl_relaxed(M4UBase + reg) & mask;
}
/* regiters of BANK0 */
#define REG_MMU_PT_BASE_ADDR (0x0)
#define F_MMU_PT_BASE_ADDR_MSK F_MSK(31, 7)
#define F_MMU_PT_BASE_ADDR_BIT32 F_MSK(2, 0)
#define REG_MMU_STA (0x8)
#define F_MMU_STA_INT_MASK F_MSK(18, 0)
#define REG_MMU_PROG_EN (0x10)
#define F_MMU_PROG_EN_TLB1 F_BIT_SET(1)
#define F_MMU_PROG_EN_TLB0 F_BIT_SET(0)
#define REG_MMU_PROG_VA (0x14)
#define F_MMU_PROG_VA_TBL_ID F_MSK(1, 0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_PROG_VA_BIT32 F_MSK(6, 5)
#endif
#define F_MMU_PROG_VA_SECURE F_BIT_SET(7)
#define F_MMU_PROG_VA_SIZE16X F_BIT_SET(8)
#define F_MMU_PROG_VA_LAYER F_BIT_SET(9)
#define F_MMU_PROG_VA_LOCK F_BIT_SET(11)
#define F_MMU_PROG_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_PROG_DSC (0x18)
#define REG_MMU_INVLDT (0x20)
#define F_MMU_INVLDT_RNG F_BIT_SET(0)
#define F_MMU_INVLDT_ALL F_BIT_SET(1)
#define F_MMU_INVLDT_VICT_ALL F_BIT_SET(2)
#define REG_MMU_INVLD_START_A (0x24)
#define REG_MMU_INVLD_END_A (0x28)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_INVLD_BIT32 F_MSK(1, 0)
#endif
#define F_MMU_INVLD_BIT31_12 F_MSK(31, 12)
#define REG_INVLID_SEL (0x2c)
#define F_MMU_INV_EN_L2 F_BIT_SET(1)
#define F_MMU_INV_EN_L1 F_BIT_SET(0)
#define REG_MMU_DUMMY 0x44
#define F_REG_MMU_IDLE_ENABLE F_BIT_SET(0)
#define REG_MMU_MISC_CTRL (0x48)
#define F_MMU_MISC_CTRL_COHERENCE_EN(MMU) (F_BIT_SET(0) << (MMU * 16))
#define F_MMU_MISC_CTRL_IN_ORDER_WR_EN(MMU) (F_BIT_SET(1) << (MMU * 16))
#define F_MMU_MISC_CTRL_STD_AXI_MODE(MMU) (F_BIT_SET(3) << (MMU * 16))
#define F_MMU_MISC_CTRL_BLOCKING_MODE(MMU) (F_BIT_SET(4) << (MMU * 16))
#define F_MMU_MISC_CTRL_HALF_ENTRY_MODE(MMU) (F_BIT_SET(5) << (MMU * 16))
#define REG_MMU_PRIORITY (0x4c)
#define F_MMU_PRIORITY_WALK_ULTRA F_BIT_SET(0)
#define F_MMU_PRIORITY_AUTO_PF_ULTRA F_BIT_SET(1)
#define F_MMU_PRIORITY_RS_FULL_ULTRA F_BIT_SET(2)
#define REG_MMU_DCM_DIS (0x50)
#define REG_MMU_WR_LEN_CTRL (0x54)
#define F_MMU_WR_LEN_CTRL_THROT_DIS(MMU) (F_BIT_SET(5) << (MMU * 0x10))
#define F_MMU_WR_LEN_CTRL_LEN(MMU) (F_MSK(4, 0) << (MMU * 0x10))
#define REG_MMU_HW_DEBUG (0x58)
#define F_MMU_HW_DEBUG_PFQ_BD_EN F_BIT_SET(0)
#define F_MMU_HW_DEBUG_L2_SCAN_ALL_INVLDT F_BIT_SET(1)
#define REG_MMU_DBG(index) (0x60 + index * 4)
#define REG_MMU_COH_THROT_CTRL (0x90)
#define F_MMU_COH_THROT_CTRL_REN0 F_BIT_SET(0)
#define F_MMU_COH_THROT_CTRL_RLMT0 F_MSK(3, 2)
#define F_MMU_COH_THROT_CTRL_WEN0 F_BIT_SET(4)
#define F_MMU_COH_THROT_CTRL_WLMT0 F_MSK(7, 6)
#define F_MMU_COH_THROT_CTRL_REN1 F_BIT_SET(8)
#define F_MMU_COH_THROT_CTRL_RLMT1 F_MSK(11, 10)
#define F_MMU_COH_THROT_CTRL_WEN1 F_BIT_SET(12)
#define F_MMU_COH_THROT_CTRL_WLMT1 F_MSK(15, 14)
#define REG_MMU_TBW_ID (0xA0)
#define F_MMU_TBW_ID_MISS F_MSK(15, 0)
#define F_MMU_TBW_ID_PFTH F_MSK(31, 16)
#define REG_MMU_READ_ENTRY (0x100)
#define F_READ_ENTRY_EN F_BIT_SET(31)
#define F_READ_ENTRY_VICT_TLB_SEL F_BIT_SET(13)
#define F_READ_ENTRY_MMx_MAIN(id) F_BIT_SET(27+id)
#define F_READ_ENTRY_PFH F_BIT_SET(26)
#define F_READ_ENTRY_MAIN_IDX(mmu, idx) \
F_VAL(idx, (19 + mmu * 6), (14 + (mmu * 6)))
#define F_READ_ENTRY_PFH_IDX(idx) F_VAL(idx, 11, 5)
#define F_READ_ENTRY_PFH_PAGE_IDX(idx) F_VAL(idx, 4, 2)
#define F_READ_ENTRY_PFH_WAY(way) F_VAL(way, 1, 0)
#define REG_MMU_DES_RDATA (0x104)
#define REG_MMU_PFH_TAG_RDATA (0x108)
#define F_PFH_TAG_VA_GET(mmu, tag) \
(F_MSK_SHIFT64(tag, 14, 3)<<(MMU_SET_MSB_OFFSET(mmu)+1))
#define F_VIC_TAG_VA_GET_L0(mmu, tag) \
(F_MSK_SHIFT(tag, 23, 17)<<(MMU_SET_MSB_OFFSET(mmu)+2))
#define F_VIC_TAG_VA_GET_L1(mmu, tag) \
(F_MSK_SHIFT(tag, 23, 17)<<(MMU_SET_MSB_OFFSET(mmu)-6))
#define F_MMU_PFH_TAG_VA_LAYER0_MSK(mmu) \
((mmu == 0)?F_MSK(31, 28):F_MSK(31, 28))
#define F_PFH_PT_BANK_BIT F_MSK(15, 16)
#define F_PFH_TAG_LAYER_BIT F_BIT_SET(2)
#define F_PFH_TAG_SEC_BIT F_BIT_SET(1)
#define F_PFH_TAG_AUTO_PFH F_BIT_SET(0)
#define REG_MMU_VICT_VLD (0x10c)
#define F_MMU_VICT_VLD_BIT(way) F_BIT_SET((way)&0xf)
#define REG_MMU_CTRL_REG (0x110)
#define F_MMU_CTRL_4GB_MODE(mode) F_BIT_VAL(mode, 17)
#define F_MMU_CTRL_RESEND_L2_EN(en) F_BIT_VAL(en, 16)
#define F_MMU_CTRL_RESEND_PFQ_EN(en) F_BIT_VAL(en, 15)
#define F_MMU_CTRL_L2TLB_EN(en) F_BIT_VAL(en, 14)
#define F_MMU_CTRL_MTLB_EN(en) F_BIT_VAL(en, 13)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_VICT_TLB_EN(en) F_BIT_VAL(en, 12)
#define F_MMU_CTRL_HANG_PREVENTION(en) F_BIT_VAL(en, 9)
#define F_MMU_CTRL_LAYER2_PFH_DIS(dis) F_BIT_VAL(dis, 7)
#define F_MMU_CTRL_INT_FREEZE_EN(en) F_BIT_VAL(en, 6)
#define F_MMU_CTRL_MONITOR_CLR(clr) F_BIT_VAL(clr, 2)
#define F_MMU_CTRL_MONITOR_EN(en) F_BIT_VAL(en, 1)
#define F_MMU_CTRL_PFH_DIS(dis) F_BIT_VAL(dis, 0)
#define REG_MMU_TFRP_PADDR (0x114)
#define F_RP_PA_REG_BIT31_7 F_MSK(31, 7)
#define F_RP_PA_REG_BIT32 F_MSK(2, 0)
#define F_MMU_TFRP_PA_SET(PA, EXT) (\
(((unsigned long long)PA) & F_RP_PA_REG_BIT31_7) | \
((((unsigned long long)PA) >> 32) & F_RP_PA_REG_BIT32))
#define REG_MMU_INT_CONTROL0 (0x120)
#define F_INT_L2_MULTI_HIT_FAULT F_BIT_SET(0)
#define F_INT_L2_TABLE_WALK_FAULT F_BIT_SET(1)
#define F_INT_L2_PFH_DMA_FIFO_OVERFLOW F_BIT_SET(2)
#define F_INT_L2_MISS_DMA_FIFO_OVERFLOW F_BIT_SET(3)
#define F_INT_L2_INVALID_DONE F_BIT_SET(4)
#define F_INT_L2_PFH_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_MISS_FIFO_ERR F_BIT_SET(6)
#define F_INT_CTL0_L2_CDB_SLICE_ERR BIT(7)
#define F_INT_CTL0_INT_CLR BIT(12)
#define REG_MMU_INT_MAIN_CONTROL (0x124)
#define F_INT_TRANSLATION_FAULT(MMU) F_BIT_SET(0+(MMU)*7)
#define F_INT_MAIN_MULTI_HIT_FAULT(MMU) F_BIT_SET(1+(MMU)*7)
#define F_INT_INVALID_PHYSICAL_ADDRESS_FAULT(MMU) F_BIT_SET(2+(MMU)*7)
#define F_INT_ENTRY_REPLACEMENT_FAULT(MMU) F_BIT_SET(3+(MMU)*7)
#define F_INT_TLB_MISS_FAULT(MMU) F_BIT_SET(4+(MMU)*7)
#define F_INT_MISS_FIFO_ERR(MMU) F_BIT_SET(5+(MMU)*7)
#define F_INT_PFH_FIFO_ERR(MMU) F_BIT_SET(6+(MMU)*7)
#define F_INT_MAIN_MAU_INT_EN(MMU) F_BIT_SET(14 + MMU)
#define F_INT_MMU_MAIN_MSK(MMU) F_MSK((6+(MMU)*7), ((MMU)*7))
#define REG_MMU_CPE_DONE (0x12C)
#define F_MMU_CPE_DONE_RNG_INVLADT BIT(0)
#define REG_MMU_L2_FAULT_ST (0x130)
#define F_MMU_L2_FAULT_MHIT BIT(0)
#define F_MMU_L2_FAULT_TBW BIT(1)
#define F_MMU_L2_FAULT_PFQ_FIFO_FULL BIT(2)
#define F_MMU_L2_FAULT_MQ_FIFO_FULL BIT(3)
#define F_MMU_L2_FAULT_INVLDT_DONE BIT(4)
#define F_INT_L2_PFH_OUT_FIFO_ERROR F_BIT_SET(5)
#define F_INT_L2_PFH_IN_FIFO_ERROR F_BIT_SET(6)
#define F_INT_L2_MISS_OUT_FIFO_ERROR F_BIT_SET(7)
#define F_INT_L2_MISS_IN_FIFO_ERR F_BIT_SET(8)
#define F_MMU_L2_FAULT_L2_CDB_SLICE_ERR BIT(9)
#define REG_MMU_FAULT_ST1 (0x134)
//same to REG_MMU_INT_MAIN_CONTROL
#define REG_MMU_TBWALK_FAULT_VA (0x138)
#define F_MMU_TBWALK_FAULT_LAYER BIT(0)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_TBWALK_FAULT_BIT32 F_MSK(10, 9)
#endif
#define F_MMU_TBWALK_FAULT_BIT31_12 F_MSK(31, 12)
#define REG_MMU_FAULT_STATUS(MMU) (0x13c+((MMU)<<3))
#define F_MMU_FAULT_VA_BIT31_12 F_MSK(31, 12)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define F_MMU_FAULT_VA_BIT32 F_MSK(11, 9)
#endif
#define F_MMU_FAULT_PA_BIT32 F_MSK(8, 6)
#define F_MMU_FAULT_INVPA F_BIT_SET(5)
#define F_MMU_FAULT_TF F_BIT_SET(4)
#define F_MMU_FAULT_VA_WRITE_BIT F_BIT_SET(1)
#define F_MMU_FAULT_VA_LAYER_BIT F_BIT_SET(0)
#define REG_MMU_INVLD_PA(MMU) (0x140+((MMU)<<3))
#define REG_MMU_INT_ID(MMU) (0x150+((MMU)<<2))
#define F_MMU_INT_L2_SRC F_MSK(30, 28)
#define F_MMU_INT_L1_SRC F_MSK(26, 24)
#define F_MMU_INT_TF_VAL(regval) (regval & F_MSK(11, 2))
#define REG_MMU_PERF_MON_PTLB (0x180)
#define F_MMU_PERF_MON_PTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_PTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_PTLB_ID_SEL F_BIT_SET(17)
#define F_MMU_PERF_MON_PTLB_AXI_SEL F_MSK(19, 18)
#define REG_MMU_PERF_MON_MTLB(MMU) (0x190 + mmu * 0x4)
#define F_MMU_PERF_MON_MTLB_ID F_MSK(15, 0)
#define F_MMU_PERF_MON_MTLB_ALL F_BIT_SET(16)
#define F_MMU_PERF_MON_MTLB_ID_SEL F_BIT_SET(17)
#define REG_MMU_PF_L1_MSCNT (0x1A0)
#define REG_MMU_PF_L2_MSCNT (0x1A4)
#define REG_MMU_PF_L1_CNT (0x1A8)
#define REG_MMU_PF_L2_CNT (0x1AC)
#define REG_MMU_ACC_CNT(MMU) (0x1C0 + MMU * 16)
#define REG_MMU_MAIN_L1_MSCNT(MMU) (0x1C4 + MMU * 16)
#define REG_MMU_MAIN_L2_MSCNT(MMU) (0x1C8 + MMU * 16)
#define REG_MMU_RS_PERF_CNT(MMU) (0x1CC + MMU * 16)
#define REG_MMU_LOOKUP_CNT(MMU) (0x1D0 + MMU * 0x20)
#define REG_MMU_PFH_VLD(VLD, WAY) (0x200 + VLD * 0x4 + WAY * 0x10)
#define F_MMU_PFH_VLD_BIT(set, way) F_BIT_SET((set)&0x1f) /* set%32 */
#define REG_MMU_RS_VA(MMU, RS) (0x380 + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_VA_BIT32 F_MSK(2, 0)
#define F_MMU_RS_VA_TBL_ID F_MSK(5, 4)
#define F_MMU_RS_VA_BIT31_12 F_MSK(31, 12)
#define REG_MMU_RS_PA(MMU, RS) (0x384 + MMU * 0x300 + RS * 0x10)
#define REG_MMU_RS_2ND_BASE(MMU, RS) (0x388 + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_2ND_BASE_MSK F_MSK(24, 0)
#define REG_MMU_RS_STA(MMU, RS) (0x38C + MMU * 0x300 + RS * 0x10)
#define F_MMU_RS_STA_IS_LTAIL BIT(0)
#define F_MMU_RS_STA_IS_LHEAD BIT(1)
#define F_MMU_RS_STA_IS_PTAIL BIT(2)
#define F_MMU_RS_STA_IS_PHEAD BIT(3)
#define F_MMU_RS_STA_PA_RDY BIT(4)
#define F_MMU_RS_STA_RDY2REQ BIT(5)
#define F_MMU_RS_STA_WRT_CMD BIT(6)
#define F_MMU_RS_STA_VLD BIT(7)
#define F_MMU_RS_STA_TO BIT(8)
#define F_MMU_RS_STA_ID F_MSK(31, 16)
#define REG_MMU_MAIN_TAG(MMU, TAG) (0x500 + MMU * 0x300 + TAG * 0x4)
#define F_MAIN_TLB_VA_MSK F_MSK(31, 12)
#define F_MAIN_TLB_VA_BIT32 F_MSK(1, 0)
#define F_MAIN_TLB_LOCK_BIT (1<<11)
#define F_MAIN_TLB_VALID_BIT (1<<10)
#define F_MAIN_TLB_LAYER_BIT F_BIT_SET(9)
#define F_MAIN_TLB_16X_BIT F_BIT_SET(8)
#define F_MAIN_TLB_SEC_BIT F_BIT_SET(7)
#define F_MAIN_TLB_INV_DES_BIT (1<<6)
#define F_MAIN_TLB_TABLE_ID_BIT(regval) F_MSK_SHIFT(regval, 5, 4)
#define REG_MMU_MAU_SA(MMU, MAU) (0x900 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_SA_EXT(MMU, MAU) (0x904 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA(MMU, MAU) (0x908 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_EA_EXT(MMU, MAU) (0x90C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_LARB_EN(MMU) (0x910 + MMU * 0x100)
#define REG_MMU_MAU_PORT_EN(MMU, MAU) (0x914 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ASRT_ID(MMU, MAU) (0x918 + MMU * 0x100 + MAU * 0)
#define F_MMU_MAU_ASRT_ID_LARB(regval) F_MSK_SHIFT(regval, 9, 5)
#define F_MMU_MAU_ASRT_ID_PORT(regval) F_MSK_SHIFT(regval, 4, 0)
#define F_MMU_MAU_ASRT_ID_VAL F_MSK(9, 0)
#define REG_MMU_MAU_ADDR(MMU, MAU) (0x91C + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_ADDR_BIT32(MMU, MAU) (0x920 + MMU * 0x100 + MAU * 0)
#define REG_MMU_MAU_CLR(MMU) (0x924 + MMU * 0x100)
#define REG_MMU_MAU_IO(MMU) (0x928 + MMU * 0x100)
#define F_MAU_BIT_VAL(val, mau) F_BIT_VAL(val, mau)
#define REG_MMU_MAU_RW(MMU) (0x92C + MMU * 0x100)
#define REG_MMU_MAU_VA(MMU) (0x930 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_STA(MMU) (0x934 + MMU * 0x100)
#define REG_MMU_MAU_ASRT_C4K(MMU) (0x938 + MMU * 0x100)
#define REG_MMU_PFH_DIST(MMU, DIST) (0xB00 + MMU * 0x80 + DIST * 0x4)
// =================== IOVA Reservation ==========================
/*
* reserved IOVA Domain for IOMMU users of HW limitation.
*/
#define MTK_IOVA_REMOVE_CNT (6)
enum mtk_reserve_region_type {
// no reserved region
IOVA_REGION_UNDEFINE,
// users cannot touch the IOVA in the reserved region
IOVA_REGION_REMOVE,
// users can only touch the IOVA in the reserved region
IOVA_REGION_STAY,
};
/*
* struct mtk_iova_domain_data: domain configuration
* @min_iova: start address of IOVAD
* @max_iova: end address of IOVAD
* @resv_start: the start address of reserved region
* @resv_size: the size of reserved region
* @resv_type: the type of reserve region
* @port_mask: the user list of IOVAD
* One user can only belongs to one IOVAD, the port mask is in unit of SMI larb.
*/
struct mtk_iova_domain_data {
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
unsigned int boundary;
#endif
unsigned long min_iova;
unsigned long max_iova;
unsigned long resv_start[MTK_IOVA_REMOVE_CNT];
unsigned long resv_size[MTK_IOVA_REMOVE_CNT];
unsigned int resv_type;
unsigned int port_mask[MTK_IOMMU_LARB_NR];
int owner;
};
#define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
#define MTK_IOVA_DOMAIN_COUNT (10) // Domain count
#define RESERVED_IOVA_ADDR_SECURE (SZ_4K)
#define RESERVED_IOVA_SIZE_SECURE (SZ_1G - SZ_4K)
#if (CONFIG_MTK_IOMMU_PGTABLE_EXT > 32)
#define RESERVED_IOVA_ADDR_CCU0 (0x0240000000UL)
#define RESERVED_IOVA_SIZE_CCU0 (0x0004000000UL)
#define RESERVED_IOVA_ADDR_CCU1 (0x0244000000UL)
#define RESERVED_IOVA_SIZE_CCU1 (0x0004000000UL)
#define RESERVED_IOVA_ADDR_APU_CODE (0x0370000000UL)
#define RESERVED_IOVA_SIZE_APU_CODE (0x0012600000UL)
#define RESERVED_IOVA_ADDR_APU_DATA (0x0310000000UL)
#define RESERVED_IOVA_SIZE_APU_DATA (0x0010000000UL)
#define RESERVED_IOVA_ADDR_APU_VLM (0x0304000000UL)
#define RESERVED_IOVA_SIZE_APU_VLM (0x0004000000UL)
#define IOVA_ADDR_4GB (1UL << 32)
#define IOVA_ADDR_8GB (2UL << 32)
#define IOVA_ADDR_12GB (3UL << 32)
#define IOVA_ADDR_16GB (4UL << 32)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT) || \
defined(CONFIG_MTK_GZ_SUPPORT_SDSP) || \
defined(CONFIG_MTK_CAM_GENIEZONE_SUPPORT))
{ /* boundary(0~4GB) IOVA space for display(larb0,1) */
.boundary = 0,
.owner = -1,
.min_iova = SZ_1G,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x3f, 0xff, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
#else
{ /* boundary(0~4GB) IOVA space for display(larb0,1) */
.boundary = 0,
.owner = -1,
.min_iova = SZ_4K,
.max_iova = IOVA_ADDR_4GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x3f, 0xff, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
#endif
{ /* boundary(4GB~8GB) IOVA space for video */
/* larb4,5,7,8 */
.boundary = 1,
.owner = -1,
.min_iova = IOVA_ADDR_4GB,
.max_iova = IOVA_ADDR_8GB - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x7ff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x0} //20~23
},
{ /* boundary(8GB~12GB) IOVA space for CAM & MDP */
/* larb2, 9, 11, 13, 14, 16, 17, 18, 19, 20*/
.boundary = 2,
.owner = -1,
.min_iova = IOVA_ADDR_8GB,
.max_iova = IOVA_ADDR_12GB - 1,
.resv_start = {RESERVED_IOVA_ADDR_CCU0,
RESERVED_IOVA_ADDR_CCU1},
.resv_size = {RESERVED_IOVA_SIZE_CCU0,
RESERVED_IOVA_SIZE_CCU1},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x0, 0x0, 0x1f, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x0, 0x0, 0x0} //20~23
},
{ /* CCU0 IOVA space */
.boundary = 2,
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU0,
.max_iova = RESERVED_IOVA_ADDR_CCU0 +
RESERVED_IOVA_SIZE_CCU0 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x600, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x1, 0x0} //20~23
},
{ /* CCU1 IOVA space */
.boundary = 2,
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU1,
.max_iova = RESERVED_IOVA_ADDR_CCU1 +
RESERVED_IOVA_SIZE_CCU1 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x30, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x1} //20~23
},
{ /* boundary(12GB~16GB) IOVA space for APU DATA */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_DATA,
.min_iova = IOVA_ADDR_12GB,
.max_iova = IOVA_ADDR_16GB - 1,
.resv_start = {RESERVED_IOVA_ADDR_APU_DATA,
RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_VLM},
.resv_size = {RESERVED_IOVA_SIZE_APU_DATA,
RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_VLM},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x2, 0x0, 0x0} //20~23
},
{ /* VPU CODE IOVA space */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_CODE,
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x1, 0x0, 0x0} //20~23
},
{ /* VPU VLM IOVA space */
.boundary = 3,
.owner = M4U_PORT_L21_APU_FAKE_VLM,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM,
.max_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x4, 0x0, 0x0} //20~23
},
};
#else
#define RESERVED_IOVA_ADDR_CCU0 (0x40000000U)
#define RESERVED_IOVA_SIZE_CCU0 (0x04000000U)
#define RESERVED_IOVA_ADDR_CCU1 (0x44000000U)
#define RESERVED_IOVA_SIZE_CCU1 (0x04000000U)
#define RESERVED_IOVA_ADDR_APU_CODE (0x70000000U)
#define RESERVED_IOVA_SIZE_APU_CODE (0x12600000U)
#define RESERVED_IOVA_ADDR_APU_DATA (0x10000000U)
#define RESERVED_IOVA_SIZE_APU_DATA (0x10000000U)
#define RESERVED_IOVA_ADDR_APU_VLM (0x48000000U)
#define RESERVED_IOVA_SIZE_APU_VLM (0x04000000U)
const struct mtk_iova_domain_data mtk_domain_array[MTK_IOVA_DOMAIN_COUNT] = {
#if (defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)) || \
defined(CONFIG_MTK_GZ_SUPPORT_SDSP)
{ //REE IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM,
.max_iova = DMA_BIT_MASK(MTK_IOVA_ADDR_BITS),
.resv_start = {RESERVED_IOVA_ADDR_APU_CODE},
.resv_size = {RESERVED_IOVA_SIZE_APU_CODE},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x3f, 0xff, 0x1f, 0x0, //0~3
0x7ff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x2, 0x0, 0x0} //20~23
},
#else
{ //public IOVA space
.owner = -1,
.min_iova = SZ_4K,
.max_iova = DMA_BIT_MASK(MTK_IOVA_ADDR_BITS),
.resv_start = {RESERVED_IOVA_ADDR_CCU0,
RESERVED_IOVA_ADDR_CCU1,
RESERVED_IOVA_ADDR_APU_CODE,
RESERVED_IOVA_ADDR_APU_VLM,
RESERVED_IOVA_ADDR_APU_DATA},
.resv_size = {RESERVED_IOVA_SIZE_CCU0,
RESERVED_IOVA_SIZE_CCU1,
RESERVED_IOVA_SIZE_APU_CODE,
RESERVED_IOVA_SIZE_APU_VLM,
RESERVED_IOVA_SIZE_APU_DATA},
.resv_type = IOVA_REGION_REMOVE,
.port_mask = {0x3f, 0xff, 0x1f, 0x0, //0~3
0x7ff, 0xff, 0x0, 0x7fff, //4~7
0x7ffffff, 0x1fffffff, 0x0, 0x1fffffff, //8~11
0x0, 0x9ff, 0xf, 0x0, //12~15
0x1ffff, 0x1ffff, 0x1ffff, 0xf, //16~19
0x3f, 0x2, 0x0, 0x0} //20~23
},
#endif
{ //CCU0 IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU0,
.max_iova = RESERVED_IOVA_ADDR_CCU0 +
RESERVED_IOVA_SIZE_CCU0 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x600, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x1, 0x0} //20~23
},
{ //CCU1 IOVA space
.owner = -1,
.min_iova = RESERVED_IOVA_ADDR_CCU1,
.max_iova = RESERVED_IOVA_ADDR_CCU1 +
RESERVED_IOVA_SIZE_CCU1 - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x30, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x0, 0x0, 0x1} //20~23
},
{ //VPU CODE IOVA space
.owner = M4U_PORT_L21_APU_FAKE_CODE,
.min_iova = RESERVED_IOVA_ADDR_APU_CODE,
.max_iova = RESERVED_IOVA_ADDR_APU_CODE +
RESERVED_IOVA_SIZE_APU_CODE - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x1, 0x0, 0x0} //20~23
},
{ //VPU VLM IOVA space
.owner = M4U_PORT_L21_APU_FAKE_VLM,
.min_iova = RESERVED_IOVA_ADDR_APU_VLM,
.max_iova = RESERVED_IOVA_ADDR_APU_VLM +
RESERVED_IOVA_SIZE_APU_VLM - 1,
.resv_type = IOVA_REGION_UNDEFINE,
.port_mask = {0x0, 0x0, 0x0, 0x0, //0~3
0x0, 0x0, 0x0, 0x0, //4~7
0x0, 0x0, 0x0, 0x0, //8~11
0x0, 0x0, 0x0, 0x0, //12~15
0x0, 0x0, 0x0, 0x0, //16~19
0x0, 0x4, 0x0, 0x0} //20~23
},
};
#endif
#define IOMMU_SECURITY_DBG_SUPPORT
/* check 17GB~32GB-1 PA for out of range */
struct mau_config_info mt6833_mau_info[MTK_IOMMU_M4U_COUNT] = {
{
.start = 0x40000000,
.end = 0xffffffff,
.port_mask = 0xffffffff,
.larb_mask = 0xffffffff,
.wr = 0x1,
.virt = 0x0,
.io = 0x1,
.start_bit32 = 0x4,
.end_bit32 = 0x7,
},
#ifdef CONFIG_MTK_APUSYS_SUPPORT
{
.start = 0x40000000,
.end = 0xffffffff,
.port_mask = 0xffffffff,
.larb_mask = 0xffffffff,
.wr = 0x1,
.virt = 0x0,
.io = 0x1,
.start_bit32 = 0x4,
.end_bit32 = 0x7,
}
#endif
};
struct mau_config_info *get_mau_info(int m4u_id)
{
if (m4u_id < MTK_IOMMU_M4U_COUNT)
return &mt6833_mau_info[m4u_id];
else
return NULL;
}
#endif
drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mt_iommu_port.h
+505
View File
@@ -0,0 +1,505 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MT_IOMMU_PORT_H__
#define __MT_IOMMU_PORT_H__
/*
* this header file is only used for mtk_iomm module
* the definition of header file is platform dependency.
*/
//enable this option if M4U new design of multiple bank
//#define IOMMU_DESIGN_OF_BANK
struct mtk_iommu_port {
char *name;
unsigned m4u_id: 2;
unsigned m4u_slave: 2;
unsigned larb_id: 6;
unsigned larb_port: 8;
unsigned tf_id: 14; /* 14 bits */
bool enable_tf;
mtk_iommu_fault_callback_t fault_fn;
void *fault_data;
};
#define MTK_IOMMU_PORT_INIT(name, id, slave, larb, tf_larb, port) {\
name, id, slave, larb, port, (((tf_larb)<<7)|((port)<<2)), 1\
}
#define SLAVE_L0 (0)
#define SLAVE_L1 (0)
#define SLAVE_L2 (0)
#define SLAVE_L3 (0)
#define SLAVE_L4 (0)
#define SLAVE_L5 (0)
#define SLAVE_L7 (0)
#define SLAVE_L8 (0)
#define SLAVE_L9 (0)
#define SLAVE_L11 (0)
#define SLAVE_L13 (0)
#define SLAVE_L14 (0)
#define SLAVE_L16 (0)
#define SLAVE_L17 (0)
#define SLAVE_L18 (0)
#define SLAVE_L19 (0)
#define SLAVE_L20 (0)
#define SLAVE_APU (0)
#define SLAVE_CCU0 (0)
#define SLAVE_CCU1 (0)
/* MM_IOMMU AXI_ID */
#define TF_LARB_L0 (0x0)
#define TF_LARB_L1 (0x4)
#define TF_LARB_L2 (0x10)
#define TF_LARB_L4 (0x8)
#define TF_LARB_L5 (0x9)
#define TF_LARB_L7 (0xc)
#define TF_LARB_L8 (0x5)//no use
#define TF_LARB_L9 (0x14)
#define TF_LARB_L11 (0x15)
#define TF_LARB_L13 (0x1d)
#define TF_LARB_L14 (0x19)
#define TF_LARB_L16 (0x1a)
#define TF_LARB_L17 (0x1f)
#define TF_LARB_L18 (0x1e)
#define TF_LARB_L19 (0x16)
#define TF_LARB_L20 (0x17)
#define TF_APU (0x0)
#define TF_CCU0 (0x1c)
#define TF_CCU1 (0x18)
/* avoid build error */
#define TF_CCU_DISP TF_CCU0
#define TF_CCU_MDP TF_CCU1
int mtk_iommu_larb_port_count[] = {
4, 5, 5, 0, 12,//0~4
0, 0, 13, 0, 29, //5~9
0, 29, 0, 12, 6, //10~14
0, 17, 17, 17, 4, //15~19
6, 3, 1, 1 //20~23
};
int mtk_iommu_larb_distance[] = {
0, 4, 9, -1, 14, //0~4
-1, -1, 26, -1, 39, //5~9
-1, 68, -1, 97, 109, //10~14
-1, 115, 132, 149, 166,//15~19
170, 176, 179, 180 //20~23
};
struct mtk_iommu_port iommu_port[] = {
/* Larb0 -- 4 */
MTK_IOMMU_PORT_INIT("L0_DISP_POSTMASK0", 0,
SLAVE_L0, 0, TF_LARB_L0, 0),
MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0_HDR", 0,
SLAVE_L0, 0, TF_LARB_L0, 1),
MTK_IOMMU_PORT_INIT("L0_OVL_RDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 2),
MTK_IOMMU_PORT_INIT("L0_DISP_RDMA0", 0,
SLAVE_L0, 0, TF_LARB_L0, 3),
/* Larb1 -- 5(9) */
MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0_HDR", 0,
SLAVE_L1, 1, TF_LARB_L1, 0),
MTK_IOMMU_PORT_INIT("L1_OVL_2L_RDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 1),
MTK_IOMMU_PORT_INIT("L1_DISP_RDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 2),
MTK_IOMMU_PORT_INIT("L1_DISP_WDMA0", 0,
SLAVE_L1, 1, TF_LARB_L1, 3),
MTK_IOMMU_PORT_INIT("L1_DISP_FAKE1", 0,
SLAVE_L1, 1, TF_LARB_L1, 4),
/* Larb2 --5(14) */
MTK_IOMMU_PORT_INIT("L2_MDP_RDMA0", 0,
SLAVE_L2, 2, TF_LARB_L2, 0),
MTK_IOMMU_PORT_INIT("L2_MDP_RDMA1", 0,
SLAVE_L2, 2, TF_LARB_L2, 1),
MTK_IOMMU_PORT_INIT("L2_MDP_WROT0", 0,
SLAVE_L2, 2, TF_LARB_L2, 2),
MTK_IOMMU_PORT_INIT("L2_MDP_WROT1", 0,
SLAVE_L2, 2, TF_LARB_L2, 3),
MTK_IOMMU_PORT_INIT("L2_MDP_DISP_FAKE0", 0,
SLAVE_L2, 2, TF_LARB_L2, 4),
/* Larb4 -- 12(26) */
MTK_IOMMU_PORT_INIT("L4_VDEC_MC_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 0),
MTK_IOMMU_PORT_INIT("L4_VDEC_UFO_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 1),
MTK_IOMMU_PORT_INIT("L4_VDEC_PP_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 2),
MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_RD_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 3),
MTK_IOMMU_PORT_INIT("L4_VDEC_PRED_WR_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 4),
MTK_IOMMU_PORT_INIT("L4_VDEC_PPWRAP_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 5),
MTK_IOMMU_PORT_INIT("L4_VDEC_TILE_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 6),
MTK_IOMMU_PORT_INIT("L4_VDEC_VLD_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 7),
MTK_IOMMU_PORT_INIT("L4_VDEC_VLD2_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 8),
MTK_IOMMU_PORT_INIT("L4_VDEC_AVC_MV_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 9),
MTK_IOMMU_PORT_INIT("L4_VDEC_RG_CTRL_DMA_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 10),
MTK_IOMMU_PORT_INIT("L4_VDEC_UFO_ENC_EXT", 0,
SLAVE_L4, 4, TF_LARB_L4, 11),
/* Larb7 --13(39) */
MTK_IOMMU_PORT_INIT("L7_VENC_RCPU", 0,
SLAVE_L7, 7, TF_LARB_L7, 0),
MTK_IOMMU_PORT_INIT("L7_VENC_REC", 0,
SLAVE_L7, 7, TF_LARB_L7, 1),
MTK_IOMMU_PORT_INIT("L7_VENC_BSDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 2),
MTK_IOMMU_PORT_INIT("L7_VENC_SV_COMV", 0,
SLAVE_L7, 7, TF_LARB_L7, 3),
MTK_IOMMU_PORT_INIT("L7_VENC_RD_COMV", 0,
SLAVE_L7, 7, TF_LARB_L7, 4),
MTK_IOMMU_PORT_INIT("L7_VENC_CUR_LUMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 5),
MTK_IOMMU_PORT_INIT("L7_VENC_CUR_CHROMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 6),
MTK_IOMMU_PORT_INIT("L7_VENC_REF_LUMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 7),
MTK_IOMMU_PORT_INIT("L7_VENC_REF_CHROMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 8),
MTK_IOMMU_PORT_INIT("L7_JPGENC_Y_RDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 9),
MTK_IOMMU_PORT_INIT("L7_JPGENC_C_RDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 10),
MTK_IOMMU_PORT_INIT("L7_JPGENC_Q_TABLE", 0,
SLAVE_L7, 7, TF_LARB_L7, 11),
MTK_IOMMU_PORT_INIT("L7_JPGENC_BSDMA", 0,
SLAVE_L7, 7, TF_LARB_L7, 12),
/*Larb9 -- 29(68) */
MTK_IOMMU_PORT_INIT("L9_IMG_IMGI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 0),
MTK_IOMMU_PORT_INIT("L9_IMG_IMGBI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 1),
MTK_IOMMU_PORT_INIT("L9_IMG_DMGI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 2),
MTK_IOMMU_PORT_INIT("L9_IMG_DEPI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 3),
MTK_IOMMU_PORT_INIT("L9_IMG_ICE_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 4),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 5),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D2", 0,
SLAVE_L9, 9, TF_LARB_L9, 6),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 7),
MTK_IOMMU_PORT_INIT("L9_IMG_CRZO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 8),
MTK_IOMMU_PORT_INIT("L9_IMG_IMG3O_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 9),
MTK_IOMMU_PORT_INIT("L9_IMG_VIPI_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 10),
MTK_IOMMU_PORT_INIT("L9_IMG_SMTI_D5", 0,
SLAVE_L9, 9, TF_LARB_L9, 11),
MTK_IOMMU_PORT_INIT("L9_IMG_TIMGO_D1", 0,
SLAVE_L9, 9, TF_LARB_L9, 12),
MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_W0", 0,
SLAVE_L9, 9, TF_LARB_L9, 13),
MTK_IOMMU_PORT_INIT("L9_IMG_UFBC_R0", 0,
SLAVE_L9, 9, TF_LARB_L9, 14),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 15),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_RDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 16),
MTK_IOMMU_PORT_INIT("L9_IMG_WPE_WDMA", 0,
SLAVE_L9, 9, TF_LARB_L9, 17),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 18),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 19),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA2", 0,
SLAVE_L9, 9, TF_LARB_L9, 20),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA3", 0,
SLAVE_L9, 9, TF_LARB_L9, 21),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA4", 0,
SLAVE_L9, 9, TF_LARB_L9, 22),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_RDMA5", 0,
SLAVE_L9, 9, TF_LARB_L9, 23),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA0", 0,
SLAVE_L9, 9, TF_LARB_L9, 24),
MTK_IOMMU_PORT_INIT("L9_IMG_MFB_WDMA1", 0,
SLAVE_L9, 9, TF_LARB_L9, 25),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE6", 0,
SLAVE_L9, 9, TF_LARB_L9, 26),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE7", 0,
SLAVE_L9, 9, TF_LARB_L9, 27),
MTK_IOMMU_PORT_INIT("L9_IMG_RESERVE8", 0,
SLAVE_L9, 9, TF_LARB_L9, 28),
/*Larb11 -- 29(97) */
MTK_IOMMU_PORT_INIT("L11_IMG_IMGI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 0),
MTK_IOMMU_PORT_INIT("L11_IMG_IMGBI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 1),
MTK_IOMMU_PORT_INIT("L11_IMG_DMGI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 2),
MTK_IOMMU_PORT_INIT("L11_IMG_DEPI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 3),
MTK_IOMMU_PORT_INIT("L11_IMG_ICE_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 4),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 5),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D2", 0,
SLAVE_L11, 11, TF_LARB_L11, 6),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 7),
MTK_IOMMU_PORT_INIT("L11_IMG_CRZO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 8),
MTK_IOMMU_PORT_INIT("L11_IMG_IMG3O_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 9),
MTK_IOMMU_PORT_INIT("L11_IMG_VIPI_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 10),
MTK_IOMMU_PORT_INIT("L11_IMG_SMTI_D5", 0,
SLAVE_L11, 11, TF_LARB_L11, 11),
MTK_IOMMU_PORT_INIT("L11_IMG_TIMGO_D1", 0,
SLAVE_L11, 11, TF_LARB_L11, 12),
MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_W0", 0,
SLAVE_L11, 11, TF_LARB_L11, 13),
MTK_IOMMU_PORT_INIT("L11_IMG_UFBC_R0", 0,
SLAVE_L11, 11, TF_LARB_L11, 14),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 15),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_RDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 16),
MTK_IOMMU_PORT_INIT("L11_IMG_WPE_WDMA", 0,
SLAVE_L11, 11, TF_LARB_L11, 17),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 18),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 19),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA2", 0,
SLAVE_L11, 11, TF_LARB_L11, 20),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA3", 0,
SLAVE_L11, 11, TF_LARB_L11, 21),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA4", 0,
SLAVE_L11, 11, TF_LARB_L11, 22),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_RDMA5", 0,
SLAVE_L11, 11, TF_LARB_L11, 23),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA0", 0,
SLAVE_L11, 11, TF_LARB_L11, 24),
MTK_IOMMU_PORT_INIT("L11_IMG_MFB_WDMA1", 0,
SLAVE_L11, 11, TF_LARB_L11, 25),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE6", 0,
SLAVE_L11, 11, TF_LARB_L11, 26),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE7", 0,
SLAVE_L11, 11, TF_LARB_L11, 27),
MTK_IOMMU_PORT_INIT("L11_IMG_RESERVE8", 0,
SLAVE_L11, 11, TF_LARB_L11, 28),
/*Larb13 -- 12(109) */
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWI", 0,
SLAVE_L13, 13, TF_LARB_L13, 0),
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO0", 0,
SLAVE_L13, 13, TF_LARB_L13, 1),
MTK_IOMMU_PORT_INIT("L13_CAM_MRAWO1", 0,
SLAVE_L13, 13, TF_LARB_L13, 2),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE1", 0,
SLAVE_L13, 13, TF_LARB_L13, 3),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE2", 0,
SLAVE_L13, 13, TF_LARB_L13, 4),
MTK_IOMMU_PORT_INIT("L13_CAM_RESERVE3", 0,
SLAVE_L13, 13, TF_LARB_L13, 5),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV4", 0,
SLAVE_L13, 13, TF_LARB_L13, 6),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV5", 0,
SLAVE_L13, 13, TF_LARB_L13, 7),
MTK_IOMMU_PORT_INIT("L13_CAM_CAMSV6", 0,
SLAVE_L13, 13, TF_LARB_L13, 8),
MTK_IOMMU_PORT_INIT("L13_CAM_CCUI", 0,
SLAVE_L13, 13, TF_LARB_L13, 9),
MTK_IOMMU_PORT_INIT("L13_CAM_CCUO", 0,
SLAVE_L13, 13, TF_LARB_L13, 10),
MTK_IOMMU_PORT_INIT("L13_CAM_FAKE", 0,
SLAVE_L13, 13, TF_LARB_L13, 11),
/*Larb14 -- 6(115) */
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE1", 0,
SLAVE_L14, 14, TF_LARB_L14, 0),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE2", 0,
SLAVE_L14, 14, TF_LARB_L14, 1),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE3", 0,
SLAVE_L14, 14, TF_LARB_L14, 2),
MTK_IOMMU_PORT_INIT("L14_CAM_RESERVE4", 0,
SLAVE_L14, 14, TF_LARB_L14, 3),
MTK_IOMMU_PORT_INIT("L14_CAM_CCUI", 0,
SLAVE_L14, 14, TF_LARB_L14, 4),
MTK_IOMMU_PORT_INIT("L14_CAM_CCUO", 0,
SLAVE_L14, 14, TF_LARB_L14, 5),
/*Larb16 -- 17(132) */
MTK_IOMMU_PORT_INIT("L16_CAM_IMGO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 0),
MTK_IOMMU_PORT_INIT("L16_CAM_RRZO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 1),
MTK_IOMMU_PORT_INIT("L16_CAM_CQI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 2),
MTK_IOMMU_PORT_INIT("L16_CAM_BPCI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 3),
MTK_IOMMU_PORT_INIT("L16_CAM_YUVO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 4),
MTK_IOMMU_PORT_INIT("L16_CAM_UFDI_R2_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 5),
MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R2_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 6),
MTK_IOMMU_PORT_INIT("L16_CAM_RAWI_R3_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 7),
MTK_IOMMU_PORT_INIT("L16_CAM_AAO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 8),
MTK_IOMMU_PORT_INIT("L16_CAM_AFO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 9),
MTK_IOMMU_PORT_INIT("L16_CAM_FLKO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 10),
MTK_IOMMU_PORT_INIT("L16_CAM_LCESO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 11),
MTK_IOMMU_PORT_INIT("L16_CAM_CRZO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 12),
MTK_IOMMU_PORT_INIT("L16_CAM_LTMSO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 13),
MTK_IOMMU_PORT_INIT("L16_CAM_RSSO_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 14),
MTK_IOMMU_PORT_INIT("L16_CAM_AAHO_R1_A_", 0,
SLAVE_L16, 16, TF_LARB_L16, 15),
MTK_IOMMU_PORT_INIT("L16_CAM_LSCI_R1_A", 0,
SLAVE_L16, 16, TF_LARB_L16, 16),
/*Larb17 -- 17(149) */
MTK_IOMMU_PORT_INIT("L17_CAM_IMGO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 0),
MTK_IOMMU_PORT_INIT("L17_CAM_RRZO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 1),
MTK_IOMMU_PORT_INIT("L17_CAM_CQI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 2),
MTK_IOMMU_PORT_INIT("L17_CAM_BPCI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 3),
MTK_IOMMU_PORT_INIT("L17_CAM_YUVO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 4),
MTK_IOMMU_PORT_INIT("L17_CAM_UFDI_R2_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 5),
MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R2_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 6),
MTK_IOMMU_PORT_INIT("L17_CAM_RAWI_R3_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 7),
MTK_IOMMU_PORT_INIT("L17_CAM_AAO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 8),
MTK_IOMMU_PORT_INIT("L17_CAM_AFO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 9),
MTK_IOMMU_PORT_INIT("L17_CAM_FLKO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 10),
MTK_IOMMU_PORT_INIT("L17_CAM_LCESO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 11),
MTK_IOMMU_PORT_INIT("L17_CAM_CRZO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 12),
MTK_IOMMU_PORT_INIT("L17_CAM_LTMSO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 13),
MTK_IOMMU_PORT_INIT("L17_CAM_RSSO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 14),
MTK_IOMMU_PORT_INIT("L17_CAM_AAHO_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 15),
MTK_IOMMU_PORT_INIT("L17_CAM_LSCI_R1_B", 0,
SLAVE_L17, 17, TF_LARB_L17, 16),
/*Larb18 -- 17(166) */
MTK_IOMMU_PORT_INIT("L18_CAM_IMGO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 0),
MTK_IOMMU_PORT_INIT("L18_CAM_RRZO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 1),
MTK_IOMMU_PORT_INIT("L18_CAM_CQI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 2),
MTK_IOMMU_PORT_INIT("L18_CAM_BPCI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 3),
MTK_IOMMU_PORT_INIT("L18_CAM_YUVO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 4),
MTK_IOMMU_PORT_INIT("L18_CAM_UFDI_R2_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 5),
MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R2_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 6),
MTK_IOMMU_PORT_INIT("L18_CAM_RAWI_R3_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 7),
MTK_IOMMU_PORT_INIT("L18_CAM_AAO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 8),
MTK_IOMMU_PORT_INIT("L18_CAM_AFO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 9),
MTK_IOMMU_PORT_INIT("L18_CAM_FLKO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 10),
MTK_IOMMU_PORT_INIT("L18_CAM_LCESO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 11),
MTK_IOMMU_PORT_INIT("L18_CAM_CRZO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 12),
MTK_IOMMU_PORT_INIT("L18_CAM_LTMSO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 13),
MTK_IOMMU_PORT_INIT("L18_CAM_RSSO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 14),
MTK_IOMMU_PORT_INIT("L18_CAM_AAHO_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 15),
MTK_IOMMU_PORT_INIT("L18_CAM_LSCI_R1_C", 0,
SLAVE_L18, 18, TF_LARB_L18, 16),
/*Larb19 -- 4(170) */
MTK_IOMMU_PORT_INIT("L19_IPE_DVS_RDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 0),
MTK_IOMMU_PORT_INIT("L19_IPE_DVS_WDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 1),
MTK_IOMMU_PORT_INIT("L19_IPE_DVP_RDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 2),
MTK_IOMMU_PORT_INIT("L19_IPE_DVP_WDMA", 0,
SLAVE_L19, 19, TF_LARB_L19, 3),
/*Larb20 -- 6(176) */
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDA", 0,
SLAVE_L20, 20, TF_LARB_L20, 0),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_RDB", 0,
SLAVE_L20, 20, TF_LARB_L20, 1),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRA", 0,
SLAVE_L20, 20, TF_LARB_L20, 2),
MTK_IOMMU_PORT_INIT("L20_IPE_FDVT_WRB", 0,
SLAVE_L20, 20, TF_LARB_L20, 3),
MTK_IOMMU_PORT_INIT("L20_IPE_RSC_RDMA0", 0,
SLAVE_L20, 20, TF_LARB_L20, 4),
MTK_IOMMU_PORT_INIT("L20_IPE_RSC_WDMA", 0,
SLAVE_L20, 20, TF_LARB_L20, 5),
/* only atf maybe need it, but kernel can't delete it,
* otherwise it affect index.
*/
/*Larb21 -- 3(179) */
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_CODE", 1,
SLAVE_APU, 21, TF_APU, 0),
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_DATA", 1,
SLAVE_APU, 21, TF_APU, 1),
MTK_IOMMU_PORT_INIT("L21_APU_FAKE_VLM", 1,
SLAVE_APU, 21, TF_APU, 2),
/*Larb22 -- 1(180) */
MTK_IOMMU_PORT_INIT("L22_CCU0", 0,
SLAVE_CCU0, 22, TF_CCU0, 0),
/*Larb23 -- 1(181) */
MTK_IOMMU_PORT_INIT("L23_CCU1", 0,
SLAVE_CCU1, 23, TF_CCU1, 0),
/*Larb23 -- 1(182: 0~181) */
MTK_IOMMU_PORT_INIT("UNKNOWN", 0, 0, 0, 0, 0)
};
/* APU_IOMMU AXI_ID */
#define TF_VP6_0 (0x0)
#define TF_VP6_1 (0x1)
#define TF_UP (0x2)
#define TF_XPU (0x3)
#define MSK_VP6_0 F_MSK(10, 7)
#define MSK_VP6_1 F_MSK(10, 7)
#define MSK_UP F_MSK(10, 7)
#define MSK_XPU F_MSK(10, 7)
#define IOMMU_APU_AXI_PORT_NR (4)
static uint32_t vpu_axi_bus_id[IOMMU_APU_AXI_PORT_NR] = {
TF_VP6_0, TF_VP6_1, TF_UP, TF_XPU};
static uint32_t vpu_axi_bus_mask[IOMMU_APU_AXI_PORT_NR] = {
MSK_VP6_0, MSK_VP6_1, MSK_UP, MSK_XPU};
static char *vpu_axi_bus_name[IOMMU_APU_AXI_PORT_NR] = {
"APU_VP6_0", "APU_VP6_1", "APU_UP", "APU_XPU"};
#ifndef M4U_PORT_NR
#define M4U_PORT_NR (181)
#endif
#endif
drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mtk_battery_property.h
+277
View File
@@ -0,0 +1,277 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef _MTK_BATTERY_PROPERTY_H
#define _MTK_BATTERY_PROPERTY_H
/* customize */
#define DIFFERENCE_FULLOCV_ITH 200 /* mA */
#define MTK_CHR_EXIST 1
#define KEEP_100_PERCENT 1
#define R_FG_VALUE 5 /* mOhm */
#define EMBEDDED_SEL 0
#define PMIC_SHUTDOWN_CURRENT 20 /* 0.01 mA */
#define FG_METER_RESISTANCE 100
#define CAR_TUNE_VALUE 100 /*1.00 */
#define NO_BAT_TEMP_COMPENSATE 0
/* NO_BAT_TEMP_COMPENSATE 1 = don't need bat_temper compensate, */
/* but fg_meter_resistance still use for SWOCV */
/* enable that soc = 0 , shutdown */
#define SHUTDOWN_GAUGE0 1
/* enable that uisoc = 1 and wait xmins then shutdown */
#define SHUTDOWN_GAUGE1_XMINS 1
/* define Xmins to shutdown*/
#define SHUTDOWN_1_TIME 5
#define SHUTDOWN_GAUGE1_VBAT_EN 0
#define SHUTDOWN_GAUGE1_VBAT 34000
#define SHUTDOWN_GAUGE0_VOLTAGE 34000
#define POWERON_SYSTEM_IBOOT 500 /* mA */
/*
* LOW_TEMP_MODE = 0
* disable LOW_TEMP_MODE
* LOW_TEMP_MODE = 1
* if battery temperautre < LOW_TEMP_MODE_TEMP
* when bootup , force C mode
* LOW_TEMP_MODE = 2
* if battery temperautre < LOW_TEMP_MODE_TEMP
* force C mode
*/
#define LOW_TEMP_MODE 0
#define LOW_TEMP_MODE_TEMP 0
#define D0_SEL 0 /* not implement */
#define AGING_SEL 0 /* not implement */
#define DLPT_UI_REMAP_EN 0
/* ADC resistor */
#define R_BAT_SENSE 4
#define R_I_SENSE 4
#define R_CHARGER_1 330
#define R_CHARGER_2 39
#define QMAX_SEL 1
#define IBOOT_SEL 0
#define SHUTDOWN_SYSTEM_IBOOT 15000 /* 0.1mA */
#define PMIC_MIN_VOL 33500
/*ui_soc related */
#define DIFFERENCE_FULL_CV 1000 /*0.01%*/
#define PSEUDO1_EN 1
#define PSEUDO100_EN 1
#define PSEUDO100_EN_DIS 0
#define DIFF_SOC_SETTING 50 /* 0.01% */
#define DIFF_BAT_TEMP_SETTING 1
#define DIFF_BAT_TEMP_SETTING_C 10
#define DISCHARGE_TRACKING_TIME 10
#define CHARGE_TRACKING_TIME 60
#define DIFFERENCE_FULLOCV_VTH 1000 /* 0.1mV */
#define CHARGE_PSEUDO_FULL_LEVEL 8000
#define FULL_TRACKING_BAT_INT2_MULTIPLY 6
/* pre tracking */
#define FG_PRE_TRACKING_EN 1
#define VBAT2_DET_TIME 5
#define VBAT2_DET_COUNTER 6
#define VBAT2_DET_VOLTAGE1 34500
#define VBAT2_DET_VOLTAGE2 32000
#define VBAT2_DET_VOLTAGE3 35000
/* PCB setting */
#define CALIBRATE_CAR_TUNE_VALUE_BY_META_TOOL
#define CALI_CAR_TUNE_AVG_NUM 60
/* Aging Compensation 1*/
#define AGING_FACTOR_MIN 90
#define AGING_FACTOR_DIFF 10
#define DIFFERENCE_VOLTAGE_UPDATE 50
#define AGING_ONE_EN 1
#define AGING1_UPDATE_SOC 30
#define AGING1_LOAD_SOC 70
#define AGING_TEMP_DIFF 10
#define AGING_TEMP_LOW_LIMIT 15
#define AGING_TEMP_HIGH_LIMIT 50
#define AGING_100_EN 1
/* Aging Compensation 2*/
#define AGING_TWO_EN 1
/* Aging Compensation 3*/
#define AGING_THIRD_EN 1
#define AGING_4_EN 1
#define AGING_5_EN 1
#define AGING_6_EN 1
#define AGING4_UPDATE_SOC 40
#define AGING4_LOAD_SOC 70
#define AGING5_UPDATE_SOC 30
#define AGING5_LOAD_SOC 70
#define AGING6_UPDATE_SOC 30
#define AGING6_LOAD_SOC 70
/* threshold */
#define HWOCV_SWOCV_DIFF 300
#define HWOCV_SWOCV_DIFF_LT 1500
#define HWOCV_SWOCV_DIFF_LT_TEMP 5
#define HWOCV_OLDOCV_DIFF 300
#define HWOCV_OLDOCV_DIFF_CHR 800
#define SWOCV_OLDOCV_DIFF 300
#define SWOCV_OLDOCV_DIFF_CHR 800
#define VBAT_OLDOCV_DIFF 1000
#define SWOCV_OLDOCV_DIFF_EMB 1000 /* 100mV */
#define VIR_OLDOCV_DIFF_EMB 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_LT 10000 /* 1000mV */
#define VIR_OLDOCV_DIFF_EMB_TMP 5
#define TNEW_TOLD_PON_DIFF 5
#define TNEW_TOLD_PON_DIFF2 15
#define PMIC_SHUTDOWN_TIME 30
#define BAT_PLUG_OUT_TIME 32
#define EXT_HWOCV_SWOCV 300
#define EXT_HWOCV_SWOCV_LT 1500
#define EXT_HWOCV_SWOCV_LT_TEMP 5
/* fgc & fgv threshold */
#define DIFFERENCE_FGC_FGV_TH1 300
#define DIFFERENCE_FGC_FGV_TH2 500
#define DIFFERENCE_FGC_FGV_TH3 300
#define DIFFERENCE_FGC_FGV_TH_SOC1 7000
#define DIFFERENCE_FGC_FGV_TH_SOC2 3000
#define NAFG_TIME_SETTING 10
#define NAFG_RATIO 100
#define NAFG_RATIO_EN 0
#define NAFG_RATIO_TMP_THR 1
#define NAFG_RESISTANCE 1500
#define PMIC_SHUTDOWN_SW_EN 1
#define FORCE_VC_MODE 0 /* 0: mix, 1:Coulomb, 2:voltage */
#define LOADING_1_EN 0
#define LOADING_2_EN 2
#define DIFF_IAVG_TH 3000
/* ZCV INTR */
#define ZCV_SUSPEND_TIME 7
#define SLEEP_CURRENT_AVG 200 /*0.1mA*/
#define ZCV_COM_VOL_LIMIT 50 /* 50mv */
#define ZCV_CAR_GAP_PERCENTAGE 5
/* Additional battery table */
#define ADDITIONAL_BATTERY_TABLE_EN 1
#define DC_RATIO_SEL 5
#define DC_R_CNT 1000 /* if set 0, dcr_start will not be 1*/
#define BAT_PAR_I 4000 /* not implement */
#define PSEUDO1_SEL 2
#define FG_TRACKING_CURRENT 30000 /* not implement */
#define FG_TRACKING_CURRENT_IBOOT_EN 0 /* not implement */
#define UI_FAST_TRACKING_EN 0
#define UI_FAST_TRACKING_GAP 300
#define KEEP_100_PERCENT_MINSOC 9000
#define SHUTDOWN_CONDITION_LOW_BAT_VOLT
#define LOW_TEMP_DISABLE_LOW_BAT_SHUTDOWN 1
#define LOW_TEMP_THRESHOLD 5
#define BATTERY_TMP_TO_DISABLE_GM30 -50
#define BATTERY_TMP_TO_DISABLE_NAFG -35
#define DEFAULT_BATTERY_TMP_WHEN_DISABLE_NAFG 25
#define BATTERY_TMP_TO_ENABLE_NAFG -20
/* #define GM30_DISABLE_NAFG */
#define POWER_ON_CAR_CHR 5
#define POWER_ON_CAR_NOCHR -35
#define SHUTDOWN_CAR_RATIO 1
#define MULTI_TEMP_GAUGE0 1 /* different temp using different gauge 0% */
#define OVER_DISCHARGE_LEVEL -1500
#define UISOC_UPDATE_TYPE 0
/*
* uisoc_update_type:
* 0: only ui_soc interrupt update ui_soc
* 1: coulomb/nafg will update ui_soc if delta car > ht/lt_gap /2
* 2: coulomb/nafg will update ui_soc
*/
/* using current to limit uisoc in 100% case*/
/* UI_FULL_LIMIT_ITH0 3000 means 300ma */
#define UI_FULL_LIMIT_EN 0
#define UI_FULL_LIMIT_SOC0 9900
#define UI_FULL_LIMIT_ITH0 2200
#define UI_FULL_LIMIT_SOC1 9900
#define UI_FULL_LIMIT_ITH1 2200
#define UI_FULL_LIMIT_SOC2 9900
#define UI_FULL_LIMIT_ITH2 2200
#define UI_FULL_LIMIT_SOC3 9900
#define UI_FULL_LIMIT_ITH3 2200
#define UI_FULL_LIMIT_SOC4 9900
#define UI_FULL_LIMIT_ITH4 2200
#define UI_FULL_LIMIT_TIME 99999
#define UI_FULL_LIMIT_FC_SOC0 9900
#define UI_FULL_LIMIT_FC_ITH0 3000
#define UI_FULL_LIMIT_FC_SOC1 9900
#define UI_FULL_LIMIT_FC_ITH1 3100
#define UI_FULL_LIMIT_FC_SOC2 9900
#define UI_FULL_LIMIT_FC_ITH2 3200
#define UI_FULL_LIMIT_FC_SOC3 9900
#define UI_FULL_LIMIT_FC_ITH3 3300
#define UI_FULL_LIMIT_FC_SOC4 9900
#define UI_FULL_LIMIT_FC_ITH4 3400
/* using voltage to limit uisoc in 1% case */
/* UI_LOW_LIMIT_VTH0=36000 means 3.6v */
#define UI_LOW_LIMIT_EN 0
#define UI_LOW_LIMIT_SOC0 200
#define UI_LOW_LIMIT_VTH0 34500
#define UI_LOW_LIMIT_SOC1 200
#define UI_LOW_LIMIT_VTH1 34500
#define UI_LOW_LIMIT_SOC2 200
#define UI_LOW_LIMIT_VTH2 34500
#define UI_LOW_LIMIT_SOC3 200
#define UI_LOW_LIMIT_VTH3 34500
#define UI_LOW_LIMIT_SOC4 200
#define UI_LOW_LIMIT_VTH4 34500
#define UI_LOW_LIMIT_TIME 99999
#define MOVING_BATTEMP_EN 1
#define MOVING_BATTEMP_THR 20
#endif
drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mtk_battery_table.h
+4203
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drivers/misc/mediatek/include/mt-plat/mt6833/include/mach/mtk_cpufreq_api.h
+87
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __MTK_CPUFREQ_API_H__
#define __MTK_CPUFREQ_API_H__
#define VOLT_PRECHANGE 0
#define VOLT_POSTCHANGE 1
#define VOLT_UP 0
#define VOLT_DOWN 1
enum cpu_dvfs_sched_type {
SCHE_INVALID,
SCHE_VALID,
SCHE_ONESHOT,
NUM_SCHE_TYPE
};
/* Schedule Assist Input */
extern int mt_cpufreq_set_by_wfi_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_set_by_schedule_load_cluster(unsigned int cluster_id,
unsigned int freq);
extern unsigned int mt_cpufreq_find_close_freq(unsigned int cluster_id,
unsigned int freq);
extern int mt_cpufreq_get_sched_enable(void);
/* PTP-OD */
extern unsigned int mt_cpufreq_get_freq_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cpu_freq(int cpu, int idx);
extern unsigned int mt_cpufreq_get_volt_by_idx(unsigned int cluster_id,
int idx);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
typedef void (*mt_cpufreq_set_ptbl_funcPTP)(unsigned int cluster_id,
int restore);
extern void mt_cpufreq_set_ptbl_registerCB(mt_cpufreq_set_ptbl_funcPTP pCB);
extern int mt_cpufreq_update_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
extern unsigned int mt_cpufreq_get_cur_volt(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_freq(unsigned int cluster_id);
extern void mt_cpufreq_ctrl_cci_volt(unsigned int volt);
extern void notify_cpu_volt_sampler(unsigned int cluster_id,
unsigned int volt, int up, int event);
typedef void (*cpuVoltsampler_func) (unsigned int cluster_id,
unsigned int mv, int up, int event);
extern void mt_cpufreq_setvolt_registerCB(cpuVoltsampler_func pCB);
/* PPB */
extern int mt_cpufreq_get_ppb_state(void);
/* PPM */
extern unsigned int mt_cpufreq_get_cur_phy_freq(unsigned int cluster_id);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_no_lock(unsigned int cluster_id);
extern void mt_cpufreq_setvolt_ocp_registerCB(cpuVoltsampler_func pCB);
extern unsigned int mt_cpufreq_find_Vboot_idx(unsigned int cluster_id);
/* Upower */
extern unsigned int mt_cpufreq_get_cpu_level(void);
/* dfd */
extern void dfd_workaround(void);
/* CPI */
extern unsigned int mt_cpufreq_get_cur_freq_idx(unsigned int cluster_id);
extern unsigned int mt_cpufreq_get_cur_cci_freq_idx(void);
extern unsigned int
mt_cpufreq_get_cur_phy_freq_idx_no_lock(unsigned int cluster_id);
typedef void (*cpuFreqsampler_func)(unsigned int cluster_id, unsigned int freq);
extern void mt_cpufreq_set_governor_freq_registerCB(cpuFreqsampler_func pCB);
/* CPUFREQ */
extern void aee_record_cpufreq_cb(unsigned int step);
extern int mt_cpufreq_update_legacy_volt(unsigned int cluster_id,
unsigned int *volt_tbl, int nr_volt_tbl);
#endif /* __MTK_CPUFREQ_API_H__ */
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