Initial commit: Linux kernel 4.19 for Unplugged OS

include/dt-bindings/memory/mt2701-larb-port.h

@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ * Author: Honghui Zhang <honghui.zhang@mediatek.com>
+ */
+
+#ifndef _MT2701_LARB_PORT_H_
+#define _MT2701_LARB_PORT_H_
+
+/*
+ * Mediatek m4u generation 1 such as mt2701 has flat m4u port numbers,
+ * the first port's id for larb[N] would be the last port's id of larb[N - 1]
+ * plus one while larb[0]'s first port number is 0. The definition of
+ * MT2701_M4U_ID_LARBx is following HW register spec.
+ * But m4u generation 2 like mt8173 have different port number, it use fixed
+ * offset for each larb, the first port's id for larb[N] would be (N * 32).
+ */
+#define LARB0_PORT_OFFSET		0
+#define LARB1_PORT_OFFSET		11
+#define LARB2_PORT_OFFSET		21
+#define LARB3_PORT_OFFSET		44
+
+#define MT2701_M4U_ID_LARB0(port)	((port) + LARB0_PORT_OFFSET)
+#define MT2701_M4U_ID_LARB1(port)	((port) + LARB1_PORT_OFFSET)
+#define MT2701_M4U_ID_LARB2(port)	((port) + LARB2_PORT_OFFSET)
+
+/* Port define for larb0 */
+#define MT2701_M4U_PORT_DISP_OVL_0		MT2701_M4U_ID_LARB0(0)
+#define MT2701_M4U_PORT_DISP_RDMA1		MT2701_M4U_ID_LARB0(1)
+#define MT2701_M4U_PORT_DISP_RDMA		MT2701_M4U_ID_LARB0(2)
+#define MT2701_M4U_PORT_DISP_WDMA		MT2701_M4U_ID_LARB0(3)
+#define MT2701_M4U_PORT_MM_CMDQ			MT2701_M4U_ID_LARB0(4)
+#define MT2701_M4U_PORT_MDP_RDMA		MT2701_M4U_ID_LARB0(5)
+#define MT2701_M4U_PORT_MDP_WDMA		MT2701_M4U_ID_LARB0(6)
+#define MT2701_M4U_PORT_MDP_ROTO		MT2701_M4U_ID_LARB0(7)
+#define MT2701_M4U_PORT_MDP_ROTCO		MT2701_M4U_ID_LARB0(8)
+#define MT2701_M4U_PORT_MDP_ROTVO		MT2701_M4U_ID_LARB0(9)
+#define MT2701_M4U_PORT_MDP_RDMA1		MT2701_M4U_ID_LARB0(10)
+
+/* Port define for larb1 */
+#define MT2701_M4U_PORT_VDEC_MC_EXT		MT2701_M4U_ID_LARB1(0)
+#define MT2701_M4U_PORT_VDEC_PP_EXT		MT2701_M4U_ID_LARB1(1)
+#define MT2701_M4U_PORT_VDEC_PPWRAP_EXT		MT2701_M4U_ID_LARB1(2)
+#define MT2701_M4U_PORT_VDEC_AVC_MV_EXT		MT2701_M4U_ID_LARB1(3)
+#define MT2701_M4U_PORT_VDEC_PRED_RD_EXT	MT2701_M4U_ID_LARB1(4)
+#define MT2701_M4U_PORT_VDEC_PRED_WR_EXT	MT2701_M4U_ID_LARB1(5)
+#define MT2701_M4U_PORT_VDEC_VLD_EXT		MT2701_M4U_ID_LARB1(6)
+#define MT2701_M4U_PORT_VDEC_VLD2_EXT		MT2701_M4U_ID_LARB1(7)
+#define MT2701_M4U_PORT_VDEC_TILE_EXT		MT2701_M4U_ID_LARB1(8)
+#define MT2701_M4U_PORT_VDEC_IMG_RESZ_EXT	MT2701_M4U_ID_LARB1(9)
+
+/* Port define for larb2 */
+#define MT2701_M4U_PORT_VENC_RCPU		MT2701_M4U_ID_LARB2(0)
+#define MT2701_M4U_PORT_VENC_REC_FRM		MT2701_M4U_ID_LARB2(1)
+#define MT2701_M4U_PORT_VENC_BSDMA		MT2701_M4U_ID_LARB2(2)
+#define MT2701_M4U_PORT_JPGENC_RDMA		MT2701_M4U_ID_LARB2(3)
+#define MT2701_M4U_PORT_VENC_LT_RCPU		MT2701_M4U_ID_LARB2(4)
+#define MT2701_M4U_PORT_VENC_LT_REC_FRM		MT2701_M4U_ID_LARB2(5)
+#define MT2701_M4U_PORT_VENC_LT_BSDMA		MT2701_M4U_ID_LARB2(6)
+#define MT2701_M4U_PORT_JPGDEC_BSDMA		MT2701_M4U_ID_LARB2(7)
+#define MT2701_M4U_PORT_VENC_SV_COMV		MT2701_M4U_ID_LARB2(8)
+#define MT2701_M4U_PORT_VENC_RD_COMV		MT2701_M4U_ID_LARB2(9)
+#define MT2701_M4U_PORT_JPGENC_BSDMA		MT2701_M4U_ID_LARB2(10)
+#define MT2701_M4U_PORT_VENC_CUR_LUMA		MT2701_M4U_ID_LARB2(11)
+#define MT2701_M4U_PORT_VENC_CUR_CHROMA		MT2701_M4U_ID_LARB2(12)
+#define MT2701_M4U_PORT_VENC_REF_LUMA		MT2701_M4U_ID_LARB2(13)
+#define MT2701_M4U_PORT_VENC_REF_CHROMA		MT2701_M4U_ID_LARB2(14)
+#define MT2701_M4U_PORT_IMG_RESZ		MT2701_M4U_ID_LARB2(15)
+#define MT2701_M4U_PORT_VENC_LT_SV_COMV		MT2701_M4U_ID_LARB2(16)
+#define MT2701_M4U_PORT_VENC_LT_RD_COMV		MT2701_M4U_ID_LARB2(17)
+#define MT2701_M4U_PORT_VENC_LT_CUR_LUMA	MT2701_M4U_ID_LARB2(18)
+#define MT2701_M4U_PORT_VENC_LT_CUR_CHROMA	MT2701_M4U_ID_LARB2(19)
+#define MT2701_M4U_PORT_VENC_LT_REF_LUMA	MT2701_M4U_ID_LARB2(20)
+#define MT2701_M4U_PORT_VENC_LT_REF_CHROMA	MT2701_M4U_ID_LARB2(21)
+#define MT2701_M4U_PORT_JPGDEC_WDMA		MT2701_M4U_ID_LARB2(22)
+
+#endif

include/dt-bindings/memory/mt2712-larb-port.h

@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT2712_H
+#define __DTS_IOMMU_PORT_MT2712_H
+
+#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
+
+#define M4U_LARB0_ID			0
+#define M4U_LARB1_ID			1
+#define M4U_LARB2_ID			2
+#define M4U_LARB3_ID			3
+#define M4U_LARB4_ID			4
+#define M4U_LARB5_ID			5
+#define M4U_LARB6_ID			6
+#define M4U_LARB7_ID			7
+#define M4U_LARB8_ID			8
+#define M4U_LARB9_ID			9
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB0_ID, 7)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_HW_IMG_RESZ_EXT	MTK_M4U_ID(M4U_LARB1_ID, 10)
+
+/* larb2 */
+#define M4U_PORT_CAM_DMA0		MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_DMA1		MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_DMA2		MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_OD1_R		MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_DISP_OD1_W		MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 6)
+
+/* larb5 */
+#define M4U_PORT_DISP_OVL2		MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_DISP_WDMA2		MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_MDP_RDMA2		MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB5_ID, 3)
+
+/* larb6 */
+#define M4U_PORT_JPGDEC_WDMA_0		MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_JPGDEC_WDMA_1		MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_JPGDEC_BSDMA_0		MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_JPGDEC_BSDMA_1		MTK_M4U_ID(M4U_LARB6_ID, 3)
+
+/* larb7 */
+#define M4U_PORT_MDP_RDMA3		MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_MDP_WROT2		MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+/* larb8 */
+#define M4U_PORT_VDO			MTK_M4U_ID(M4U_LARB8_ID, 0)
+#define M4U_PORT_NR			MTK_M4U_ID(M4U_LARB8_ID, 1)
+#define M4U_PORT_WR_CHANNEL0		MTK_M4U_ID(M4U_LARB8_ID, 2)
+
+/* larb9 */
+#define M4U_PORT_TVD			MTK_M4U_ID(M4U_LARB9_ID, 0)
+#define M4U_PORT_WR_CHANNEL1		MTK_M4U_ID(M4U_LARB9_ID, 1)
+
+#endif

include/dt-bindings/memory/mt6761-larb-port.h

@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Owen Chen <owen.chen@mediatek.com>
+ */
+#ifndef _DTS_IOMMU_PORT_MT6761_H_
+#define _DTS_IOMMU_PORT_MT6761_H_
+
+#define MTK_M4U_ID(larb, port)	(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x7)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
+
+
+
+#define M4U_LARB0_ID		8
+#define M4U_LARB1_ID		11
+#define M4U_LARB2_ID		24
+
+#define MTK_IOMMU_LARB_NR 3
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0	MTK_M4U_ID(0, 1)
+#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(0, 2)
+#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(0, 3)
+#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(0, 4)
+#define M4U_PORT_MDP_WDMA0		MTK_M4U_ID(0, 5)
+#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(0, 6)
+#define M4U_PORT_DISP_FAKE0		MTK_M4U_ID(0, 7)
+/* larb1 */
+#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(1, 0)
+#define M4U_PORT_VENC_REC		MTK_M4U_ID(1, 1)
+#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(1, 2)
+#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(1, 3)
+#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(1, 4)
+#define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(1, 5)
+#define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(1, 6)
+#define M4U_PORT_VENC_CUR_LUMA	MTK_M4U_ID(1, 7)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(1, 8)
+#define M4U_PORT_VENC_REF_LUMA	MTK_M4U_ID(1, 9)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(1, 10)
+/* larb2 */
+#define M4U_PORT_CAM_IMGO		MTK_M4U_ID(2, 0)
+#define M4U_PORT_CAM_RRZO		MTK_M4U_ID(2, 1)
+#define M4U_PORT_CAM_AAO		MTK_M4U_ID(2, 2)
+#define M4U_PORT_CAM_LCSO		MTK_M4U_ID(2, 3)
+#define M4U_PORT_CAM_ESFKO		MTK_M4U_ID(2, 4)
+#define M4U_PORT_CAM_IMGO_S		MTK_M4U_ID(2, 5)
+#define M4U_PORT_CAM_IMGO_S2		MTK_M4U_ID(2, 6)
+#define M4U_PORT_CAM_LSCI		MTK_M4U_ID(2, 7)
+#define M4U_PORT_CAM_LSCI_D		MTK_M4U_ID(2, 8)
+#define M4U_PORT_CAM_AFO		MTK_M4U_ID(2, 9)
+#define M4U_PORT_CAM_AFO_D		MTK_M4U_ID(2, 10)
+#define M4U_PORT_CAM_BPCI		MTK_M4U_ID(2, 11)
+#define M4U_PORT_CAM_BPCI_D		MTK_M4U_ID(2, 12)
+#define M4U_PORT_CAM_UFDI		MTK_M4U_ID(2, 13)
+#define M4U_PORT_CAM_IMGI		MTK_M4U_ID(2, 14)
+#define M4U_PORT_CAM_IMG2O		MTK_M4U_ID(2, 15)
+#define M4U_PORT_CAM_IMG3O		MTK_M4U_ID(2, 16)
+#define M4U_PORT_CAM_VIPI		MTK_M4U_ID(2, 17)
+#define M4U_PORT_CAM_VIP2I		MTK_M4U_ID(2, 18)
+#define M4U_PORT_CAM_VIP3I		MTK_M4U_ID(2, 19)
+#define M4U_PORT_CAM_ICEI		MTK_M4U_ID(2, 20)
+#define M4U_PORT_CAM_FD_RP		MTK_M4U_ID(2, 21)
+#define M4U_PORT_CAM_FD_WR		MTK_M4U_ID(2, 22)
+#define M4U_PORT_CAM_FD_RB		MTK_M4U_ID(2, 23)
+
+#define M4U_PORT_UNKNOWN		(M4U_PORT_CAM_FD_RB+1)
+
+#endif

include/dt-bindings/memory/mt6768-larb-port.h

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+#ifndef _DTS_IOMMU_PORT_MT6768_H_
+#define _DTS_IOMMU_PORT_MT6768_H_
+
+#define MTK_M4U_ID(larb, port)	(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)	(((id) >> 5) & 0xf)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)	((id) & 0x1f)
+
+#define MTK_IOMMU_LARB_NR	(5)
+
+/* larb0 -- 8*/
+#define M4U_PORT_DISP_OVL0	MTK_M4U_ID(0, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0	MTK_M4U_ID(0, 1)
+#define M4U_PORT_DISP_RDMA0	MTK_M4U_ID(0, 2)
+#define M4U_PORT_DISP_WDMA0	MTK_M4U_ID(0, 3)
+#define M4U_PORT_MDP_RDMA0	MTK_M4U_ID(0, 4)
+#define M4U_PORT_MDP_WDMA0	MTK_M4U_ID(0, 5)
+#define M4U_PORT_MDP_WROT0	MTK_M4U_ID(0, 6)
+#define M4U_PORT_DISP_FAKE0	MTK_M4U_ID(0, 7)
+/* larb1 -- 9*/
+#define M4U_PORT_HW_VDEC_MC_EXT	MTK_M4U_ID(1, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT	MTK_M4U_ID(1, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(1, 2)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(1, 3)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(1, 4)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(1, 5)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(1, 6)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(1, 7)
+#define M4U_PORT_HW_VDEC_TILE_EXT	MTK_M4U_ID(1, 8)
+/* larb2 -- 12*/
+#define M4U_PORT_CAM_IMGI	MTK_M4U_ID(2, 0)
+#define M4U_PORT_CAM_IMG2O	MTK_M4U_ID(2, 1)
+#define M4U_PORT_CAM_IMG3O	MTK_M4U_ID(2, 2)
+#define M4U_PORT_CAM_VIPI	MTK_M4U_ID(2, 3)
+#define M4U_PORT_CAM_LCEI	MTK_M4U_ID(2, 4)
+#define M4U_PORT_CAM_FD_RP	MTK_M4U_ID(2, 5)
+#define M4U_PORT_CAM_FD_WR	MTK_M4U_ID(2, 6)
+#define M4U_PORT_CAM_FD_RB	MTK_M4U_ID(2, 7)
+#define M4U_PORT_CAM_DPE_RDMA	MTK_M4U_ID(2, 8)
+#define M4U_PORT_CAM_DPE_WDMA	MTK_M4U_ID(2, 9)
+#define M4U_PORT_CAM_RSC_RDMA	MTK_M4U_ID(2, 10)
+#define M4U_PORT_CAM_RSC_WDMA	MTK_M4U_ID(2, 11)
+/*larb3 -- 21*/
+#define M4U_PORT_CAM_IMGO	MTK_M4U_ID(3, 0)
+#define M4U_PORT_CAM_RRZO	MTK_M4U_ID(3, 1)
+#define M4U_PORT_CAM_AAO	MTK_M4U_ID(3, 2)
+#define M4U_PORT_CAM_AFO	MTK_M4U_ID(3, 3)
+#define M4U_PORT_CAM_LSCI0	MTK_M4U_ID(3, 4)
+#define M4U_PORT_CAM_LSCI1	MTK_M4U_ID(3, 5)
+#define M4U_PORT_CAM_PDO	MTK_M4U_ID(3, 6)
+#define M4U_PORT_CAM_BPCI	MTK_M4U_ID(3, 7)
+#define M4U_PORT_CAM_LCSO	MTK_M4U_ID(3, 8)
+#define M4U_PORT_CAM_RSSO_A	MTK_M4U_ID(3, 9)
+#define M4U_PORT_CAM_RSSO_B	MTK_M4U_ID(3, 10)
+#define M4U_PORT_CAM_UFEO	MTK_M4U_ID(3, 11)
+#define M4U_PORT_CAM_SOC0	MTK_M4U_ID(3, 12)
+#define M4U_PORT_CAM_SOC1	MTK_M4U_ID(3, 13)
+#define M4U_PORT_CAM_SOC2	MTK_M4U_ID(3, 14)
+#define M4U_PORT_CAM_CCUI	MTK_M4U_ID(3, 15)
+#define M4U_PORT_CAM_CCUO	MTK_M4U_ID(3, 16)
+#define M4U_PORT_CAM_CACI	MTK_M4U_ID(3, 17)
+#define M4U_PORT_CAM_RAWI_A	MTK_M4U_ID(3, 18)
+#define M4U_PORT_CAM_RAWI_B	MTK_M4U_ID(3, 19)
+#define M4U_PORT_CAM_CCUG	MTK_M4U_ID(3, 20)
+/*larb4 -- 11*/
+#define M4U_PORT_VENC_RCPU	MTK_M4U_ID(4, 0)
+#define M4U_PORT_VENC_REC	MTK_M4U_ID(4, 1)
+#define M4U_PORT_VENC_BSDMA	MTK_M4U_ID(4, 2)
+#define M4U_PORT_VENC_SV_COMV	MTK_M4U_ID(4, 3)
+#define M4U_PORT_VENC_RD_COMV	MTK_M4U_ID(4, 4)
+#define M4U_PORT_JPGENC_RDMA	MTK_M4U_ID(4, 5)
+#define M4U_PORT_JPGENC_BSDMA	MTK_M4U_ID(4, 6)
+#define M4U_PORT_VENC_CUR_LUMA	MTK_M4U_ID(4, 7)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(4, 8)
+#define M4U_PORT_VENC_REF_LUMA	MTK_M4U_ID(4, 9)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(4, 10)
+
+#define M4U_PORT_UNKNOWN	(M4U_PORT_VENC_REF_CHROMA + 1)
+#define M4U_PORT_NR (61)
+
+/* for pusedo ccu device */
+#define CCU_PSEUDO_LARBID (MTK_IOMMU_LARB_NR + 1)
+#define MISC_PSEUDO_LARBID (MTK_IOMMU_LARB_NR + 2)
+#endif

include/dt-bindings/memory/mt6779-larb-port.h

@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Chao Hao <chao.hao@mediatek.com>
+ */
+
+#ifndef _DTS_IOMMU_PORT_MT6779_H_
+#define _DTS_IOMMU_PORT_MT6779_H_
+
+#define MTK_M4U_ID(larb, port)		 (((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_M4U_TO_LARB(id)		 (((id) >> 5) & 0xf)
+/* PortID within the local arbiter */
+#define MTK_M4U_TO_PORT(id)		 ((id) & 0x1f)
+
+#define MTK_IOMMU_LARB_NR		 11
+
+#define M4U_LARB0_ID			 0
+#define M4U_LARB1_ID			 1
+#define M4U_LARB2_ID			 2
+#define M4U_LARB3_ID			 3
+#define M4U_LARB4_ID			 4
+#define M4U_LARB5_ID			 5
+#define M4U_LARB6_ID			 6
+#define M4U_LARB7_ID			 7
+#define M4U_LARB8_ID			 8
+#define M4U_LARB9_ID			 9
+#define M4U_LARB10_ID			 10
+#define M4U_LARB11_ID			 11
+#define M4U_LARB12_ID			 12
+#define M4U_LARB13_ID			 13
+
+/* larb0 */
+#define M4U_PORT_DISP_POSTMASK0		 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_OVL0_HDR		 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_OVL1_HDR		 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OVL0		 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OVL1		 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_PVRIC0		 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_DISP_RDMA0		 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_DISP_WDMA0		 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_DISP_FAKE0		 MTK_M4U_ID(M4U_LARB0_ID, 8)
+
+/* larb1 */
+#define M4U_PORT_DISP_OVL0_2L_HDR	 MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_DISP_OVL1_2L_HDR	 MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_DISP_OVL0_2L		 MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_DISP_OVL1_2L		 MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_DISP_RDMA1		 MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_MDP_PVRIC0		 MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_MDP_PVRIC1		 MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_MDP_RDMA0		 MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_MDP_RDMA1		 MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_MDP_WROT0_R		 MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_MDP_WROT0_W		 MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_MDP_WROT1_R		 MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_MDP_WROT1_W		 MTK_M4U_ID(M4U_LARB1_ID, 12)
+#define M4U_PORT_DISP_FAKE1		 MTK_M4U_ID(M4U_LARB1_ID, 13)
+
+/* larb2-VDEC */
+#define M4U_PORT_HW_VDEC_MC_EXT          MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT         MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT          MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT     MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT     MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT      MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT        MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT         MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT        MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT      MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_HW_VDEC_UFO_ENC_EXT     MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11)
+
+/*larb3-VENC*/
+#define M4U_PORT_VENC_RCPU		 MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC		 MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV		 MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV		 MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_VENC_NBM_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE	 MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_JPGENC_Y_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_JPGENC_C_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_JPGENC_Q_TABLE		 MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_JPGENC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 10)
+#define M4U_PORT_JPGDEC_WDMA		 MTK_M4U_ID(M4U_LARB3_ID, 11)
+#define M4U_PORT_JPGDEC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 12)
+#define M4U_PORT_VENC_NBM_WDMA		 MTK_M4U_ID(M4U_LARB3_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE	 MTK_M4U_ID(M4U_LARB3_ID, 14)
+#define M4U_PORT_VENC_CUR_LUMA		 MTK_M4U_ID(M4U_LARB3_ID, 15)
+#define M4U_PORT_VENC_CUR_CHROMA	 MTK_M4U_ID(M4U_LARB3_ID, 16)
+#define M4U_PORT_VENC_REF_LUMA		 MTK_M4U_ID(M4U_LARB3_ID, 17)
+#define M4U_PORT_VENC_REF_CHROMA	 MTK_M4U_ID(M4U_LARB3_ID, 18)
+
+/*larb4-dummy*/
+
+/*larb5-IMG*/
+#define M4U_PORT_IMGI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_IMGBI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_DMGI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_DEPI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_LCEI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_SMTI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_SMTO_D2		 MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_SMTO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CRZO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_IMG3O_D1		 MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_VIPI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_WPE_RDMA1		 MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_WPE_RDMA0		 MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_WPE_WDMA		 MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_TIMGO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_MFB_RDMA0		 MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_MFB_RDMA1		 MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_MFB_RDMA2		 MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_MFB_RDMA3		 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_MFB_WDMA		 MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_RESERVE1		 MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_RESERVE2		 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_RESERVE3		 MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_RESERVE4		 MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_RESERVE5		 MTK_M4U_ID(M4U_LARB5_ID, 24)
+#define M4U_PORT_RESERVE6		 MTK_M4U_ID(M4U_LARB5_ID, 25)
+
+/*larb6-IMG*/
+#define M4U_PORT_IMG_IPUO		 MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_IMG_IPU3O		 MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_IMG_IPUI		 MTK_M4U_ID(M4U_LARB6_ID, 2)
+
+/*larb7-DVS*/
+#define M4U_PORT_DVS_RDMA		 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_DVS_WDMA		 MTK_M4U_ID(M4U_LARB7_ID, 1)
+#define M4U_PORT_DVP_RDMA		 MTK_M4U_ID(M4U_LARB7_ID, 2)
+#define M4U_PORT_DVP_WDMA		 MTK_M4U_ID(M4U_LARB7_ID, 3)
+
+/*larb8-IPESYS*/
+#define M4U_PORT_FDVT_RDA		 MTK_M4U_ID(M4U_LARB8_ID, 0)
+#define M4U_PORT_FDVT_RDB		 MTK_M4U_ID(M4U_LARB8_ID, 1)
+#define M4U_PORT_FDVT_WRA		 MTK_M4U_ID(M4U_LARB8_ID, 2)
+#define M4U_PORT_FDVT_WRB		 MTK_M4U_ID(M4U_LARB8_ID, 3)
+#define M4U_PORT_FE_RD0			 MTK_M4U_ID(M4U_LARB8_ID, 4)
+#define M4U_PORT_FE_RD1			 MTK_M4U_ID(M4U_LARB8_ID, 5)
+#define M4U_PORT_FE_WR0			 MTK_M4U_ID(M4U_LARB8_ID, 6)
+#define M4U_PORT_FE_WR1			 MTK_M4U_ID(M4U_LARB8_ID, 7)
+#define M4U_PORT_RSC_RDMA0		 MTK_M4U_ID(M4U_LARB8_ID, 8)
+#define M4U_PORT_RSC_WDMA		 MTK_M4U_ID(M4U_LARB8_ID, 9)
+
+/*larb9-CAM*/
+#define M4U_PORT_CAM_IMGO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 0)
+#define M4U_PORT_CAM_RRZO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 1)
+#define M4U_PORT_CAM_LSCI_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 2)
+#define M4U_PORT_CAM_BPCI_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 3)
+#define M4U_PORT_CAM_YUVO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 4)
+#define M4U_PORT_CAM_UFDI_R2_C		 MTK_M4U_ID(M4U_LARB9_ID, 5)
+#define M4U_PORT_CAM_RAWI_R2_C		 MTK_M4U_ID(M4U_LARB9_ID, 6)
+#define M4U_PORT_CAM_RAWI_R5_C		 MTK_M4U_ID(M4U_LARB9_ID, 7)
+#define M4U_PORT_CAM_CAMSV_1		 MTK_M4U_ID(M4U_LARB9_ID, 8)
+#define M4U_PORT_CAM_CAMSV_2		 MTK_M4U_ID(M4U_LARB9_ID, 9)
+#define M4U_PORT_CAM_CAMSV_3		 MTK_M4U_ID(M4U_LARB9_ID, 10)
+#define M4U_PORT_CAM_CAMSV_4		 MTK_M4U_ID(M4U_LARB9_ID, 11)
+#define M4U_PORT_CAM_CAMSV_5		 MTK_M4U_ID(M4U_LARB9_ID, 12)
+#define M4U_PORT_CAM_CAMSV_6		 MTK_M4U_ID(M4U_LARB9_ID, 13)
+#define M4U_PORT_CAM_AAO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 14)
+#define M4U_PORT_CAM_AFO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 15)
+#define M4U_PORT_CAM_FLKO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 16)
+#define M4U_PORT_CAM_LCESO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 17)
+#define M4U_PORT_CAM_CRZO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 18)
+#define M4U_PORT_CAM_LTMSO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 19)
+#define M4U_PORT_CAM_RSSO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 20)
+#define M4U_PORT_CAM_CCUI		 MTK_M4U_ID(M4U_LARB9_ID, 21)
+#define M4U_PORT_CAM_CCUO		 MTK_M4U_ID(M4U_LARB9_ID, 22)
+#define M4U_PORT_CAM_FAKE		 MTK_M4U_ID(M4U_LARB9_ID, 23)
+
+/*larb10-CAM_A*/
+#define M4U_PORT_CAM_IMGO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 0)
+#define M4U_PORT_CAM_RRZO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 1)
+#define M4U_PORT_CAM_LSCI_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 2)
+#define M4U_PORT_CAM_BPCI_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 3)
+#define M4U_PORT_CAM_YUVO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 4)
+#define M4U_PORT_CAM_UFDI_R2_A		 MTK_M4U_ID(M4U_LARB10_ID, 5)
+#define M4U_PORT_CAM_RAWI_R2_A		 MTK_M4U_ID(M4U_LARB10_ID, 6)
+#define M4U_PORT_CAM_RAWI_R5_A		 MTK_M4U_ID(M4U_LARB10_ID, 7)
+#define M4U_PORT_CAM_IMGO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 8)
+#define M4U_PORT_CAM_RRZO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 9)
+#define M4U_PORT_CAM_LSCI_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 10)
+#define M4U_PORT_CAM_BPCI_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 11)
+#define M4U_PORT_CAM_YUVO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 12)
+#define M4U_PORT_CAM_UFDI_R2_B		 MTK_M4U_ID(M4U_LARB10_ID, 13)
+#define M4U_PORT_CAM_RAWI_R2_B		 MTK_M4U_ID(M4U_LARB10_ID, 14)
+#define M4U_PORT_CAM_RAWI_R5_B		 MTK_M4U_ID(M4U_LARB10_ID, 15)
+#define M4U_PORT_CAM_CAMSV_0		 MTK_M4U_ID(M4U_LARB10_ID, 16)
+#define M4U_PORT_CAM_AAO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 17)
+#define M4U_PORT_CAM_AFO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 18)
+#define M4U_PORT_CAM_FLKO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 19)
+#define M4U_PORT_CAM_LCESO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 20)
+#define M4U_PORT_CAM_CRZO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 21)
+#define M4U_PORT_CAM_AAO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 22)
+#define M4U_PORT_CAM_AFO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 23)
+#define M4U_PORT_CAM_FLKO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 24)
+#define M4U_PORT_CAM_LCESO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 25)
+#define M4U_PORT_CAM_CRZO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 26)
+#define M4U_PORT_CAM_LTMSO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 27)
+#define M4U_PORT_CAM_RSSO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 28)
+#define M4U_PORT_CAM_LTMSO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 29)
+#define M4U_PORT_CAM_RSSO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 30)
+
+/*larb11-CAM-IPU*/
+#define M4U_PORT_CAM_IPUO		 MTK_M4U_ID(M4U_LARB11_ID, 0)
+#define M4U_PORT_CAM_IPU2O		 MTK_M4U_ID(M4U_LARB11_ID, 1)
+#define M4U_PORT_CAM_IPU3O		 MTK_M4U_ID(M4U_LARB11_ID, 2)
+#define M4U_PORT_CAM_IPUI		 MTK_M4U_ID(M4U_LARB11_ID, 3)
+#define M4U_PORT_CAM_IPU2I		 MTK_M4U_ID(M4U_LARB11_ID, 4)
+
+#define M4U_PORT_CCU0			 MTK_M4U_ID(M4U_LARB12_ID, 0)
+#define M4U_PORT_CCU1			 MTK_M4U_ID(M4U_LARB12_ID, 1)
+
+#define M4U_PORT_VPU			 MTK_M4U_ID(M4U_LARB13_ID, 0)
+#define M4U_PORT_MDLA			 MTK_M4U_ID(M4U_LARB13_ID, 1)
+
+#define M4U_PORT_UNKNOWN		 (M4U_PORT_MDLA + 1)
+
+#endif

include/dt-bindings/memory/mt6781-larb-port.h

@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+#ifndef _DTS_IOMMU_PORT_MT6781_H_
+#define _DTS_IOMMU_PORT_MT6781_H_
+
+#define MTK_M4U_ID(larb, port)			(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)			(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)			((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID			(21)
+#define CCU0_PSEUDO_LARBID			(22)
+#define CCU1_PSEUDO_LARBID			(23)
+/* 3, 5, 6, 8 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR			(24)
+
+/*********************************************************/
+/* larb0 -- 4 */
+#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 3)
+/* larb1 -- 5 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_DISP_WDMA0			MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 4)
+/* larb2 -- 5 */
+#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)
+/* larb3 -- null */
+/* larb4 -- 14 */
+#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_UFO_ENC_EXT		MTK_M4U_ID(4, 10)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
+#define M4U_PORT_L4_MINI_MDP_R0_EXT		MTK_M4U_ID(4, 12)
+#define M4U_PORT_L4_MINI_MDP_W0_EXT		MTK_M4U_ID(4, 13)
+/* larb5 -- null */
+/* larb6 -- null */
+/* larb7 -- 13 */
+#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_C_RDMA		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_Q_TABLE		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
+/* larb8 -- null */
+/* larb9 -- 29 */
+/* port0~port14 is used, port15~port28 is not used */
+#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1		MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0		MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA		MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0		MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1		MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2		MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3		MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4		MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5		MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0		MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1		MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6		MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7		MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8		MTK_M4U_ID(9, 28)
+/* larb10 -- null */
+/* larb11 -- 29 */
+/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */
+#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6		MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7		MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8		MTK_M4U_ID(11, 28)
+/* larb12 -- null */
+/* larb13 -- 12 */
+#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_RESERVE1		MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_RESERVE2		MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_RESERVE3		MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)
+/* larb14 -- 6 */
+#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_RESERVE4		MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)
+/* larb15 -- null */
+/* larb16 -- 17 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)
+/* larb17 -- 17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)
+/* larb18 -- 17 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)
+/* larb19 -- 4 */
+#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)
+/* larb20 -- 6 */
+#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)
+/* fake larb -- 5 */
+#define M4U_PORT_L21_APU_FAKE_CODE		MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA		MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM		MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU0		MTK_M4U_ID(CCU0_PSEUDO_LARBID, 0)
+#define M4U_PORT_L23_CCU1		MTK_M4U_ID(CCU1_PSEUDO_LARBID, 0)
+
+#define M4U_PORT_GPU				MTK_M4U_ID(31, 31)
+#define M4U_PORT_UNKNOWN			(M4U_PORT_L23_CCU1 + 1)
+#define M4U_PORT_NR				(183)
+
+/*********************************************************/
+/* for pusedo fake device */
+#define MISC_PSEUDO_LARBID			MTK_IOMMU_LARB_NR
+#define APU_PSEUDO_LARBID_CODE			(MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA			(MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM			(MTK_IOMMU_LARB_NR + 3)
+
+#define M4U_PORT_APU				M4U_PORT_L21_APU_FAKE_DATA
+
+/* for debug debug */
+#define M4U_PORT_APU_CODE			M4U_PORT_L21_APU_FAKE_CODE
+#define M4U_PORT_CCU				M4U_PORT_L23_CCU1
+#define M4U_PORT_OVL_DEBUG			M4U_PORT_L0_DISP_FAKE0/*no use*/
+#define M4U_PORT_MDP_DEBUG			M4U_PORT_L0_DISP_POSTMASK0
+#define M4U_PORT_BOUNDARY0_DEBUG		M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG		M4U_PORT_L4_VDEC_MC_EXT
+#define M4U_PORT_BOUNDARY2_DEBUG		M4U_PORT_L11_IMG_IMGI_D1
+#define M4U_PORT_BOUNDARY3_DEBUG		M4U_PORT_L21_APU_FAKE_DATA
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) \
+	&& (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS			34
+#define MTK_PHYS_ADDR_BITS			35
+#else
+#define MTK_IOVA_ADDR_BITS			32
+#define MTK_PHYS_ADDR_BITS			34
+#endif
+
+/* the total number of iommu(include mm and vpu) */
+#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_APUSYS_SUPPORT)
+#define MTK_IOMMU_M4U_COUNT			1
+#else
+#define MTK_IOMMU_M4U_COUNT			2
+#endif
+
+/* iommu hw register define */
+#define MTK_IOMMU_DEBUG_REG_NR			(6)
+#define MTK_IOMMU_WAY_NR			(4)
+#define MTK_IOMMU_RS_COUNT			(16)
+#define MTK_IOMMU_MMU_COUNT			(2)
+#define MTK_IOMMU_TAG_COUNT			(64)
+#define MTK_IOMMU_BANK_COUNT			(5)
+#define MTK_IOMMU_MAU_COUNT			(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)		MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)		MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE			(8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+/* the number of apu_iommu */
+#define APU_IOMMU_INDEX				(1)
+
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+
+#endif

include/dt-bindings/memory/mt6785-larb-port.h

@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+#ifndef _DTS_IOMMU_PORT_H_
+#define _DTS_IOMMU_PORT_H_
+
+#define MTK_M4U_ID(larb, port)            (((larb) << 5) | port)
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)	(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)	((id) & 0x1f)
+
+#define M4U_LARB_CCU                      (7) // 2 ports
+#define M4U_LARB_APU                      (8) // 2 ports
+#define MTK_IOMMU_LARB_NR	(9)
+
+/*larb0 -MMSYS-9*/
+#define M4U_PORT_DISP_POSTMASK0	            MTK_M4U_ID(0, 0)
+#define M4U_PORT_DISP_OVL0_HDR	            MTK_M4U_ID(0, 1)
+#define M4U_PORT_DISP_OVL1_HDR	            MTK_M4U_ID(0, 2)
+#define M4U_PORT_DISP_OVL0	                MTK_M4U_ID(0, 3)
+#define M4U_PORT_DISP_OVL1	                MTK_M4U_ID(0, 4)
+#define M4U_PORT_DISP_PVRIC0	            MTK_M4U_ID(0, 5)
+#define M4U_PORT_DISP_RDMA0	                MTK_M4U_ID(0, 6)
+#define M4U_PORT_DISP_WDMA0	                MTK_M4U_ID(0, 7)
+#define M4U_PORT_DISP_FAKE0	                MTK_M4U_ID(0, 8)
+/*larb1-MMSYS-14*/
+#define M4U_PORT_DISP_OVL0_2L_HDR	        MTK_M4U_ID(1, 0)
+#define M4U_PORT_DISP_OVL1_2L_HDR	        MTK_M4U_ID(1, 1)
+#define M4U_PORT_DISP_OVL0_2L	            MTK_M4U_ID(1, 2)
+#define M4U_PORT_DISP_OVL1_2L	            MTK_M4U_ID(1, 3)
+#define M4U_PORT_DISP_RDMA1	                MTK_M4U_ID(1, 4)
+#define M4U_PORT_MDP_PVRIC0                 MTK_M4U_ID(1, 5)
+#define M4U_PORT_MDP_PVRIC1	                MTK_M4U_ID(1, 6)
+#define M4U_PORT_MDP_RDMA0                  MTK_M4U_ID(1, 7)
+#define M4U_PORT_MDP_RDMA1                  MTK_M4U_ID(1, 8)
+#define M4U_PORT_MDP_WROT0_R                MTK_M4U_ID(1, 9)
+#define M4U_PORT_MDP_WROT0_W                MTK_M4U_ID(1, 10)
+#define M4U_PORT_MDP_WROT1_R                MTK_M4U_ID(1, 11)
+#define M4U_PORT_MDP_WROT1_W                MTK_M4U_ID(1, 12)
+#define M4U_PORT_DISP_FAKE1                 MTK_M4U_ID(1, 13)
+/*larb2-VDEC-12*/
+#define M4U_PORT_HW_VDEC_MC_EXT             MTK_M4U_ID(2, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT	        MTK_M4U_ID(2, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT             MTK_M4U_ID(2, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	    MTK_M4U_ID(2, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	    MTK_M4U_ID(2, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT         MTK_M4U_ID(2, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT           MTK_M4U_ID(2, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT	        MTK_M4U_ID(2, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	        MTK_M4U_ID(2, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	        MTK_M4U_ID(2, 9)
+#define M4U_PORT_HW_VDEC_UFO_ENC_EXT	    MTK_M4U_ID(2, 10)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(2, 11)
+/*larb3-VENC-19*/
+#define M4U_PORT_VENC_RCPU                  MTK_M4U_ID(3, 0)
+#define M4U_PORT_VENC_REC                   MTK_M4U_ID(3, 1)
+#define M4U_PORT_VENC_BSDMA                 MTK_M4U_ID(3, 2)
+#define M4U_PORT_VENC_SV_COMV               MTK_M4U_ID(3, 3)
+#define M4U_PORT_VENC_RD_COMV               MTK_M4U_ID(3, 4)
+#define M4U_PORT_VENC_NBM_RDMA              MTK_M4U_ID(3, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE         MTK_M4U_ID(3, 6)
+#define M4U_PORT_JPGENC_Y_RDMA              MTK_M4U_ID(3, 7)
+#define M4U_PORT_JPGENC_C_RDMA              MTK_M4U_ID(3, 8)
+#define M4U_PORT_JPGENC_Q_TABLE             MTK_M4U_ID(3, 9)
+#define M4U_PORT_JPGENC_BSDMA               MTK_M4U_ID(3, 10)
+#define M4U_PORT_JPGDEC_WDMA                MTK_M4U_ID(3, 11)
+#define M4U_PORT_JPGDEC_BSDMA               MTK_M4U_ID(3, 12)
+#define M4U_PORT_VENC_NBM_WDMA              MTK_M4U_ID(3, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE         MTK_M4U_ID(3, 14)
+#define M4U_PORT_VENC_CUR_LUMA              MTK_M4U_ID(3, 15)
+#define M4U_PORT_VENC_CUR_CHROMA            MTK_M4U_ID(3, 16)
+#define M4U_PORT_VENC_REF_LUMA              MTK_M4U_ID(3, 17)
+#define M4U_PORT_VENC_REF_CHROMA            MTK_M4U_ID(3, 18)
+/* larb4-IMG-3
+ * HW disconnected
+#define M4U_PORT_IPUO_LARB4		    MTK_M4U_ID(4, 0)
+#define M4U_PORT_IPU3O_LARB4	            MTK_M4U_ID(4, 1)
+#define M4U_PORT_IPUI_LARB4		    MTK_M4U_ID(4, 2)
+ */
+/*larb5-IMG-26*/
+#define M4U_PORT_IMGI                   MTK_M4U_ID(5, 0)
+#define M4U_PORT_IMG2O                  MTK_M4U_ID(5, 1)
+#define M4U_PORT_IMG3O                  MTK_M4U_ID(5, 2)
+#define M4U_PORT_VIPI                   MTK_M4U_ID(5, 3)
+#define M4U_PORT_LCEI                   MTK_M4U_ID(5, 4)
+#define M4U_PORT_SMXI                   MTK_M4U_ID(5, 5)
+#define M4U_PORT_SMXO                   MTK_M4U_ID(5, 6)
+#define M4U_PORT_WPE0_RDMA1             MTK_M4U_ID(5, 7)
+#define M4U_PORT_WPE0_RDMA0             MTK_M4U_ID(5, 8)
+#define M4U_PORT_WPE0_WDMA              MTK_M4U_ID(5, 9)
+#define M4U_PORT_FDVT_RDB                   MTK_M4U_ID(5, 10)
+#define M4U_PORT_FDVT_WRA                   MTK_M4U_ID(5, 11)
+#define M4U_PORT_FDVT_RDA                   MTK_M4U_ID(5, 12)
+#define M4U_PORT_WPE1_RDMA0             MTK_M4U_ID(5, 13)
+#define M4U_PORT_WPE1_RDMA1             MTK_M4U_ID(5, 14)
+#define M4U_PORT_WPE1_WDMA              MTK_M4U_ID(5, 15)
+#define M4U_PORT_DPE_RDMA               MTK_M4U_ID(5, 16)
+#define M4U_PORT_DPE_WDMA               MTK_M4U_ID(5, 17)
+#define M4U_PORT_MFB_RDMA0              MTK_M4U_ID(5, 18)
+#define M4U_PORT_MFB_RDMA1              MTK_M4U_ID(5, 19)
+#define M4U_PORT_MFB_WDMA               MTK_M4U_ID(5, 20)
+#define M4U_PORT_RSC_RDMA0              MTK_M4U_ID(5, 21)
+#define M4U_PORT_RSC_WDMA               MTK_M4U_ID(5, 22)
+#define M4U_PORT_OWE_RDMA               MTK_M4U_ID(5, 23)
+#define M4U_PORT_OWE_WDMA               MTK_M4U_ID(5, 24)
+#define M4U_PORT_FDVT_WRB               MTK_M4U_ID(5, 25)
+/*larb6-IMG-31*/
+#define M4U_PORT_IMGO                   MTK_M4U_ID(6, 0)
+#define M4U_PORT_RRZO                   MTK_M4U_ID(6, 1)
+#define M4U_PORT_AAO                        MTK_M4U_ID(6, 2)
+#define M4U_PORT_AFO                    MTK_M4U_ID(6, 3)
+#define M4U_PORT_LSCI_0                     MTK_M4U_ID(6, 4)
+#define M4U_PORT_LSCI_1                     MTK_M4U_ID(6, 5)
+#define M4U_PORT_PDO                    MTK_M4U_ID(6, 6)
+#define M4U_PORT_BPCI                   MTK_M4U_ID(6, 7)
+#define M4U_PORT_LSCO                       MTK_M4U_ID(6, 8)
+#define M4U_PORT_RSSO_A                      MTK_M4U_ID(6, 9)
+#define M4U_PORT_UFEO                        MTK_M4U_ID(6, 10)
+#define M4U_PORT_SOCO                    MTK_M4U_ID(6, 11)
+#define M4U_PORT_SOC1                   MTK_M4U_ID(6, 12)
+#define M4U_PORT_SOC2                   MTK_M4U_ID(6, 13)
+#define M4U_PORT_CCUI                   MTK_M4U_ID(6, 14)
+#define M4U_PORT_CCUO                   MTK_M4U_ID(6, 15)
+#define M4U_PORT_RAWI_A                   MTK_M4U_ID(6, 16)
+#define M4U_PORT_CCUG                       MTK_M4U_ID(6, 17)
+#define M4U_PORT_PSO                     MTK_M4U_ID(6, 18)
+#define M4U_PORT_AFO_1                    MTK_M4U_ID(6, 19)
+#define M4U_PORT_LSCI_2                   MTK_M4U_ID(6, 20)
+#define M4U_PORT_PDI                        MTK_M4U_ID(6, 21)
+#define M4U_PORT_FLKO                       MTK_M4U_ID(6, 22)
+#define M4U_PORT_LMVO                       MTK_M4U_ID(6, 23)
+#define M4U_PORT_UFGO                       MTK_M4U_ID(6, 24)
+#define M4U_PORT_SPARE                      MTK_M4U_ID(6, 25)
+#define M4U_PORT_SPARE_2                    MTK_M4U_ID(6, 26)
+#define M4U_PORT_SPARE_3                    MTK_M4U_ID(6, 27)
+#define M4U_PORT_SPARE_4                    MTK_M4U_ID(6, 28)
+#define M4U_PORT_SPARE_5                    MTK_M4U_ID(6, 29)
+#define FAKE_ENGINE                         MTK_M4U_ID(6, 30)
+
+/*larb7-CAM-5/
+ * HW disconnected
+#define M4U_PORT_IPUO                       MTK_M4U_ID(7, 0)
+#define M4U_PORT_IPU2O                      MTK_M4U_ID(7, 1)
+#define M4U_PORT_IPU3O                      MTK_M4U_ID(7, 2)
+#define M4U_PORT_IPUI                       MTK_M4U_ID(7, 3)
+#define M4U_PORT_IPU2I                      MTK_M4U_ID(7, 4)
+*/
+
+/* smi common - 2 */
+#define M4U_PORT_CCU0                       MTK_M4U_ID(M4U_LARB_CCU, 0)
+#define M4U_PORT_CCU1                       MTK_M4U_ID(M4U_LARB_CCU, 1)
+
+#define M4U_PORT_VPU                        MTK_M4U_ID(M4U_LARB_APU, 0)
+#define M4U_PORT_VPU_DATA                   MTK_M4U_ID(M4U_LARB_APU, 1)
+
+#define M4U_PORT_UNKNOWN	                (M4U_PORT_VPU_DATA + 1)
+
+#define M4U_PORT_APU          M4U_PORT_VPU_DATA
+#define M4U_PORT_CCU          M4U_PORT_CCU0
+#define M4U_PORT_OVL_DEBUG    M4U_PORT_DISP_FAKE0
+#define M4U_PORT_MDP_DEBUG    M4U_PORT_DISP_FAKE1
+
+#ifndef M4U_PORT_NR
+#define M4U_PORT_NR (115)   // 9 + 14 + 12 +19 + 26 + 31 + 4
+#endif
+
+//sw design
+#define MISC_PSEUDO_LARBID_DISP                  (MTK_IOMMU_LARB_NR)
+#define APU_PSEUDO_LARBID_DATA                  (MTK_IOMMU_LARB_NR + 1)
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) && \
+	(CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS 34
+#define MTK_PHYS_ADDR_BITS 35
+#else
+#define MTK_IOVA_ADDR_BITS 32
+#define MTK_PHYS_ADDR_BITS 34
+#endif
+
+#ifdef CONFIG_FPGA_EARLY_PORTING
+#define MTK_IOMMU_M4U_COUNT (1)
+#else
+#define MTK_IOMMU_M4U_COUNT (2)
+#endif
+#define MTK_IOMMU_DEBUG_REG_NR   (6)
+#define MTK_IOMMU_WAY_NR   (4)
+#define MTK_IOMMU_RS_COUNT	(16)
+#define MTK_IOMMU_MMU_COUNT	(2)
+#define MTK_IOMMU_TAG_COUNT	(64)
+#define MTK_IOMMU_BANK_COUNT	(5)
+#define MTK_IOMMU_MAU_COUNT	(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)	MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)	MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE     (8)
+#define MTK_IOMMU_LARB_CODEC_MIN (4)
+#define MTK_IOMMU_LARB_CODEC_MAX (11)
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+#define APU_IOMMU_INDEX (1)
+
+#endif

include/dt-bindings/memory/mt6833-larb-port.h

@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+#ifndef _DTS_IOMMU_PORT_MT6833_H_
+#define _DTS_IOMMU_PORT_MT6833_H_
+
+#define MTK_M4U_ID(larb, port)			(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)			(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)			((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID			(21)
+#define CCU0_PSEUDO_LARBID			(22)
+#define CCU1_PSEUDO_LARBID			(23)
+/* 3, 5, 6, 8 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR			(24)
+
+/*********************************************************/
+/* larb0 -- 4 */
+#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 3)
+/* larb1 -- 5 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_DISP_WDMA0			MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 4)
+/* larb2 -- 5 */
+#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)
+/* larb3 -- null */
+/* larb4 -- 12 */
+#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_UFO_ENC_EXT		MTK_M4U_ID(4, 10)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
+/* larb5 -- null */
+/* larb6 -- null */
+/* larb7 -- 13 */
+#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_C_RDMA		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_Q_TABLE		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
+/* larb8 -- null */
+/* larb9 -- 29 */
+/* port0~port14 is used, port15~port28 is not used */
+#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1		MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0		MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA		MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0		MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1		MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2		MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3		MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4		MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5		MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0		MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1		MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6		MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7		MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8		MTK_M4U_ID(9, 28)
+/* larb10 -- null */
+/* larb11 -- 29 */
+/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */
+#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6		MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7		MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8		MTK_M4U_ID(11, 28)
+/* larb12 -- null */
+/* larb13 -- 12 */
+#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_RESERVE1		MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_RESERVE2		MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_RESERVE3		MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)
+/* larb14 -- 6 */
+#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_RESERVE4		MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)
+/* larb15 -- null */
+/* larb16 -- 17 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)
+/* larb17 -- 17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)
+/* larb18 -- 17 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)
+/* larb19 -- 4 */
+#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)
+/* larb20 -- 6 */
+#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)
+/* fake larb -- 5 */
+#define M4U_PORT_L21_APU_FAKE_CODE		MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA		MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM		MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU0		MTK_M4U_ID(CCU0_PSEUDO_LARBID, 0)
+#define M4U_PORT_L23_CCU1		MTK_M4U_ID(CCU1_PSEUDO_LARBID, 0)
+
+#define M4U_PORT_GPU				MTK_M4U_ID(31, 31)
+#define M4U_PORT_UNKNOWN			(M4U_PORT_L23_CCU1 + 1)
+#define M4U_PORT_NR				(181)
+
+/*********************************************************/
+/* for pusedo fake device */
+#define MISC_PSEUDO_LARBID			MTK_IOMMU_LARB_NR
+#define APU_PSEUDO_LARBID_CODE			(MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA			(MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM			(MTK_IOMMU_LARB_NR + 3)
+
+#define M4U_PORT_APU				M4U_PORT_L21_APU_FAKE_DATA
+
+/* for debug debug */
+#define M4U_PORT_APU_CODE			M4U_PORT_L21_APU_FAKE_CODE
+#define M4U_PORT_CCU				M4U_PORT_L23_CCU1
+#define M4U_PORT_OVL_DEBUG			M4U_PORT_L0_DISP_FAKE0/*no use*/
+#define M4U_PORT_MDP_DEBUG			M4U_PORT_L0_DISP_POSTMASK0
+#define M4U_PORT_BOUNDARY0_DEBUG		M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG		M4U_PORT_L4_VDEC_MC_EXT
+#define M4U_PORT_BOUNDARY2_DEBUG		M4U_PORT_L11_IMG_IMGI_D1
+#define M4U_PORT_BOUNDARY3_DEBUG		M4U_PORT_L21_APU_FAKE_DATA
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) \
+	&& (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS			34
+#define MTK_PHYS_ADDR_BITS			35
+#else
+#define MTK_IOVA_ADDR_BITS			32
+#define MTK_PHYS_ADDR_BITS			34
+#endif
+
+/* the total number of iommu(include mm and vpu) */
+#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_APUSYS_SUPPORT)
+#define MTK_IOMMU_M4U_COUNT			1
+#else
+#define MTK_IOMMU_M4U_COUNT			2
+#endif
+
+/* iommu hw register define */
+#define MTK_IOMMU_DEBUG_REG_NR			(6)
+#define MTK_IOMMU_WAY_NR			(4)
+#define MTK_IOMMU_RS_COUNT			(16)
+#define MTK_IOMMU_MMU_COUNT			(2)
+#define MTK_IOMMU_TAG_COUNT			(64)
+#define MTK_IOMMU_BANK_COUNT			(5)
+#define MTK_IOMMU_MAU_COUNT			(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)		MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)		MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE			(8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+/* the number of apu_iommu */
+#define APU_IOMMU_INDEX				(1)
+
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+
+#endif

include/dt-bindings/memory/mt6853-larb-port.h

@@ -0,0 +1,298 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2016 MediaTek Inc.
+ */
+
+#ifndef _DTS_IOMMU_PORT_MT6853_H_
+#define _DTS_IOMMU_PORT_MT6853_H_
+
+#if defined CONFIG_MACH_MT6877
+#include "mt6877-larb-port.h"
+#else
+
+#define MTK_M4U_ID(larb, port)			(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)			(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)			((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID			(21)
+#define CCU0_PSEUDO_LARBID			(22)
+#define CCU1_PSEUDO_LARBID			(23)
+/* 3, 5, 6, 8 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR			(24)
+
+/*********************************************************/
+/* larb0 -- 4 */
+#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 3)
+/* larb1 -- 5 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_DISP_WDMA0			MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 4)
+/* larb2 -- 5 */
+#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)
+/* larb3 -- null */
+/* larb4 -- 12 */
+#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_UFO_ENC_EXT		MTK_M4U_ID(4, 10)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
+/* larb5 -- null */
+/* larb6 -- null */
+/* larb7 -- 13 */
+#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_C_RDMA		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_Q_TABLE		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
+/* larb8 -- null */
+/* larb9 -- 29 */
+/* port0~port14 is used, port15~port28 is not used */
+#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1		MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0		MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA		MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0		MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1		MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2		MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3		MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4		MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5		MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0		MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1		MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6		MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7		MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8		MTK_M4U_ID(9, 28)
+/* larb10 -- null */
+/* larb11 -- 29 */
+/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */
+#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6		MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7		MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8		MTK_M4U_ID(11, 28)
+/* larb12 -- null */
+/* larb13 -- 12 */
+#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_RESERVE1		MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_RESERVE2		MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_RESERVE3		MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)
+/* larb14 -- 6 */
+#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_RESERVE4		MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)
+/* larb15 -- null */
+/* larb16 -- 17 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)
+/* larb17 -- 17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)
+/* larb18 -- 17 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)
+/* larb19 -- 4 */
+#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)
+/* larb20 -- 6 */
+#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)
+/* fake larb -- 5 */
+#define M4U_PORT_L21_APU_FAKE_CODE		MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA		MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM		MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU0		MTK_M4U_ID(CCU0_PSEUDO_LARBID, 0)
+#define M4U_PORT_L23_CCU1		MTK_M4U_ID(CCU1_PSEUDO_LARBID, 0)
+
+#define M4U_PORT_GPU				MTK_M4U_ID(31, 31)
+#define M4U_PORT_UNKNOWN			(M4U_PORT_L23_CCU1 + 1)
+#define M4U_PORT_NR				(181)
+
+/*********************************************************/
+/* for pusedo fake device */
+#define MISC_PSEUDO_LARBID			MTK_IOMMU_LARB_NR
+#define APU_PSEUDO_LARBID_CODE			(MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA			(MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM			(MTK_IOMMU_LARB_NR + 3)
+
+#define M4U_PORT_APU				M4U_PORT_L21_APU_FAKE_DATA
+
+/* for debug debug */
+#define M4U_PORT_APU_CODE			M4U_PORT_L21_APU_FAKE_CODE
+#define M4U_PORT_CCU				M4U_PORT_L23_CCU1
+#define M4U_PORT_OVL_DEBUG			M4U_PORT_L0_DISP_FAKE0/*no use*/
+#define M4U_PORT_MDP_DEBUG			M4U_PORT_L0_DISP_POSTMASK0
+#define M4U_PORT_BOUNDARY0_DEBUG		M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG		M4U_PORT_L4_VDEC_MC_EXT
+#define M4U_PORT_BOUNDARY2_DEBUG		M4U_PORT_L11_IMG_IMGI_D1
+#define M4U_PORT_BOUNDARY3_DEBUG		M4U_PORT_L21_APU_FAKE_DATA
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) \
+	&& (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS			34
+#define MTK_PHYS_ADDR_BITS			35
+#else
+#define MTK_IOVA_ADDR_BITS			32
+#define MTK_PHYS_ADDR_BITS			34
+#endif
+
+/* the total number of iommu(include mm and vpu) */
+#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_APUSYS_SUPPORT)
+#define MTK_IOMMU_M4U_COUNT			1
+#else
+#define MTK_IOMMU_M4U_COUNT			2
+#endif
+
+/* iommu hw register define */
+#define MTK_IOMMU_DEBUG_REG_NR			(6)
+#define MTK_IOMMU_WAY_NR			(4)
+#define MTK_IOMMU_RS_COUNT			(16)
+#define MTK_IOMMU_MMU_COUNT			(2)
+#define MTK_IOMMU_TAG_COUNT			(64)
+#define MTK_IOMMU_BANK_COUNT			(5)
+#define MTK_IOMMU_MAU_COUNT			(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)		MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)		MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE			(8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+
+/* no use delete it for mt6853? */
+#define MTK_IOMMU_LARB_CODEC_MIN		(4)
+#define MTK_IOMMU_LARB_CODEC_MAX		(11)
+
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+/* the number of apu_iommu */
+#define APU_IOMMU_INDEX				(1)
+
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+#endif
+
+#endif

include/dt-bindings/memory/mt6873-larb-port.h

@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef _DTS_IOMMU_PORT_MT6873_H_
+#define _DTS_IOMMU_PORT_MT6873_H_
+
+#define MTK_M4U_ID(larb, port)			(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)			(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)			((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID			(21)
+#define CCU0_PSEUDO_LARBID			(22)
+#define CCU1_PSEUDO_LARBID			(23)
+/* 6, 10, 12, 15 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR			(24)
+
+/*********************************************************/
+/* larb0 -- 6 */
+#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_RDMA0			MTK_M4U_ID(0, 3)
+#define M4U_PORT_L0_DISP_WDMA0			MTK_M4U_ID(0, 4)
+#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 5)
+/* larb1 -- 8 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA2_HDR		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_OVL_2L_RDMA2		MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_MDP_RDMA4		MTK_M4U_ID(1, 4)
+#define M4U_PORT_L1_DISP_RDMA4			MTK_M4U_ID(1, 5)
+#define M4U_PORT_L1_DISP_UFBC_WDMA0		MTK_M4U_ID(1, 6)
+#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 7)
+/* larb2 -- 5 */
+#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)
+/* larb3 -- null */
+/* larb4 -- 11 */
+#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 10)
+/* larb5 -- 8 */
+#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT		MTK_M4U_ID(5, 0)
+#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT		MTK_M4U_ID(5, 1)
+#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT	MTK_M4U_ID(5, 2)
+#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT	MTK_M4U_ID(5, 3)
+#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT		MTK_M4U_ID(5, 4)
+#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT		MTK_M4U_ID(5, 5)
+#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT	MTK_M4U_ID(5, 6)
+#define M4U_PORT_L5_VDEC_UFO_ENC_EXT		MTK_M4U_ID(5, 7)
+/* larb6 -- null */
+/* larb7 -- 15 */
+#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_Q_RDMA		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_C_TABLE		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 12)
+#define M4U_PORT_L7_VENC_SUB_R_LUMA		MTK_M4U_ID(7, 13)
+#define M4U_PORT_L7_VENC_SUB_W_LUMA		MTK_M4U_ID(7, 14)
+/* larb8 -- 27 */
+#define M4U_PORT_L8_VENC_RCPU			MTK_M4U_ID(8, 0)
+#define M4U_PORT_L8_VENC_RECP			MTK_M4U_ID(8, 1)
+#define M4U_PORT_L8_VENC_BSDMA			MTK_M4U_ID(8, 2)
+#define M4U_PORT_L8_VENC_SUB_W_LUMA		MTK_M4U_ID(8, 3)
+#define M4U_PORT_L8_VENC_SV_COMV		MTK_M4U_ID(8, 4)
+#define M4U_PORT_L8_VENC_RD_COMV		MTK_M4U_ID(8, 5)
+#define M4U_PORT_L8_VENC_NBM_RDMA		MTK_M4U_ID(8, 6)
+#define M4U_PORT_L8_VENC_NBM_RDMA_LITE		MTK_M4U_ID(8, 7)
+#define M4U_PORT_L8_VENC_FCS_NBM_RDMA		MTK_M4U_ID(8, 8)
+#define M4U_PORT_L8_JPGENC_Y_RDMA		MTK_M4U_ID(8, 9)
+#define M4U_PORT_L8_JPGENC_C_RDMA		MTK_M4U_ID(8, 10)
+#define M4U_PORT_L8_JPGENC_Q_TABLE		MTK_M4U_ID(8, 11)
+#define M4U_PORT_L8_JPGENC_BSDMA		MTK_M4U_ID(8, 12)
+#define M4U_PORT_L8_JPGENC_HUFF_OFFSET0		MTK_M4U_ID(8, 13)
+#define M4U_PORT_L8_JPGENC_WDMA0		MTK_M4U_ID(8, 14)
+#define M4U_PORT_L8_JPGENC_BSDMA0		MTK_M4U_ID(8, 15)
+#define M4U_PORT_L8_JPGENC_HUFF_OFFSET1		MTK_M4U_ID(8, 16)
+#define M4U_PORT_L8_JPGENC_WDMA1		MTK_M4U_ID(8, 17)
+#define M4U_PORT_L8_JPGENC_BSDMA1		MTK_M4U_ID(8, 18)
+#define M4U_PORT_L8_VENC_NBM_WDMA		MTK_M4U_ID(8, 19)
+#define M4U_PORT_L8_VENC_NBM_WDMA_LITE		MTK_M4U_ID(8, 20)
+#define M4U_PORT_L8_VENC_FCS_NBM_WDMA		MTK_M4U_ID(8, 21)
+#define M4U_PORT_L8_VENC_SUB_R_LUMA		MTK_M4U_ID(8, 22)
+#define M4U_PORT_L8_VENC_CUR_LUMA		MTK_M4U_ID(8, 23)
+#define M4U_PORT_L8_VENC_CUR_CHROMA		MTK_M4U_ID(8, 24)
+#define M4U_PORT_L8_VENC_REF_LUMA		MTK_M4U_ID(8, 25)
+#define M4U_PORT_L8_VENC_REF_CHROMA		MTK_M4U_ID(8, 26)
+/* larb9 -- 29 */
+/* port0~port14 is used, port15~port28 is not used */
+#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1		MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0		MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA		MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0		MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1		MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2		MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3		MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4		MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5		MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0		MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1		MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6		MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7		MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8		MTK_M4U_ID(9, 28)
+/* larb10 -- apu null */
+/* larb11 -- 29 */
+/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */
+#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6		MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7		MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8		MTK_M4U_ID(11, 28)
+/* larb12 -- apu null */
+/* larb13 -- 12 */
+#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_CAMSV1			MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_CAMSV2			MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_CAMSV3			MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)
+/* larb14 -- 6 */
+#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_CAMSV0			MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)
+/* larb15 -- apu null */
+/* larb16 -- 17 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)
+/* larb17 -- 17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)
+/* larb18 -- 17 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)
+/* larb19 -- 4 */
+#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)
+/* larb20 -- 6 */
+#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)
+
+/*above all real larb_port(0~20) */
+#define M4U_LARB_PORT_NR			(217)
+
+/* fake larb -- 5 */
+#define M4U_PORT_L21_APU_FAKE_CODE		MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA		MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM		MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU0		MTK_M4U_ID(CCU0_PSEUDO_LARBID, 0)
+#define M4U_PORT_L23_CCU1		MTK_M4U_ID(CCU1_PSEUDO_LARBID, 0)
+
+#define M4U_PORT_UNKNOWN			(M4U_PORT_L23_CCU1 + 1)
+
+/* Note: M4U_PORT_GPU must be more than M4U_PORT_UNKNOWN */
+#define M4U_PORT_GPU				MTK_M4U_ID(31, 31)
+
+/* include fake port.... to M4U_PORT_L23_CCU1 */
+#define M4U_PORT_NR				(222)
+
+/*********************************************************/
+/* for pusedo fake device */
+#define MISC_PSEUDO_LARBID			MTK_IOMMU_LARB_NR
+#define APU_PSEUDO_LARBID_CODE			(MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA			(MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM			(MTK_IOMMU_LARB_NR + 3)
+
+#define M4U_PORT_APU				M4U_PORT_L21_APU_FAKE_DATA
+
+/* for debug debug */
+#define M4U_PORT_APU_CODE			M4U_PORT_L21_APU_FAKE_CODE
+#define M4U_PORT_CCU				M4U_PORT_L23_CCU1
+#define M4U_PORT_OVL_DEBUG			M4U_PORT_L0_DISP_FAKE0/*no use*/
+#define M4U_PORT_MDP_DEBUG			M4U_PORT_L0_DISP_POSTMASK0
+#define M4U_PORT_BOUNDARY0_DEBUG		M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG		M4U_PORT_L8_VENC_RCPU
+#define M4U_PORT_BOUNDARY2_DEBUG		M4U_PORT_L11_IMG_IMGI_D1
+#define M4U_PORT_BOUNDARY3_DEBUG		M4U_PORT_L21_APU_FAKE_DATA
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) \
+	&& (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS			34
+#define MTK_PHYS_ADDR_BITS			35
+#else
+#define MTK_IOVA_ADDR_BITS			32
+#define MTK_PHYS_ADDR_BITS			34
+#endif
+
+/* the total number of iommu(include mm and vpu) */
+#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_APUSYS_SUPPORT)
+#define MTK_IOMMU_M4U_COUNT			1
+#else
+#define MTK_IOMMU_M4U_COUNT			2
+#endif
+
+/* iommu hw register define */
+#define MTK_IOMMU_DEBUG_REG_NR			(6)
+#define MTK_IOMMU_WAY_NR			(4)
+#define MTK_IOMMU_RS_COUNT			(16)
+#define MTK_IOMMU_MMU_COUNT			(2)
+#define MTK_IOMMU_TAG_COUNT			(64)
+#define MTK_IOMMU_BANK_COUNT			(5)
+#define MTK_IOMMU_MAU_COUNT			(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)		MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)		MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE			(8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+
+/* no use delete it for mt6873? */
+#define MTK_IOMMU_LARB_CODEC_MIN		(4)
+#define MTK_IOMMU_LARB_CODEC_MAX		(11)
+
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+/* the number of apu_iommu */
+#define APU_IOMMU_INDEX				(1)
+
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+
+#endif

include/dt-bindings/memory/mt6877-larb-port.h

@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef _DTS_IOMMU_PORT_MT6833_H_
+#define _DTS_IOMMU_PORT_MT6833_H_
+
+#define MTK_M4U_ID(larb, port)			(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)			(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)			((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID			(21)
+#define CCU0_PSEUDO_LARBID			(22)
+#define CCU1_PSEUDO_LARBID			(23)
+/* 3, 5, 6, 8 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR			(24)
+
+/*********************************************************/
+/* larb0 -- 5 */
+#define M4U_PORT_L0_DISP_POSTMASK0		MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0			MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_DISP_UFBC_WDMA0		MTK_M4U_ID(0, 3)
+#define M4U_PORT_L0_DISP_FAKE0			MTK_M4U_ID(0, 4)
+/* larb1 -- 7 */
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR		MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_DISP_RDMA0			MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_DISP_WDMA0			MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_DISP_FAKE1			MTK_M4U_ID(1, 4)
+#define M4U_PORT_L1_OVL_2L_RDMA1_HDR	MTK_M4U_ID(1, 5)
+#define M4U_PORT_L1_OVL_2L_RDMA1		MTK_M4U_ID(1, 6)
+/* larb2 -- 5 */
+#define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA1			MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0			MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_DISP_FAKE0		MTK_M4U_ID(2, 4)
+/* larb3 -- null */
+/* larb4 -- 12 */
+#define M4U_PORT_L4_VDEC_MC_EXT			MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT			MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT		MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT		MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_UFO_ENC_EXT		MTK_M4U_ID(4, 10)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
+/* larb5 -- null */
+/* larb6 -- null */
+/* larb7 -- 15 */
+#define M4U_PORT_L7_VENC_RCPU			MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC			MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA			MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SUB_W_LUMA		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_SV_COMV		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_RD_COMV		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_JPGENC_Y_RDMA		MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_JPGENC_C_RDMA		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_JPGENC_Q_TABLE		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_BSDMA		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_VENC_SUB_R_LUMA		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_VENC_CUR_LUMA		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_VENC_CUR_CHROMA		MTK_M4U_ID(7, 12)
+#define M4U_PORT_L7_VENC_REF_LUMA		MTK_M4U_ID(7, 13)
+#define M4U_PORT_L7_VENC_REF_CHROMA		MTK_M4U_ID(7, 14)
+/* larb8 -- null */
+/* larb9 -- 29 */
+/* port0~port14 is used, port15~port28 is not used */
+#define M4U_PORT_L9_IMG_IMGI_D1			MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1		MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1			MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1			MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1			MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1			MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2			MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1			MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1			MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1		MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1			MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5			MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1		MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0			MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0			MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1		MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0		MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA		MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0		MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1		MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2		MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3		MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4		MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5		MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0		MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1		MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6		MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7		MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8		MTK_M4U_ID(9, 28)
+/* larb10 -- null */
+/* larb11 -- 29 */
+/* port15~port25 is used, port0 ~ port14, port 26~port28 is not used */
+#define M4U_PORT_L11_IMG_IMGI_D1		MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1		MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1		MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1		MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1			MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1		MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2		MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1		MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1		MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1		MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1		MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5		MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1		MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0		MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0		MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1		MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0		MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA		MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0		MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1		MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2		MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3		MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4		MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5		MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0		MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1		MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6		MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7		MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8		MTK_M4U_ID(11, 28)
+/* larb12 -- null */
+/* larb13 -- 15 */
+#define M4U_PORT_L13_CAM_MRAWI			MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0			MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1			MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_CAMSV1			MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_CAMSV2			MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_CAMSV3			MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4			MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5			MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6			MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI			MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO			MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 11)
+#define M4U_PORT_L13_CAM_PADI0			MTK_M4U_ID(13, 12)
+#define M4U_PORT_L13_CAM_PADI1			MTK_M4U_ID(13, 13)
+#define M4U_PORT_L13_CAM_PDAO			MTK_M4U_ID(13, 14)
+
+/* larb14 -- 10 */
+#define M4U_PORT_L14_CAM_RESERVE1		MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_RESERVE2		MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_RESERVE3		MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_RESERVE4		MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI			MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO			MTK_M4U_ID(14, 5)
+#define M4U_PORT_L14_CAMSV7			MTK_M4U_ID(14, 6)
+#define M4U_PORT_L14_CAMSV8			MTK_M4U_ID(14, 7)
+#define M4U_PORT_L14_CAMSV9			MTK_M4U_ID(14, 8)
+#define M4U_PORT_L14_CAMSV10			MTK_M4U_ID(14, 9)
+
+/* larb15 -- null */
+/* larb16 -- 17 */
+#define M4U_PORT_L16_CAM_IMGO_R1_A		MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A		MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A		MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A		MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A		MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A		MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A		MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A		MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A		MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A		MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A		MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A		MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A		MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A		MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A		MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A		MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A		MTK_M4U_ID(16, 16)
+/* larb17 -- 17 */
+#define M4U_PORT_L17_CAM_IMGO_R1_B		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B		MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B		MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B		MTK_M4U_ID(17, 16)
+/* larb18 -- 17 */
+#define M4U_PORT_L18_CAM_IMGO_R1_C		MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C		MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C		MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C		MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C		MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C		MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C		MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C		MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C		MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C		MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C		MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C		MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C		MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C		MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C		MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C		MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C		MTK_M4U_ID(18, 16)
+/* larb19 -- 4 */
+#define M4U_PORT_L19_IPE_DVS_RDMA		MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA		MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA		MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA		MTK_M4U_ID(19, 3)
+/* larb20 -- 6 */
+#define M4U_PORT_L20_IPE_FDVT_RDA		MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB		MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA		MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB		MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0		MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA		MTK_M4U_ID(20, 5)
+/* fake larb -- 5 */
+#define M4U_PORT_L21_APU_FAKE_CODE		MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA		MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM		MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU0		MTK_M4U_ID(CCU0_PSEUDO_LARBID, 0)
+#define M4U_PORT_L23_CCU1		MTK_M4U_ID(CCU1_PSEUDO_LARBID, 0)
+
+#define M4U_PORT_GPU				MTK_M4U_ID(31, 31)
+#define M4U_PORT_UNKNOWN			(M4U_PORT_L23_CCU1 + 1)
+#define M4U_PORT_NR				(193)
+
+/*********************************************************/
+/* for pusedo fake device */
+#define MISC_PSEUDO_LARBID			MTK_IOMMU_LARB_NR
+#define APU_PSEUDO_LARBID_CODE			(MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA			(MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM			(MTK_IOMMU_LARB_NR + 3)
+
+#define M4U_PORT_APU				M4U_PORT_L21_APU_FAKE_DATA
+
+/* for debug debug */
+#define M4U_PORT_APU_CODE			M4U_PORT_L21_APU_FAKE_CODE
+#define M4U_PORT_CCU				M4U_PORT_L23_CCU1
+#define M4U_PORT_OVL_DEBUG			M4U_PORT_L0_DISP_FAKE0/*no use*/
+#define M4U_PORT_MDP_DEBUG			M4U_PORT_L0_DISP_POSTMASK0
+#define M4U_PORT_BOUNDARY0_DEBUG		M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG		M4U_PORT_L4_VDEC_MC_EXT
+#define M4U_PORT_BOUNDARY2_DEBUG		M4U_PORT_L11_IMG_IMGI_D1
+#define M4U_PORT_BOUNDARY3_DEBUG		M4U_PORT_L21_APU_FAKE_DATA
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) \
+	&& (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS			34
+#define MTK_PHYS_ADDR_BITS			35
+#else
+#define MTK_IOVA_ADDR_BITS			32
+#define MTK_PHYS_ADDR_BITS			34
+#endif
+
+/* the total number of iommu(include mm and vpu) */
+#if defined(CONFIG_FPGA_EARLY_PORTING) || !defined(CONFIG_MTK_APUSYS_SUPPORT)
+#define MTK_IOMMU_M4U_COUNT			1
+#else
+#define MTK_IOMMU_M4U_COUNT			2
+#endif
+
+/* iommu hw register define */
+#define MTK_IOMMU_DEBUG_REG_NR			(6)
+#define MTK_IOMMU_WAY_NR			(4)
+#define MTK_IOMMU_RS_COUNT			(16)
+#define MTK_IOMMU_MMU_COUNT			(2)
+#define MTK_IOMMU_TAG_COUNT			(64)
+#define MTK_IOMMU_BANK_COUNT			(5)
+#define MTK_IOMMU_MAU_COUNT			(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)		MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)		MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE			(8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+/* the number of apu_iommu */
+#define APU_IOMMU_INDEX				(1)
+
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+
+#endif

include/dt-bindings/memory/mt6877-msdc.h

@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#ifndef _DT_BINDINGS_MMC_MT6877_H
+#define _DT_BINDINGS_MMC_MT6877_H
+
+#define MSDC_EMMC               (0)
+#define MSDC_SD                 (1)
+#define MSDC_SDIO               (2)
+
+#define MSDC_CD_HIGH            (1)
+#define MSDC_CD_LOW             (0)
+
+#define MSDC0_CLKSRC_26MHZ      (0)
+#define MSDC0_CLKSRC_400MHZ     (1)
+
+#define MSDC1_CLKSRC_26MHZ     (0)
+#define MSDC1_CLKSRC_208MHZ    (1)
+#define MSDC1_CLKSRC_200MHZ    (2)
+
+#define MSDC_SMPL_RISING        (0)
+#define MSDC_SMPL_FALLING       (1)
+#define MSDC_SMPL_SEPARATE      (2)
+
+#endif /* _DT_BINDINGS_MMC_MT6877_H */

include/dt-bindings/memory/mt6885-larb-port.h

@@ -0,0 +1,354 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+*/
+#ifndef _DTS_IOMMU_PORT_MT6885_H_
+#define _DTS_IOMMU_PORT_MT6885_H_
+
+#define MTK_M4U_ID(larb, port)	(((larb) << 5) | (port))
+
+/* Local arbiter ID */
+#define MTK_IOMMU_TO_LARB(id)	(((id) >> 5) & 0x1f)
+/* PortID within the local arbiter */
+#define MTK_IOMMU_TO_PORT(id)	((id) & 0x1f)
+
+#define APU_PSEUDO_LARBID (21)
+#define CCU_PSEUDO_LARBID_DISP (22)
+#define CCU_PSEUDO_LARBID_MDP (23)
+#define CCU_PSEUDO_LARBID_NODE CCU_PSEUDO_LARBID_MDP
+/* 6, 10, 12, 15 is not applied for IOMMU*/
+#define MTK_IOMMU_LARB_NR	(24)
+
+/* larb0 -- 15*/
+#define M4U_PORT_L0_DISP_POSTMASK0	MTK_M4U_ID(0, 0)
+#define M4U_PORT_L0_MDP_RDMA4		MTK_M4U_ID(0, 1)
+#define M4U_PORT_L0_OVL_RDMA0_HDR		MTK_M4U_ID(0, 2)
+#define M4U_PORT_L0_OVL_2L_RDMA1_HDR	MTK_M4U_ID(0, 3)
+#define M4U_PORT_L0_OVL_2L_RDMA3_HDR	MTK_M4U_ID(0, 4)
+#define M4U_PORT_L0_OVL_RDMA0	MTK_M4U_ID(0, 5)
+#define M4U_PORT_L0_OVL_2L_RDMA1		MTK_M4U_ID(0, 6)
+#define M4U_PORT_L0_OVL_2L_RDMA3	MTK_M4U_ID(0, 7)
+#define M4U_PORT_L0_OVL_RDMA1_SYSRAM	MTK_M4U_ID(0, 8)
+#define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM		MTK_M4U_ID(0, 9)
+#define M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM		MTK_M4U_ID(0, 10)
+#define M4U_PORT_L0_DISP_WDMA0		MTK_M4U_ID(0, 11)
+#define M4U_PORT_L0_DISP_RDMA0		MTK_M4U_ID(0, 12)
+#define M4U_PORT_L0_DISP_UFBC_WDMA0		MTK_M4U_ID(0, 13)
+#define M4U_PORT_L0_DISP_FAKE0		MTK_M4U_ID(0, 14)
+/* larb1 -- 15*/
+#define M4U_PORT_L1_DISP_POSTMASK1	MTK_M4U_ID(1, 0)
+#define M4U_PORT_L1_MDP_RDMA5		MTK_M4U_ID(1, 1)
+#define M4U_PORT_L1_OVL_RDMA1_HDR		MTK_M4U_ID(1, 2)
+#define M4U_PORT_L1_OVL_2L_RDMA0_HDR	MTK_M4U_ID(1, 3)
+#define M4U_PORT_L1_OVL_2L_RDMA2_HDR	MTK_M4U_ID(1, 4)
+#define M4U_PORT_L1_OVL_RDMA1	MTK_M4U_ID(1, 5)
+#define M4U_PORT_L1_OVL_2L_RDMA0		MTK_M4U_ID(1, 6)
+#define M4U_PORT_L1_OVL_2L_RDMA2	MTK_M4U_ID(1, 7)
+#define M4U_PORT_L1_OVL_RDMA0_SYSRAM	MTK_M4U_ID(1, 8)
+#define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM		MTK_M4U_ID(1, 9)
+#define M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM		MTK_M4U_ID(1, 10)
+#define M4U_PORT_L1_DISP_WDMA1		MTK_M4U_ID(1, 11)
+#define M4U_PORT_L1_DISP_RDMA1		MTK_M4U_ID(1, 12)
+#define M4U_PORT_L1_DISP_UFBC_WDMA1		MTK_M4U_ID(1, 13)
+#define M4U_PORT_L1_DISP_FAKE1		MTK_M4U_ID(1, 14)
+/* larb2 -- 6*/
+#define M4U_PORT_L2_MDP_RDMA0		MTK_M4U_ID(2, 0)
+#define M4U_PORT_L2_MDP_RDMA2		MTK_M4U_ID(2, 1)
+#define M4U_PORT_L2_MDP_WROT0		MTK_M4U_ID(2, 2)
+#define M4U_PORT_L2_MDP_WROT2		MTK_M4U_ID(2, 3)
+#define M4U_PORT_L2_MDP_FILMGRAIN0	MTK_M4U_ID(2, 4)
+#define M4U_PORT_L2_MDP_FAKE0		MTK_M4U_ID(2, 5)
+/* larb3 -- 6*/
+#define M4U_PORT_L3_MDP_RDMA1		MTK_M4U_ID(3, 0)
+#define M4U_PORT_L3_MDP_RDMA3		MTK_M4U_ID(3, 1)
+#define M4U_PORT_L3_MDP_WROT1		MTK_M4U_ID(3, 2)
+#define M4U_PORT_L3_MDP_WROT3		MTK_M4U_ID(3, 3)
+#define M4U_PORT_L3_MDP_FILMGRAIN1	MTK_M4U_ID(3, 4)
+#define M4U_PORT_L3_MDP_FAKE1		MTK_M4U_ID(3, 5)
+/* larb4 -- 11*/
+#define M4U_PORT_L4_VDEC_MC_EXT_MDP		MTK_M4U_ID(4, 0)
+#define M4U_PORT_L4_VDEC_UFO_EXT_MDP		MTK_M4U_ID(4, 1)
+#define M4U_PORT_L4_VDEC_PP_EXT_MDP		MTK_M4U_ID(4, 2)
+#define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP	MTK_M4U_ID(4, 3)
+#define M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP	MTK_M4U_ID(4, 4)
+#define M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP		MTK_M4U_ID(4, 5)
+#define M4U_PORT_L4_VDEC_TILE_EXT_MDP		MTK_M4U_ID(4, 6)
+#define M4U_PORT_L4_VDEC_VLD_EXT_MDP		MTK_M4U_ID(4, 7)
+#define M4U_PORT_L4_VDEC_VLD2_EXT_MDP		MTK_M4U_ID(4, 8)
+#define M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP		MTK_M4U_ID(4, 9)
+#define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP	MTK_M4U_ID(4, 10)
+/* larb5 -- 8*/
+#define M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP	MTK_M4U_ID(5, 0)
+#define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP	MTK_M4U_ID(5, 1)
+#define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP	MTK_M4U_ID(5, 2)
+#define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP	MTK_M4U_ID(5, 3)
+#define M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP	MTK_M4U_ID(5, 4)
+#define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP	MTK_M4U_ID(5, 5)
+#define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP	MTK_M4U_ID(5, 6)
+#define M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP	MTK_M4U_ID(5, 7)
+/* larb6 -- not existed*/
+/* larb7 --/ 27*/
+#define M4U_PORT_L7_VENC_RCPU_DISP		MTK_M4U_ID(7, 0)
+#define M4U_PORT_L7_VENC_REC_DISP		MTK_M4U_ID(7, 1)
+#define M4U_PORT_L7_VENC_BSDMA_DISP		MTK_M4U_ID(7, 2)
+#define M4U_PORT_L7_VENC_SV_COMV_DISP		MTK_M4U_ID(7, 3)
+#define M4U_PORT_L7_VENC_RD_COMV_DISP		MTK_M4U_ID(7, 4)
+#define M4U_PORT_L7_VENC_NBM_RDMA_DISP		MTK_M4U_ID(7, 5)
+#define M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP	MTK_M4U_ID(7, 6)
+#define M4U_PORT_L7_JPGENC_Y_RDMA_DISP		MTK_M4U_ID(7, 7)
+#define M4U_PORT_L7_JPGENC_C_RDMA_DISP		MTK_M4U_ID(7, 8)
+#define M4U_PORT_L7_JPGENC_Q_TABLE_DISP		MTK_M4U_ID(7, 9)
+#define M4U_PORT_L7_JPGENC_BSDMA_DISP		MTK_M4U_ID(7, 10)
+#define M4U_PORT_L7_JPGENC_WDMA0_DISP		MTK_M4U_ID(7, 11)
+#define M4U_PORT_L7_JPGENC_BSDMA0_DISP		MTK_M4U_ID(7, 12)
+#define M4U_PORT_L7_VENC_NBM_WDMA_DISP		MTK_M4U_ID(7, 13)
+#define M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP	MTK_M4U_ID(7, 14)
+#define M4U_PORT_L7_VENC_CUR_LUMA_DISP		MTK_M4U_ID(7, 15)
+#define M4U_PORT_L7_VENC_CUR_CHROMA_DISP	MTK_M4U_ID(7, 16)
+#define M4U_PORT_L7_VENC_REF_LUMA_DISP		MTK_M4U_ID(7, 17)
+#define M4U_PORT_L7_VENC_REF_CHROMA_DISP	MTK_M4U_ID(7, 18)
+#define M4U_PORT_L7_VENC_SUB_R_LUMA_DISP	MTK_M4U_ID(7, 19)
+#define M4U_PORT_L7_VENC_SUB_W_LUMA_DISP	MTK_M4U_ID(7, 20)
+#define M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP	MTK_M4U_ID(7, 21)
+#define M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP	MTK_M4U_ID(7, 22)
+#define M4U_PORT_L7_JPGENC_WDMA1_DISP		MTK_M4U_ID(7, 23)
+#define M4U_PORT_L7_JPGENC_BSDMA1_DISP		MTK_M4U_ID(7, 24)
+#define M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP	MTK_M4U_ID(7, 25)
+#define M4U_PORT_L7_JPGENC_HUFF_OFFSET0_DISP	MTK_M4U_ID(7, 26)
+/* larb8 -- 27*/
+#define M4U_PORT_L8_VENC_RCPU_MDP		MTK_M4U_ID(8, 0)
+#define M4U_PORT_L8_VENC_REC_MDP		MTK_M4U_ID(8, 1)
+#define M4U_PORT_L8_VENC_BSDMA_MDP		MTK_M4U_ID(8, 2)
+#define M4U_PORT_L8_VENC_SV_COMV_MDP		MTK_M4U_ID(8, 3)
+#define M4U_PORT_L8_VENC_RD_COMV_MDP		MTK_M4U_ID(8, 4)
+#define M4U_PORT_L8_VENC_NBM_RDMA_MDP		MTK_M4U_ID(8, 5)
+#define M4U_PORT_L8_VENC_NBM_RDMA_LITE_MDP	MTK_M4U_ID(8, 6)
+#define M4U_PORT_L8_JPGENC_Y_RDMA_MDP		MTK_M4U_ID(8, 7)
+#define M4U_PORT_L8_JPGENC_C_RDMA_MDP		MTK_M4U_ID(8, 8)
+#define M4U_PORT_L8_JPGENC_Q_TABLE_MDP		MTK_M4U_ID(8, 9)
+#define M4U_PORT_L8_JPGENC_BSDMA_MDP		MTK_M4U_ID(8, 10)
+#define M4U_PORT_L8_JPGENC_WDMA0_MDP		MTK_M4U_ID(8, 11)
+#define M4U_PORT_L8_JPGENC_BSDMA0_MDP		MTK_M4U_ID(8, 12)
+#define M4U_PORT_L8_VENC_NBM_WDMA_MDP		MTK_M4U_ID(8, 13)
+#define M4U_PORT_L8_VENC_NBM_WDMA_LITE_MDP	MTK_M4U_ID(8, 14)
+#define M4U_PORT_L8_VENC_CUR_LUMA_MDP		MTK_M4U_ID(8, 15)
+#define M4U_PORT_L8_VENC_CUR_CHROMA_MDP		MTK_M4U_ID(8, 16)
+#define M4U_PORT_L8_VENC_REF_LUMA_MDP		MTK_M4U_ID(8, 17)
+#define M4U_PORT_L8_VENC_REF_CHROMA_MDP		MTK_M4U_ID(8, 18)
+#define M4U_PORT_L8_VENC_SUB_R_LUMA_MDP		MTK_M4U_ID(8, 19)
+#define M4U_PORT_L8_VENC_SUB_W_LUMA_MDP		MTK_M4U_ID(8, 20)
+#define M4U_PORT_L8_VENC_FCS_NBM_RDMA_MDP	MTK_M4U_ID(8, 21)
+#define M4U_PORT_L8_VENC_FCS_NBM_WDMA_MDP	MTK_M4U_ID(8, 22)
+#define M4U_PORT_L8_JPGENC_WDMA1_MDP		MTK_M4U_ID(8, 23)
+#define M4U_PORT_L8_JPGENC_BSDMA1_MDP		MTK_M4U_ID(8, 24)
+#define M4U_PORT_L8_JPGENC_HUFF_OFFSET1_MDP	MTK_M4U_ID(8, 25)
+#define M4U_PORT_L8_JPGENC_HUFF_OFFSET0_MDP	MTK_M4U_ID(8, 26)
+/* larb9 -- 29*/
+#define M4U_PORT_L9_IMG_IMGI_D1_MDP	MTK_M4U_ID(9, 0)
+#define M4U_PORT_L9_IMG_IMGBI_D1_MDP	MTK_M4U_ID(9, 1)
+#define M4U_PORT_L9_IMG_DMGI_D1_MDP	MTK_M4U_ID(9, 2)
+#define M4U_PORT_L9_IMG_DEPI_D1_MDP	MTK_M4U_ID(9, 3)
+#define M4U_PORT_L9_IMG_ICE_D1_MDP	MTK_M4U_ID(9, 4)
+#define M4U_PORT_L9_IMG_SMTI_D1_MDP	MTK_M4U_ID(9, 5)
+#define M4U_PORT_L9_IMG_SMTO_D2_MDP	MTK_M4U_ID(9, 6)
+#define M4U_PORT_L9_IMG_SMTO_D1_MDP	MTK_M4U_ID(9, 7)
+#define M4U_PORT_L9_IMG_CRZO_D1_MDP	MTK_M4U_ID(9, 8)
+#define M4U_PORT_L9_IMG_IMG3O_D1_MDP	MTK_M4U_ID(9, 9)
+#define M4U_PORT_L9_IMG_VIPI_D1_MDP	MTK_M4U_ID(9, 10)
+#define M4U_PORT_L9_IMG_SMTI_D5_MDP	MTK_M4U_ID(9, 11)
+#define M4U_PORT_L9_IMG_TIMGO_D1_MDP	MTK_M4U_ID(9, 12)
+#define M4U_PORT_L9_IMG_UFBC_W0_MDP	MTK_M4U_ID(9, 13)
+#define M4U_PORT_L9_IMG_UFBC_R0_MDP	MTK_M4U_ID(9, 14)
+#define M4U_PORT_L9_IMG_WPE_RDMA1_MDP	MTK_M4U_ID(9, 15)
+#define M4U_PORT_L9_IMG_WPE_RDMA0_MDP	MTK_M4U_ID(9, 16)
+#define M4U_PORT_L9_IMG_WPE_WDMA_MDP	MTK_M4U_ID(9, 17)
+#define M4U_PORT_L9_IMG_MFB_RDMA0_MDP	MTK_M4U_ID(9, 18)
+#define M4U_PORT_L9_IMG_MFB_RDMA1_MDP	MTK_M4U_ID(9, 19)
+#define M4U_PORT_L9_IMG_MFB_RDMA2_MDP	MTK_M4U_ID(9, 20)
+#define M4U_PORT_L9_IMG_MFB_RDMA3_MDP	MTK_M4U_ID(9, 21)
+#define M4U_PORT_L9_IMG_MFB_RDMA4_MDP	MTK_M4U_ID(9, 22)
+#define M4U_PORT_L9_IMG_MFB_RDMA5_MDP	MTK_M4U_ID(9, 23)
+#define M4U_PORT_L9_IMG_MFB_WDMA0_MDP	MTK_M4U_ID(9, 24)
+#define M4U_PORT_L9_IMG_MFB_WDMA1_MDP	MTK_M4U_ID(9, 25)
+#define M4U_PORT_L9_IMG_RESERVE6_MDP	MTK_M4U_ID(9, 26)
+#define M4U_PORT_L9_IMG_RESERVE7_MDP	MTK_M4U_ID(9, 27)
+#define M4U_PORT_L9_IMG_RESERVE8_MDP	MTK_M4U_ID(9, 28)
+/* larb10 -- not existed*/
+/* larb11 -- 29*/
+#define M4U_PORT_L11_IMG_IMGI_D1_DISP	MTK_M4U_ID(11, 0)
+#define M4U_PORT_L11_IMG_IMGBI_D1_DISP	MTK_M4U_ID(11, 1)
+#define M4U_PORT_L11_IMG_DMGI_D1_DISP	MTK_M4U_ID(11, 2)
+#define M4U_PORT_L11_IMG_DEPI_D1_DISP	MTK_M4U_ID(11, 3)
+#define M4U_PORT_L11_IMG_ICE_D1_DISP	MTK_M4U_ID(11, 4)
+#define M4U_PORT_L11_IMG_SMTI_D1_DISP	MTK_M4U_ID(11, 5)
+#define M4U_PORT_L11_IMG_SMTO_D2_DISP	MTK_M4U_ID(11, 6)
+#define M4U_PORT_L11_IMG_SMTO_D1_DISP	MTK_M4U_ID(11, 7)
+#define M4U_PORT_L11_IMG_CRZO_D1_DISP	MTK_M4U_ID(11, 8)
+#define M4U_PORT_L11_IMG_IMG3O_D1_DISP	MTK_M4U_ID(11, 9)
+#define M4U_PORT_L11_IMG_VIPI_D1_DISP	MTK_M4U_ID(11, 10)
+#define M4U_PORT_L11_IMG_SMTI_D5_DISP	MTK_M4U_ID(11, 11)
+#define M4U_PORT_L11_IMG_TIMGO_D1_DISP	MTK_M4U_ID(11, 12)
+#define M4U_PORT_L11_IMG_UFBC_W0_DISP	MTK_M4U_ID(11, 13)
+#define M4U_PORT_L11_IMG_UFBC_R0_DISP	MTK_M4U_ID(11, 14)
+#define M4U_PORT_L11_IMG_WPE_RDMA1_DISP	MTK_M4U_ID(11, 15)
+#define M4U_PORT_L11_IMG_WPE_RDMA0_DISP	MTK_M4U_ID(11, 16)
+#define M4U_PORT_L11_IMG_WPE_WDMA_DISP	MTK_M4U_ID(11, 17)
+#define M4U_PORT_L11_IMG_MFB_RDMA0_DISP	MTK_M4U_ID(11, 18)
+#define M4U_PORT_L11_IMG_MFB_RDMA1_DISP	MTK_M4U_ID(11, 19)
+#define M4U_PORT_L11_IMG_MFB_RDMA2_DISP	MTK_M4U_ID(11, 20)
+#define M4U_PORT_L11_IMG_MFB_RDMA3_DISP	MTK_M4U_ID(11, 21)
+#define M4U_PORT_L11_IMG_MFB_RDMA4_DISP	MTK_M4U_ID(11, 22)
+#define M4U_PORT_L11_IMG_MFB_RDMA5_DISP	MTK_M4U_ID(11, 23)
+#define M4U_PORT_L11_IMG_MFB_WDMA0_DISP	MTK_M4U_ID(11, 24)
+#define M4U_PORT_L11_IMG_MFB_WDMA1_DISP	MTK_M4U_ID(11, 25)
+#define M4U_PORT_L11_IMG_RESERVE6_DISP	MTK_M4U_ID(11, 26)
+#define M4U_PORT_L11_IMG_RESERVE7_DISP	MTK_M4U_ID(11, 27)
+#define M4U_PORT_L11_IMG_RESERVE8_DISP	MTK_M4U_ID(11, 28)
+/* larb12 -- not existed*/
+/* larb13 -- 12*/
+#define M4U_PORT_L13_CAM_MRAWI_MDP	MTK_M4U_ID(13, 0)
+#define M4U_PORT_L13_CAM_MRAWO0_MDP	MTK_M4U_ID(13, 1)
+#define M4U_PORT_L13_CAM_MRAWO1_MDP	MTK_M4U_ID(13, 2)
+#define M4U_PORT_L13_CAM_CAMSV1_MDP	MTK_M4U_ID(13, 3)
+#define M4U_PORT_L13_CAM_CAMSV2_MDP	MTK_M4U_ID(13, 4)
+#define M4U_PORT_L13_CAM_CAMSV3_MDP	MTK_M4U_ID(13, 5)
+#define M4U_PORT_L13_CAM_CAMSV4_MDP	MTK_M4U_ID(13, 6)
+#define M4U_PORT_L13_CAM_CAMSV5_MDP	MTK_M4U_ID(13, 7)
+#define M4U_PORT_L13_CAM_CAMSV6_MDP	MTK_M4U_ID(13, 8)
+#define M4U_PORT_L13_CAM_CCUI_MDP	MTK_M4U_ID(13, 9)
+#define M4U_PORT_L13_CAM_CCUO_MDP	MTK_M4U_ID(13, 10)
+#define M4U_PORT_L13_CAM_FAKE_MDP	MTK_M4U_ID(13, 11)
+/* larb14 -- 6*/
+#define M4U_PORT_L14_CAM_MRAWI_DISP	MTK_M4U_ID(14, 0)
+#define M4U_PORT_L14_CAM_MRAWO0_DISP	MTK_M4U_ID(14, 1)
+#define M4U_PORT_L14_CAM_MRAWO1_DISP	MTK_M4U_ID(14, 2)
+#define M4U_PORT_L14_CAM_CAMSV0_DISP	MTK_M4U_ID(14, 3)
+#define M4U_PORT_L14_CAM_CCUI_DISP	MTK_M4U_ID(14, 4)
+#define M4U_PORT_L14_CAM_CCUO_DISP	MTK_M4U_ID(14, 5)
+/* larb15 -- no iommu user*/
+/* larb16 -- 17*/
+#define M4U_PORT_L16_CAM_IMGO_R1_A_MDP	MTK_M4U_ID(16, 0)
+#define M4U_PORT_L16_CAM_RRZO_R1_A_MDP	MTK_M4U_ID(16, 1)
+#define M4U_PORT_L16_CAM_CQI_R1_A_MDP	MTK_M4U_ID(16, 2)
+#define M4U_PORT_L16_CAM_BPCI_R1_A_MDP	MTK_M4U_ID(16, 3)
+#define M4U_PORT_L16_CAM_YUVO_R1_A_MDP	MTK_M4U_ID(16, 4)
+#define M4U_PORT_L16_CAM_UFDI_R2_A_MDP	MTK_M4U_ID(16, 5)
+#define M4U_PORT_L16_CAM_RAWI_R2_A_MDP	MTK_M4U_ID(16, 6)
+#define M4U_PORT_L16_CAM_RAWI_R3_A_MDP	MTK_M4U_ID(16, 7)
+#define M4U_PORT_L16_CAM_AAO_R1_A_MDP	MTK_M4U_ID(16, 8)
+#define M4U_PORT_L16_CAM_AFO_R1_A_MDP	MTK_M4U_ID(16, 9)
+#define M4U_PORT_L16_CAM_FLKO_R1_A_MDP	MTK_M4U_ID(16, 10)
+#define M4U_PORT_L16_CAM_LCESO_R1_A_MDP	MTK_M4U_ID(16, 11)
+#define M4U_PORT_L16_CAM_CRZO_R1_A_MDP	MTK_M4U_ID(16, 12)
+#define M4U_PORT_L16_CAM_LTMSO_R1_A_MDP	MTK_M4U_ID(16, 13)
+#define M4U_PORT_L16_CAM_RSSO_R1_A_MDP	MTK_M4U_ID(16, 14)
+#define M4U_PORT_L16_CAM_AAHO_R1_A_MDP	MTK_M4U_ID(16, 15)
+#define M4U_PORT_L16_CAM_LSCI_R1_A_MDP	MTK_M4U_ID(16, 16)
+/* larb17 -- 17*/
+#define M4U_PORT_L17_CAM_IMGO_R1_B_DISP		MTK_M4U_ID(17, 0)
+#define M4U_PORT_L17_CAM_RRZO_R1_B_DISP		MTK_M4U_ID(17, 1)
+#define M4U_PORT_L17_CAM_CQI_R1_B_DISP		MTK_M4U_ID(17, 2)
+#define M4U_PORT_L17_CAM_BPCI_R1_B_DISP		MTK_M4U_ID(17, 3)
+#define M4U_PORT_L17_CAM_YUVO_R1_B_DISP		MTK_M4U_ID(17, 4)
+#define M4U_PORT_L17_CAM_UFDI_R2_B_DISP		MTK_M4U_ID(17, 5)
+#define M4U_PORT_L17_CAM_RAWI_R2_B_DISP		MTK_M4U_ID(17, 6)
+#define M4U_PORT_L17_CAM_RAWI_R3_B_DISP		MTK_M4U_ID(17, 7)
+#define M4U_PORT_L17_CAM_AAO_R1_B_DISP		MTK_M4U_ID(17, 8)
+#define M4U_PORT_L17_CAM_AFO_R1_B_DISP		MTK_M4U_ID(17, 9)
+#define M4U_PORT_L17_CAM_FLKO_R1_B_DISP		MTK_M4U_ID(17, 10)
+#define M4U_PORT_L17_CAM_LCESO_R1_B_DISP	MTK_M4U_ID(17, 11)
+#define M4U_PORT_L17_CAM_CRZO_R1_B_DISP		MTK_M4U_ID(17, 12)
+#define M4U_PORT_L17_CAM_LTMSO_R1_B_DISP	MTK_M4U_ID(17, 13)
+#define M4U_PORT_L17_CAM_RSSO_R1_B_DISP		MTK_M4U_ID(17, 14)
+#define M4U_PORT_L17_CAM_AAHO_R1_B_DISP		MTK_M4U_ID(17, 15)
+#define M4U_PORT_L17_CAM_LSCI_R1_B_DISP		MTK_M4U_ID(17, 16)
+/* larb18 -- 17*/
+#define M4U_PORT_L18_CAM_IMGO_R1_C_MDP	MTK_M4U_ID(18, 0)
+#define M4U_PORT_L18_CAM_RRZO_R1_C_MDP	MTK_M4U_ID(18, 1)
+#define M4U_PORT_L18_CAM_CQI_R1_C_MDP	MTK_M4U_ID(18, 2)
+#define M4U_PORT_L18_CAM_BPCI_R1_C_MDP	MTK_M4U_ID(18, 3)
+#define M4U_PORT_L18_CAM_YUVO_R1_C_MDP	MTK_M4U_ID(18, 4)
+#define M4U_PORT_L18_CAM_UFDI_R2_C_MDP	MTK_M4U_ID(18, 5)
+#define M4U_PORT_L18_CAM_RAWI_R2_C_MDP	MTK_M4U_ID(18, 6)
+#define M4U_PORT_L18_CAM_RAWI_R3_C_MDP	MTK_M4U_ID(18, 7)
+#define M4U_PORT_L18_CAM_AAO_R1_C_MDP	MTK_M4U_ID(18, 8)
+#define M4U_PORT_L18_CAM_AFO_R1_C_MDP	MTK_M4U_ID(18, 9)
+#define M4U_PORT_L18_CAM_FLKO_R1_C_MDP	MTK_M4U_ID(18, 10)
+#define M4U_PORT_L18_CAM_LCESO_R1_C_MDP	MTK_M4U_ID(18, 11)
+#define M4U_PORT_L18_CAM_CRZO_R1_C_MDP	MTK_M4U_ID(18, 12)
+#define M4U_PORT_L18_CAM_LTMSO_R1_C_MDP	MTK_M4U_ID(18, 13)
+#define M4U_PORT_L18_CAM_RSSO_R1_C_MDP	MTK_M4U_ID(18, 14)
+#define M4U_PORT_L18_CAM_AAHO_R1_C_MDP	MTK_M4U_ID(18, 15)
+#define M4U_PORT_L18_CAM_LSCI_R1_C_MDP	MTK_M4U_ID(18, 16)
+/* larb19 -- 4*/
+#define M4U_PORT_L19_IPE_DVS_RDMA_DISP	MTK_M4U_ID(19, 0)
+#define M4U_PORT_L19_IPE_DVS_WDMA_DISP	MTK_M4U_ID(19, 1)
+#define M4U_PORT_L19_IPE_DVP_RDMA_DISP	MTK_M4U_ID(19, 2)
+#define M4U_PORT_L19_IPE_DVP_WDMA_DISP	MTK_M4U_ID(19, 3)
+/* larb20 -- 6*/
+#define M4U_PORT_L20_IPE_FDVT_RDA_DISP	MTK_M4U_ID(20, 0)
+#define M4U_PORT_L20_IPE_FDVT_RDB_DISP	MTK_M4U_ID(20, 1)
+#define M4U_PORT_L20_IPE_FDVT_WRA_DISP	MTK_M4U_ID(20, 2)
+#define M4U_PORT_L20_IPE_FDVT_WRB_DISP	MTK_M4U_ID(20, 3)
+#define M4U_PORT_L20_IPE_RSC_RDMA0_DISP	MTK_M4U_ID(20, 4)
+#define M4U_PORT_L20_IPE_RSC_WDMA_DISP	MTK_M4U_ID(20, 5)
+
+#define M4U_PORT_L21_APU_FAKE_CODE  MTK_M4U_ID(APU_PSEUDO_LARBID, 0)
+#define M4U_PORT_L21_APU_FAKE_DATA  MTK_M4U_ID(APU_PSEUDO_LARBID, 1)
+#define M4U_PORT_L21_APU_FAKE_VLM  MTK_M4U_ID(APU_PSEUDO_LARBID, 2)
+#define M4U_PORT_L22_CCU_DISP  MTK_M4U_ID(CCU_PSEUDO_LARBID_DISP, 0)
+#define M4U_PORT_L23_CCU_MDP  MTK_M4U_ID(CCU_PSEUDO_LARBID_MDP, 0)
+#define M4U_PORT_UNKNOWN	(M4U_PORT_L23_CCU_MDP + 1)
+#define M4U_PORT_GPU    MTK_M4U_ID(31, 31)
+#define M4U_PORT_NR (257)
+
+#define M4U_PORT_APU	(M4U_PORT_L21_APU_FAKE_DATA)
+#define M4U_PORT_APU_CODE    (M4U_PORT_L21_APU_FAKE_CODE)
+#define M4U_PORT_CCU	(M4U_PORT_L23_CCU_MDP)
+#define M4U_PORT_OVL_DEBUG M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_MDP_DEBUG M4U_PORT_L2_MDP_FAKE0
+#define M4U_PORT_BOUNDARY0_DEBUG    M4U_PORT_L0_DISP_FAKE0
+#define M4U_PORT_BOUNDARY1_DEBUG    M4U_PORT_L8_VENC_RCPU_MDP
+#define M4U_PORT_BOUNDARY2_DEBUG    M4U_PORT_L2_MDP_FAKE0
+#define M4U_PORT_BOUNDARY3_DEBUG    M4U_PORT_L21_APU_FAKE_DATA
+
+/* for pusedo ccu device */
+#define MISC_PSEUDO_LARBID_DISP (MTK_IOMMU_LARB_NR)
+#define APU_PSEUDO_LARBID_CODE (MTK_IOMMU_LARB_NR + 1)
+#define APU_PSEUDO_LARBID_DATA (MTK_IOMMU_LARB_NR + 2)
+#define APU_PSEUDO_LARBID_VLM (MTK_IOMMU_LARB_NR + 3)
+#define CCU_PSEUDO_LARBID_LARB (MTK_IOMMU_LARB_NR + 4)
+
+#if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) && \
+	(CONFIG_MTK_IOMMU_PGTABLE_EXT == 34)
+#define MTK_IOVA_ADDR_BITS 34
+#define MTK_PHYS_ADDR_BITS 35
+#else
+#define MTK_IOVA_ADDR_BITS 32
+#define MTK_PHYS_ADDR_BITS 34
+#endif
+
+#ifdef CONFIG_FPGA_EARLY_PORTING
+#define MTK_IOMMU_M4U_COUNT (1)
+#else
+#define MTK_IOMMU_M4U_COUNT (4)
+#endif
+#define MTK_IOMMU_DEBUG_REG_NR   (6)
+#define MTK_IOMMU_WAY_NR   (4)
+#define MTK_IOMMU_RS_COUNT	(16)
+#define MTK_IOMMU_MMU_COUNT	(2)
+#define MTK_IOMMU_TAG_COUNT	(64)
+#define MTK_IOMMU_BANK_COUNT	(5)
+#define MTK_IOMMU_MAU_COUNT	(1)
+#define MTK_MMU_NUM_OF_IOMMU(m4u_id)	MTK_IOMMU_MMU_COUNT
+#define MTK_MAU_NUM_OF_MMU(mmu_id)	MTK_IOMMU_MAU_COUNT
+#define MMU_PAGE_PER_LINE     (8)
+#define MMU_ENTRY_PER_VICTIM		(16)
+#define MTK_IOMMU_LARB_CODEC_MIN (4)
+#define MTK_IOMMU_LARB_CODEC_MAX (11)
+#define MTK_IOMMU_IOVA_BOUNDARY_COUNT \
+(1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32))
+
+#define APU_IOMMU_INDEX (2)
+#define MTK_IOMMU_PORT_TRANSFER_DISABLE
+#endif

include/dt-bindings/memory/mt8173-larb-port.h

@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8173_H
+#define __DTS_IOMMU_PORT_MT8173_H
+
+#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
+
+#define M4U_LARB0_ID			0
+#define M4U_LARB1_ID			1
+#define M4U_LARB2_ID			2
+#define M4U_LARB3_ID			3
+#define M4U_LARB4_ID			4
+#define M4U_LARB5_ID			5
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
+
+/* larb2 */
+#define M4U_PORT_IMGO			MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_RRZO			MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_AAO			MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_LCSO			MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_ESFKO			MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_IMGO_D			MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_LSCI			MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_LSCI_D			MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_BPCI			MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_BPCI_D			MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_UFDI			MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_IMGI			MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_IMG2O			MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_IMG3O			MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_VIPI			MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_VIP2I			MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_VIP3I			MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_LCEI			MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_RB			MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_RP			MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_WR			MTK_M4U_ID(M4U_LARB2_ID, 20)
+
+/* larb3 */
+#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_JPGDEC_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_JPGDEC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 10)
+#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 11)
+#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 12)
+#define M4U_PORT_VENC_NBM_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 14)
+
+/* larb4 */
+#define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 5)
+
+/* larb5 */
+#define M4U_PORT_VENC_RCPU_SET2		MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_VENC_REC_FRM_SET2	MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_VENC_REF_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_VENC_REC_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_VENC_BSDMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_VENC_CUR_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_VENC_CUR_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_VENC_RD_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_VENC_SV_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 8)
+
+#endif

include/dt-bindings/memory/mt8183-larb-port.h

@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8183_H
+#define __DTS_IOMMU_PORT_MT8183_H
+
+#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
+
+#define M4U_LARB0_ID			0
+#define M4U_LARB1_ID			1
+#define M4U_LARB2_ID			2
+#define M4U_LARB3_ID			3
+#define M4U_LARB4_ID			4
+#define M4U_LARB5_ID			5
+#define M4U_LARB6_ID			6
+#define M4U_LARB7_ID			7
+
+/* larb0 */
+#define	M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define	M4U_PORT_DISP_2L_OVL0_LARB0     MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define	M4U_PORT_DISP_2L_OVL1_LARB0     MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define	M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define	M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define	M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define	M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define	M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define	M4U_PORT_MDP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define	M4U_PORT_DISP_FAKE0		MTK_M4U_ID(M4U_LARB0_ID, 9)
+
+/* larb1 */
+#define	M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define	M4U_PORT_HW_VDEC_PP_EXT         MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define	M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define	M4U_PORT_HW_VDEC_AVC_MV_EXT     MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define	M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define	M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define	M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
+
+/* larb2 VPU0 */
+#define	M4U_PORT_IMG_IPUO		MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define	M4U_PORT_IMG_IPU3O		MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define	M4U_PORT_IMG_IPUI		MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 VPU1 */
+#define	M4U_PORT_CAM_IPUO		MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define	M4U_PORT_CAM_IPU2O		MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define	M4U_PORT_CAM_IPU3O		MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define	M4U_PORT_CAM_IPUI		MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define	M4U_PORT_CAM_IPU2I		MTK_M4U_ID(M4U_LARB3_ID, 4)
+
+/* larb4 */
+#define	M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define	M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define	M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define	M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define	M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define	M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define	M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB4_ID, 6)
+#define	M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB4_ID, 7)
+#define	M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB4_ID, 8)
+#define	M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB4_ID, 9)
+#define	M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB4_ID, 10)
+
+/* larb5 */
+#define	M4U_PORT_CAM_IMGI		MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define	M4U_PORT_CAM_IMG2O		MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define	M4U_PORT_CAM_IMG3O		MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define	M4U_PORT_CAM_VIPI		MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define	M4U_PORT_CAM_LCEI		MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define	M4U_PORT_CAM_SMXI		MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define	M4U_PORT_CAM_SMXO		MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define	M4U_PORT_CAM_WPE0_RDMA1		MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define	M4U_PORT_CAM_WPE0_RDMA0		MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define	M4U_PORT_CAM_WPE0_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define	M4U_PORT_CAM_FDVT_RP		MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define	M4U_PORT_CAM_FDVT_WR		MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define	M4U_PORT_CAM_FDVT_RB		MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define	M4U_PORT_CAM_WPE1_RDMA0		MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define	M4U_PORT_CAM_WPE1_RDMA1		MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define	M4U_PORT_CAM_WPE1_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define	M4U_PORT_CAM_DPE_RDMA		MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define	M4U_PORT_CAM_DPE_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define	M4U_PORT_CAM_MFB_RDMA0		MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define	M4U_PORT_CAM_MFB_RDMA1		MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define	M4U_PORT_CAM_MFB_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define	M4U_PORT_CAM_RSC_RDMA0		MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define	M4U_PORT_CAM_RSC_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define	M4U_PORT_CAM_OWE_RDMA		MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define	M4U_PORT_CAM_OWE_WDMA		MTK_M4U_ID(M4U_LARB5_ID, 24)
+
+/* larb6 */
+#define	M4U_PORT_CAM_IMGO		MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define	M4U_PORT_CAM_RRZO		MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define	M4U_PORT_CAM_AAO		MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define	M4U_PORT_CAM_AFO		MTK_M4U_ID(M4U_LARB6_ID, 3)
+#define	M4U_PORT_CAM_LSCI0		MTK_M4U_ID(M4U_LARB6_ID, 4)
+#define	M4U_PORT_CAM_LSCI1		MTK_M4U_ID(M4U_LARB6_ID, 5)
+#define	M4U_PORT_CAM_PDO		MTK_M4U_ID(M4U_LARB6_ID, 6)
+#define	M4U_PORT_CAM_BPCI		MTK_M4U_ID(M4U_LARB6_ID, 7)
+#define	M4U_PORT_CAM_LCSO		MTK_M4U_ID(M4U_LARB6_ID, 8)
+#define	M4U_PORT_CAM_CAM_RSSO_A		MTK_M4U_ID(M4U_LARB6_ID, 9)
+#define	M4U_PORT_CAM_UFEO		MTK_M4U_ID(M4U_LARB6_ID, 10)
+#define	M4U_PORT_CAM_SOCO		MTK_M4U_ID(M4U_LARB6_ID, 11)
+#define	M4U_PORT_CAM_SOC1		MTK_M4U_ID(M4U_LARB6_ID, 12)
+#define	M4U_PORT_CAM_SOC2		MTK_M4U_ID(M4U_LARB6_ID, 13)
+#define	M4U_PORT_CAM_CCUI		MTK_M4U_ID(M4U_LARB6_ID, 14)
+#define	M4U_PORT_CAM_CCUO		MTK_M4U_ID(M4U_LARB6_ID, 15)
+#define	M4U_PORT_CAM_RAWI_A		MTK_M4U_ID(M4U_LARB6_ID, 16)
+#define	M4U_PORT_CAM_CCUG		MTK_M4U_ID(M4U_LARB6_ID, 17)
+#define	M4U_PORT_CAM_PSO		MTK_M4U_ID(M4U_LARB6_ID, 18)
+#define	M4U_PORT_CAM_AFO_1		MTK_M4U_ID(M4U_LARB6_ID, 19)
+#define	M4U_PORT_CAM_LSCI_2		MTK_M4U_ID(M4U_LARB6_ID, 20)
+#define	M4U_PORT_CAM_PDI		MTK_M4U_ID(M4U_LARB6_ID, 21)
+#define	M4U_PORT_CAM_FLKO		MTK_M4U_ID(M4U_LARB6_ID, 22)
+#define	M4U_PORT_CAM_LMVO		MTK_M4U_ID(M4U_LARB6_ID, 23)
+#define	M4U_PORT_CAM_UFGO		MTK_M4U_ID(M4U_LARB6_ID, 24)
+#define	M4U_PORT_CAM_SPARE		MTK_M4U_ID(M4U_LARB6_ID, 25)
+#define	M4U_PORT_CAM_SPARE_2		MTK_M4U_ID(M4U_LARB6_ID, 26)
+#define	M4U_PORT_CAM_SPARE_3		MTK_M4U_ID(M4U_LARB6_ID, 27)
+#define	M4U_PORT_CAM_SPARE_4		MTK_M4U_ID(M4U_LARB6_ID, 28)
+#define	M4U_PORT_CAM_SPARE_5		MTK_M4U_ID(M4U_LARB6_ID, 29)
+#define	M4U_PORT_CAM_SPARE_6		MTK_M4U_ID(M4U_LARB6_ID, 30)
+
+/* CCU */
+#define	M4U_PORT_CCU0			MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define	M4U_PORT_CCU1			MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+#endif

include/dt-bindings/memory/mtk-smi-larb-port.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015-2016 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_MTK_IOMMU_PORT_H_
+#define __DTS_MTK_IOMMU_PORT_H_
+
+#define SMI_LARB_PORT_NR_MAX		32
+#define MTK_LARB_NR_MAX			32
+#define MTK_M4U_DOM_NR_MAX		8
+
+#define MTK_M4U_DOM_ID(dom, larb, port)	((dom & 0x7) << 12 |\
+					 ((larb & 0x1f) << 5) | (port & 0x1f))
+
+/* The default dom is 0. */
+#define MTK_M4U_ID(larb, port)		MTK_M4U_DOM_ID(0, larb, port)
+#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
+#define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
+#define MTK_M4U_TO_DOM(id)		(((id) >> 12) & 0x7)
+
+#endif

include/dt-bindings/memory/tegra114-mc.h

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_EPP	3
+#define TEGRA_SWGROUP_G2	4
+#define TEGRA_SWGROUP_AVPC	5
+#define TEGRA_SWGROUP_NV	6
+#define TEGRA_SWGROUP_HDA	7
+#define TEGRA_SWGROUP_HC	8
+#define TEGRA_SWGROUP_MSENC	9
+#define TEGRA_SWGROUP_PPCS	10
+#define TEGRA_SWGROUP_VDE	11
+#define TEGRA_SWGROUP_MPCORELP	12
+#define TEGRA_SWGROUP_MPCORE	13
+#define TEGRA_SWGROUP_VI	14
+#define TEGRA_SWGROUP_ISP	15
+#define TEGRA_SWGROUP_XUSB_HOST	16
+#define TEGRA_SWGROUP_XUSB_DEV	17
+#define TEGRA_SWGROUP_EMUCIF	18
+#define TEGRA_SWGROUP_TSEC	19
+
+#define TEGRA114_MC_RESET_AVPC		0
+#define TEGRA114_MC_RESET_DC		1
+#define TEGRA114_MC_RESET_DCB		2
+#define TEGRA114_MC_RESET_EPP		3
+#define TEGRA114_MC_RESET_2D		4
+#define TEGRA114_MC_RESET_HC		5
+#define TEGRA114_MC_RESET_HDA		6
+#define TEGRA114_MC_RESET_ISP		7
+#define TEGRA114_MC_RESET_MPCORE	8
+#define TEGRA114_MC_RESET_MPCORELP	9
+#define TEGRA114_MC_RESET_MPE		10
+#define TEGRA114_MC_RESET_3D		11
+#define TEGRA114_MC_RESET_3D2		12
+#define TEGRA114_MC_RESET_PPCS		13
+#define TEGRA114_MC_RESET_VDE		14
+#define TEGRA114_MC_RESET_VI		15
+
+#endif

include/dt-bindings/memory/tegra124-mc.h

@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA124_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_AFI	3
+#define TEGRA_SWGROUP_AVPC	4
+#define TEGRA_SWGROUP_HDA	5
+#define TEGRA_SWGROUP_HC	6
+#define TEGRA_SWGROUP_MSENC	7
+#define TEGRA_SWGROUP_PPCS	8
+#define TEGRA_SWGROUP_SATA	9
+#define TEGRA_SWGROUP_VDE	10
+#define TEGRA_SWGROUP_MPCORELP	11
+#define TEGRA_SWGROUP_MPCORE	12
+#define TEGRA_SWGROUP_ISP2	13
+#define TEGRA_SWGROUP_XUSB_HOST	14
+#define TEGRA_SWGROUP_XUSB_DEV	15
+#define TEGRA_SWGROUP_ISP2B	16
+#define TEGRA_SWGROUP_TSEC	17
+#define TEGRA_SWGROUP_A9AVP	18
+#define TEGRA_SWGROUP_GPU	19
+#define TEGRA_SWGROUP_SDMMC1A	20
+#define TEGRA_SWGROUP_SDMMC2A	21
+#define TEGRA_SWGROUP_SDMMC3A	22
+#define TEGRA_SWGROUP_SDMMC4A	23
+#define TEGRA_SWGROUP_VIC	24
+#define TEGRA_SWGROUP_VI	25
+
+#define TEGRA124_MC_RESET_AFI		0
+#define TEGRA124_MC_RESET_AVPC		1
+#define TEGRA124_MC_RESET_DC		2
+#define TEGRA124_MC_RESET_DCB		3
+#define TEGRA124_MC_RESET_HC		4
+#define TEGRA124_MC_RESET_HDA		5
+#define TEGRA124_MC_RESET_ISP2		6
+#define TEGRA124_MC_RESET_MPCORE	7
+#define TEGRA124_MC_RESET_MPCORELP	8
+#define TEGRA124_MC_RESET_MSENC		9
+#define TEGRA124_MC_RESET_PPCS		10
+#define TEGRA124_MC_RESET_SATA		11
+#define TEGRA124_MC_RESET_VDE		12
+#define TEGRA124_MC_RESET_VI		13
+#define TEGRA124_MC_RESET_VIC		14
+#define TEGRA124_MC_RESET_XUSB_HOST	15
+#define TEGRA124_MC_RESET_XUSB_DEV	16
+#define TEGRA124_MC_RESET_TSEC		17
+#define TEGRA124_MC_RESET_SDMMC1	18
+#define TEGRA124_MC_RESET_SDMMC2	19
+#define TEGRA124_MC_RESET_SDMMC3	20
+#define TEGRA124_MC_RESET_SDMMC4	21
+#define TEGRA124_MC_RESET_ISP2B		22
+#define TEGRA124_MC_RESET_GPU		23
+
+#endif

include/dt-bindings/memory/tegra186-mc.h

@@ -0,0 +1,111 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA186_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA186_MC_H
+
+/* special clients */
+#define TEGRA186_SID_INVALID		0x00
+#define TEGRA186_SID_PASSTHROUGH	0x7f
+
+/* host1x clients */
+#define TEGRA186_SID_HOST1X		0x01
+#define TEGRA186_SID_CSI		0x02
+#define TEGRA186_SID_VIC		0x03
+#define TEGRA186_SID_VI			0x04
+#define TEGRA186_SID_ISP		0x05
+#define TEGRA186_SID_NVDEC		0x06
+#define TEGRA186_SID_NVENC		0x07
+#define TEGRA186_SID_NVJPG		0x08
+#define TEGRA186_SID_NVDISPLAY		0x09
+#define TEGRA186_SID_TSEC		0x0a
+#define TEGRA186_SID_TSECB		0x0b
+#define TEGRA186_SID_SE			0x0c
+#define TEGRA186_SID_SE1		0x0d
+#define TEGRA186_SID_SE2		0x0e
+#define TEGRA186_SID_SE3		0x0f
+
+/* GPU clients */
+#define TEGRA186_SID_GPU		0x10
+
+/* other SoC clients */
+#define TEGRA186_SID_AFI		0x11
+#define TEGRA186_SID_HDA		0x12
+#define TEGRA186_SID_ETR		0x13
+#define TEGRA186_SID_EQOS		0x14
+#define TEGRA186_SID_UFSHC		0x15
+#define TEGRA186_SID_AON		0x16
+#define TEGRA186_SID_SDMMC4		0x17
+#define TEGRA186_SID_SDMMC3		0x18
+#define TEGRA186_SID_SDMMC2		0x19
+#define TEGRA186_SID_SDMMC1		0x1a
+#define TEGRA186_SID_XUSB_HOST		0x1b
+#define TEGRA186_SID_XUSB_DEV		0x1c
+#define TEGRA186_SID_SATA		0x1d
+#define TEGRA186_SID_APE		0x1e
+#define TEGRA186_SID_SCE		0x1f
+
+/* GPC DMA clients */
+#define TEGRA186_SID_GPCDMA_0		0x20
+#define TEGRA186_SID_GPCDMA_1		0x21
+#define TEGRA186_SID_GPCDMA_2		0x22
+#define TEGRA186_SID_GPCDMA_3		0x23
+#define TEGRA186_SID_GPCDMA_4		0x24
+#define TEGRA186_SID_GPCDMA_5		0x25
+#define TEGRA186_SID_GPCDMA_6		0x26
+#define TEGRA186_SID_GPCDMA_7		0x27
+
+/* APE DMA clients */
+#define TEGRA186_SID_APE_1		0x28
+#define TEGRA186_SID_APE_2		0x29
+
+/* camera RTCPU */
+#define TEGRA186_SID_RCE		0x2a
+
+/* camera RTCPU on host1x address space */
+#define TEGRA186_SID_RCE_1X		0x2b
+
+/* APE DMA clients */
+#define TEGRA186_SID_APE_3		0x2c
+
+/* camera RTCPU running on APE */
+#define TEGRA186_SID_APE_CAM		0x2d
+#define TEGRA186_SID_APE_CAM_1X		0x2e
+
+/*
+ * The BPMP has its SID value hardcoded in the firmware. Changing it requires
+ * considerable effort.
+ */
+#define TEGRA186_SID_BPMP		0x32
+
+/* for SMMU tests */
+#define TEGRA186_SID_SMMU_TEST		0x33
+
+/* host1x virtualization channels */
+#define TEGRA186_SID_HOST1X_CTX0	0x38
+#define TEGRA186_SID_HOST1X_CTX1	0x39
+#define TEGRA186_SID_HOST1X_CTX2	0x3a
+#define TEGRA186_SID_HOST1X_CTX3	0x3b
+#define TEGRA186_SID_HOST1X_CTX4	0x3c
+#define TEGRA186_SID_HOST1X_CTX5	0x3d
+#define TEGRA186_SID_HOST1X_CTX6	0x3e
+#define TEGRA186_SID_HOST1X_CTX7	0x3f
+
+/* host1x command buffers */
+#define TEGRA186_SID_HOST1X_VM0		0x40
+#define TEGRA186_SID_HOST1X_VM1		0x41
+#define TEGRA186_SID_HOST1X_VM2		0x42
+#define TEGRA186_SID_HOST1X_VM3		0x43
+#define TEGRA186_SID_HOST1X_VM4		0x44
+#define TEGRA186_SID_HOST1X_VM5		0x45
+#define TEGRA186_SID_HOST1X_VM6		0x46
+#define TEGRA186_SID_HOST1X_VM7		0x47
+
+/* SE data buffers */
+#define TEGRA186_SID_SE_VM0		0x48
+#define TEGRA186_SID_SE_VM1		0x49
+#define TEGRA186_SID_SE_VM2		0x4a
+#define TEGRA186_SID_SE_VM3		0x4b
+#define TEGRA186_SID_SE_VM4		0x4c
+#define TEGRA186_SID_SE_VM5		0x4d
+#define TEGRA186_SID_SE_VM6		0x4e
+#define TEGRA186_SID_SE_VM7		0x4f
+
+#endif

include/dt-bindings/memory/tegra20-mc.h

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA20_MC_H
+
+#define TEGRA20_MC_RESET_AVPC		0
+#define TEGRA20_MC_RESET_DC		1
+#define TEGRA20_MC_RESET_DCB		2
+#define TEGRA20_MC_RESET_EPP		3
+#define TEGRA20_MC_RESET_2D		4
+#define TEGRA20_MC_RESET_HC		5
+#define TEGRA20_MC_RESET_ISP		6
+#define TEGRA20_MC_RESET_MPCORE		7
+#define TEGRA20_MC_RESET_MPEA		8
+#define TEGRA20_MC_RESET_MPEB		9
+#define TEGRA20_MC_RESET_MPEC		10
+#define TEGRA20_MC_RESET_3D		11
+#define TEGRA20_MC_RESET_PPCS		12
+#define TEGRA20_MC_RESET_VDE		13
+#define TEGRA20_MC_RESET_VI		14
+
+#endif

include/dt-bindings/memory/tegra210-mc.h

@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_AFI	3
+#define TEGRA_SWGROUP_AVPC	4
+#define TEGRA_SWGROUP_HDA	5
+#define TEGRA_SWGROUP_HC	6
+#define TEGRA_SWGROUP_NVENC	7
+#define TEGRA_SWGROUP_PPCS	8
+#define TEGRA_SWGROUP_SATA	9
+#define TEGRA_SWGROUP_MPCORE	10
+#define TEGRA_SWGROUP_ISP2	11
+#define TEGRA_SWGROUP_XUSB_HOST	12
+#define TEGRA_SWGROUP_XUSB_DEV	13
+#define TEGRA_SWGROUP_ISP2B	14
+#define TEGRA_SWGROUP_TSEC	15
+#define TEGRA_SWGROUP_A9AVP	16
+#define TEGRA_SWGROUP_GPU	17
+#define TEGRA_SWGROUP_SDMMC1A	18
+#define TEGRA_SWGROUP_SDMMC2A	19
+#define TEGRA_SWGROUP_SDMMC3A	20
+#define TEGRA_SWGROUP_SDMMC4A	21
+#define TEGRA_SWGROUP_VIC	22
+#define TEGRA_SWGROUP_VI	23
+#define TEGRA_SWGROUP_NVDEC	24
+#define TEGRA_SWGROUP_APE	25
+#define TEGRA_SWGROUP_NVJPG	26
+#define TEGRA_SWGROUP_SE	27
+#define TEGRA_SWGROUP_AXIAP	28
+#define TEGRA_SWGROUP_ETR	29
+#define TEGRA_SWGROUP_TSECB	30
+
+#define TEGRA210_MC_RESET_AFI		0
+#define TEGRA210_MC_RESET_AVPC		1
+#define TEGRA210_MC_RESET_DC		2
+#define TEGRA210_MC_RESET_DCB		3
+#define TEGRA210_MC_RESET_HC		4
+#define TEGRA210_MC_RESET_HDA		5
+#define TEGRA210_MC_RESET_ISP2		6
+#define TEGRA210_MC_RESET_MPCORE	7
+#define TEGRA210_MC_RESET_NVENC		8
+#define TEGRA210_MC_RESET_PPCS		9
+#define TEGRA210_MC_RESET_SATA		10
+#define TEGRA210_MC_RESET_VI		11
+#define TEGRA210_MC_RESET_VIC		12
+#define TEGRA210_MC_RESET_XUSB_HOST	13
+#define TEGRA210_MC_RESET_XUSB_DEV	14
+#define TEGRA210_MC_RESET_A9AVP		15
+#define TEGRA210_MC_RESET_TSEC		16
+#define TEGRA210_MC_RESET_SDMMC1	17
+#define TEGRA210_MC_RESET_SDMMC2	18
+#define TEGRA210_MC_RESET_SDMMC3	19
+#define TEGRA210_MC_RESET_SDMMC4	20
+#define TEGRA210_MC_RESET_ISP2B		21
+#define TEGRA210_MC_RESET_GPU		22
+#define TEGRA210_MC_RESET_NVDEC		23
+#define TEGRA210_MC_RESET_APE		24
+#define TEGRA210_MC_RESET_SE		25
+#define TEGRA210_MC_RESET_NVJPG		26
+#define TEGRA210_MC_RESET_AXIAP		27
+#define TEGRA210_MC_RESET_ETR		28
+#define TEGRA210_MC_RESET_TSECB		29
+
+#endif

include/dt-bindings/memory/tegra30-mc.h

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA30_MC_H
+
+#define TEGRA_SWGROUP_PTC	0
+#define TEGRA_SWGROUP_DC	1
+#define TEGRA_SWGROUP_DCB	2
+#define TEGRA_SWGROUP_EPP	3
+#define TEGRA_SWGROUP_G2	4
+#define TEGRA_SWGROUP_MPE	5
+#define TEGRA_SWGROUP_VI	6
+#define TEGRA_SWGROUP_AFI	7
+#define TEGRA_SWGROUP_AVPC	8
+#define TEGRA_SWGROUP_NV	9
+#define TEGRA_SWGROUP_NV2	10
+#define TEGRA_SWGROUP_HDA	11
+#define TEGRA_SWGROUP_HC	12
+#define TEGRA_SWGROUP_PPCS	13
+#define TEGRA_SWGROUP_SATA	14
+#define TEGRA_SWGROUP_VDE	15
+#define TEGRA_SWGROUP_MPCORELP	16
+#define TEGRA_SWGROUP_MPCORE	17
+#define TEGRA_SWGROUP_ISP	18
+
+#define TEGRA30_MC_RESET_AFI		0
+#define TEGRA30_MC_RESET_AVPC		1
+#define TEGRA30_MC_RESET_DC		2
+#define TEGRA30_MC_RESET_DCB		3
+#define TEGRA30_MC_RESET_EPP		4
+#define TEGRA30_MC_RESET_2D		5
+#define TEGRA30_MC_RESET_HC		6
+#define TEGRA30_MC_RESET_HDA		7
+#define TEGRA30_MC_RESET_ISP		8
+#define TEGRA30_MC_RESET_MPCORE		9
+#define TEGRA30_MC_RESET_MPCORELP	10
+#define TEGRA30_MC_RESET_MPE		11
+#define TEGRA30_MC_RESET_3D		12
+#define TEGRA30_MC_RESET_3D2		13
+#define TEGRA30_MC_RESET_PPCS		14
+#define TEGRA30_MC_RESET_SATA		15
+#define TEGRA30_MC_RESET_VDE		16
+#define TEGRA30_MC_RESET_VI		17
+
+#endif