Initial commit: Linux kernel 4.19 for Unplugged OS

2025-10-06 13:52:42 +00:00
commit d30235b04c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_INFRACFG_H
+#define __SOC_MEDIATEK_INFRACFG_H
+
+#define MT8173_TOP_AXI_PROT_EN_MCI_M2		BIT(0)
+#define MT8173_TOP_AXI_PROT_EN_MM_M0		BIT(1)
+#define MT8173_TOP_AXI_PROT_EN_MM_M1		BIT(2)
+#define MT8173_TOP_AXI_PROT_EN_MMAPB_S		BIT(6)
+#define MT8173_TOP_AXI_PROT_EN_L2C_M2		BIT(9)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI		BIT(11)
+#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD		BIT(12)
+#define MT8173_TOP_AXI_PROT_EN_CCI_M2		BIT(13)
+#define MT8173_TOP_AXI_PROT_EN_MFG_S		BIT(14)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M0		BIT(15)
+#define MT8173_TOP_AXI_PROT_EN_PERI_M1		BIT(16)
+#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS		BIT(17)
+#define MT8173_TOP_AXI_PROT_EN_CQ_DMA		BIT(18)
+#define MT8173_TOP_AXI_PROT_EN_GCPU		BIT(19)
+#define MT8173_TOP_AXI_PROT_EN_IOMMU		BIT(20)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M0		BIT(21)
+#define MT8173_TOP_AXI_PROT_EN_MFG_M1		BIT(22)
+#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT	BIT(23)
+
+#define MT2701_TOP_AXI_PROT_EN_MM_M0		BIT(1)
+#define MT2701_TOP_AXI_PROT_EN_CONN_M		BIT(2)
+#define MT2701_TOP_AXI_PROT_EN_CONN_S		BIT(8)
+
+#define MT7622_TOP_AXI_PROT_EN_ETHSYS		(BIT(3) | BIT(17))
+#define MT7622_TOP_AXI_PROT_EN_HIF0		(BIT(24) | BIT(25))
+#define MT7622_TOP_AXI_PROT_EN_HIF1		(BIT(26) | BIT(27) | \
+						 BIT(28))
+#define MT7622_TOP_AXI_PROT_EN_WB		(BIT(2) | BIT(6) | \
+						 BIT(7) | BIT(8))
+
+#define MT6779_IFR_SET				0x02A0
+#define MT6779_IFR_CLR				0x02A4
+
+#define MT6779_IFR1_SET				0x02A8
+#define MT6779_IFR1_CLR				0x02AC
+#define MT6779_IFR2_SET				0x0714
+#define MT6779_IFR2_CLR				0x0718
+#define MT6779_IFRMCU_SET			0x02C4
+#define MT6779_IFRMCU_CLR			0x02C8
+#define MT6779_IFRMM_SET			0x02D4
+#define MT6779_IFRMM_CLR			0x02D8
+
+#define MT6779_IFR_STA1				0x0228
+#define MT6779_IFR1_STA1			0x0258
+#define MT6779_IFR1_STA2			0x0724
+#define MT6779_IFRMM_STA1			0x02EC
+#define MT6779_IFRMCU_STA1			0x02E4
+
+#define MT6779_SMI_SET				0x03C4
+#define MT6779_SMI_CLR				0x03C8
+#define MT6779_SMI_STA				0x03C0
+
+#define MT6779_IFR_SI0_SET			0x3B8
+#define MT6779_IFR_SI0_CLR			0x3BC
+#define MT6779_IFR_PDN_SI2_CTL			0x234
+#define MT6779_IFR_SI0_STA			0x0
+#define MT6779_IFR_SI2_STA			0x28
+
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
+		bool reg_update);
+int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
+		bool reg_update);
+#endif /* __SOC_MEDIATEK_INFRACFG_H */
@@ -0,0 +1,432 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ */
+
+#ifndef __MTK_CMDQ_H__
+#define __MTK_CMDQ_H__
+
+#include <linux/mailbox_client.h>
+#include <linux/mailbox/mtk-cmdq-mailbox.h>
+
+#define CMDQ_SPR_FOR_TEMP		0
+#define CMDQ_THR_SPR_IDX0		0
+#define CMDQ_THR_SPR_IDX1		1
+#define CMDQ_THR_SPR_IDX2		2
+#define CMDQ_THR_SPR_IDX3		3
+#define CMDQ_THR_SPR_MAX		4
+
+#define CMDQ_TPR_ID			56
+#define CMDQ_HANDSHAKE_REG		59
+#define CMDQ_GPR_CNT_ID			32
+#define CMDQ_CPR_STRAT_ID		0x8000
+#define CMDQ_CPR_TPR_MASK		0x8000
+#define CMDQ_CPR_DISP_CNT		0x8001
+#define CMDQ_EVENT_MAX			0x3FF
+#define CMDQ_CPR_DDR_USR_CNT		0x8002
+#define CMDQ_CPR_SLP_GPR_MAX		0x8003
+
+#define CMDQ_GPR_CNT_ID			32
+#define CMDQ_CPR_STRAT_ID		0x8000
+#define SUBSYS_NO_SUPPORT		99
+
+/* GCE provide 26M timer, thus each tick 1/26M second,
+ * which is, 1 microsecond = 26 ticks
+ */
+#define CMDQ_US_TO_TICK(_t)		(_t * 26)
+#define CMDQ_TICK_TO_US(_t)		(do_div(_t, 26))
+
+extern int gce_shift_bit;
+
+
+#define CMDQ_REG_SHIFT_ADDR(addr)	((addr) >> gce_shift_bit)
+#define CMDQ_REG_REVERT_ADDR(addr)	((addr) << gce_shift_bit)
+
+/* GCE provide 32/64 bit General Purpose Register (GPR)
+ * use as data cache or address register
+ *	 32bit: R0-R15
+ *	 64bit: P0-P7
+ * Note:
+ *	R0-R15 and P0-P7 actullay share same memory
+ *	R0 use as mask in instruction, thus be care of use R1/P0.
+ */
+enum cmdq_gpr {
+	/* 32bit R0 to R15 */
+	CMDQ_GPR_R00 = 0x00,
+	CMDQ_GPR_R01 = 0x01,
+	CMDQ_GPR_R02 = 0x02,
+	CMDQ_GPR_R03 = 0x03,
+	CMDQ_GPR_R04 = 0x04,
+	CMDQ_GPR_R05 = 0x05,
+	CMDQ_GPR_R06 = 0x06,
+	CMDQ_GPR_R07 = 0x07,
+	CMDQ_GPR_R08 = 0x08,
+	CMDQ_GPR_R09 = 0x09,
+	CMDQ_GPR_R10 = 0x0A,
+	CMDQ_GPR_R11 = 0x0B,
+	CMDQ_GPR_R12 = 0x0C,
+	CMDQ_GPR_R13 = 0x0D,
+	CMDQ_GPR_R14 = 0x0E,
+	CMDQ_GPR_R15 = 0x0F,
+
+	/* 64bit P0 to P7 */
+	CMDQ_GPR_P0 = 0x10,
+	CMDQ_GPR_P1 = 0x11,
+	CMDQ_GPR_P2 = 0x12,
+	CMDQ_GPR_P3 = 0x13,
+	CMDQ_GPR_P4 = 0x14,
+	CMDQ_GPR_P5 = 0x15,
+	CMDQ_GPR_P6 = 0x16,
+	CMDQ_GPR_P7 = 0x17,
+};
+
+/* Define GCE tokens which not change by platform */
+enum gce_event {
+	/* GCE handshake event 768~783 */
+	CMDQ_EVENT_HANDSHAKE = 768,
+
+	CMDQ_TOKEN_SECURE_THR_EOF = 647,
+	CMDQ_TOKEN_TPR_LOCK = 652,
+
+	/* GPR timer token, 994 to 1009 (for gpr r0 to r15) */
+	CMDQ_EVENT_GPR_TIMER = 994,
+};
+
+struct cmdq_pkt;
+
+struct cmdq_subsys {
+	u32 base;
+	u8 id;
+};
+
+struct cmdq_base {
+	struct cmdq_subsys subsys[32];
+	u8 count;
+	u16 cpr_base;
+	u8 cpr_cnt;
+};
+
+struct cmdq_client {
+	struct mbox_client client;
+	struct mbox_chan *chan;
+	void *cl_priv;
+	struct mutex chan_mutex;
+};
+
+struct cmdq_operand {
+	/* register type */
+	bool reg;
+	union {
+		/* index */
+		u16 idx;
+		/* value */
+		u16 value;
+	};
+};
+
+enum CMDQ_LOGIC_ENUM {
+	CMDQ_LOGIC_ASSIGN = 0,
+	CMDQ_LOGIC_ADD = 1,
+	CMDQ_LOGIC_SUBTRACT = 2,
+	CMDQ_LOGIC_MULTIPLY = 3,
+	CMDQ_LOGIC_XOR = 8,
+	CMDQ_LOGIC_NOT = 9,
+	CMDQ_LOGIC_OR = 10,
+	CMDQ_LOGIC_AND = 11,
+	CMDQ_LOGIC_LEFT_SHIFT = 12,
+	CMDQ_LOGIC_RIGHT_SHIFT = 13
+};
+
+enum CMDQ_CONDITION_ENUM {
+	CMDQ_CONDITION_ERROR = -1,
+
+	/* these are actual HW op code */
+	CMDQ_EQUAL = 0,
+	CMDQ_NOT_EQUAL = 1,
+	CMDQ_GREATER_THAN_AND_EQUAL = 2,
+	CMDQ_LESS_THAN_AND_EQUAL = 3,
+	CMDQ_GREATER_THAN = 4,
+	CMDQ_LESS_THAN = 5,
+
+	CMDQ_CONDITION_MAX,
+};
+
+struct cmdq_flush_completion {
+	struct cmdq_pkt *pkt;
+	struct completion cmplt;
+	s32 err;
+};
+
+u32 cmdq_subsys_id_to_base(struct cmdq_base *cmdq_base, int id);
+
+/**
+ * cmdq_pkt_realloc_cmd_buffer() - reallocate command buffer for CMDQ packet
+ * @pkt:	the CMDQ packet
+ * @size:	the request size
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_realloc_cmd_buffer(struct cmdq_pkt *pkt, size_t size);
+
+/**
+ * cmdq_register_device() - register device which needs CMDQ
+ * @dev:	device for CMDQ to access its registers
+ *
+ * Return: cmdq_base pointer or NULL for failed
+ */
+struct cmdq_base *cmdq_register_device(struct device *dev);
+
+/**
+ * cmdq_mbox_create() - create CMDQ mailbox client and channel
+ * @dev:	device of CMDQ mailbox client
+ * @index:	index of CMDQ mailbox channel
+ *
+ * Return: CMDQ mailbox client pointer
+ */
+struct cmdq_client *cmdq_mbox_create(struct device *dev, int index);
+void cmdq_mbox_stop(struct cmdq_client *cl);
+
+void cmdq_mbox_pool_set_limit(struct cmdq_client *cl, u32 limit);
+void cmdq_mbox_pool_create(struct cmdq_client *cl);
+void cmdq_mbox_pool_clear(struct cmdq_client *cl);
+
+void *cmdq_mbox_buf_alloc(struct device *dev, dma_addr_t *pa_out);
+void cmdq_mbox_buf_free(struct device *dev, void *va, dma_addr_t pa);
+
+s32 cmdq_dev_get_event(struct device *dev, const char *name);
+
+struct cmdq_pkt_buffer *cmdq_pkt_alloc_buf(struct cmdq_pkt *pkt);
+
+void cmdq_pkt_free_buf(struct cmdq_pkt *pkt);
+
+s32 cmdq_pkt_add_cmd_buffer(struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_mbox_destroy() - destroy CMDQ mailbox client and channel
+ * @client:	the CMDQ mailbox client
+ */
+void cmdq_mbox_destroy(struct cmdq_client *client);
+
+/**
+ * cmdq_pkt_create() - create a CMDQ packet
+ * @client:	the CMDQ mailbox client
+ *
+ * Return: CMDQ packet pointer
+ */
+struct cmdq_pkt *cmdq_pkt_create(struct cmdq_client *client);
+
+/**
+ * cmdq_pkt_destroy() - destroy the CMDQ packet
+ * @pkt:	the CMDQ packet
+ */
+void cmdq_pkt_destroy(struct cmdq_pkt *pkt);
+
+u64 *cmdq_pkt_get_va_by_offset(struct cmdq_pkt *pkt, size_t offset);
+
+dma_addr_t cmdq_pkt_get_pa_by_offset(struct cmdq_pkt *pkt, u32 offset);
+
+dma_addr_t cmdq_pkt_get_curr_buf_pa(struct cmdq_pkt *pkt);
+
+void *cmdq_pkt_get_curr_buf_va(struct cmdq_pkt *pkt);
+
+s32 cmdq_pkt_append_command(struct cmdq_pkt *pkt, u16 arg_c, u16 arg_b,
+	u16 arg_a, u8 s_op, u8 arg_c_type, u8 arg_b_type, u8 arg_a_type,
+	enum cmdq_code code);
+
+s32 cmdq_pkt_move(struct cmdq_pkt *pkt, u16 reg_idx, u64 value);
+
+s32 cmdq_pkt_read(struct cmdq_pkt *pkt, struct cmdq_base *clt_base,
+	dma_addr_t src_addr, u16 dst_reg_idx);
+
+s32 cmdq_pkt_read_reg(struct cmdq_pkt *pkt, u8 subsys, u16 offset,
+	u16 dst_reg_idx);
+
+s32 cmdq_pkt_read_addr(struct cmdq_pkt *pkt, dma_addr_t addr, u16 dst_reg_idx);
+
+s32 cmdq_pkt_write_reg(struct cmdq_pkt *pkt, u8 subsys,
+	u16 offset, u16 src_reg_idx, u32 mask);
+
+s32 cmdq_pkt_write_value(struct cmdq_pkt *pkt, u8 subsys,
+	u16 offset, u32 value, u32 mask);
+
+s32 cmdq_pkt_write_reg_addr(struct cmdq_pkt *pkt, dma_addr_t addr,
+	u16 src_reg_idx, u32 mask);
+
+s32 cmdq_pkt_write_value_addr(struct cmdq_pkt *pkt, dma_addr_t addr,
+	u32 value, u32 mask);
+
+s32 cmdq_pkt_store_value(struct cmdq_pkt *pkt, u16 indirect_dst_reg_idx,
+	u16 dst_addr_low, u32 value, u32 mask);
+
+s32 cmdq_pkt_store_value_reg(struct cmdq_pkt *pkt, u16 indirect_dst_reg_idx,
+	u16 dst_addr_low, u16 indirect_src_reg_idx, u32 mask);
+
+s32 cmdq_pkt_store64_value_reg(struct cmdq_pkt *pkt,
+	u16 indirect_dst_reg_idx, u16 indirect_src_reg_idx);
+
+s32 cmdq_pkt_write_indriect(struct cmdq_pkt *pkt, struct cmdq_base *clt_base,
+	dma_addr_t addr, u16 src_reg_idx, u32 mask);
+
+/**
+ * cmdq_pkt_write() - append write command to the CMDQ packet
+ * @pkt:	the CMDQ packet
+ * @value:	the specified target register value
+ * @clt_base:	the CMDQ base
+ * @addr:	target register address
+ * @mask:	the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+s32 cmdq_pkt_write(struct cmdq_pkt *pkt, struct cmdq_base *clt_base,
+	dma_addr_t addr, u32 value, u32 mask);
+
+s32 cmdq_pkt_mem_move(struct cmdq_pkt *pkt, struct cmdq_base *clt_base,
+	dma_addr_t src_addr, dma_addr_t dst_addr, u16 swap_reg_idx);
+
+s32 cmdq_pkt_assign_command(struct cmdq_pkt *pkt, u16 reg_idx, u32 value);
+
+s32 cmdq_pkt_logic_command(struct cmdq_pkt *pkt, enum CMDQ_LOGIC_ENUM s_op,
+	u16 result_reg_idx,
+	struct cmdq_operand *left_operand,
+	struct cmdq_operand *right_operand);
+
+s32 cmdq_pkt_jump(struct cmdq_pkt *pkt, s32 offset);
+
+s32 cmdq_pkt_jump_addr(struct cmdq_pkt *pkt, dma_addr_t addr);
+
+s32 cmdq_pkt_cond_jump_abs(struct cmdq_pkt *pkt,
+	u16 addr_reg_idx,
+	struct cmdq_operand *left_operand,
+	struct cmdq_operand *right_operand,
+	enum CMDQ_CONDITION_ENUM condition_operator);
+
+s32 cmdq_pkt_poll_addr(struct cmdq_pkt *pkt, u32 value, u32 addr, u32 mask,
+	u8 reg_gpr);
+
+s32 cmdq_pkt_poll_reg(struct cmdq_pkt *pkt, u32 value, u8 subsys,
+	u16 offset, u32 mask);
+
+/**
+ * cmdq_pkt_poll() - append polling command with mask to the CMDQ packet
+ * @pkt:	the CMDQ packet
+ * @value:	the specified target register value
+ * @subsys:	the CMDQ subsys id
+ * @offset:	register offset from module base
+ * @mask:	the specified target register mask
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+s32 cmdq_pkt_poll(struct cmdq_pkt *pkt, struct cmdq_base *clt_base,
+	u32 value, u32 addr, u32 mask, u8 reg_gpr);
+
+int cmdq_pkt_timer_en(struct cmdq_pkt *pkt);
+
+/* cmdq_pkt_sleep() - append commands to wait a short time in microsecond
+ * @pkt:	the CMDQ packet
+ * @tick:	sleep time in tick, use CMDQ_MS_TO_TICK to translate into ms
+ * @reg_gpr:	GPR use to counting
+ *
+ * Return 0 for success; else the error code is returned
+ */
+s32 cmdq_pkt_sleep(struct cmdq_pkt *pkt, u32 tick, u16 reg_gpr);
+
+s32 cmdq_pkt_poll_timeout(struct cmdq_pkt *pkt, u32 value, u8 subsys,
+	phys_addr_t addr, u32 mask, u16 count, u16 reg_gpr);
+
+void cmdq_pkt_perf_end(struct cmdq_pkt *pkt);
+void cmdq_pkt_perf_begin(struct cmdq_pkt *pkt);
+u32 *cmdq_pkt_get_perf_ret(struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_wfe() - append wait for event command to the CMDQ packet
+ * @pkt:	the CMDQ packet
+ * @event:	the desired event type to "wait and CLEAR"
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event);
+
+int cmdq_pkt_wait_no_clear(struct cmdq_pkt *pkt, u16 event);
+
+int cmdq_pkt_acquire_event(struct cmdq_pkt *pkt, u16 event);
+
+/**
+ * cmdq_pkt_clear_event() - append clear event command to the CMDQ packet
+ * @pkt:	the CMDQ packet
+ * @event:	the desired event to be cleared
+ *
+ * Return: 0 for success; else the error code is returned
+ */
+s32 cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event);
+
+s32 cmdq_pkt_set_event(struct cmdq_pkt *pkt, u16 event);
+
+s32 cmdq_pkt_handshake_event(struct cmdq_pkt *pkt, u16 event);
+
+s32 cmdq_pkt_finalize(struct cmdq_pkt *pkt);
+
+s32 cmdq_pkt_finalize_loop(struct cmdq_pkt *pkt);
+
+/**
+ * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ
+ *                          packet and call back at the end of done packet
+ * @client:	the CMDQ mailbox client
+ * @pkt:	the CMDQ packet
+ * @cb:		called at the end of done packet
+ * @data:	this data will pass back to cb
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to asynchronously execute the CMDQ packet and call back
+ * at the end of done packet. Note that this is an ASYNC function. When the
+ * function returned, it may or may not be finished.
+ */
+s32 cmdq_pkt_flush_async(struct cmdq_pkt *pkt,
+	cmdq_async_flush_cb cb, void *data);
+
+int cmdq_pkt_wait_complete(struct cmdq_pkt *pkt);
+
+s32 cmdq_pkt_flush_threaded(struct cmdq_pkt *pkt,
+	cmdq_async_flush_cb cb, void *data);
+
+/**
+ * cmdq_pkt_flush() - trigger CMDQ to execute the CMDQ packet
+ * @pkt:	the CMDQ packet
+ *
+ * Return: 0 for success; else the error code is returned
+ *
+ * Trigger CMDQ to execute the CMDQ packet. Note that this is a
+ * synchronous flush function. When the function returned, the recorded
+ * commands have been done.
+ */
+s32 cmdq_pkt_flush(struct cmdq_pkt *pkt);
+
+void cmdq_buf_print_wfe(char *text, u32 txt_sz,
+	u32 offset, void *inst);
+
+void cmdq_buf_cmd_parse(u64 *buf, u32 cmd_nr, dma_addr_t buf_pa,
+	dma_addr_t cur_pa, const char *info, void *chan);
+
+s32 cmdq_pkt_dump_buf(struct cmdq_pkt *pkt, dma_addr_t curr_pa);
+
+int cmdq_dump_pkt(struct cmdq_pkt *pkt, dma_addr_t pc, bool dump_inst);
+
+void cmdq_pkt_set_err_cb(struct cmdq_pkt *pkt,
+	cmdq_async_flush_cb cb, void *data);
+
+struct cmdq_thread_task_info {
+	dma_addr_t		pa_base;
+	struct cmdq_pkt		*pkt;
+	struct list_head	list_entry;
+};
+
+struct cmdq_timeout_info {
+	u32 irq;
+	u32 irq_en;
+	dma_addr_t curr_pc;
+	u32 *curr_pc_va;
+	dma_addr_t end_addr;
+	u32 task_num;
+	struct cmdq_thread_task_info *timeout_task;
+	struct list_head task_list;
+};
+#endif	/* __MTK_CMDQ_H__ */
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+
+#ifndef __MTK_LPM_H__
+#define __MTK_LPM_H__
+
+#include <linux/cpu_pm.h>
+#include <linux/cpuidle.h>
+#include <asm/cpuidle.h>
+
+
+#define MTK_CPUIDLE_PM_NAME	"mtk_cpuidle_pm"
+
+struct mtk_cpuidle_op {
+	/*prompt to platform driver that cpu will enter idle state */
+	int (*cpuidle_prepare)(struct cpuidle_driver *drv, int index);
+
+	/*notify platform driver that cpu will leave idle state */
+	void (*cpuidle_resume)(struct cpuidle_driver *drv, int index);
+};
+
+int mtk_lpm_drv_cpuidle_ops_set(struct mtk_cpuidle_op *op);
+#endif
@@ -0,0 +1,318 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_MBOX_H__
+#define __MTK_MBOX_H__
+
+#include <linux/platform_device.h>
+#include <linux/completion.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+
+/*
+ * mbox slot size definition
+ * 1 slot for 4 bytes
+ */
+#define MBOX_SLOT_SIZE 4
+
+struct mtk_mbox_pin_send;
+struct mtk_mbox_pin_recv;
+
+typedef int (*mbox_rx_cb_t)(void *);
+typedef int (*mbox_pin_cb_t)(unsigned int ipi_id, void *prdata, void *data,
+	unsigned int len);
+typedef void (*mbox_ipi_cb_t)(struct mtk_mbox_pin_recv *, void *);
+
+/*
+ * mbox receive information
+ *
+ * poll_count  :mbox polling success count
+ * recv_irq_count :mbox receive irq count
+ * notify_count   :mbox irq notify count
+ * cb_count :mbox execute callback function count
+ * pre_timestamp  :time stamp before callback function
+ * post_timestamp :time stamp after callback function
+ */
+struct mtk_mbox_recv_record {
+	uint32_t poll_count;
+	uint32_t recv_irq_count;
+	uint32_t notify_count;
+	uint32_t cb_count;
+	uint64_t pre_timestamp;
+	uint64_t post_timestamp;
+};
+
+/*
+ * mbox send information
+ *
+ */
+struct mtk_mbox_send_record {
+};
+
+/*
+ * mbox record information
+ *
+ * write_count    :mbox write success count
+ * busy_count     :mbox read success count
+ * trig_irq_count :mbox trigger irq success count
+ */
+struct mtk_mbox_record {
+	uint32_t write_count;
+	uint32_t busy_count;
+	uint32_t trig_irq_count;
+};
+
+/*
+ * mbox pin structure, this is for send definition,
+ * ipi=endpoint=pin
+ * mbox     : (mbox number)mbox number of the pin, up to 16(plt)
+ * offset   : (slot)msg offset in share memory, up to 1024*4 KB(plt)
+ * send_opt : (opt)send opt, 0:send ,1: send for response(plt)
+ * lock     : (lock)polling lock 0:unuse,1:used
+ * msg_size : (slot)message size in words, 4 bytes alignment(plt)
+ * pin_index  : (bit offset)pin index in the mbox(plt)
+ * chan_id    : (u32) ipc channel id(plt)
+ * mutex      : (mutex)mutex for remote response
+ * completion : (completion)completion for remote response
+ * pin_lock   : (spinlock_t)lock of the pin
+ * send_record: send pin record information
+ */
+struct mtk_mbox_pin_send {
+	unsigned int mbox     : 4,
+				 offset   : 20,
+				 send_opt : 2,
+				 lock    : 2;
+	unsigned int msg_size;
+	unsigned int pin_index;
+	unsigned int chan_id;
+	struct mutex mutex_send;
+	struct completion comp_ack;  // to remove
+	spinlock_t pin_lock;
+	struct mtk_mbox_send_record send_record;
+};
+
+/*
+ * mbox pin structure, this is for receive definition,
+ * ipi=endpoint=pin
+ * mbox     : (mbox number)mbox number of the pin, up to 16(plt)
+ * offset   : (slot)msg offset in share memory, up to 1024*4 KB(plt)
+ * recv_opt : (opt)recv option,  0:receive ,1: response(plt)
+ * lock     : (lock)polling lock 0:unuse,1:used
+ * buf_full_opt : (opt)buffer option 0:drop, 1:assert, 2:overwrite(plt)
+ * cb_ctx_opt : (opt)callback option 0:isr context, 1:process context(plt)
+ * msg_size   : (slot)msg used slots in the mbox, 4 bytes alignment(plt)
+ * pin_index  : (bit offset)pin index in the mbox(plt)
+ * chan_id : (u32) ipc channel id(plt)
+ * notify     : (completion)notify process
+ * mbox_pin_cb: (cb)cb function
+ * pin_buf : (void*)buffer point
+ * prdata  : (void*)private data
+ * pin_lock: (spinlock_t)lock of the pin
+ * recv_record: receive pin record information
+ */
+struct mtk_mbox_pin_recv {
+	unsigned int mbox     : 4,
+				 offset   : 20,
+				 recv_opt     : 2,
+				 lock         : 2,
+				 buf_full_opt : 2,
+				 cb_ctx_opt   : 2;
+	unsigned int msg_size;
+	unsigned int pin_index;
+	unsigned int chan_id;
+	struct completion notify;
+	mbox_pin_cb_t mbox_pin_cb;
+	void *pin_buf;
+	void *prdata;
+	spinlock_t pin_lock;
+	struct mtk_mbox_recv_record recv_record;
+};
+
+
+/*
+ * mtk mbox device,Mbox is a dedicate hardware of a tinysys consists of:
+ * 1) a share memory tightly coupled to the tinysys
+ * 2) several IRQs
+ *
+ * @ipi_cb: the callback handler for synchronization layer
+ * @ipi_priv: private data for synchronization layer
+ * @pre_cb: the callback handler in the begin of mbox receiving ipi
+ * @post_cb: the callback handler in the end of mbox receiving ipi
+ * @prdata: private data for the callback use
+ */
+struct mtk_mbox_device {
+	/* Identity of the device */
+	const char *name;
+	unsigned int id;
+	/* Following are platform specific interface*/
+	struct mtk_mbox_pin_recv *pin_recv_table;
+	struct mtk_mbox_pin_send *pin_send_table;
+	struct mtk_mbox_info *info_table;
+	unsigned int count;
+	unsigned int recv_count;
+	unsigned int send_count;
+	void (*memcpy_to_tiny)(void __iomem *dest, const void *src, int size);
+	void (*memcpy_from_tiny)(void *dest, const void __iomem *src, int size);
+	mbox_ipi_cb_t ipi_cb;
+	void *ipi_priv;
+	mbox_rx_cb_t pre_cb;
+	mbox_rx_cb_t post_cb;
+	void *prdata;
+	bool log_enable;
+};
+
+/*
+ * mbox callback function context definition
+ * 0: isr context, 1:process context
+ */
+enum MBOX_PIN_CTX {
+	MBOX_CB_IN_ISR   = 0,
+	MBOX_CB_IN_PROCESS  = 1,
+};
+
+/*
+ * mbox buffer full action definition
+ * 0:drop, 1:assert, 2:overwrite
+ */
+enum MBOX_BUF_OPT {
+	MBOX_BUF_FULL_DROP       = 0,
+	MBOX_BUF_FULL_ASSERT     = 1,
+	MBOX_BUF_FULL_OVERWRITE  = 2,
+	MBOX_BUF_COPY_DONE       = 3,
+	MBOX_BUF_FULL_RET        = 4,
+};
+
+/*
+ * mbox recv action definition
+ * 0:receive message, 1:receive ack
+ */
+enum MBOX_RECV_OPT {
+	MBOX_RECV_MESSAGE  = 0,
+	MBOX_RECV_ACK      = 1,
+};
+
+/*
+ * mbox information
+ *
+ * mbdev  :mbox device
+ * irq_num:identity of mbox irq
+ * id     :mbox id
+ * slot   :how many slots that mbox used
+ * opt    :option for tx mode, 0:mbox, 1:share memory 2:queue
+ * enable :mbox status, 0:disable, 1: enable
+ * is64d  :mbox is64d status, 0:32d, 1: 64d
+ * base   :mbox base address
+ * set_irq_reg  :mbox set irq register
+ * clr_irq_reg  :mbox clear irq register
+ * init_base_reg:mbox initialize register
+ * mbox lock    :lock of mbox
+ * record       :mbox record information
+ */
+struct mtk_mbox_info {
+	struct mtk_mbox_device *mbdev;
+	int irq_num;
+	unsigned int id;
+	unsigned int slot;
+	unsigned int opt;
+	bool enable;
+	bool is64d;
+	void __iomem *base;
+	void __iomem *set_irq_reg;
+	void __iomem *clr_irq_reg;
+	void __iomem *init_base_reg;
+	void __iomem *send_status_reg;
+	void __iomem *recv_status_reg;
+	spinlock_t mbox_lock;
+	struct mtk_mbox_record record;
+};
+
+/*
+ * mbox return value definition
+ */
+enum MBOX_RETURN {
+	MBOX_POST_CB_ERR  = -8,
+	MBOX_PRE_CB_ERR   = -7,
+	MBOX_READ_SZ_ERR  = -6,
+	MBOX_WRITE_SZ_ERR = -5,
+	MBOX_PARA_ERR     = -4,
+	MBOX_CONFIG_ERR   = -3,
+	MBOX_IRQ_ERR      = -2,
+	MBOX_PLT_ERR      = -1,
+	MBOX_DONE         = 0,
+	MBOX_PIN_BUSY     = 1,
+};
+
+/*
+ * mbox message options
+ * 0: mbox
+ * 1: share memory
+ * 2: mbox with queue
+ * 3: share memory with queue
+ */
+enum {
+	MBOX_OPT_DIRECT = 0,
+	MBOX_OPT_SMEM   = 1,
+	MBOX_OPT_QUEUE_DIR  = 2,
+	MBOX_OPT_QUEUE_SMEM  = 3,
+};
+
+/*
+ * mtk ipi message header
+ *
+ * id       :message id
+ * len      :data length in byte
+ * options  :options
+ * reserved :reserved
+ */
+struct mtk_ipi_msg_hd {
+	uint32_t id;
+	uint32_t len;
+	uint32_t options;
+	uint32_t reserved;
+};
+
+struct mtk_ipi_msg {
+	struct mtk_ipi_msg_hd ipihd;
+	void *data;
+};
+
+int mtk_mbox_write_hd(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int slot, void *msg);
+int mtk_mbox_read_hd(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int slot, void *dest);
+int mtk_mbox_write(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int slot, void *data, unsigned int len);
+int mtk_mbox_read(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int slot, void *data, unsigned int len);
+int mtk_mbox_clr_irq(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int irq);
+int mtk_mbox_trigger_irq(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int irq);
+unsigned int mtk_mbox_read_recv_irq(struct mtk_mbox_device *mbdev,
+		unsigned int mbox);
+int mtk_mbox_set_base_addr(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		unsigned int addr);
+unsigned int mtk_mbox_check_send_irq(struct mtk_mbox_device *mbdev,
+		unsigned int mbox, unsigned int pin_index);
+int mtk_mbox_probe(struct platform_device *pdev, struct mtk_mbox_device *mbdev,
+		unsigned int mbox);
+int mtk_mbox_cb_register(struct mtk_mbox_device *mbdev, unsigned int pin_offset,
+		mbox_pin_cb_t mbox_pin_cb, void *prdata);
+int mtk_mbox_polling(struct mtk_mbox_device *mbdev, unsigned int mbox,
+		void *data, struct mtk_mbox_pin_recv *pin_recv);
+int mtk_smem_init(struct platform_device *pdev, struct mtk_mbox_device *mbdev,
+		unsigned int mbox, void __iomem *base,
+		void __iomem *set_irq_reg, void __iomem *clr_irq_reg,
+		void __iomem *send_status_reg, void __iomem *recv_status_reg);
+void mtk_mbox_dump_all(struct mtk_mbox_device *mbdev);
+void mtk_mbox_dump_recv(struct mtk_mbox_device *mbdev, unsigned int pin);
+void mtk_mbox_dump_recv_pin(struct mtk_mbox_device *mbdev,
+	struct mtk_mbox_pin_recv *pin_recv);
+void mtk_mbox_dump_send(struct mtk_mbox_device *mbdev, unsigned int pin);
+void mtk_mbox_dump(struct mtk_mbox_device *mbdev, unsigned int mbox);
+int mtk_mbox_log_enable(struct mtk_mbox_device *mbdev, bool enable);
+void mtk_mbox_reset_record(struct mtk_mbox_device *mbdev);
+#endif
+
@@ -0,0 +1,150 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef _LINUX_MTK_PM_QOS_H
+#define _LINUX_MTK_PM_QOS_H
+
+
+enum {
+	MTK_PM_QOS_RESERVED = 0,
+
+	MTK_PM_QOS_MEMORY_BANDWIDTH,
+	MTK_PM_QOS_MEMORY_EXT_BANDWIDTH,
+	MTK_PM_QOS_HRT_BANDWIDTH,
+	MTK_PM_QOS_DDR_OPP,
+	MTK_PM_QOS_VCORE_OPP,
+	MTK_PM_QOS_SCP_VCORE_REQUEST,
+
+	MTK_PM_QOS_VVPU_OPP,
+	MTK_PM_QOS_VMDLA_OPP,
+
+	PM_QOS_DISP_FREQ,
+	PM_QOS_MDP_FREQ,
+	PM_QOS_VDEC_FREQ,
+	PM_QOS_VENC_FREQ,
+	PM_QOS_IMG_FREQ,
+	PM_QOS_CAM_FREQ,
+	PM_QOS_DPE_FREQ,
+	PM_QOS_MM0_BANDWIDTH_LIMITER,
+	PM_QOS_MM1_BANDWIDTH_LIMITER,
+	MTK_PM_QOS_CPU_MEMORY_BANDWIDTH,
+	MTK_PM_QOS_GPU_MEMORY_BANDWIDTH,
+	MTK_PM_QOS_OTHER_MEMORY_BANDWIDTH,
+	MTK_PM_QOS_POWER_MODEL_DDR_REQUEST,
+	MTK_PM_QOS_POWER_MODEL_VCORE_REQUEST,
+	MTK_PM_QOS_VCORE_DVFS_FORCE_OPP,
+	MTK_PM_QOS_MEMORY_BANDWIDTH_TEST,
+
+	/* insert new class ID */
+	MTK_PM_QOS_NUM_CLASSES,
+};
+
+#define PM_QOS_ISP_HRT_BANDWIDTH MTK_PM_QOS_HRT_BANDWIDTH
+#define PM_QOS_MM_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_BANDWIDTH
+#define PM_QOS_APU_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_EXT_BANDWIDTH
+#define MTK_PM_QOS_ISP_HRT_BANDWIDTH PM_QOS_ISP_HRT_BANDWIDTH
+#define MTK_PM_QOS_MM_MEMORY_BANDWIDTH MTK_PM_QOS_MEMORY_BANDWIDTH
+
+#define MTK_PM_QOS_MEMORY_BANDWIDTH_DEFAULT_VALUE	0
+#define MTK_PM_QOS_HRT_BANDWIDTH_DEFAULT_VALUE		0
+#define MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE		16
+#define MTK_PM_QOS_VCORE_OPP_DEFAULT_VALUE		16
+#define MTK_PM_QOS_SCP_VCORE_REQUEST_DEFAULT_VALUE	16
+#define MTK_PM_QOS_VVPU_OPP_DEFAULT_VALUE		3
+#define MTK_PM_QOS_VMDLA_OPP_DEFAULT_VALUE		3
+#define PM_QOS_MM_FREQ_DEFAULT_VALUE		0
+#define PM_QOS_MM_BANDWIDTH_LIMITER_DEFAULT_VALUE	0
+#define MTK_PM_QOS_POWER_MODEL_DDR_REQUEST_DEFAULT_VALUE	0
+#define MTK_PM_QOS_POWER_MODEL_VCORE_REQUEST_DEFAULT_VALUE	0
+#define MTK_PM_QOS_VCORE_DVFS_FORCE_OPP_DEFAULT_VALUE	32
+#define PM_QOS_ISP_HRT_BANDWIDTH_DEFAULT_VALUE         0
+#define PM_QOS_APU_MEMORY_BANDWIDTH_DEFAULT_VALUE      0
+#define PM_QOS_MM_MEMORY_BANDWIDTH_DEFAULT_VALUE	0
+
+
+#if defined(CONFIG_MACH_MT6761) || defined(CONFIG_MACH_MT6765) || defined(CONFIG_MACH_MT6779)
+enum ddr_opp {
+	DDR_OPP_0 = 0,
+	DDR_OPP_1,
+	DDR_OPP_2,
+	DDR_OPP_3,
+	DDR_OPP_4,
+	DDR_OPP_5,
+	DDR_OPP_6,
+	DDR_OPP_7,
+	DDR_OPP_UNREQ = MTK_PM_QOS_DDR_OPP_DEFAULT_VALUE,
+};
+
+enum vcore_opp {
+	VCORE_OPP_0 = 0,
+	VCORE_OPP_1,
+	VCORE_OPP_2,
+	VCORE_OPP_3,
+	VCORE_OPP_4,
+	VCORE_OPP_5,
+	VCORE_OPP_6,
+	VCORE_OPP_7,
+	VCORE_OPP_UNREQ = MTK_PM_QOS_VCORE_OPP_DEFAULT_VALUE,
+};
+#endif
+
+struct mtk_pm_qos_request {
+	struct list_head list_node;
+	struct plist_node node;
+	unsigned int pm_qos_class;
+	char owner[20];
+};
+
+#if IS_ENABLED(CONFIG_MTK_PMQOS)
+void mtk_pm_qos_add_request(struct mtk_pm_qos_request *req,
+	unsigned int mtk_pm_qos_class, s32 value);
+void mtk_pm_qos_update_request(struct mtk_pm_qos_request *req,
+	s32 new_value);
+void mtk_pm_qos_remove_request(struct mtk_pm_qos_request *req);
+int mtk_pm_qos_request(unsigned int mtk_pm_qos_class);
+int mtk_pm_qos_add_notifier(unsigned int mtk_pm_qos_class,
+	struct notifier_block *notifier);
+int mtk_pm_qos_remove_notifier(unsigned int mtk_pm_qos_class,
+	struct notifier_block *notifier);
+int mtk_pm_qos_request(unsigned int pm_qos_class);
+int mtk_pm_qos_request_active(struct mtk_pm_qos_request *req);
+#else
+static inline void mtk_pm_qos_add_request(struct mtk_pm_qos_request *req,
+	unsigned int mtk_pm_qos_class, s32 value)
+{
+}
+static inline void mtk_pm_qos_update_request(
+	struct mtk_pm_qos_request *req, s32 new_value)
+{
+}
+static inline void mtk_pm_qos_remove_request(struct mtk_pm_qos_request *req)
+{
+}
+
+static inline int mtk_pm_qos_request(unsigned int mtk_pm_qos_class)
+{
+	return 0;
+}
+static inline int mtk_pm_qos_add_notifier(unsigned int mtk_pm_qos_class,
+	struct notifier_block *notifier)
+{
+	return 0;
+}
+
+static inline int mtk_pm_qos_remove_notifier(unsigned int mtk_pm_qos_class,
+	struct notifier_block *notifier)
+{
+	return 0;
+}
+
+static inline int mtk_pm_qos_request_active(struct mtk_pm_qos_request *req)
+{
+	return 0;
+}
+
+#endif
+
+#endif
+
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_CACHE__
+#define __MTK_CACHE__
+
+/*
+ * Be careful!!
+ *
+ * functions here are used for limited drivers which need
+ * special cache operation.
+ * please make sure you need these non-standard operations
+ * Anything in doubt, please discuss with the system service
+ * member.
+ *
+ */
+void __inner_flush_dcache_L1(void);
+void __inner_flush_dcache_L2(void);
+void __inner_flush_dcache_all(void);
+void __inner_clean_dcache_L1(void);
+void __inner_clean_dcache_L2(void);
+void __inner_clean_dcache_all(void);
+void __inner_inv_dcache_L1(void);
+void __inner_inv_dcache_L2(void);
+void __inner_inv_dcache_all(void);
+void __disable_dcache__inner_flush_dcache_L1(void);
+void __disable_dcache__inner_flush_dcache_L1__inner_flush_dcache_L2(void);
+void __disable_dcache__inner_clean_dcache_L1__inner_clean_dcache_L2(void);
+void dis_D_inner_fL1L2(void);
+void dis_D_inner_flush_all(void);
+void __flush_dcache_user_area(void *start, unsigned int size);
+void __clean_dcache_user_area(void *start, unsigned int size);
+void __inval_dcache_user_area(void *start, unsigned int size);
+
+#endif /* end of __MTK_CACHE__ */
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __SOC_MTK_DVFSRC_H
+#define __SOC_MTK_DVFSRC_H
+
+#define MTK_DVFSRC_CMD_BW_REQUEST	0
+#define MTK_DVFSRC_CMD_OPP_REQUEST	1
+#define MTK_DVFSRC_CMD_VCORE_REQUEST	2
+#define MTK_DVFSRC_CMD_HRTBW_REQUEST	3
+#define MTK_DVFSRC_CMD_VSCP_REQUEST	4
+#define MTK_DVFSRC_CMD_FORCE_OPP_REQUEST	5
+#define MTK_DVFSRC_CMD_DRAM_REQUEST	7
+#define MTK_DVFSRC_CMD_EXT_DRAM_REQUEST	8
+#define MTK_DVFSRC_CMD_EXT_BW_REQUEST	9
+
+#define MTK_DVFSRC_CMD_VCORE_QUERY	0
+#define MTK_DVFSRC_CMD_VCP_QUERY	1
+#define MTK_DVFSRC_CMD_CURR_LEVEL_QUERY	2
+
+#define MTK_SIP_SPM_DVFSRC_INIT 0
+
+#if IS_ENABLED(CONFIG_MTK_DVFSRC)
+void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd, u64 data);
+int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd, int *data);
+#else
+static inline void mtk_dvfsrc_send_request(const struct device *dev, u32 cmd,
+						u64 data)
+{ }
+static inline int mtk_dvfsrc_query_info(const struct device *dev, u32 cmd,
+						int *data)
+{ return -EINVAL; }
+#endif
+
+static inline struct device_node *dvfsrc_parse_required_opp(
+	struct device_node *np, int index)
+{
+	struct device_node *required_np;
+
+	required_np = of_parse_phandle(np, "required-opps", index);
+	if (unlikely(!required_np)) {
+		pr_notice("%s: Unable to parse required-opps: %pOF, index: %d\n",
+		       __func__, np, index);
+	}
+
+	return required_np;
+}
+
+static inline int dvfsrc_get_required_opp_performance_state(
+	struct device_node *np, int index)
+{
+	struct device_node *required_np;
+	int pstate = -EINVAL;
+
+	required_np = dvfsrc_parse_required_opp(np, index);
+	if (!required_np)
+		return -EINVAL;
+
+	of_property_read_u32(required_np, "opp-level", &pstate);
+	of_node_put(required_np);
+
+	return pstate;
+}
+#endif/* CONFIG_MTK_DVFSRC */
+
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef __SOC_MTK_MMDVFS_H
+#define __SOC_MTK_MMDVFS_H
+
+#if IS_ENABLED(CONFIG_MTK_MMDVFS)
+int register_mmdvfs_notifier(struct notifier_block *nb);
+int unregister_mmdvfs_notifier(struct notifier_block *nb);
+#else
+static inline int register_mmdvfs_notifier(struct notifier_block *nb)
+{ return -EINVAL; }
+static inline int unregister_mmdvfs_notifier(struct notifier_block *nb)
+{ return -EINVAL; }
+
+#endif /* CONFIG_MTK_MMDVFS */
+
+#endif
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_SIP_SVC_H
+#define __MTK_SIP_SVC_H
+
+/* Error Code */
+#define SIP_SVC_E_SUCCESS               0
+#define SIP_SVC_E_NOT_SUPPORTED         -1
+#define SIP_SVC_E_INVALID_PARAMS        -2
+#define SIP_SVC_E_INVALID_RANGE         -3
+#define SIP_SVC_E_PERMISSION_DENIED     -4
+
+#ifdef CONFIG_ARM64
+#define MTK_SIP_SMC_CONVENTION          ARM_SMCCC_SMC_64
+#else
+#define MTK_SIP_SMC_CONVENTION          ARM_SMCCC_SMC_32
+#endif
+
+#ifdef CONFIG_ARM64
+#define MTK_SIP_SMC_AARCH_BIT		0x40000000
+#else
+#define MTK_SIP_SMC_AARCH_BIT		0x00000000
+#endif
+
+#define MTK_SIP_SMC_CMD(fn_id) \
+	ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
+			   ARM_SMCCC_OWNER_SIP, fn_id)
+
+/* 0x82000200 - 0x820003FF & 0xC2000300 - 0xC20003FF */
+/* Debug feature and ATF related */
+#define MTK_SIP_KERNEL_WDT \
+	MTK_SIP_SMC_CMD(0x200)
+#define MTK_SIP_KERNEL_GIC_DUMP \
+	MTK_SIP_SMC_CMD(0x201)
+#define MTK_SIP_KERNEL_TIME_SYNC \
+	MTK_SIP_SMC_CMD(0x202)
+#define MTK_SIP_KERNEL_ATF_DEBUG \
+	MTK_SIP_SMC_CMD(0x204)
+#define MTK_SIP_KERNEL_DFD \
+	MTK_SIP_SMC_CMD(0x205)
+
+/* CCCI debug feature */
+#define MTK_SIP_KERNEL_CCCI_GET_INFO \
+	MTK_SIP_SMC_CMD(0x206)
+
+/* SPM related SMC call */
+#define MTK_SIP_KERNEL_SPM_SUSPEND_ARGS \
+	MTK_SIP_SMC_CMD(0x220)
+#define MTK_SIP_KERNEL_SPM_FIRMWARE_STATUS \
+	MTK_SIP_SMC_CMD(0x221)
+#define MTK_SIP_KERNEL_SPM_IRQ0_HANDLER \
+	MTK_SIP_SMC_CMD(0x222)
+#define MTK_SIP_KERNEL_SPM_AP_MDSRC_REQ \
+	MTK_SIP_SMC_CMD(0x223)
+#define MTK_SIP_KERNEL_SPM_PWR_CTRL_ARGS \
+	MTK_SIP_SMC_CMD(0x224)
+#define MTK_SIP_KERNEL_SPM_LEGACY_SLEEP \
+	MTK_SIP_SMC_CMD(0x225)
+#define MTK_SIP_KERNEL_SPM_VCOREFS_ARGS \
+	MTK_SIP_SMC_CMD(0x226)
+
+/* SPM deepidle related SMC call */
+#define MTK_SIP_KERNEL_SPM_DPIDLE_ARGS \
+	MTK_SIP_SMC_CMD(0x227)
+
+/* SPM SODI related SMC call */
+#define MTK_SIP_KERNEL_SPM_SODI_ARGS \
+	MTK_SIP_SMC_CMD(0x228)
+
+/* SPM sleep deepidle related SMC call */
+#define MTK_SIP_KERNEL_SPM_SLEEP_DPIDLE_ARGS \
+	MTK_SIP_SMC_CMD(0x229)
+/* SPM ARGS */
+#define MTK_SIP_KERNEL_SPM_ARGS \
+	MTK_SIP_SMC_CMD(0x22A)
+
+/* SPM get pwr_ctrl args */
+#define MTK_SIP_KERNEL_SPM_GET_PWR_CTRL_ARGS \
+	MTK_SIP_SMC_CMD(0x22B)
+
+/* SPM Check security CG (for deepidle/SODI) */
+#define MTK_SIP_KERNEL_CHECK_SECURE_CG \
+	MTK_SIP_SMC_CMD(0x22D)
+
+/* SCP DVFS */
+#define MTK_SIP_KERNEL_SCP_DVFS_CTRL \
+	MTK_SIP_SMC_CMD(0x232)
+
+/* AMMS related SMC call */
+#define MTK_SIP_KERNEL_AMMS_GET_FREE_ADDR \
+	MTK_SIP_SMC_CMD(0x250)
+#define MTK_SIP_KERNEL_AMMS_GET_FREE_LENGTH \
+	MTK_SIP_SMC_CMD(0x251)
+#define MTK_SIP_KERNEL_AMMS_GET_PENDING \
+	MTK_SIP_SMC_CMD(0x252)
+#define MTK_SIP_KERNEL_AMMS_ACK_PENDING \
+	MTK_SIP_SMC_CMD(0x253)
+#define MTK_SIP_KERNEL_AMMS_MD_POS_ADDR \
+	MTK_SIP_SMC_CMD(0x254)
+#define MTK_SIP_KERNEL_AMMS_MD_POS_LENGTH \
+	MTK_SIP_SMC_CMD(0x255)
+#define MTK_SIP_KERNEL_AMMS_GET_MD_POS_ADDR \
+	MTK_SIP_SMC_CMD(0x256)
+#define MTK_SIP_KERNEL_AMMS_GET_MD_POS_LENGTH \
+	MTK_SIP_SMC_CMD(0x257)
+#define MTK_SIP_KERNEL_AMMS_GET_SEQ_ID \
+	MTK_SIP_SMC_CMD(0x258)
+
+/* Security related SMC call */
+/* DEVMPU */
+#define MTK_SIP_KERNEL_DEVMPU_VIO_GET \
+	MTK_SIP_SMC_CMD(0x264)
+#define MTK_SIP_KERNEL_DEVMPU_PERM_GET \
+	MTK_SIP_SMC_CMD(0x265)
+#define MTK_SIP_KERNEL_DEVMPU_VIO_CLR \
+	MTK_SIP_SMC_CMD(0x268)
+/* TRNG */
+#define MTK_SIP_KERNEL_GET_RND \
+	MTK_SIP_SMC_CMD(0x26A)
+/* DEVAPC */
+#define MTK_SIP_KERNEL_DAPC_PERM_GET \
+	MTK_SIP_SMC_CMD(0x26B)
+#define MTK_SIP_KERNEL_CLR_SRAMROM_VIO \
+	MTK_SIP_SMC_CMD(0x26C)
+#define MTK_SIP_KERNEL_DAPC_DUMP \
+	MTK_SIP_SMC_CMD(0x26D)
+
+/* eMMC related SMC call */
+#define MTK_SIP_KERNEL_HW_FDE_KEY \
+	MTK_SIP_SMC_CMD(0x272)
+#define MTK_SIP_KERNEL_HW_FDE_MSDC_CTL \
+	MTK_SIP_SMC_CMD(0x273)
+
+/* UFS related SMC call */
+#define MTK_SIP_UFS_CONTROL \
+	MTK_SIP_SMC_CMD(0x276)
+
+/* I2C related SMC call */
+#define MTK_SIP_I2C_CONTROL \
+	MTK_SIP_SMC_CMD(0x2A0)
+
+/* M4U related SMC call */
+#define MTK_M4U_DEBUG_DUMP \
+	MTK_SIP_SMC_CMD(0x2B0)
+
+/* Debug related SMC call */
+#define MTK_SIP_KERNEL_CCCI_CONTROL \
+	MTK_SIP_SMC_CMD(0x505)
+/* VCOREFS */
+#define MTK_SIP_VCOREFS_CONTROL \
+	MTK_SIP_SMC_CMD(0x506)
+/* MTK LPM */
+#define MTK_SIP_MTK_LPM_CONTROL \
+	MTK_SIP_SMC_CMD(0x507)
+/* EMIMPU */
+#define MTK_SIP_EMIMPU_CONTROL \
+	MTK_SIP_SMC_CMD(0x50B)
+#define MTK_SIP_KERNEL_EMIMPU_WRITE \
+	MTK_SIP_SMC_CMD(0x260)
+#define MTK_SIP_KERNEL_EMIMPU_READ \
+	MTK_SIP_SMC_CMD(0x261)
+#define MTK_SIP_KERNEL_EMIMPU_SET \
+	MTK_SIP_SMC_CMD(0x262)
+#define MTK_SIP_KERNEL_EMIMPU_CLEAR \
+	MTK_SIP_SMC_CMD(0x263)
+
+/* TEEs related SMC call */
+#define MTK_SIP_KERNEL_TEE_CONTROL \
+	MTK_SIP_SMC_CMD(0x516)
+
+/* AUDIO related SMC call */
+#define MTK_SIP_AUDIO_CONTROL \
+	MTK_SIP_SMC_CMD(0x517)
+
+/* VPU */
+#define MTK_SIP_APUSYS_CONTROL \
+	MTK_SIP_SMC_CMD(0x51E)
+
+/* dptx related SMC call */
+#define MTK_SIP_DP_CONTROL \
+	MTK_SIP_SMC_CMD(0x523)
+
+/* TMEM */
+#define MTK_SIP_KERNEL_TMEM_CONTROL \
+	MTK_SIP_SMC_CMD(0x524)
+
+/* APU VCORE CG control related SMC call */
+#define MTK_SIP_KERNEL_APU_VCORE_CG_CTL \
+	MTK_SIP_SMC_CMD(0x2B1)
+
+/* USB related SMC call */
+#define MTK_SIP_KERNEL_USB_CONTROL \
+	MTK_SIP_SMC_CMD(0x527)
+
+/* SDA */
+#define MTK_SIP_SDA_CONTROL \
+        (0x82000525 | MTK_SIP_SMC_AARCH_BIT)
+
+ /* Clock Buffer */
+  #define MTK_SIP_CLKBUF_CONTROL \
+	(0x82000520 | MTK_SIP_SMC_AARCH_BIT)
+
+
+#endif
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __MTK_TINYSYS_IPI_H__
+#define __MTK_TINYSYS_IPI_H__
+
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mbox.h>
+
+
+#define IPI_SEND_WAIT       0
+#define IPI_SEND_POLLING    1
+
+enum mtk_ipi_dev {
+	IPI_DEV_SCP,
+	IPI_DEV_SSPM,
+	IPI_DEV_ADSP,
+	IPI_DEV_MCUPM,
+	IPI_DEV_CPUEB,
+	IPI_DEV_APUSYS,
+	IPI_DEV_GPUEB,
+	IPI_DEV_VCP,
+	IPI_DEV_TOTAL,
+};
+
+enum ipi_stage {
+	SEND_MSG,
+	ISR_RECV_MSGV,
+	RECV_MSG,
+	SEND_ACK,
+	ISR_RECV_ACK,
+	RECV_ACK,
+	UNUSED = 0xF,
+};
+
+typedef int (*ipi_tx_cb_t)(void *);
+
+struct ipimon_s {
+	unsigned short idx;
+	unsigned long long ts;
+};
+
+/**
+ * struct mtk_ipi_chan_table - channel table that belong to mtk_ipi_device
+ * @ept: the rpmsg endpoint of this channel
+ * @rpchan: info used to create the endpoint
+ * @pin_send: the mbox send pin table address of this channel
+ * @pin_recv: the mbox receive pin table address of this channel
+ * @holder: keep 1 if there are ipi waiters (to wait the reply)
+ * @ipi_stage: transmission stage for t0~t5 (default is 0xF)
+ * @ipi_seqno: sequence count of the IPI pin processed
+ * @ipi_record: timestamp of each ipi transmission stage
+ *
+ * All of these data should be initialized by mtk_ipi_device_register()
+ */
+struct mtk_ipi_chan_table {
+	struct rpmsg_endpoint *ept;
+	struct mtk_rpmsg_channel_info *rpchan;
+	struct mtk_mbox_pin_send *pin_send;
+	struct mtk_mbox_pin_recv *pin_recv;
+	atomic_t holder;
+	unsigned int ipi_stage: 4,
+		 ipi_seqno : 28;
+	struct ipimon_s ipi_record[3];
+	int trysend_count;
+	int polling_count;
+};
+
+/**
+ * struct mtk_ipi_device - device for represent the tinysys using mtk ipi
+ * @name: name of tinysys device
+ * @id: device id (used to match between rpmsg drivers and devices)
+ * @mrpdev: mtk rpmsg channel device
+ * @mbdev: mtk mbox device
+ * @table: channel table with endpoint & channel_info & mbox_pin info
+ * @mutex_ipi_reg: the lock must be taken when user register ipi
+ * @pre_cb: the callback handler before ipi send data
+ * @post_cb: the callback handler after ipi send data
+ * @prdata: private data for the callback use
+ * @timeout_handler: the callback for waiting reply timeout
+ * @lock_monitor: the lock for dump ipi timestamp
+ * @ipi_last_done: the last processed ipi transmission
+ * @ipi_inited: set when mtk_ipi_device_register() done
+ *
+ * Tinysys platform has necessary to define the vcalue of 'name', 'id', 'mbdev';
+ * and optional to define the 'pre_cb', 'post_cb', 'prdata', 'timeout_handler'.
+ * Othes would be initialized by mtk_ipi_device_register().
+ */
+struct mtk_ipi_device  {
+	const char *name;
+	int id;
+	struct mtk_rpmsg_device *mrpdev;
+	struct mtk_mbox_device *mbdev;
+	struct mtk_ipi_chan_table *table;
+	struct mutex mutex_ipi_reg;
+	ipi_tx_cb_t pre_cb;
+	ipi_tx_cb_t post_cb;
+	void *prdata;
+	void (*timeout_handler)(int id);
+	spinlock_t lock_monitor;
+	int ipi_last_done;
+	int ipi_inited;
+};
+
+
+#define IPI_ACTION_DONE		0
+#define IPI_DEV_ILLEGAL		-1 /* ipi device is not initial */
+#define IPI_DUPLEX		-2 /* the ipi has be registered */
+#define IPI_UNAVAILABLE		-3 /* can't find this ipi pin define */
+#define IPI_NO_MSGBUF		-4 /* receiver doesn't has message buffer */
+#define IPI_NO_MEMORY		-5 /* message length is large than defined */
+#define IPI_PIN_BUSY		-6 /* send message timeout */
+#define IPI_COMPL_TIMEOUT	-7 /* polling or wait for ack ipi timeout */
+#define IPI_PRE_CB_FAIL		-8 /* pre-callback fail */
+#define IPI_POST_CB_FAIL	-9 /* post-callback fail */
+#define IPI_RPMSG_ERR		-99 /* some error from rpmsg layer */
+
+
+int mtk_ipi_device_register(struct mtk_ipi_device *ipidev,
+		struct platform_device *pdev, struct mtk_mbox_device *mbox,
+		unsigned int ipi_chan_count);
+int mtk_ipi_device_reset(struct mtk_ipi_device *ipidev);
+
+int mtk_ipi_register(struct mtk_ipi_device *ipidev, int ipi_id,
+		mbox_pin_cb_t cb, void *prdata, void *msg);
+int mtk_ipi_unregister(struct mtk_ipi_device *ipidev, int ipi_id);
+
+int mtk_ipi_send(struct mtk_ipi_device *ipidev, int ipi_id,
+		int opt, void *data, int len, int retry_timeout);
+int mtk_ipi_send_compl(struct mtk_ipi_device *ipidev, int ipi_id,
+		int opt, void *data, int len, unsigned long timeout);
+int mtk_ipi_recv(struct mtk_ipi_device *ipidev, int ipi_id);
+int mtk_ipi_recv_reply(struct mtk_ipi_device *ipidev, int ipi_id,
+		void *reply_data, int len);
+
+void ipi_monitor_dump(struct mtk_ipi_device *ipidev);
+void mtk_ipi_tracking(struct mtk_ipi_device *ipidev, bool en);
+
+#endif
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+
+#ifndef __SOC_MEDIATEK_PMIC_WRAP_H
+#define __SOC_MEDIATEK_PMIC_WRAP_H
+
+extern struct regmap *pwrap_node_to_regmap(struct device_node *np);
+
+#endif /* __SOC_MEDIATEK_PMIC_WRAP_H */
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __SOC_MEDIATEK_SCPSYS_EXT_H
+#define __SOC_MEDIATEK_SCPSYS_EXT_H
+
+#define MAX_STEPS	7
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs,			\
+		_en_ofs, _sta_ofs, _mask, _set_ack_mask,	\
+		_clr_ack_mask) {				\
+		.type = _type,					\
+		.set_ofs = _set_ofs,				\
+		.clr_ofs = _clr_ofs,				\
+		.en_ofs = _en_ofs,				\
+		.sta_ofs = _sta_ofs,				\
+		.mask = _mask,					\
+		.set_ack_mask = _set_ack_mask,			\
+		.clr_ack_mask = _clr_ack_mask,			\
+	}
+
+enum regmap_type {
+	IFR_TYPE,
+	SMI_TYPE,
+	IFR_WAYEN_TYPE,
+	MAX_REGMAP_TYPE,
+};
+
+struct bus_prot {
+	enum regmap_type type;
+	u32 set_ofs;
+	u32 clr_ofs;
+	u32 en_ofs;
+	u32 sta_ofs;
+	u32 mask;
+	u32 set_ack_mask;
+	u32 clr_ack_mask;
+};
+
+int mtk_scpsys_ext_set_bus_protection(const struct bus_prot *bp_table,
+	struct regmap *infracfg, struct regmap *smi_common,
+	struct regmap *infracfg_nao);
+int mtk_scpsys_ext_clear_bus_protection(const struct bus_prot *bp_table,
+	struct regmap *infracfg, struct regmap *smi_common,
+	struct regmap *infracfg_nao);
+
+#endif /* __SOC_MEDIATEK_SCPSYS_EXT_H */