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Initial commit: Linux kernel 4.19 for Unplugged OS

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ziv committed 2025-10-06 13:52:42 +00:00
commit d30235b04c
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include/memory/jedec_ddr.h
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/*
* Definitions for DDR memories based on JEDEC specs
*
* Copyright (C) 2012 Texas Instruments, Inc.
*
* Aneesh V <aneesh@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __LINUX_JEDEC_DDR_H
#define __LINUX_JEDEC_DDR_H
#include <linux/types.h>
/* DDR Densities */
#define DDR_DENSITY_64Mb 1
#define DDR_DENSITY_128Mb 2
#define DDR_DENSITY_256Mb 3
#define DDR_DENSITY_512Mb 4
#define DDR_DENSITY_1Gb 5
#define DDR_DENSITY_2Gb 6
#define DDR_DENSITY_4Gb 7
#define DDR_DENSITY_8Gb 8
#define DDR_DENSITY_16Gb 9
#define DDR_DENSITY_32Gb 10
/* DDR type */
#define DDR_TYPE_DDR2 1
#define DDR_TYPE_DDR3 2
#define DDR_TYPE_LPDDR2_S4 3
#define DDR_TYPE_LPDDR2_S2 4
#define DDR_TYPE_LPDDR2_NVM 5
/* DDR IO width */
#define DDR_IO_WIDTH_4 1
#define DDR_IO_WIDTH_8 2
#define DDR_IO_WIDTH_16 3
#define DDR_IO_WIDTH_32 4
/* Number of Row bits */
#define R9 9
#define R10 10
#define R11 11
#define R12 12
#define R13 13
#define R14 14
#define R15 15
#define R16 16
/* Number of Column bits */
#define C7 7
#define C8 8
#define C9 9
#define C10 10
#define C11 11
#define C12 12
/* Number of Banks */
#define B1 0
#define B2 1
#define B4 2
#define B8 3
/* Refresh rate in nano-seconds */
#define T_REFI_15_6 15600
#define T_REFI_7_8 7800
#define T_REFI_3_9 3900
/* tRFC values */
#define T_RFC_90 90000
#define T_RFC_110 110000
#define T_RFC_130 130000
#define T_RFC_160 160000
#define T_RFC_210 210000
#define T_RFC_300 300000
#define T_RFC_350 350000
/* Mode register numbers */
#define DDR_MR0 0
#define DDR_MR1 1
#define DDR_MR2 2
#define DDR_MR3 3
#define DDR_MR4 4
#define DDR_MR5 5
#define DDR_MR6 6
#define DDR_MR7 7
#define DDR_MR8 8
#define DDR_MR9 9
#define DDR_MR10 10
#define DDR_MR11 11
#define DDR_MR16 16
#define DDR_MR17 17
#define DDR_MR18 18
/*
* LPDDR2 related defines
*/
/* MR4 register fields */
#define MR4_SDRAM_REF_RATE_SHIFT 0
#define MR4_SDRAM_REF_RATE_MASK 7
#define MR4_TUF_SHIFT 7
#define MR4_TUF_MASK (1 << 7)
/* MR4 SDRAM Refresh Rate field values */
#define SDRAM_TEMP_NOMINAL 0x3
#define SDRAM_TEMP_RESERVED_4 0x4
#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5
#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6
#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7
#define NUM_DDR_ADDR_TABLE_ENTRIES 11
#define NUM_DDR_TIMING_TABLE_ENTRIES 4
/* Structure for DDR addressing info from the JEDEC spec */
struct lpddr2_addressing {
u32 num_banks;
u32 tREFI_ns;
u32 tRFCab_ps;
};
/*
* Structure for timings from the LPDDR2 datasheet
* All parameters are in pico seconds(ps) unless explicitly indicated
* with a suffix like tRAS_max_ns below
*/
struct lpddr2_timings {
u32 max_freq;
u32 min_freq;
u32 tRPab;
u32 tRCD;
u32 tWR;
u32 tRAS_min;
u32 tRRD;
u32 tWTR;
u32 tXP;
u32 tRTP;
u32 tCKESR;
u32 tDQSCK_max;
u32 tDQSCK_max_derated;
u32 tFAW;
u32 tZQCS;
u32 tZQCL;
u32 tZQinit;
u32 tRAS_max_ns;
};
/*
* Min value for some parameters in terms of number of tCK cycles(nCK)
* Please set to zero parameters that are not valid for a given memory
* type
*/
struct lpddr2_min_tck {
u32 tRPab;
u32 tRCD;
u32 tWR;
u32 tRASmin;
u32 tRRD;
u32 tWTR;
u32 tXP;
u32 tRTP;
u32 tCKE;
u32 tCKESR;
u32 tFAW;
};
extern const struct lpddr2_addressing
lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES];
extern const struct lpddr2_timings
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
#endif /* __LINUX_JEDEC_DDR_H */
include/memory/mediatek/dramc.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Sagy Shih <sagy.shih@mediatek.com>
*/
#ifndef __DRAMC_H__
#define __DRAMC_H__
struct mr_info_t {
unsigned int mr_index;
unsigned int mr_value;
};
struct reg_ctrl_t {
unsigned int offset;
unsigned int mask;
unsigned int shift;
};
struct fmeter_dev_t {
unsigned int version;
unsigned int crystal_freq;
unsigned int shu_of;
struct reg_ctrl_t shu_lv;
struct reg_ctrl_t pll_id;
struct reg_ctrl_t pll_md[2];
struct reg_ctrl_t sdmpcw[2];
struct reg_ctrl_t prediv[2];
struct reg_ctrl_t posdiv[2];
struct reg_ctrl_t ckdiv4[2];
struct reg_ctrl_t cldiv2[2];
struct reg_ctrl_t fbksel[2];
#ifdef CONFIG_MEDIATEK_DRAMC
struct reg_ctrl_t dqsopen[2];
#endif
struct reg_ctrl_t dqopen[2];
#ifdef CONFIG_MEDIATEK_DRAMC
struct reg_ctrl_t ckdiv4_ca[2];
#endif
};
struct mr4_dev_t {
unsigned int version;
struct reg_ctrl_t mr4_rg;
};
struct dramc_dev_t {
unsigned int dram_type;
unsigned int support_ch_cnt;
unsigned int ch_cnt;
unsigned int rk_cnt;
unsigned int mr_cnt;
unsigned int freq_cnt;
unsigned int *rk_size;
unsigned int *freq_step;
struct mr_info_t *mr_info_ptr;
void __iomem **dramc_chn_base_ao;
void __iomem **dramc_chn_base_nao;
void __iomem **ddrphy_chn_base_ao;
void __iomem **ddrphy_chn_base_nao;
void __iomem *sleep_base;
void *mr4_dev_ptr;
void *fmeter_dev_ptr;
};
enum DRAM_TYPE {
TYPE_DDR1 = 1,
TYPE_LPDDR2,
TYPE_LPDDR3,
TYPE_PCDDR3,
TYPE_LPDDR4,
TYPE_LPDDR4X,
TYPE_LPDDR4P,
TYPE_LPDDR5
};
#ifdef CONFIG_MEDIATEK_DRAMC
#define DPM_IRQ_CHA 0
#define DPM_IRQ_CHB 1
#endif
int mtk_dramc_get_steps_freq(unsigned int step);
unsigned int mtk_dramc_get_ddr_type(void);
unsigned int mtk_dramc_get_data_rate(void);
unsigned int mtk_dramc_get_mr4(unsigned int ch);
#endif /* __DRAMC_H__ */
include/memory/mediatek/emi.h
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/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
* Author: Sagy Shih <sagy.shih@mediatek.com>
*/
#ifndef __EMI_H__
#define __EMI_H__
#include <linux/workqueue.h>
#include <linux/irqreturn.h>
#include <linux/dcache.h>
#if IS_ENABLED(CONFIG_MTK_ENG_BUILD)
#define MTK_EMIMPU_DBG_ENABLE
#endif
#define MTK_EMIMPU_NO_PROTECTION 0
#define MTK_EMIMPU_SEC_RW 1
#define MTK_EMIMPU_SEC_RW_NSEC_R 2
#define MTK_EMIMPU_SEC_RW_NSEC_W 3
#define MTK_EMIMPU_SEC_R_NSEC_R 4
#define MTK_EMIMPU_FORBIDDEN 5
#define MTK_EMIMPU_SEC_R_NSEC_RW 6
#define MTK_EMIMPU_UNLOCK false
#define MTK_EMIMPU_LOCK true
#define MTK_EMIMPU_SET 0
#define MTK_EMIMPU_CLEAR 1
#define MTK_EMIMPU_READ 2
#define MTK_EMIMPU_SLVERR 3
#define MTK_EMIDBG_DUMP 4
#define MTK_EMIDBG_MSG 5
#define MTK_EMIMPU_READ_SA 0
#define MTK_EMIMPU_READ_EA 1
#define MTK_EMIMPU_READ_APC 2
#define MTK_EMI_MAX_TOKEN 4
#ifdef CONFIG_MTK_EMI
#define MTK_EMI_MAX_CMD_LEN 4096
#endif
#ifdef CONFIG_MEDIATEK_EMI
#define MTK_EMI_MAX_CMD_LEN 256
struct emi_addr_map {
int emi;
int channel;
int rank;
int bank;
int row;
int column;
};
#endif
struct reg_info_t {
unsigned int offset;
unsigned int value;
unsigned int leng;
};
#ifdef CONFIG_MTK_EMI
struct emicen_dev_t {
unsigned int emi_cen_cnt;
unsigned int ch_cnt;
unsigned int rk_cnt;
unsigned long long *rk_size;
void __iomem **emi_cen_base;
void __iomem **emi_chn_base;
};
struct emimpu_dbg_cb {
void (*func)(void);
struct emimpu_dbg_cb *next_dbg_cb;
};
struct emimpu_dev_t {
unsigned int region_cnt;
unsigned int domain_cnt;
unsigned int addr_align;
unsigned long long dram_start;
unsigned long long dram_end;
unsigned int dump_cnt;
unsigned int clear_reg_cnt;
unsigned int clear_md_reg_cnt;
unsigned int emi_cen_cnt;
struct reg_info_t *dump_reg;
struct reg_info_t *clear_reg;
struct reg_info_t *clear_md_reg;
void __iomem **emi_cen_base;
void __iomem **emi_mpu_base;
char *violation_msg;
unsigned int in_msg_dump;
unsigned int show_region;
unsigned int ctrl_intf;
struct emimpu_region_t *ap_rg_info;
struct emimpu_dbg_cb *dbg_cb_list;
};
#endif
#ifdef CONFIG_MEDIATEK_EMI
struct emimpu_dev_t {
unsigned int region_cnt;
unsigned int domain_cnt;
unsigned int addr_align;
unsigned long long dram_start;
unsigned long long dram_end;
unsigned int dump_cnt;
unsigned int clear_reg_cnt;
unsigned int clear_md_reg_cnt;
unsigned int emi_cen_cnt;
struct reg_info_t *dump_reg;
struct reg_info_t *clear_reg;
struct reg_info_t *clear_md_reg;
void __iomem **emi_cen_base;
void __iomem **emi_mpu_base;
unsigned int show_region;
unsigned int ctrl_intf;
struct emimpu_region_t *ap_rg_info;
};
#endif
struct emiisu_dev_t {
unsigned int buf_size;
void __iomem *buf_addr;
void __iomem *ver_addr;
void __iomem *con_addr;
struct dentry *dump_dir;
struct dentry *dump_buf;
unsigned int ctrl_intf;
};
struct emimpu_region_t {
unsigned long long start;
unsigned long long end;
unsigned int rg_num;
bool lock;
unsigned int *apc;
};
/* mtk emicen api */
unsigned int mtk_emicen_get_ch_cnt(void);
unsigned int mtk_emicen_get_rk_cnt(void);
unsigned int mtk_emicen_get_rk_size(unsigned int rk_id);
#ifdef CONFIG_MEDIATEK_EMI
int mtk_emicen_addr2dram(unsigned long addr, struct emi_addr_map *map);
#endif
/* mtk emidbg api */
void mtk_emidbg_dump(void);
/* mtk emimpu api */
int mtk_emimpu_init_region(
struct emimpu_region_t *rg_info, unsigned int rg_num);
int mtk_emimpu_set_addr(struct emimpu_region_t *rg_info,
unsigned long long start, unsigned long long end);
int mtk_emimpu_set_apc(struct emimpu_region_t *rg_info,
unsigned int d_num, unsigned int apc);
int mtk_emimpu_lock_region(struct emimpu_region_t *rg_info, bool lock);
int mtk_emimpu_set_protection(struct emimpu_region_t *rg_info);
int mtk_emimpu_free_region(struct emimpu_region_t *rg_info);
int mtk_emimpu_clear_protection(struct emimpu_region_t *rg_info);
int mtk_emimpu_prehandle_register(irqreturn_t (*bypass_func)
(unsigned int emi_id, struct reg_info_t *dump, unsigned int leng));
int mtk_emimpu_postclear_register(void (*clear_func)
(unsigned int emi_id));
#ifdef CONFIG_MTK_EMI
int mtk_emimpu_debugdump_register(void (*debug_func)(void));
#endif
int mtk_emimpu_md_handling_register(void (*md_handling_func)
(unsigned int emi_id, struct reg_info_t *dump, unsigned int leng));
void mtk_clear_md_violation(void);
int mtk_emimpu_register_callback(irqreturn_t (*debug_dump)
(unsigned int emi_id, struct reg_info_t *dump, unsigned int len));
#endif /* __EMI_H__ */