// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 MediaTek Inc.
 *
 */
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt6761-pinfunc.h>
#include <dt-bindings/memory/mt6761-larb-port.h>
#include <dt-bindings/mmc/mt6761-msdc.h>
#include <dt-bindings/clock/mt6761-clk.h>
#include <dt-bindings/iio/mt635x-auxadc.h>
#include <dt-bindings/gce/mt6765-gce.h>
#include <dt-bindings/reset/mt6761-resets.h>
#include <dt-bindings/soc/mediatek,boot-mode.h>
#include <dt-bindings/phy/phy.h>
#include <generated/autoconf.h>
/ {
	model = "MT6761";
	compatible = "mediatek,MT6761";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	/* chosen */
	chosen: chosen {
		bootargs = "console=tty0 console=ttyS0,921600n1 vmalloc=400M \
				slub_debug=OFZPU page_owner=on \
				swiotlb=noforce \
				cgroup.memory=nosocket,nokmem \
				androidboot.hardware=mt6761 \
				maxcpus=8 loop.max_part=7 \
				firmware_class.path=/vendor/firmware";
	};

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;
		opp0 {
			opp-hz = /bits/ 64 <850000000>;
			opp-microvolt = <650000>;
		};
		opp1 {
			opp-hz = /bits/ 64 <918000000>;
			opp-microvolt = <668750>;
		};
		opp2 {
			opp-hz = /bits/ 64 <987000000>;
			opp-microvolt = <687500>;
		};
		opp3 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-microvolt = <706250>;
		};
		opp4 {
			opp-hz = /bits/ 64 <1125000000>;
			opp-microvolt = <725000>;
		};
		opp5 {
			opp-hz = /bits/ 64 <1216000000>;
			opp-microvolt = <750000>;
		};
		opp6 {
			opp-hz = /bits/ 64 <1308000000>;
			opp-microvolt = <775000>;
		};
		opp7 {
			opp-hz = /bits/ 64 <1400000000>;
			opp-microvolt = <800000>;
		};
		opp8 {
			opp-hz = /bits/ 64 <1466000000>;
			opp-microvolt = <825000>;
		};
		opp9 {
			opp-hz = /bits/ 64 <1533000000>;
			opp-microvolt = <850000>;
		};
		opp10 {
			opp-hz = /bits/ 64 <1633000000>;
			opp-microvolt = <887500>;
		};
		opp11 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <912500>;
		};
		opp12 {
			opp-hz = /bits/ 64 <1767000000>;
			opp-microvolt = <937500>;
		};
		opp13 {
			opp-hz = /bits/ 64 <1834000000>;
			opp-microvolt = <962500>;
		};
		opp14 {
			opp-hz = /bits/ 64 <1917000000>;
			opp-microvolt = <993750>;
		};
		opp15 {
			opp-hz = /bits/ 64 <2001000000>;
			opp-microvolt = <1025000>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			enable-method = "psci";
			clock-frequency = <2340000000>;
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <275>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&SODI &SODI3 &DPIDLE &SUSPEND>;
		};

		cpu1: cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
			clock-frequency = <2340000000>;
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <275>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&SODI &SODI3 &DPIDLE &SUSPEND>;
		};

		cpu2: cpu@002 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			enable-method = "psci";
			clock-frequency = <2340000000>;
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <275>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&SODI &SODI3 &DPIDLE &SUSPEND>;
		};

		cpu3: cpu@003 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			enable-method = "psci";
			clock-frequency = <2340000000>;
			operating-points-v2 = <&cluster0_opp>;
			dynamic-power-coefficient = <275>;
			capacity-dmips-mhz = <1024>;
			cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
				<&SODI &SODI3 &DPIDLE &SUSPEND>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		idle-states {
			entry-method = "arm,psci";

			STANDBY: standby {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00000001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			MCDI_CPU: mcdi-cpu {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			MCDI_CLUSTER: mcdi-cluster {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010001>;
				entry-latency-us = <600>;
				exit-latency-us = <600>;
				min-residency-us = <1200>;
			};

			SODI: sodi {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010002>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
			};

			SODI3: sodi3 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010003>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
			};

			DPIDLE: dpidle {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010004>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
			};

			SUSPEND: suspend {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x01010005>;
				entry-latency-us = <800>;
				exit-latency-us = <1000>;
				min-residency-us = <2000>;
			};
		};
	};

	psci {
		compatible      = "arm,psci-1.0";
		method          = "smc";
	};

	pmu {
		compatible = "arm,cortex-a7-pmu";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	l2c_parity {
		compatible = "mediatek,l2c_parity-v1";
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000 0 0x20000000>;
	};

	reserved-memory {
		/*TODO: add reserved memory node here*/
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		reserve-memory-sspm_share {
			compatible = "mediatek,reserve-memory-sspm_share";
			no-map;
			status = "okay";
#ifdef CONFIG_MTK_GMO_RAM_OPTIMIZE
			size = <0 0x110000>; /* 1M + 64K */
#else
			size = <0 0x510000>; /* 5M + 64K */
#endif
			alignment = <0 0x10000>;
			alloc-ranges = <0 0x40000000 0 0x60000000>;
		};

		reserve-memory-scp_share {
			compatible = "mediatek,reserve-memory-scp_share";
			no-map;
#ifdef CONFIG_MTK_TINYSYS_SCP_LOGGER_SUPPORT
			size = <0 0x00300000>;
#else
			size = <0 0x00100000>;
#endif
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x50000000>;
		};

		consys_mem: consys-reserve-memory {
			compatible = "mediatek,consys-reserve-memory";
			no-map;
			size = <0 0x400000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		wifi_mem: wifi-reserve-memory {
			compatible = "shared-dma-pool";
			no-map;
			size = <0 0x300000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

#ifdef CONFIG_MICROTRUST_TEE_SUPPORT
		soter-shared-mem {
			compatible = "microtrust,shared_mem";
			no-map;
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
	defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
			size = <0 0x800000>;
			alignment = <0 0x1000000>;
#else
			size = <0 0x200000>;
			alignment = <0 0x200000>;
#endif
			alloc-ranges = <0 0x40000000 0 0x50000000>;
		};
#endif

	};

	/* Microtrust SW IRQ number 188(220) ~ 193(225) */
	utos {
		compatible = "microtrust,utos";
		interrupts = <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
	};
	utos_tester {
		compatible = "microtrust,tester-v1";
	};

	cpu_dbgapb: cpu_dbgapb@0d410000 {
		compatible = "mediatek,hw_dbg";
		num = <8>;
		reg =	<0 0x0d410000 0 0x1000>,
			<0 0x0d510000 0 0x1000>,
			<0 0x0d610000 0 0x1000>,
			<0 0x0d710000 0 0x1000>,
			<0 0x0d810000 0 0x1000>,
			<0 0x0d910000 0 0x1000>,
			<0 0x0da10000 0 0x1000>,
			<0 0x0db10000 0 0x1000>;
	};

	/* ATF logger SW IRQ number 110 = 32 + 78 */
	atf_logger {
		compatible = "mediatek,atf_logger";
		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
	};

	/* AMMS SW IRQ number GIC:99 DTS:67*/
	amms_control {
		compatible = "mediatek,amms";
		interrupts = <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>;
	};

	gic: interrupt-controller@0c000000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		#redistributor-regions = <1>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>, // distributor
		      <0 0x0c080000 0 0x200000>, // redistributor
		      <0 0x10200a80 0 0x50>; // intpol
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	sysirq: intpol-controller@10200a80 {
		compatible = "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200a80 0 0x50>;
	};

	infracfg_ao: infracfg_ao@10001000 {
		compatible = "mediatek,common-infracfg_ao",
			     "mediatek,infracfg_ao",
			     "mediatek,mt6761-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>;
		#clock-cells = <1>;
	};

	mcdi@00110100 {
		compatible = "mediatek,mt6761-mcdi";
		reg = <0 0x00110100 0 0x800>;
	};

	scpsys: scpsys@10001000 {
		compatible = "mediatek,mt6761-scpsys", "syscon";
		reg =	<0 0x10001000 0 0x1000>, /* infra_ao */
				<0 0x10006000 0 0x1000>, /* spm */
				<0 0x14002000 0 0x1000>, /* spi_common */
				<0 0x1020e000 0 0x1000>, /* infracfg */
				<0 0x18004000 0 0x1000>; /* connsys */
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			<&topckgen CLK_TOP_MFG_SEL>,
			<&mmsys_config CLK_MM_SMI_COMM0>,
			<&mmsys_config CLK_MM_SMI_COMM1>,
			<&mmsys_config CLK_MM_SMI_COMMON>,
			<&mmsys_config CLK_MM_SMI_LARB0>,
			<&camsys CLK_CAM_LARB2>,
			<&camsys CLK_CAM>,
			<&mmsys_config CLK_MM_SMI_CAM>,
			<&mmsys_config CLK_MM_SMI_IMG>;
		clock-names = "mm", "mfg",
			"mm-0", "mm-1", "mm-2", "mm-3",
			"cam-0", "cam-1", "cam-2", "cam-3";
		#clock-cells = <1>;
	};

	scp_infra: scp_infra@10001000 {
		compatible = "mediatek,scpinfra";
		reg = <0 0x10001000 0 0x1000>;
	};

	topckgen: topckgen@10000000 {
		compatible = "mediatek,mt6761-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	dcm: dcm@10001000 {
		compatible = "mediatek,mt6761-dcm";
		reg = <0 0x10001000 0 0x1000>,
		      <0 0x10200000 0 0x4000>,
		      <0 0x10228000 0 0x2000>,
		      <0 0x1022a000 0 0x2000>,
		      <0 0x10230000 0 0x2000>,
		      <0 0x10232000 0 0x2000>,
		      <0 0x1022d000 0 0x1000>,
		      <0 0x10235000 0 0x1000>;
		reg-names = "infra_ao",
			"mcucfg",
			"ddrphy0_ao",
			"dramc0_ao",
			"ddrphy1_ao",
			"dramc1_ao",
			"emi_ch0",
			"emi_ch1";
	};

	io_cfg_lt: io_cfg_lt@10002000 {
		compatible = "mediatek,io_cfg_lt";
		reg = <0 0x10002000 0 0x200>;
	};

	io_cfg_lm: io_cfg_lm@10002200 {
		compatible = "mediatek,io_cfg_lm";
		reg = <0 0x10002200 0 0x200>;
	};

	io_cfg_lb: io_cfg_lb@10002400 {
		compatible = "mediatek,io_cfg_lb";
		reg = <0 0x10002400 0 0x200>;
	};

	io_cfg_bl: io_cfg_bl@10002600 {
		compatible = "mediatek,io_cfg_bl";
		reg = <0 0x10002600 0 0x200>;
	};

	io_cfg_rr: io_cfg_rr@10002800 {
		compatible = "mediatek,io_cfg_rr";
		reg = <0 0x10002800 0 0x200>;
	};

	io_cfg_rb: io_cfg_rb@10002a00 {
		compatible = "mediatek,io_cfg_rb";
		reg = <0 0x10002a00 0 0x200>;
	};

	io_cfg_rt: io_cfg_rt@10002c00 {
		compatible = "mediatek,io_cfg_rt";
		reg = <0 0x10002c00 0 0x200>;
	};

	pericfg: pericfg@10003000 {
		compatible = "mediatek,pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	efuse_dbg@10004000 {
		compatible = "mediatek,efuse_dbg";
		reg = <0 0x10004000 0 0x1000>;
	};

	smart_pa: smart_pa {

	};

	tcpc_pd: tcpc_pd {

	};

	md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {

	};

	md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {

	};

	gpio_usage_mapping:gpio {
		compatible = "mediatek,gpio_usage_mapping";
	};

	gpio: gpio@10005000 {
		compatible = "mediatek,gpio", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	syscfg_pctl_0: syscfg_pctl_0@10005000 {
		compatible = "mediatek,mt6761-pctl-0-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	sleep: sleep@10006000 {
		compatible = "mediatek,sleep", "syscon";
		mediatek,pwrap-regmap = <&pwrap>;
		reg = <0 0x10006000 0 0x1000>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
		wakeup-source = <&keypad 0 (1 << 2)>,
				<&consys 1 (1 << 5)>,
				<&mddriver 3 (1 << 25)>;
	};

	eint: eint@1000b000 {
		compatible = "mediatek,eint";
		reg = <0 0x1000b000 0 0x1000>;
	};

	pio: pinctrl@10005000 {
		compatible = "mediatek,mt6761-pinctrl";
		reg_bases = <&gpio>,
			<&io_cfg_lt>,
			<&io_cfg_lm>,
			<&io_cfg_lb>,
			<&io_cfg_bl>,
			<&io_cfg_rr>,
			<&io_cfg_rb>,
			<&io_cfg_rt>;
		pins-are-numbered;
		gpio-controller;
		gpio-ranges = <&pio 0 0 179>;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	toprgu: toprgu@10007000 {
		compatible = "mediatek,mt6761-wdt",
			      "mediatek,mt6589-wdt",
			      "mediatek,toprgu",
			      "syscon", "simple-mfd";
		reg = <0 0x10007000 0 0x1000>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_NONE>;
		#reset-cells = <1>;
		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x24>;
			mask = <0xF>;
			mode-charger = <BOOT_CHARGER>;
			mode-recovery = <BOOT_RECOVERY>;
			mode-bootloader = <BOOT_BOOTLOADER>;
			mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
			mode-kpoc = <BOOT_KPOC>;
			mode-ddr-reserve = <BOOT_DDR_RSVD>;
			mode-meta = <BOOT_META>;
			mode-rpmbpk = <BOOT_RPMBPK>;
		};
	};

	chipid@08000000 {
		compatible = "mediatek,chipid";
		reg = <0 0x08000000 0 0x0004>,
		      <0 0x08000004 0 0x0004>,
		      <0 0x08000008 0 0x0004>,
		      <0 0x0800000c 0 0x0004>;
	};

	mobicore {
		compatible = "trustonic,mobicore";
		interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
	};

	tkcore {
	    compatible = "trustkernel,tkcore";
	    interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
		clock-frequency = <13000000>;
		/*used for fpga*/
		/*clock-frequency = <150000000>;*/
	};

	clocks {
		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};

		clk13m: clk13m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <13000000>;
		};

		clk32k: clk32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	hacc@1000a000 {
		compatible = "mediatek,hacc";
		reg = <0 0x1000a000 0 0x1000>;
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
	};

	apirq@1000b000 {
		compatible = "mediatek,apirq";
		reg = <0 0x1000b000 0 0x1000>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
	};

	regulator_vibrator {
		compatible = "regulator-vibrator";
		min-volt = <2300000>;
		max-volt = <3200000>;
		min-limit = <15>;
		max-limit = <15000>;
		vib-supply = <&mt_pmic_vibr_ldo_reg>;
	};

	apmixed: apmixed@1000c000 {
		compatible = "mediatek,mt6761-apmixedsys", "syscon";
		reg = <0 0x1000c000 0 0xe00>;
		#clock-cells = <1>;
	};

	fhctl: fhctl@1000ce00 {
			compatible = "mediatek,mt6761-fhctl";
			reg = <0 0x1000ce00 0 0x100>;
			mediatek,apmixed = <&apmixed>;

			armpll {
				mediatek,fh-id = <0>;
				mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL>;
				mediatek,fh-cpu-pll;
			};

			mainpll {
				mediatek,fh-id = <1>;
				mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
			};

			msdcpll {
				mediatek,fh-id = <2>;
				mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
			};

			mfgpll {
				mediatek,fh-id = <3>;
				mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
			};

			mpll {
				mediatek,fh-id = <5>;
				mediatek,fh-pll-id = <CLK_APMIXED_MPLL>;
			};

			mmpll {
				mediatek,fh-id = <6>;
				mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
			};
	       };

	pwrap: pwrap@1000d000 {
		compatible = "mediatek,mt6761-pwrap", "syscon";
		reg = <0 0x1000d000 0 0x1000>;
		reg-names = "pwrap";
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk26m>, <&infracfg_ao CLK_IFR_PMIC_AP>,
				<&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
		clock-names = "spi", "wrap", "ulposc";

		main_pmic: main_pmic {
			compatible = "mediatek,mt6357";
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupt-parent = <&pio>;
			interrupts = <144 IRQ_TYPE_LEVEL_HIGH 144 0>;

			mtk_battery_oc_throttling {
				compatible =
					"mediatek,mt6357-battery_oc_throttling";
				oc-thd-h = <4670>;
				oc-thd-l = <5500>;
			};
		};
	};

	scp: scp@10500000 {
		compatible = "mediatek,scp";
		status = "okay";
		reg = <0 0x10500000 0 0x40000>,
		      <0 0x105c0000 0 0x3000>,
		      <0 0x105c4000 0 0x1000>,
		      <0 0x105d4000 0 0x6000>;
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
		core_1 = "enable";
		scp_sramSize = <0x00040000>;
		scp_mpuRegionId = <27>;
		scp_feature_tbl = <0 47>,   /* vow */
				  <1 356>,  /* dsp */
				  <2 62>,   /* sensor */
				  <3 47>,   /* mp3 */
				  <4 26>,   /* flp */
				  <5 0>,    /* rtos */
				  <6 200>,  /* speaker */
				  <7 0>,    /* vcore */
				  <8 100>,  /* barge in */
				  <9 10>;   /* vow dump */

		scp_mem_key = "mediatek,reserve-memory-scp_share";
#ifdef CONFIG_MTK_TINYSYS_SCP_LOGGER_SUPPORT
		scp_mem_tbl = <1 0x100000>, /* sensor */
			      <4 0x200000>; /* logger */
#else
		scp_mem_tbl = <1 0x100000>; /* sensor */
#endif
	};

	scp_dvfs {
		compatible = "mediatek,scp_dvfs";
		clocks = <&topckgen CLK_TOP_SCP_SEL>,
			<&clk26m>,
			<&topckgen CLK_TOP_SYSPLL4_D2>,
			<&topckgen CLK_TOP_UNIVPLL2_D2>,
			<&topckgen CLK_TOP_SYSPLL1_D2>,
			<&topckgen CLK_TOP_UNIVPLL1_D2>,
			<&topckgen CLK_TOP_SYSPLL_D3>,
			<&topckgen CLK_TOP_UNIVPLL_D3>;

		clock-names = "clk_mux",
			"clk_pll_0",
			"clk_pll_1",
			"clk_pll_2",
			"clk_pll_3",
			"clk_pll_4",
			"clk_pll_5",
			"clk_pll_6";

		dvfsrc-opp-num = <3>;
		dvfs-opp =
		/*	vcore	vsram	uv	dvfsrc	spm	freq	mux */
		<	0xff	0xff	0xff	0x0	0x0	250	0>,
		<	0xff	0xff	0xff	0x0	0x0	273	3>,
		<	0xff	0xff	0xff	0x2	0x8	330	5>,
		<	0xff	0xff	0xff	0x3	0xC	416	6>;

		pmic = <&main_pmic>;
		pmic-feature = "pmic-vow-lp", "pmic-pmrc";
		/*
		 * feature on off setting.
		 * 1: turns on, 0: turns off.
		 */
		pmic-feature-cfg = <0 0>;

		gpio = <&gpio 1>;
		gpio-feature = "gpio-mode";
		gpio-feature-cfg = <0>;
	};

	sleep_reg_md@1000f000 {
		compatible = "mediatek,sleep_reg_md";
		reg = <0 0x1000f000 0 0x1000>;
	};

	keypad: kp@10010000 {
		compatible = "mediatek,kp";
		reg = <0 0x10010000 0 0x1000>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
		clocks = <&clk26m>;
		clock-names = "kpd";
	};

	mrdump_ext_rst: mrdump_ext_rst {
		compatible = "mediatek, mrdump_ext_rst-eint";
		force_mode = "EINT";
		mode = "IRQ";
		status = "okay";
	};

	touch: touch {
		compatible = "goodix,touch";
	};

	accdet: accdet {
		compatible = "mediatek,pmic-accdet";
	};

	goodix_fp: fingerprint {
		compatible = "mediatek,goodix-fp";
	};

	topmisc@10011000 {
		compatible = "mediatek,topmisc";
		reg = <0 0x10011000 0 0x1000>;
	};

	dvfsrc: dvfsrc@10012000 {
		compatible = "mediatek,mt6761-dvfsrc";
		reg = <0 0x10012000 0 0x1000>,
			<0 0x10006000 0 0x1000>;
		reg-names = "dvfsrc", "spm";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		dvfsrc_freq_opp2: opp2 {
			opp-level = <2>;
		};
		dvfsrc_freq_opp1: opp1 {
			opp-level = <1>;
		};
		dvfsrc_freq_opp0: opp0 {
			opp-level = <0>;
		};

		dvfsrc-up {
			compatible = "mediatek,mt6761-dvfsrc-up";
		};

		dvfsrc-debug {
			compatible = "mediatek,mt6761-dvfsrc-debug";
			required-opps = <&dvfsrc_freq_opp0>,
					<&dvfsrc_freq_opp1>,
					<&dvfsrc_freq_opp2>;
		};

		dvfsrc-met {
			compatible = "mediatek,mt6761-dvfsrc-met";
		};

		qos@00110b80 {
			compatible = "mediatek,mt6761-qos";
			reg = <0 0x00110b80 0 0x80>;
		};
	};

	mbist_ao@10013000 {
		compatible = "mediatek,mbist_ao";
		reg = <0 0x10013000 0 0x1000>;
	};

	apcldmain_ao@10014000 {
		compatible = "mediatek,apcldmain_ao";
		reg = <0 0x10014000 0 0x400>;
	};

	apcldmaout_ao@10014400 {
		compatible = "mediatek,apcldmaout_ao";
		reg = <0 0x10014400 0 0x400>;
	};

	apcldmamisc_ao@10014800 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014800 0 0x400>;
	};

	apcldmamisc_ao@10014c00 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014c00 0 0x400>;
	};

	aes_top0@10016000 {
		compatible = "mediatek,aes_top0";
		reg = <0 0x10016000 0 0x1000>;
	};

	timer: timer@10017000 {
		compatible = "mediatek,sys_timer",
			     "mediatek,mt6761-timer",
			     "mediatek,mt6765-timer";
		reg = <0 0x10017000 0 0x1000>;
		reg-names = "sys_timer_base";
		interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk13m>;
	};

	modem_temp_share@10018000 {
		compatible = "mediatek,modem_temp_share";
		reg = <0 0x10018000 0 0x1000>;
	};

	security_ao@1001a000 {
		compatible = "mediatek,security_ao";
		reg = <0 0x1001a000 0 0x1000>;
	};

	topckgen_ao@1001b000 {
		compatible = "mediatek,topckgen_ao";
		reg = <0 0x1001b000 0 0x1000>;
	};

	iocfg_0@10002000 {
		compatible = "mediatek,iocfg_0";
		reg = <0 0x10002000 0 0x200>;
	};

	iocfg_1@10002200 {
		compatible = "mediatek,iocfg_1";
		reg = <0 0x10002200 0 0x200>;
	};

	iocfg_2@10002400 {
		compatible = "mediatek,iocfg_2";
		reg = <0 0x10002400 0 0x200>;
	};

	iocfg_3@10002600 {
		compatible = "mediatek,iocfg_3";
		reg = <0 0x10002600 0 0x200>;
	};

	iocfg_4@10002800 {
		compatible = "mediatek,iocfg_4";
		reg = <0 0x10002800 0 0x200>;
	};

	iocfg_5@10002a00 {
		compatible = "mediatek,iocfg_5";
		reg = <0 0x10002a00 0 0x200>;
	};

	mdcldmain_ao@10015000 {
		compatible = "mediatek,mdcldmain_ao";
		reg = <0 0x10015000 0 0x400>;
	};

	mdcldmaout_ao@10015400 {
		compatible = "mediatek,mdcldmaout_ao";
		reg = <0 0x10015400 0 0x400>;
	};

	mdcldmamisc_ao@10015800 {
		compatible = "mediatek,mdcldmamisc_ao";
		reg = <0 0x10015800 0 0x400>;
	};

	sys_cirq@10204000 {
		compatible = "mediatek,sys_cirq";
		reg = <0 0x10204000 0 0x1000>;
		mediatek,cirq_num = <209>;
		mediatek,spi_start_offset = <16>;
		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10200000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200000 0 0x200>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcucfg@10200200 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200200 0 0x200>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10200400 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200400 0 0x200>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcucfg@10200600 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200600 0 0x200>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcucfg@10200800 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200800 0 0x200>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcucfg@10200a00 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200a00 0 0x300>;
		interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10200f00 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10200f00 0 0x100>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10201000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10201000 0 0x1000>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10202000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10202000 0 0x1000>;
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg@10203000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x10203000 0 0x1000>;
		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>;
	};

	mcucfg_mp0_counter@10200000 {
		compatible = "mediatek,mcucfg_mp0_counter";
		reg = <0 0x10200000 0 0x4000>;
	};

	iommu: m4u@10205000 {
		cell-index = <0>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x10205000 0 0x1000>;
		mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
		#iommu-cells = <1>;
	};

	devapc@10207000 {
		compatible = "mediatek,devapc";
		reg = <0 0x10207000 0 0x1000>;
		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_DEVICE_APC>;
		clock-names = "devapc-infra-clock";
	};

	hwrng: hwrng {
		compatible = "mediatek,mt67xx-rng";
	};

	bus_dbg@10208000 {
		compatible = "mediatek,bus_dbg-v2";
		reg = <0 0x10208000 0 0x1000>,
			<0 0x10001000 0 0x1000>;
		mediatek,bus_dbg_con_offset = <0x2fc>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
	};

	ap_ccif0@10209000 {
		compatible = "mediatek,ap_ccif0";
		reg = <0 0x10209000 0 0x1000>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif0@1020a000 {
		compatible = "mediatek,md_ccif0";
		reg = <0 0x1020a000 0 0x1000>;
	};

	ap_ccif1@1020b000 {
		compatible = "mediatek,ap_ccif1";
		reg = <0 0x1020b000 0 0x1000>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif1@1020c000 {
		compatible = "mediatek,md_ccif1";
		reg = <0 0x1020c000 0 0x1000>;
	};

	infra_mbist@1020d000 {
		compatible = "mediatek,infra_mbist";
		reg = <0 0x1020d000 0 0x1000>;
	};

	infracfg@1020e000 {
		compatible = "mediatek,infracfg";
		reg = <0 0x1020e000 0 0x1000>;
	};

	trng@1020f000 {
		compatible = "mediatek,trng";
		reg = <0 0x1020f000 0 0x1000>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>;
	};

	dxcc_sec@10210000 {
		compatible = "mediatek,dxcc_sec";
		reg = <0 0x10210000 0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
	};

	mcupm_sram2@10211000 {
		compatible = "mediatek,mcupm_sram2";
		reg = <0 0x10211000 0 0x1000>;
	};

	cq_dma@10212000 {
		compatible = "mediatek,mt-cqdma-v1";
		reg = <0 0x10212000 0 0x80>,
			<0 0x10212080 0 0x80>,
			<0 0x10212100 0 0x68>;
		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_LOW>,
				<GIC_SPI 58 IRQ_TYPE_LEVEL_LOW>,
				<GIC_SPI 59 IRQ_TYPE_LEVEL_LOW>;
		nr_channel = <3>;
		keep_clock_ao = "yes";
		clocks = <&infracfg_ao CLK_IFR_CQ_DMA>;
		clock-names = "cqdma";
	};

	mcupm_sram3@10213000 {
		compatible = "mediatek,mcupm_sram3";
		reg = <0 0x10213000 0 0x1000>;
	};

	sramrom@10214000 {
		compatible = "mediatek,sramrom";
		reg = <0 0x10214000 0 0x1000>;
	};

	mcupm_reg@10216000 {
		compatible = "mediatek,mcupm_reg";
		reg = <0 0x10216000 0 0x1000>;
	};

	mcupm_sram0@10217000 {
		compatible = "mediatek,mcupm_sram0";
		reg = <0 0x10217000 0 0x1000>;
	};

	mcupm_sram1@10218000 {
		compatible = "mediatek,mcupm_sram1";
		reg = <0 0x10218000 0 0x1000>;
	};

	emi@10219000 {
		compatible = "mediatek,emi";
		reg = <0 0x10219000 0 0x1000>, /* CEN EMI */
			<0 0x10226000 0 0x1000>, /* EMI MPU */
			<0 0x1022d000 0 0x1000>, /* CHA EMI */
			<0 0x10235000 0 0x1000>; /* CHB EMI */
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; /* MPU */
	};

	apcldmain@1021b000 {
		compatible = "mediatek,apcldmain";
		reg = <0 0x1021b000 0 0x100>;
	};

	apcldmaout@1021b400 {
		compatible = "mediatek,apcldmaout";
		reg = <0 0x1021b400 0 0x100>;
	};

	apcldmamisc@1021b800 {
		compatible = "mediatek,apcldmamisc";
		reg = <0 0x1021b800 0 0x100>;
		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
	};

	mdcldmain@1021c000 {
		compatible = "mediatek,mdcldmain";
		reg = <0 0x1021c000 0 0x400>;
	};

	mdcldmaout@1021c400 {
		compatible = "mediatek,mdcldmaout";
		reg = <0 0x1021c400 0 0x400>;
	};

	mdcldmamisc@1021c800 {
		compatible = "mediatek,mdcldmamisc";
		reg = <0 0x1021c800 0 0x1000>;
	};

 ccifdriver:ccifdriver@10209000 {
		compatible = "mediatek,ccci_ccif";
		reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
			<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
		mediatek,sram_size = <512>;
		/*CCIF0 174/206, CCIF0 175/207*/
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_CCIF_AP>,
			<&infracfg_ao CLK_IFR_CCIF_MD>,
			<&infracfg_ao CLK_IFR_CCIF1_AP>,
			<&infracfg_ao CLK_IFR_CCIF1_MD>,
			<&infracfg_ao CLK_IFR_CCIF2_AP>,
			<&infracfg_ao CLK_IFR_CCIF2_MD>;
		clock-names = "infra-ccif-ap",
			"infra-ccif-md",
			"infra-ccif1-ap",
			"infra-ccif1-md",
			"infra-ccif2-ap",
			"infra-ccif2-md";
	};

	cldmadriver:cldmadriver@10014000 {
		compatible = "mediatek,ccci_cldma";
		reg = <0 0x10014000 0 0x1000>, /*AP_CLDMA_AO "mediatek,apcldmain_ao*/
			  <0 0x1021b000 0 0x1000>; /*AP_CLDMA_PDN "mediatek,apcldmain*/
		/* IRQ_CLDMA "mediatek,apcldmamisc" */
		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
		mediatek,cldma_capability = <6>;
		mediatek,md_generation = <6293>;
		mediatek,platform = <6761>;
		clocks = <&infracfg_ao CLK_IFR_CLDMA_BCLK>;
		clock-names = "infra-cldma-bclk";
		cldma-infracfg = <&infracfg_ao>;
	};

	mddriver:mddriver@10014000 {
		compatible = "mediatek,mddriver", "mediatek,mddriver-mt6761";
		/*
		 * AP_CLDMA_AO "mediatek,apcldmain_ao"
		 * AP_CLDMA_PDN "mediatek,apcldmain"
		 * AP_CCIF_BASE "mediatek,ap_ccif0"
		 * MD_CCIF_BASE "mediatek,md_ccif0"
		 */
		reg =	<0 0x10014000 0 0x1000>,
			<0 0x1021b000 0 0x1000>,
			<0 0x10209000 0 0x1000>,
			<0 0x1020a000 0 0x1000>;
		/*
		 * IRQ_CLDMA "mediatek,apcldmamisc"
		 * IRQ_CCIF0 "mediatek,ap_ccif0"
		 * IRQ_CCIF1
		 * IRQ_MDWDT "mediatek,md_rgu"
		 */
		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 205 IRQ_TYPE_EDGE_FALLING>;
		mediatek,mdhif_type = <3>; /* bit0~3: CLDMA|CCIF|DPMAIF */
		mediatek,md_id = <0>;
		mediatek,ap_plat_info = <6761>;
		mediatek,md_generation = <6293>;
		mediatek,offset_apon_md1 = <0x1C24>;
		mediatek,cldma_capability = <6>;
		clocks = <&scpsys SCP_SYS_MD1>,
			<&infracfg_ao CLK_IFR_CLDMA_BCLK>,
			<&infracfg_ao CLK_IFR_CCIF_AP>,
			<&infracfg_ao CLK_IFR_CCIF_MD>,
			<&infracfg_ao CLK_IFR_CCIF1_AP>,
			<&infracfg_ao CLK_IFR_CCIF1_MD>,
			<&infracfg_ao CLK_IFR_CCIF2_AP>,
			<&infracfg_ao CLK_IFR_CCIF2_MD>;
		clock-names = "scp-sys-md1-main",
			"infra-cldma-bclk",
			"infra-ccif-ap",
			"infra-ccif-md",
			"infra-ccif1-ap",
			"infra-ccif1-md",
			"infra-ccif2-ap",
			"infra-ccif2-md";
		_vmodem-supply = <&mt_pmic_vmodem_buck_reg>;
		_vcore-supply = <&mt_pmic_vcore_buck_reg>;
		ccci-infracfg = <&infracfg_ao>;
	};
	md_auxadc:md_auxadc {
		compatible = "mediatek,md_auxadc";
		io-channels = <&auxadc 2>;
		io-channel-names = "md-channel",
			"md-battery";
	};

	bpi_bsi_slv0@1021e000 {
		compatible = "mediatek,bpi_bsi_slv0";
		reg = <0 0x1021e000 0 0x1000>;
	};

	bpi_bsi_slv1@1021f000 {
		compatible = "mediatek,bpi_bsi_slv1";
		reg = <0 0x1021f000 0 0x6000>;
	};

	bpi_bsi_slv2@10225000 {
		compatible = "mediatek,bpi_bsi_slv2";
		reg = <0 0x10225000 0 0x1000>;
	};

	dvfsp@10227000 {
		compatible = "mediatek,dvfsp";
		reg = <0 0x10227000 0 0x1000>;
	};

	dvfsp@00110c00 {
		compatible = "mediatek,mt6761-dvfsp";
		reg = <0 0x00110c00 0 0x1400>,
		      <0 0x00110c00 0 0x1400>;
		nvmem-cells = <&efuse_segment>;
		nvmem-cell-names = "efuse_segment_cell";
	};

	dramc@1022a000 {
		compatible = "mediatek,dramc";
		reg = <0 0x1022a000 0 0x2000>, /* DRAMC AO CHA */
			<0 0x10232000 0 0x2000>, /* DRAMC AO CHB */
			<0 0x1022c000 0 0x1000>, /* DRAMC NAO CHA */
			<0 0x10234000 0 0x1000>, /* DRAMC NAO CHB */
			<0 0x10228000 0 0x2000>, /* DDRPHY AO CHA */
			<0 0x10230000 0 0x2000>, /* DDRPHY AO CHB */
			<0 0x1022e000 0 0x1000>, /* DDRPHY NAO CHA */
			<0 0x10236000 0 0x1000>; /* DDRPHY NAO CHB */
	};

	gce: gce@10238000 {
		compatible = "mediatek,gce", "syscon";
		reg = <0 0x10238000 0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		g3d_config_base = <0x13000000 0 0xffff0000>;
		mmsys_config_base = <0x14000000 1 0xffff0000>;
		disp_dither_base = <0x14010000 2 0xffff0000>;
		mm_na_base = <0x14020000 3 0xffff0000>;
		imgsys_base = <0x15020000 4 0xffff0000>;
		vdec_gcon_base = <0x18800000 5 0xffff0000>;
		venc_gcon_base = <0x18810000 6 0xffff0000>;
		conn_peri_base = <0x18820000 7 0xffff0000>;
		topckgen_base = <0x18830000 8 0xffff0000>;
		kp_base = <0x18840000 9 0xffff0000>;
		scp_sram_base = <0x10000000 10 0xffff0000>;
		infra_na3_base = <0x10010000 11 0xffff0000>;
		infra_na4_base = <0x10020000 12 0xffff0000>;
		scp_base = <0x10030000 13 0xffff0000>;
		mcucfg_base = <0x10040000 14 0xffff0000>;
		gcpu_base = <0x10050000 15 0xffff0000>;
		usb0_base = <0x10200000 16 0xffff0000>;
		usb_sif_base = <0x10280000 17 0xffff0000>;
		audio_base = <0x17000000 18 0xffff0000>;
		vdec_base = <0x17010000 19 0xffff0000>;
		msdc2_base = <0x17020000 20 0xffff0000>;
		vdec1_base = <0x17030000 21 0xffff0000>;
		msdc3_base = <0x18000000 22 0xffff0000>;
		ap_dma_base = <0x18010000 23 0xffff0000>;
		gce_base = <0x18020000 24 0xffff0000>;
		vdec2_base = <0x18040000 25 0xffff0000>;
		vdec3_base = <0x18050000 26 0xffff0000>;
		camsys_base = <0x18080000 27 0xffff0000>;
		camsys1_base = <0x180a0000 28 0xffff0000>;
		camsys2_base = <0x180b0000 29 0xffff0000>;
		pwm_sw_base = <0x1100e000 99 0xffff0000>;
		mipitx0_base = <0x11c80000 99 0xffff0000>;
		mdp_rdma0_sof = <0>;
		mdp_ccorr0_sof = <1>;
		mdp_rsz0_sof = <2>;
		mdp_rsz1_sof = <3>;
		mdp_wdma_sof = <4>;
		mdp_wrot0_sof = <5>;
		mdp_tdshp0_sof = <6>;
		disp_ovl0_sof = <7>;
		disp_2l_ovl0_sof = <8>;
		disp_rdma0_sof = <9>;
		disp_wdma0_sof = <10>;
		disp_color0_sof = <11>;
		disp_ccorr0_sof = <12>;
		disp_aal0_sof = <13>;
		disp_gamma0_sof = <14>;
		disp_dither0_sof = <15>;
		disp_dsi0_sof = <16>;
		disp_rsz0_sof = <17>;
		img_dl_relay_sof = <18>;
		disp_pwm0_sof = <19>;
		mdp_rdma0_frame_done = <20>;
		mdp_ccorr0_frame_done = <21>;
		mdp_rsz0_frame_done = <22>;
		mdp_rsz1_frame_done = <23>;
		mdp_wrot0_write_frame_done = <24>;
		mdp_wdma_frame_done = <25>;
		mdp_tdshp0_frame_done = <26>;
		disp_ovl0_frame_done = <27>;
		disp_2l_ovl0_frame_done = <28>;
		disp_rsz0_frame_done = <29>;
		disp_rdma0_frame_done = <30>;
		disp_wdma0_frame_done = <31>;
		disp_color0_frame_done = <32>;
		disp_ccorr0_frame_done = <33>;
		disp_aal0_frame_done = <34>;
		disp_gamma0_frame_done = <35>;
		disp_dither0_frame_done = <36>;
		disp_dsi0_frame_done = <37>;
		stream_done_0 = <130>;
		stream_done_1 = <131>;
		stream_done_2 = <132>;
		stream_done_3 = <133>;
		stream_done_4 = <134>;
		stream_done_5 = <135>;
		stream_done_6 = <136>;
		stream_done_7 = <137>;
		stream_done_8 = <138>;
		stream_done_9 = <139>;
		buf_underrun_event_0 = <140>;
		dsi0_te_event = <141>;
		dsi0_irq_event = <142>;
		dsi0_done_event = <143>;
		disp_wdma0_rst_done = <147>;
		mdp_wdma_rst_done = <148>;
		mdp_wrot0_rst_done = <149>;
		mdp_rdma0_rst_done = <151>;
		disp_ovl0_frame_rst_done_pusle = <152>;
		dip_cq_thread2_frame_done = <257>;
		dip_cq_thread1_frame_done = <258>;
		dip_cq_thread0_frame_done = <259>;
		isp_frame_done_p1_1 = <260>;
		isp_frame_done_p1_0 = <261>;
		camsv_0_pass1_done = <262>;
		camsv_1_pass1_done = <263>;
		seninf_0_fifo_full = <264>;
		seninf_1_fifo_full = <265>;
		seninf_2_fifo_full = <266>;
		seninf_3_fifo_full = <267>;
		seninf_4_fifo_full = <268>;
		seninf_5_fifo_full = <269>;
		seninf_6_fifo_full = <270>;
		seninf_7_fifo_full = <271>;
		venc_done = <289>;
		jpgenc_done = <290>;
		jpgdec_done = <291>;
		venc_mb_done = <292>;
		venc_128byte_cnt_done = <293>;
		max_prefetch_cnt = <1>;
		prefetch_size = <96>;
		sram_size_cpr_64 = <64>;
		mmsys_config = <&dispsys_config>;
		mdp_rdma0 = <&mdp_rdma0>;
		mdp_rsz0 = <&mdp_rsz0>;
		mdp_rsz1 = <&mdp_rsz1>;
		mdp_wdma0 = <&mdp_wdma0>;
		mdp_wrot0 = <&mdp_wrot0>;
		mdp_tdshp0 = <&mdp_tdshp0>;
		mdp_color0 = <&disp_color0>;
		mdp_ccorr0 = <&mdp_ccorr>;
		mm_mutex = <&disp_mutex0>;
		sram_share_cnt = <1>;
		sram_share_engine = <10>;
		sram_share_event = <710>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>;
		clock-names = "GCE", "GCE_TIMER";
		mediatek,mailbox-gce = <&gce_mbox>;
		thread_count = <16>;
		secure_thread = <8 10>;
		mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 1 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 2 0 CMDQ_THR_PRIO_5>,
			<&gce_mbox 3 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 5 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 6 200 CMDQ_THR_PRIO_3>,
			<&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
			<&gce_mbox_svp 8 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox_svp 9 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox_svp 10 0 CMDQ_THR_PRIO_1>,
#else
			<&gce_mbox 8 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 9 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 10 0 CMDQ_THR_PRIO_1>,
#endif
			<&gce_mbox 11 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 13 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
			<&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
#else
			<&gce_mbox 15 0 CMDQ_THR_PRIO_1>;
#endif
	};

	gce_mbox: gce_mbox@10238000 {
		compatible = "mediatek,mt6761-gce";
		reg = <0 0x10238000 0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		#mbox-cells = <3>;
		#gce-event-cells = <1>;
		#gce-subsys-cells = <2>;
		default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>;
		clock-names = "gce", "gce-timer";
	};

#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
	gce_mbox_svp: gce_mbox_svp@10238000 {
		compatible = "mediatek,mailbox-gce-svp";
		reg = <0 0x10238000 0 0x4000>;
		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
		#mbox-cells = <3>;
		clocks = <&infracfg_ao CLK_IFR_GCE>,
			<&infracfg_ao CLK_IFR_GCE_26M>;
		clock-names = "gce", "GCE_TIMER";
	};
#endif

	ap_ccif2@1023c000 {
		compatible = "mediatek,ap_ccif2";
		reg = <0 0x1023c000 0 0x1000>;
		interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif2@1023d000 {
		compatible = "mediatek,md_ccif2";
		reg = <0 0x1023d000 0 0x1000>;
	};

	ap_ccif3@1023e000 {
		compatible = "mediatek,ap_ccif3";
		reg = <0 0x1023e000 0 0x1000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
	};

	md_ccif3@1023f000 {
		compatible = "mediatek,md_ccif3";
		reg = <0 0x1023f000 0 0x1000>;
	};

	sspm@10440000 {
		compatible = "mediatek,mt6761-sspm";
		reg = <0 0x10440000 0 0x10000>,
			<0 0x10450000 0 0x100>,
			<0 0x10451000 0 0x8>,
			<0 0x10460000 0 0x100>,
			<0 0x10461000 0 0x8>,
			<0 0x10470000 0 0x100>,
			<0 0x10471000 0 0x8>,
			<0 0x10480000 0 0x100>,
			<0 0x10481000 0 0x8>,
			<0 0x10490000 0 0x100>,
			<0 0x10491000 0 0x8>;

		reg-names = "cfgreg",
			"mbox0_base",
			"mbox0_ctrl",
			"mbox1_base",
			"mbox1_ctrl",
			"mbox2_base",
			"mbox2_ctrl",
			"mbox3_base",
			"mbox3_ctrl",
			"mbox4_base",
			"mbox4_ctrl";

		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "ipc",
			"mbox0",
			"mbox1",
			"mbox2",
			"mbox3",
			"mbox4";
	};

	gic500@0c000000 {
		compatible = "mediatek,gic500";
		reg = <0 0x0c000000 0 0x400000>;
	};

	gic_cpu@0c400000 {
		compatible = "mediatek,gic_cpu";
		reg = <0 0x0c400000 0 0x40000>;
	};

	dfd@10200b00 {
		compatible = "mediatek,dfd";
		reg = <0 0x10200b00 0 0x10000>;

		mediatek,enabled = <1>;
		mediatek,chain_length = <0x61a8>;
		mediatek,rg_dfd_timeout = <0xa0>;
		mediatek,check_dfd_support = <1>;
		mediatek,dfd_infra_base = <0x390>;
		mediatek,dfd_ap_addr_offset = <24>;
		mediatek,dfd_latch_offset = <0x48>;
		reg_base = <&toprgu>;
	};

	dbg_cti@0d020000 {
		compatible = "mediatek,dbg_cti";
		reg = <0 0x0d020000 0 0x10000>;
	};

	dbg_etr@0d030000 {
		compatible = "mediatek,dbg_etr";
		reg = <0 0x0d030000 0 0x10000>;
	};

	dbg_funnel@0d040000 {
		compatible = "mediatek,dbg_funnel";
		reg = <0 0x0d040000 0 0x10000>;
	};

	dbg_dem@0d0a0000 {
		compatible = "mediatek,dbg_dem";
		reg = <0 0x0d0a0000 0 0x10000>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
	};

	dbg_mdsys1@0d0c0000 {
		compatible = "mediatek,dbg_mdsys1";
		reg = <0 0x0d0c0000 0 0x40000>;
	};

	dbg_apmcu_mp0@0d400000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d400000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d410000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d410000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d420000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d420000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d430000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d430000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d440000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d440000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d510000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d510000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d520000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d520000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d530000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d530000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d540000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d540000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d610000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d610000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d620000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d620000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d630000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d630000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d640000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d640000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d710000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d710000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d720000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d720000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d730000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d730000 0 0x1000>;
	};

	dbg_apmcu_mp0@0d740000 {
		compatible = "mediatek,dbg_apmcu_mp0";
		reg = <0 0x0d740000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d800000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d800000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d810000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d810000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d820000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d820000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d830000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d830000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d840000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d840000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d910000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d910000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d920000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d920000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d930000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d930000 0 0x1000>;
	};

	dbg_apmcu_mp1@0d940000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0d940000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da10000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da10000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da20000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da20000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da30000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da30000 0 0x1000>;
	};

	dbg_apmcu_mp1@0da40000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0da40000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db10000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db10000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db20000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db20000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db30000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db30000 0 0x1000>;
	};

	dbg_apmcu_mp1@0db40000 {
		compatible = "mediatek,dbg_apmcu_mp1";
		reg = <0 0x0db40000 0 0x1000>;
	};

	ap_dma@11000000 {
		compatible = "mediatek,ap_dma";
		reg = <0 0x11000000 0 0x1000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_LOW>;
	};

	auxadc: auxadc@11001000 {
		compatible = "mediatek,mt6765-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_FALLING>;
		clocks = <&infracfg_ao CLK_IFR_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		/* Auxadc efuse calibration */
		/* 1. Auxadc cali on/off bit shift */
		mediatek,cali-en-bit = <20>;
		/* 2. Auxadc cali ge bits shift */
		mediatek,cali-ge-bit = <10>;
		/* 3. Auxadc cali oe bits shift */
		mediatek,cali-oe-bit = <0>;
		/* 4. Auxadc cali efuse reg offset */
		mediatek,cali-efuse-reg-offset = <0x1a8>;
		nvmem = <&efuse>;
		nvmem-names = "mtk_efuse";
		#interconnect-cells = <1>;
	};

	apdma: dma-controller@11000580 {
		compatible = "mediatek,mt6577-uart-dma";
		reg = <0 0x11000680 0 0x80>,
		      <0 0x11000700 0 0x80>,
		      <0 0x11000780 0 0x80>,
		      <0 0x11000800 0 0x80>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 60 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "apdma";
		dma-requests = <4>;
		#dma-bits = <34>;
		#dma-cells = <1>;
	};

	uart0: serial@11020000 {
		compatible = "mediatek,mt6761-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x1000>;
		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&clk26m>, <&infracfg_ao CLK_IFR_UART0>;
		clock-names = "baud", "bus";
		dmas = <&apdma 0 &apdma 1>;
		dma-names = "tx", "rx";
	};

	uart1: serial@11030000 {
		compatible = "mediatek,mt6761-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x1000>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&clk26m>, <&infracfg_ao CLK_IFR_UART1>;
		clock-names = "baud", "bus";
		dmas = <&apdma 2 &apdma 3>;
		dma-names = "tx", "rx";
	};

	pwm: pwm@11006000 {
		compatible = "mediatek,pwm";
		reg = <0 0x11006000 0 0x1000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_PWM1>,
				<&infracfg_ao CLK_IFR_PWM2>,
				<&infracfg_ao CLK_IFR_PWM3>,
				<&infracfg_ao CLK_IFR_PWM4>,
				<&infracfg_ao CLK_IFR_PWM5>,
				<&infracfg_ao CLK_IFR_RG_PWM_FBCLK6>,
				<&infracfg_ao CLK_IFR_PWM_HCLK>,
				<&infracfg_ao CLK_IFR_PWM>;
		clock-names = "PWM1-main", "PWM2-main",
				"PWM3-main", "PWM4-main",
				"PWM5-main", "PWM6-main",
				"PWM-HCLK-main", "PWM-main";
	};

	i2c_common: i2c_common {
		compatible = "mediatek,i2c_common";
		dma_support = /bits/ 8 <2>;
		idvfs = /bits/ 8 <1>;
		set_dt_div = /bits/ 8 <1>;
		check_max_freq = /bits/ 8 <1>;
		ver = /bits/ 8 <2>;
		set_ltiming = /bits/ 8 <1>;
		ext_time_config = /bits/ 16 <0x1801>;
		cnt_constraint = /bits/ 8 <1>;
	};

	i2c0: i2c0@11007000 {
		compatible = "mediatek,i2c";
		id = <0>;
		reg = <0 0x11007000 0 0x1000>,
			<0 0x11000080 0 0x80>;
		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <83>;
		sda-gpio-id = <82>;
		gpio_start = <0x10002a00>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x50>;
		rsel_cfg = <0x70>;
		aed = <0x1a>;
		mediatek,hs_only;
	};

	i2c1: i2c1@11008000 {
		compatible = "mediatek,i2c";
		id = <1>;
		reg = <0 0x11008000 0 0x1000>,
			<0 0x11000100 0 0x80>;
		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <84>;
		sda-gpio-id = <81>;
		gpio_start = <0x10002a00>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x50>;
		rsel_cfg = <0x70>;
		aed = <0x1a>;
		mediatek,hs_only;
	};

	i2c2: i2c2@11009000 {
		compatible = "mediatek,i2c";
		id = <2>;
		reg = <0 0x11009000 0 0x1000>,
			<0 0x11000180 0 0x180>;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <103>;
		sda-gpio-id = <104>;
		gpio_start = <0x10002800>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x60>;
		rsel_cfg = <0xa0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
		mediatek,hs_only;
	};

	i2c3: i2c3@1100f000 {
		compatible = "mediatek,i2c";
		id = <3>;
		reg = <0 0x1100f000 0 0x1000>,
			<0 0x11000300 0 0x100>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
		<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <50>;
		sda-gpio-id = <51>;
		gpio_start = <0x10002600>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x90>;
		rsel_cfg = <0xb0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		mediatek,hs_only;
	};

	i2c4: i2c4@11011000 {
		compatible = "mediatek,i2c";
		id = <4>;
		reg = <0 0x11011000 0 0x1000>,
			<0 0x11000400 0 0x180>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <105>;
		sda-gpio-id = <106>;
		gpio_start = <0x10002800>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x60>;
		rsel_cfg = <0xa0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
		mediatek,hs_only;
	};

	i2c5: i2c5@11016000 {
		compatible = "mediatek,i2c";
		id = <5>;
		reg = <0 0x11016000 0 0x1000>,
			<0 0x11000580 0 0x80>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <48>;
		sda-gpio-id = <49>;
		gpio_start = <0x10002600>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x90>;
		rsel_cfg = <0xb0>;
		aed = <0x1a>;
		mediatek,hs_only;
	};

	i2c6: i2c6@1100d000 {
		compatible = "mediatek,i2c";
		id = <6>;
		reg = <0 0x1100d000 0 0x1000>,
			<0 0x11000600 0 0x80>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
			<&infracfg_ao CLK_IFR_AP_DMA>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <161>;
		sda-gpio-id = <162>;
		gpio_start = <0x10002c00>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x50>;
		rsel_cfg = <0x70>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
		mediatek,hs_only;
	};
	i2c7: i2c7 {};
	i2c8: i2c8 {};
	i2c9: i2c9 {};

	spi0: spi0@1100a000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x1100a000 0 0x1000>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	therm_ctrl@1100b000 {
		compatible = "mediatek,therm_ctrl";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_THERM>;
		clock-names = "therm-main";
		nvmem = <&efuse>;
		nvmem-names = "mtk_efuse";
		nvmem-cells = <&cpu_freq_segment>,
					<&thermal_efuse>;
		nvmem-cell-names = "cpu_freq_segment_cell",
						"thermal_efuse_cell";
	};
	tboard_thermistor1: thermal-sensor1 {
		compatible = "mediatek,mtboard-thermistor1";
		io-channels = <&auxadc 0>;
		io-channel-names = "thermistor-ch0";
		interconnects = <&auxadc 0>;
	};

	tboard_thermistor2: thermal-sensor2 {
		compatible = "mediatek,mtboard-thermistor2";
		io-channels = <&auxadc 1>;
		io-channel-names = "thermistor-ch1";
		interconnects = <&auxadc 1>;
	};
	tboard_thermistor3: thermal-sensor3 {
		compatible = "mediatek,mtboard-thermistor3";
		io-channels = <&auxadc 2>;
		io-channel-names = "thermistor-ch2";
		interconnects = <&auxadc 2>;
	};
	eem_fsm@1100b000 {
		compatible = "mediatek,eem_fsm";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_LOW>;
		nvmem = <&efuse>;
		nvmem-names = "mtk_efuse";
		nvmem-cells = <&efuse_segment>;
		nvmem-cell-names = "efuse_segment_cell";
	};

	btif@1100c000 {
		compatible = "mediatek,btif";
			/*btif base*/
		reg = <0 0x1100c000 0 0x1000>,
			/*btif tx dma base*/
		    <0 0x11000880 0 0x80>,
			/*btif rx dma base*/
		    <0 0x11000900 0 0x80>;
			/*btif irq, IRQS_Sync ID, btif_irq_b*/
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
			/*btif tx dma irq*/
			   <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>,
			/*btif rx dma irq*/
			   <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg_ao CLK_IFR_BTIF>,
			/*btif clock*/
		       <&infracfg_ao CLK_IFR_AP_DMA>;
			/*ap dma clock*/
		clock-names = "btifc","apdmac";
	};

	consys: consys@18002000 {
		compatible = "mediatek,mt6761-consys";
		#address-cells = <2>;
		#size-cells = <2>;
			/*CONN_MCU_CONFIG_BASE */
		reg = <0 0x18002000 0 0x1000>,
			/*TOP_RGU_BASE */
		    <0 0x10007000 0 0x0100>,
			/*INFRACFG_AO_BASE */
		    <0 0x10001000 0 0x1000>,
			/*SPM_BASE */
		    <0 0x10006000 0 0x1000>,
			/*CONN_HIF_ON_BASE */
		    <0 0x18007000 0 0x1000>,
			/*CONN_TOP_MISC_OFF_BASE */
		    <0 0x180b1000 0 0x1000>,
			/*CONN_MCU_CFG_ON_BASE */
		    <0 0x180a3000 0 0x1000>,
			/*CONN_MCU_CIRQ_BASE */
		    <0 0x180a5000 0 0x800>,
			/*CONN_TOP_MISC_ON_BASE */
		    <0 0x180c1000 0 0x1000>,
			/*CONN_HIF_PDMA_BASE */
		    <0 0x18004000 0 0x1000>;
			/*BGF_EINT conn2ap_btif_wakeup_out_b*/
		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>,
			/*WDT_EINT conn_wdt_irq_b*/
			   <GIC_SPI 213 IRQ_TYPE_LEVEL_LOW>,
			/*conn2ap_sw_irq*/
			   <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
		clocks = <&scpsys SCP_SYS_CONN>;
		clock-names = "conn";
		pmic = <&main_pmic>;
		memory-region = <&consys_mem>;
	};

	wifi@18000000 {
		compatible = "mediatek,wifi";
		reg = <0 0x18000000 0 0x100000>;
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_LOW>;
		memory-region = <&wifi_mem>;
	};

	disp_pwm@1100e000 {
		compatible = "mediatek,disp_pwm";
		reg = <0 0x1100e000 0 0x1000>;
	};

	spi1: spi1@11010000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11010000 0 0x1000>;
		interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi2: spi2@11012000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11012000 0 0x1000>;
		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi3: spi3@11013000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11013000 0 0x1000>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI3>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi4: spi4@11014000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11014000 0 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI4>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi5: spi5@11015000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11015000 0 0x1000>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
				<&topckgen CLK_TOP_SPI_SEL>,
				<&infracfg_ao CLK_IFR_SPI5>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	imp_iic@11017000 {
		compatible = "mediatek,imp_iic";
		reg = <0 0x11017000 0 0x1000>;
	};

	nfi@11018000 {
		compatible = "mediatek,nfi";
		reg = <0 0x11018000 0 0x1000>;
	};

	nfiecc@11019000 {
		compatible = "mediatek,nfiecc";
		reg = <0 0x11019000 0 0x1000>;
	};

	usb: usb0@11200000 {
		compatible = "mediatek,mt6761-usb20";
		reg = <0 0x11200000 0 0x10000>,
		      <0 0x11cc0000 0 0x10000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_LOW>;
		mode = <2>;
		multipoint = <1>;
		num_eps = <16>;
		clocks = <&infracfg_ao CLK_IFR_ICUSB>,
			<&topckgen CLK_TOP_USB_TOP_SEL>,
			<&topckgen CLK_TOP_UNIVPLL3_D4>;
		clock-names = "usb0",
			"usb0_clk_top_sel",
			"usb0_clk_univpll3_d4";
		pericfg= <&pericfg>;
		interrupt-names = "mc";
		phys = <&u2port0 PHY_TYPE_USB2>;
		dr_mode = "otg";
		usb-role-switch;
	};

	u2phy0: usb-phy@11210000 {
		compatible = "mediatek,generic-tphy-v1";
		reg = <0 0x11cc0000 0 0x0800>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "okay";
		u2port0: usb-phy@11210000 {
			reg = <0 0x11cc0800 0 0x100>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			nvmem-cells = <&u2_phy_data>;
			nvmem-cell-names = "intr_cal";
			nvmem-cell-masks = <0x1f>;
			status = "okay";
		};
	};

	msdc0:msdc@11230000 {
		compatible = "mediatek,msdc";
		reg = <0 0x11230000 0 0x10000>;
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
	};

	msdc1:msdc@11240000 {
		compatible = "mediatek,msdc";
		reg = <0 0x11240000 0 0x10000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
	};

	msdc2:msdc@11250000 {
		compatible = "mediatek,msdc2";
		reg = <0 0x11250000 0 0x10000>;
	};

	msdc3:msdc@11260000 {
		compatible = "mediatek,msdc3";
		reg = <0 0x11250000 0 0x10000>;
	};

	msdc1_ins:msdc1_ins@0 {
		compatible = "mediatek,mt6761-sdcard-ins";
	};

	msdc0_top@11cd0000 {
		compatible = "mediatek,msdc0_top";
		reg = <0 0x11cd0000 0 0x1000>;
	};

	msdc1_top@11c90000 {
		compatible = "mediatek,msdc1_top";
		reg = <0 0x11c90000 0 0x1000>;
	};

	usb1p_sif@11210000 {
		compatible = "mediatek,usb1p_sif";
		reg = <0 0x11210000 0 0x10000>;
	};

	audclk: audclk@11220000 {
		compatible = "mediatek,mt6761-audsys", "syscon";
		reg = <0 0x11220000 0 0x1000>;
		#clock-cells = <1>;
	};

	audio: audio@11220000 {
		compatible = "mediatek,audio", "syscon";
		reg = <0 0x11220000 0 0x1000>;
		/* interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; */
		mediatek,btcvsd_snd = <&btcvsd_snd>;
	};

	audgpio: mt_soc_dl1_pcm@11220000 {
		compatible = "mediatek,mt_soc_pcm_dl1";
		reg = <0 0x11220000 0 0x1000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&audclk CLK_AUDIO_AFE>,
			<&audclk CLK_AUDIO_DAC>,
			<&audclk CLK_AUDIO_DAC_PREDIS>,
			<&audclk CLK_AUDIO_ADC>,
			<&audclk CLK_AUDIO_22M>,
			<&audclk CLK_AUDIO_APLL_TUNER>,
			<&audclk CLK_AUDIO_TML>,
			<&infracfg_ao CLK_IFR_AUDIO>,
			<&infracfg_ao CLK_IFR_AUDIO_26M_BCLK>,
			<&topckgen CLK_TOP_AUDIO_SEL>,
			<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
			<&topckgen CLK_TOP_SYSPLL1_D4>,
			<&topckgen CLK_TOP_AUD_1_SEL>,
			<&topckgen CLK_TOP_APLL1>,
			<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
			<&topckgen CLK_TOP_APLL1_D8>,
			<&apmixed CLK_APMIXED_APLL1>,
			<&clk26m>;
		clock-names = "aud_afe_clk",
			"aud_dac_clk",
			"aud_dac_predis_clk",
			"aud_adc_clk",
			"aud_apll22m_clk",
			"aud_apll1_tuner_clk",
			"aud_tml_clk",
			"aud_infra_clk",
			"mtkaif_26m_clk",
			"top_mux_audio",
			"top_mux_audio_int",
			"top_sys_pll1_d4",
			"top_mux_aud_1",
			"top_apll1_ck",
			"top_mux_aud_eng1",
			"top_apll1_d8",
			"apmixed_apll1",
			"top_clk26m_clk";
	};
	audio_sram@11221000 {
		compatible = "mediatek,audio_sram";
		reg = <0 0x11221000 0 0x9000>;
	};

	btcvsd_snd: mtk-btcvsd-snd@18050000 {
		compatible = "mediatek,mtk-btcvsd-snd";
		reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
		    <0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
		mediatek,infracfg = <&infracfg_ao>;
		mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
		/*INFRA MISC, conn_bt_cvsd_mask*/
		/*cvsd_mcu_read, write, packet_indicator*/
	};

	mipi_rx_ana_csi0a: mipi_rx_ana_csi0a@11c10000 {
		compatible = "mediatek,mt6761-mipi0a", "syscon";
		reg = <0 0x11c10000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi1@11c20000 {
		compatible = "mediatek,mipi_rx_ana_csi1";
		reg = <0 0x11c20000 0 0x10000>;
	};

mipi_rx_ana_csi0b: mipi_rx_ana_csi0b@11c11000 {
		compatible = "mediatek,mt6761-mipi0b", "syscon";
		reg = <0 0x11c11000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi1a: mipi_rx_ana_csi1a@11c12000 {
		compatible = "mediatek,mt6761-mipi1a", "syscon";
		reg = <0 0x11c12000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi1b: mipi_rx_ana_csi1b@11c13000 {
		compatible = "mediatek,mt6761-mipi1b", "syscon";
		reg = <0 0x11c13000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi2a: mipi_rx_ana_csi2a@11c14000 {
		compatible = "mediatek,mt6761-mipi2a", "syscon";
		reg = <0 0x11c14000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi2b: mipi_rx_ana_csi2b@11c15000 {
		compatible = "mediatek,mt6761-mipi2b", "syscon";
		reg = <0 0x11c15000 0 0x1000>;
		#clock-cells = <1>;
	};

	mipi_rx_ana_csi2@11c30000 {
		compatible = "mediatek,mipi_rx_ana_csi2";
		reg = <0 0x11c30000 0 0x10000>;
	};

	efuse: efuse@11c50000 {
		compatible = "mediatek,devinfo";
		reg = <0 0x11c50000 0 0x10000>;

		#address-cells = <1>;
		#size-cells = <1>;

		efuse_segment: segment@78 {
			reg = <0x78 0x4>;
		};
		cpu_freq_segment: segment@1c {
			reg = <0x1c 0x4>;
		};
		thermal_efuse: segment@190 {
			reg = <0x190 0xc>;
		};
		efuse_analog7: efuse_analog7@1ac {
			reg = <0x1ac 0x4>;
		};
		u2_phy_data: u2_phy_data@1ac {
			reg = <0x1ac 0x4>;
		};
	};

	mipi_tx0@11c80000 {
		compatible = "mediatek,mipi_tx0";
		reg = <0 0x11c80000 0 0x10000>;
	};

	msdc1_pad_macro@11c90000 {
		compatible = "mediatek,msdc1_pad_macro";
		reg = <0 0x11c90000 0 0x10000>;
	};

	msdc0_pad_macro@11cd0000 {
		compatible = "mediatek,msdc0_pad_macro";
		reg = <0 0x11cd0000 0 0x10000>;
	};

	mfg_clark: mfg_clark@13000000 {
		compatible = "mediatek,clark";
		reg = <0 0x13000000 0 0x80000>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "RGX";
		clock-frequency = <570000000>;
		ged-supply = <&ged>;
	};

	mfg_cfg: mfg_cfg@13ffe000 {
		compatible = "mediatek,mfgcfg", "syscon";
		reg = <0 0x13ffe000 0 0x1000>;
		#clock-cells = <1>;
	};

	gpufreq: gpufreq {
		compatible = "mediatek,mt6761-gpufreq";
		clocks =
			<&topckgen CLK_TOP_MFG_SEL>,
			<&topckgen CLK_TOP_MFGPLL>,
			<&clk26m>,
			<&scpsys SCP_SYS_MFG_ASYNC>,
			<&scpsys SCP_SYS_MFG>,
			<&scpsys SCP_SYS_MFG_CORE0>;
		clock-names =
			"clk_mux",
			"clk_main_parent",
			"clk_sub_parent",
			"mtcmos_mfg_async",
			"mtcmos_mfg",
			"mtcmos_mfg_core0";
		nvmem-cells = <&efuse_segment>;
		nvmem-cell-names = "efuse_segment_cell";
		vcore-supply = <&mt_pmic_vcore_buck_reg>;
	};

	ged: ged {
		compatible = "mediatek,ged";
		gpufreq-supply = <&gpufreq>;
	};

	mmsys_config: mmsys_config@14000000 {
		compatible = "mediatek,mt6761-mmsys_config", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
		#clock-cells = <1>;
	};

	dispsys_config: dispsys_config@14000000 {
		compatible = "mediatek,mmsys_config", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_CAM_MDP>,
				<&mmsys_config CLK_MM_IMG_DL_RELAY>,
				<&mmsys_config CLK_MM_IMG_DL_ASYNC_TOP>;
		clock-names = "CAM_MDP", "IMG_DL_RELAY", "IMG_DL_ASYNC_TOP";
	};

	nfc:nfc {
		compatible = "mediatek,nfc-gpio-v2";
		gpio-rst = <172>;
		gpio-rst-std = <&pio 172 0x0>;
		gpio-irq = <10>;
		gpio-irq-std = <&pio 10 0x0>;
	};

	irq_nfc: irq_nfc {
		compatible = "mediatek,irq_nfc-eint";
	};

	disp_mutex0: disp_mutex0@14001000 {
		compatible = "mediatek,disp_mutex0";
		reg = <0 0x14001000 0 0x1000>;
		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
	};

	smi_common: smi_common@14002000 {
		compatible = "mediatek,smi_common",
			     "mediatek,mt6761-smi-common";
		reg = <0 0x14002000 0 0x1000>;
		mmsys_config = <&dispsys_config>;
		clocks = <&scpsys SCP_SYS_DIS>,
			<&mmsys_config CLK_MM_SMI_COMM0>,
			<&mmsys_config CLK_MM_SMI_COMM1>,
			<&mmsys_config CLK_MM_SMI_COMMON>;
		clock-names = "apb", "gals0", "gals1", "smi";
		mediatek,smi-id = <3>;
		mediatek,smi-cnt = <4>;
	};

	mmdvfs_pmqos {
		compatible = "mediatek,mmdvfs_pmqos";
		mm_step0 = <436 1 0 1>;
		mm_step0_ext = <436 2 6 0x10C4EC>;
		mm_step1 = <312 1 0 2>;
		mm_step1_ext = <312 2 6 0x10C4EC>;
		mm_step2 = <227 1 0 3>;
		mm_step2_ext = <227 2 6 0x117627>;
		vopp_steps = <0 1 3>;
		disp_freq = "mm_step0", "mm_step1", "mm_step2";
		mdp_freq = "mm_step0", "mm_step1", "mm_step2";
		cam_freq = "mm_step0","mm_step1","mm_step2";
		img_freq = "mm_step0","mm_step1","mm_step2";
		vdec_freq = "mm_step0","mm_step1","mm_step2";
		venc_freq = "mm_step0","mm_step1","mm_step2";
		clocks = <&topckgen CLK_TOP_MM_SEL>,	/* 0 */
			<&topckgen CLK_TOP_MMPLL>,			/* 1 */
			<&topckgen CLK_TOP_UNIVPLL1_D2>,	/* 2 */
			<&topckgen CLK_TOP_MMPLL_D2>;		/* 3 */
		clock-names = "mmdvfs_clk_mm_sel_ck",	/* 0 */
			"mmdvfs_clk_mmpll_ck",				/* 1 */
			"mmdvfs_clk_univpll1_d2_ck",		/* 2 */
			"mmdvfs_clk_mmpll_d2_ck";			/* 3 */
	};

	smi_larb0: smi_larb0@14003000 {

		compatible = "mediatek,smi_larb0", "mediatek,smi_larb",
			     "mediatek,mt6761-smi-larb";
		reg = <0 0x14003000 0 0x1000>;
		mediatek,larb-id = <0>;
		clocks = <&scpsys SCP_SYS_DIS>,
			<&mmsys_config CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
	mediatek,smi-id = <0>;
	};

	mdp_rdma0: mdp_rdma0@14004000 {
		compatible = "mediatek,mdp_rdma0";
		reg = <0 0x14004000 0 0x1000>;
		interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RDMA0>;
		clock-names = "MDP_RDMA0";
	};

	mdp_ccorr: mdp_ccorr0@14005000 {
		compatible = "mediatek,mdp_ccorr0";
		reg = <0 0x14005000 0 0x1000>;
		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_CCORR0>;
		clock-names = "MDP_CCORR";
	};

	mdp_rsz0: mdp_rsz0@14006000 {
		compatible = "mediatek,mdp_rsz0";
		reg = <0 0x14006000 0 0x1000>;
		interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RSZ0>;
		clock-names = "MDP_RSZ0";
	};

	mdp_rsz1: mdp_rsz1@14007000 {
		compatible = "mediatek,mdp_rsz1";
		reg = <0 0x14007000 0 0x1000>;
		interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_RSZ1>;
		clock-names = "MDP_RSZ1";
	};

	mdp_wdma0: mdp_wdma0@14008000 {
		compatible = "mediatek,mdp_wdma0";
		reg = <0 0x14008000 0 0x1000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_WDMA0>;
		clock-names = "MDP_WDMA";
	};

	mdp_wrot0: mdp_wrot0@14009000 {
		compatible = "mediatek,mdp_wrot0";
		reg = <0 0x14009000 0 0x1000>;
		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&mmsys_config CLK_MM_MDP_WROT0>;
		clock-names = "MDP_WROT0";
	};

	mdp_tdshp0: mdp_tdshp0@1400a000 {
		compatible = "mediatek,mdp_tdshp0";
		reg = <0 0x1400a000 0 0x1000>;
		clocks = <&mmsys_config CLK_MM_MDP_TDSHP0>;
		clock-names = "MDP_TDSHP";
	};

	disp_ovl0@1400b000 {
		compatible = "mediatek,disp_ovl0";
		reg = <0 0x1400b000 0 0x1000>;
		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_ovl0_2l@1400c000 {
		compatible = "mediatek,disp_ovl0_2l";
		reg = <0 0x1400c000 0 0x1000>;
		interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_rdma0@1400d000 {
		compatible = "mediatek,disp_rdma0";
		reg = <0 0x1400d000 0 0x1000>;
		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_wdma0@1400e000 {
		compatible = "mediatek,disp_wdma0";
		reg = <0 0x1400e000 0 0x1000>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_color0: disp_color0@1400f000 {
		compatible = "mediatek,disp_color0";
		reg = <0 0x1400f000 0 0x1000>;
		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_ccorr0@14010000 {
		compatible = "mediatek,disp_ccorr0";
		reg = <0 0x14010000 0 0x1000>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_aal0@14011000 {
		compatible = "mediatek,disp_aal0";
		reg = <0 0x14011000 0 0x1000>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_gamma0@14012000 {
		compatible = "mediatek,disp_gamma0";
		reg = <0 0x14012000 0 0x1000>;
		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_dither0@14013000 {
		compatible = "mediatek,disp_dither0";
		reg = <0 0x14013000 0 0x1000>;
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
	};

	dsi0@14014000 {
		compatible = "mediatek,dsi0";
		reg = <0 0x14014000 0 0x1000>;
		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
	};

	disp_rsz0@14015000 {
		compatible = "mediatek,disp_rsz0";
		reg = <0 0x14015000 0 0x1000>;
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_LOW>;
	};

	mtkfb: mtkfb@0 {
		compatible = "mediatek,mtkfb";
	};

	dispsys {
		compatible = "mediatek,dispsys";
		mediatek,larb = <&smi_larb0>;
		clocks = <&scpsys SCP_SYS_DIS>,
			<&mmsys_config CLK_MM_SMI_COMMON>,
			<&mmsys_config CLK_MM_SMI_LARB0>,
			<&mmsys_config CLK_MM_SMI_COMM0>,
			<&mmsys_config CLK_MM_SMI_COMM1>,
			<&mmsys_config CLK_MM_DISP_OVL0>,
			<&mmsys_config CLK_MM_DISP_OVL0_2L>,
			<&mmsys_config CLK_MM_DISP_RDMA0>,
			<&mmsys_config CLK_MM_DISP_WDMA0>,
			<&mmsys_config CLK_MM_DISP_COLOR0>,
			<&mmsys_config CLK_MM_DISP_CCORR0>,
			<&mmsys_config CLK_MM_DISP_AAL0>,
			<&mmsys_config CLK_MM_DISP_GAMMA0>,
			<&mmsys_config CLK_MM_DISP_DITHER0>,
			<&mmsys_config CLK_MM_DSI0>,
			<&mmsys_config CLK_MM_DIG_DSI>,
			<&mmsys_config CLK_MM_F26M_HRTWT>,
			<&mmsys_config CLK_MM_DISP_RSZ0>,
			<&apmixed CLK_APMIXED_MIPID0_26M>,
			<&topckgen CLK_TOP_DISP_PWM_SEL>,
			<&infracfg_ao CLK_IFR_DISP_PWM>,
			<&clk26m>,
			<&topckgen CLK_TOP_UNIVPLL2_D4>,
			<&topckgen CLK_TOP_ULPOSC1_D2>,
			<&topckgen CLK_TOP_ULPOSC1_D8>;

		clock-names = "MMSYS_MTCMOS",
			"MMSYS_SMI_COMMON",
			"MMSYS_SMI_LARB0",
			"MMSYS_GALS_COMM0",
			"MMSYS_GALS_COMM1",
			"MMSYS_DISP_OVL0",
			"MMSYS_DISP_OVL0_2L",
			"MMSYS_DISP_RDMA0",
			"MMSYS_DISP_WDMA0",
			"MMSYS_DISP_COLOR0",
			"MMSYS_DISP_CCORR0",
			"MMSYS_DISP_AAL0",
			"MMSYS_DISP_GAMMA0",
			"MMSYS_DISP_DITHER0",
			"MMSYS_DSI0_MM_CK",
			"MMSYS_DSI0_IF_CK",
			"MMSYS_26M",
			"MMSYS_DISP_RSZ0",
			"APMIXED_MIPI_26M",
			"TOP_MUX_DISP_PWM",
			"DISP_PWM",
			"TOP_26M",
			"TOP_UNIVPLL2_D4",
			"TOP_ULPOSC1_D2",
			"TOP_ULPOSC1_D8";
	};
	dsi_te: dsi_te {
		compatible = "mediatek, DSI_TE-eint";
		status = "disabled";
	};

	mm_mutex: mm_mutex@14016000 {
		compatible = "mediatek,mm_mutex";
		reg = <0 0x14016000 0 0x1000>;
	};

	camsys: camsys@15000000  {
		compatible = "mediatek,mt6761-camsys", "syscon";
		reg = <0 0x15000000  0 0x1000>;
		#clock-cells = <1>;
	};

	ispsys@15000000 {
		compatible = "mediatek,mt6761-ispsys";
		reg = <0x0 0x15004000 0x0 0x9000
			0x0 0x1500d000 0x0 0x1000
			0x0 0x15000000 0x0 0x52000
			0x0 0x15040000 0x0 0x8000
			0x0 0x10215000 0x0 0x3000
			0x0 0x10211000 0x0 0x1000>;
		interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>, /* CAM0 */
		<GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>, /* CAM1 */
		<GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>, /* CAM2 */
		<GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>, /* CAMSV1 */
		<GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>, /* CAMSV1 */
		<GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>, /* CAMSV0 */
		<GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; /* CAMSV0 */
		clocks = <&scpsys SCP_SYS_DIS>,
				<&scpsys SCP_SYS_CAM>,
				<&camsys CLK_CAM_LARB2>,
				<&camsys CLK_CAM>,
				<&camsys CLK_CAMTG>,
				<&camsys CLK_CAM_SENINF>,
				<&camsys CLK_CAMSV0>,
				<&camsys CLK_CAMSV1>,
				<&mmsys_config CLK_MM_SMI_COMM0>,
				<&mmsys_config CLK_MM_SMI_COMM1>,
				<&mmsys_config CLK_MM_SMI_COMMON>;


		clock-names = "CG_SCP_SYS_DIS",
				"CG_SCP_SYS_CAM",
				"CG_CAM_LARB2",
				"CG_CAM",
				"CG_CAMTG",
				"CG_CAM_SENINF",
				"CG_CAMSV0",
				"CG_CAMSV1",
				"CG_MM_SMI_COMM0",
				"CG_MM_SMI_COMM1",
				"CG_MM_SMI_COMMON";
	};

	smi_larb2: smi_larb2@15001000 {

		compatible = "mediatek,smi_larb2", "mediatek,smi_larb",
			     "mediatek,mt6761-smi-larb";
		reg = <0 0x15001000 0 0x1000>;
		mediatek,larb-id = <2>;
		clocks = <&scpsys SCP_SYS_CAM>,
			 <&mmsys_config CLK_MM_SMI_IMG>,
			 <&camsys CLK_CAM_LARB2>;
		clock-names = "apb", "gals", "smi";
		mediatek,smi-id = <2>;
	};

	cam@15004000 {
		compatible = "mediatek,cam";
		reg = <0 0x15004000 0 0x1000>;
	};

	cam_lut@15005000 {
		compatible = "mediatek,cam_lut";
		reg = <0 0x15005000 0 0x1000>;
	};

	camd@15006000 {
		compatible = "mediatek,camd";
		reg = <0 0x15006000 0 0x1000>;
	};

	cam_dma@15007000 {
		compatible = "mediatek,cam_dma";
		reg = <0 0x15007000 0 0x1000>;
	};

	fdvt@1500b000 {
		compatible = "mediatek,fdvt";
		reg = <0 0x1500b000 0 0x1000>;
		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&camsys CLK_CAM_FDVT>;
		clock-names = "FD_CLK_CAM_FDVT";
	};

	cam_inner@1500d000 {
		compatible = "mediatek,cam_inner";
		reg = <0 0x1500d000 0 0x1000>;
	};

	camd_inner@1500e000 {
		compatible = "mediatek,camd_inner";
		reg = <0 0x1500e000 0 0x1000>;
	};

	cam_inner_dma@1500f000 {
		compatible = "mediatek,cam_inner_dma";
		reg = <0 0x1500f000 0 0x1000>;
	};


	camsv0@15050000 {
		compatible = "mediatek,camsv0";
		reg = <0 0x15050000 0 0x1000>;
	};

	camsv1@15051000 {
		compatible = "mediatek,camsv1";
		reg = <0 0x15051000 0 0x1000>;
	};


	kd_camera_hw1: kd_camera_hw1@15040000 {
		compatible = "mediatek,camera_hw";
		reg = <0 0x15040000 0 0x1000>;
		/* SENINF_ADDR */
		/* Camera Common Clock Framework (CCF) */
		clocks = <&topckgen CLK_TOP_CAMTG_SEL>,
		<&topckgen CLK_TOP_CAMTG1_SEL>,
		<&topckgen CLK_TOP_CAMTG2_SEL>,
		<&topckgen CLK_TOP_CAMTG3_SEL>,
		<&topckgen CLK_TOP_USB20_192M_D32>,
		<&topckgen CLK_TOP_USB20_192M_D16>,
		<&topckgen CLK_TOP_UNIVPLL2_D32>,
		<&topckgen CLK_TOP_USB20_192M_D4>,
		<&topckgen CLK_TOP_UNIVPLL2_D8>,
		<&topckgen CLK_TOP_USB20_192M_D8>,
		<&clk26m>,
		<&camsys CLK_CAM_SENINF>,
		<&apmixed CLK_APMIXED_MIPIC0_26M>,
		<&apmixed CLK_APMIXED_MIPIC1_26M>,
		<&mipi_rx_ana_csi0a CLK_MIPI0A_CSR_CSI_EN_0A>,
		<&topckgen CLK_TOP_CAMTM_SEL>,
		<&topckgen CLK_TOP_UNIVPLL2_D2>,
		<&scpsys SCP_SYS_CAM>;


		clock-names = "CLK_TOP_CAMTG_SEL",
			"CLK_TOP_CAMTG1_SEL",
			"CLK_TOP_CAMTG2_SEL",
			"CLK_TOP_CAMTG3_SEL",
			"CLK_MCLK_6M",
			"CLK_MCLK_12M",
			"CLK_MCLK_13M",
			"CLK_MCLK_48M",
			"CLK_MCLK_52M",
			"CLK_MCLK_24M",
			"CLK_MCLK_26M",
			"CLK_CAM_SENINF_CG",
			"CLK_MIPI_C0_26M_CG",
			"CLK_MIPI_C1_26M_CG",
			"CLK_MIPI_ANA_0A_CG",
			"CLK_TOP_CAMTM_SEL_CG",
			"CLK_TOP_CAMTM_208_CG",
			"CLK_SCP_SYS_CAM";
	};

	camera_af_hw_node: camera_af_hw_node {
		compatible = "mediatek,camera_af_lens";
		camaf_m1_pmic-supply = <&mt_pmic_vldo28_ldo_reg>;
	};

	flashlight_core: flashlight_core {
		compatible = "mediatek,flashlight_core";
	};

	flashlights_mt6370: flashlights_mt6370 {
		compatible = "mediatek,flashlights_mt6370";
		decouple = <0>;
		channel@1 {
			type = <0>;
			ct = <0>;
			part = <0>;
		};
		channel@2 {
			type = <0>;
			ct = <1>;
			part = <0>;
		};
	};

	flashlights_aw3644: flashlights_aw3644 {
		compatible = "mediatek,flashlights_aw3644";
	};

	vcodecsys: vcodecsys@17000000 {
		compatible =  "mediatek,mt6761-vcodecsys", "syscon";
		reg = <0 0x17000000 0 0x10000>;
		#clock-cells = <1>;
	};

	venc_gcon: venc_gcon@17000000 {
		compatible = "mediatek,venc_gcon", "syscon";
		reg = <0 0x17000000 0 0x10000>;
		clocks = <&scpsys SCP_SYS_DIS>,
			<&scpsys SCP_SYS_VCODEC>,
			<&mmsys_config CLK_MM_SMI_COMM0>,
			<&mmsys_config CLK_MM_SMI_COMM1>,
			<&mmsys_config CLK_MM_SMI_COMMON>,
			<&vcodecsys CLK_VENC_SET3_VDEC>,
			<&vcodecsys CLK_VENC_SET1_VENC>;
		clock-names = "MT_SCP_SYS_DIS",
			"MT_SCP_SYS_VCODEC",
			"MT_CG_MM_SMI_COMM0",
			"MT_CG_MM_SMI_COMM1",
			"MT_CG_MM_SMI_COMMON",
			"MT_CG_VDEC",
			"MT_CG_VENC";
	};

	smi_larb1: smi_larb1@17010000 {

		compatible = "mediatek,smi_larb1", "mediatek,smi_larb",
			     "mediatek,mt6761-smi-larb";
		reg = <0 0x17010000 0 0x1000>;
		mediatek,larb-id = <1>;
		clocks = <&scpsys SCP_SYS_VCODEC>,
			 <&vcodecsys CLK_VENC_SET1_VENC>;
		clock-names = "apb", "smi";
		mediatek,smi-id = <1>;
	};

	venc@17020000 {
		compatible = "mediatek,venc";
		reg = <0 0x17020000 0 0x10000>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>;
	};

	venc_jpg@17030000 {
		compatible = "mediatek,venc_jpg";
		reg = <0 0x17030000 0 0x10000>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>;
		clocks =
			<&vcodecsys CLK_VENC_SET2_JPGENC>;
		clock-names =
			"MT_CG_VENC_JPGENC";
	};

	vdec@17040000 {
		compatible = "mediatek,vdec";
		reg = <0 0x17040000 0 0x10000>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>;
	};

	mbist@17050000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17050000 0 0x10000>;
	};

	otg_iddig: otg_iddig{
		compatible = "mediatek,usb_iddig_bi_eint";
	};

	odm: odm{
		compatible = "simple-bus";
		/* reserved for overlay by odm */
	};

	audio_snd_card {
		compatible = "mediatek,audio_snd_card";
	};

	mt_soc_deep_buffer_dl_pcm {
		compatible = "mediatek,mt_soc_pcm_deep_buffer_dl";
	};

	mt_soc_ul1_pcm {
		compatible = "mediatek,mt_soc_pcm_capture";
	};

	mt_soc_voice_md1 {
		compatible = "mediatek,mt_soc_pcm_voice_md1";
	};

	mt_soc_uldlloopback_pcm {
		compatible = "mediatek,mt_soc_pcm_uldlloopback";
	};

	mt_soc_i2s0_pcm {
		compatible = "mediatek,mt_soc_pcm_dl1_i2s0";
	};

	mt_soc_mrgrx_pcm {
		compatible = "mediatek,mt_soc_pcm_mrgrx";
	};

	mt_soc_mrgrx_awb_pcm {
		compatible = "mediatek,mt_soc_pcm_mrgrx_awb";
	};

	mt_soc_fm_i2s_pcm {
		compatible = "mediatek,mt_soc_pcm_fm_i2s";
	};

	mt_soc_fm_i2s_awb_pcm {
		compatible = "mediatek,mt_soc_pcm_fm_i2s_awb";
	};

	mt_soc_i2s0dl1_pcm {
		compatible = "mediatek,mt_soc_pcm_dl1_i2s0dl1";
	};

	mt_soc_dl1_awb_pcm {
		compatible = "mediatek,mt_soc_pcm_dl1_awb";
	};

	mt_soc_voice_md1_bt {
		compatible = "mediatek,mt_soc_pcm_voice_md1_bt";
	};

	mt_soc_voip_bt_out {
		compatible = "mediatek,mt_soc_pcm_dl1_bt";
	};

	mt_soc_voip_bt_in {
		compatible = "mediatek,mt_soc_pcm_bt_dai";
	};

	mt_soc_tdmrx_pcm {
		compatible = "mediatek,mt_soc_tdm_capture";
	};

	mt_soc_fm_mrgtx_pcm {
		compatible = "mediatek,mt_soc_pcm_fmtx";
	};

	mt_soc_ul2_pcm {
		compatible = "mediatek,mt_soc_pcm_capture2";
	};

	mt_soc_i2s0_awb_pcm {
		compatible = "mediatek,mt_soc_pcm_i2s0_awb";
	};

	mt_soc_voice_md2 {
		compatible = "mediatek,mt_soc_pcm_voice_md2";
	};

	mt_soc_routing_pcm {
		compatible = "mediatek,mt_soc_pcm_routing";
		/*i2s1clk-gpio = <7 6>;*/
		/*i2s1dat-gpio = <5 6>;*/
		/*i2s1mclk-gpio = <9 6>;*/
		/*i2s1ws-gpio = <6 6>;*/
	};

	mt_soc_voice_md2_bt {
		compatible = "mediatek,mt_soc_pcm_voice_md2_bt";
	};

	mt_soc_hp_impedance_pcm {
		compatible = "mediatek,mt_soc_pcm_hp_impedance";
	};

	mt_soc_dummy_pcm {
		compatible = "mediatek,mt_soc_pcm_dummy";
	};

	mt_soc_codec_dummy_name {
		compatible = "mediatek,mt_soc_codec_dummy";
	};

	mt_soc_routing_dai_name {
		compatible = "mediatek,mt_soc_dai_routing";
	};

	mt_soc_dai_name {
		compatible = "mediatek,mt_soc_dai_stub";
	};

	mt_soc_dl2_pcm {
		compatible = "mediatek,mt_soc_pcm_dl2";
	};

	mt_soc_anc_pcm {
		compatible = "mediatek,mt_soc_pcm_anc";
	};

	mt_soc_pcm_voice_ultra {
		compatible = "mediatek,mt_soc_pcm_voice_ultra";
	};

	mt_soc_pcm_voice_usb {
		compatible = "mediatek,mt_soc_pcm_voice_usb";
	};

	mt_soc_pcm_voice_usb_echoref {
		compatible = "mediatek,mt_soc_pcm_voice_usb_echoref";
	};

	lk_charger: lk_charger {
		compatible = "mediatek,lk_charger";
		enable_anime;
		enable_pe_plus;
		enable_pd20_reset;
		power_path_support;
		max_charger_voltage = <6500000>;
		fast_charge_voltage = <3000000>;

		/* charging current */
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		non_std_ac_charger_current = <500000>;
		charging_host_charger_current = <1500000>;
		ta_ac_charger_current = <3000000>;
		pd_charger_current = <500000>;

		/* battery temperature protection */
		temp_t4_threshold = <50>;
		temp_t3_threshold = <45>;
		temp_t1_threshold = <0>;
	};

	pe: pe {
		compatible = "mediatek,charger,pe";
		gauge = <&mtk_gauge>;

		ta_12v_support;
		ta_9v_support;

		pe_ichg_level_threshold = <1000000>; /* uA */
		ta_start_battery_soc = <0>;
		ta_stop_battery_soc = <85>;
		min_charger_voltage = <4600000>;

		ta_ac_12v_input_current = <3200000>;
		ta_ac_9v_input_current = <3200000>;
		ta_ac_7v_input_current = <3200000>;
		pe_charger_current = <3000000>;
	};

	pe2: pe2 {
		compatible = "mediatek,charger,pe2";
		gauge = <&mtk_gauge>;

		/* PE 2.0 */
		pe20_ichg_level_threshold = <1000000>; /* uA */
		ta_start_battery_soc = <0>;
		ta_stop_battery_soc = <85>;
		min_charger_voltage = <4600000>;

		/* cable measurement impedance */
		cable_imp_threshold = <699>;
		vbat_cable_imp_threshold = <3900000>; /* uV */

		/* single charger */
		sc_input_current = <3200000>;
		sc_charger_current = <3000000>;

		/* dual charger in series */
		dcs_input_current = <3200000>;
		dcs_chg1_charger_current = <1500000>;
		dcs_chg2_charger_current = <1500000>;

		dual_polling_ieoc = <450000>;
		slave_mivr_diff = <100000>;
	};

	pdc: pdc {
		compatible = "mediatek,charger,pd";
		gauge = <&mtk_gauge>;

		min_charger_voltage = <4600000>;
		pd_vbus_low_bound = <5000000>;
		pd_vbus_upper_bound = <5000000>;
		vsys_watt = <5000000>;
		ibus_err = <14>;

		pd_stop_battery_soc = <80>;

		/* single charger */
		sc_input_current = <3200000>;
		sc_charger_current = <3000000>;

		/* dual charger in series */
		dcs_input_current = <3200000>;
		dcs_chg1_charger_current = <1500000>;
		dcs_chg2_charger_current = <1500000>;

		/* dual charger */
		dual_polling_ieoc = <450000>;
		slave_mivr_diff = <100000>;
	};

	pe4: pe4 {
		compatible = "mediatek,charger,pe4";
		gauge = <&mtk_gauge>;

		min_charger_voltage = <4600000>;
		pe40_stop_battery_soc = <80>;

		high_temp_to_leave_pe40 = <46>;
		high_temp_to_enter_pe40 = <39>;
		low_temp_to_leave_pe40 = <10>;
		low_temp_to_enter_pe40 = <16>;
		ibus_err = <14>;

		/* PE 4.0 cable impedance (mohm) */
		pe40_r_cable_1a_lower = <500>;
		pe40_r_cable_2a_lower = <351>;
		pe40_r_cable_3a_lower = <240>;

		/* single charger */
		sc_input_current = <3200000>;
		sc_charger_current = <3000000>;

		/* dual charger in series*/
		dcs_input_current = <3200000>;
		dcs_chg1_charger_current = <1500000>;
		dcs_chg2_charger_current = <1500000>;

		dual_polling_ieoc = <450000>;
		slave_mivr_diff = <100000>;
	};

	charger: charger {
		compatible = "mediatek,charger";
		gauge = <&mtk_gauge>;
		charger = <&mt6370_chg>;
		bootmode = <&chosen>;
		pmic = <&main_pmic>;

		algorithm_name = "Basic";
		charger_configuration= <0>;

		/* common */
		battery_cv = <4350000>;
		max_charger_voltage = <6500000>;
		min_charger_voltage = <4600000>;

		/* sw jeita */
		/* enable_sw_jeita; */
		jeita_temp_above_t4_cv = <4240000>;
		jeita_temp_t3_to_t4_cv = <4240000>;
		jeita_temp_t2_to_t3_cv = <4340000>;
		jeita_temp_t1_to_t2_cv = <4240000>;
		jeita_temp_t0_to_t1_cv = <4040000>;
		jeita_temp_below_t0_cv = <4040000>;
		temp_t4_thres = <50>;
		temp_t4_thres_minus_x_degree = <47>;
		temp_t3_thres = <45>;
		temp_t3_thres_minus_x_degree = <39>;
		temp_t2_thres = <10>;
		temp_t2_thres_plus_x_degree = <16>;
		temp_t1_thres = <0>;
		temp_t1_thres_plus_x_degree = <6>;
		temp_t0_thres = <0>;
		temp_t0_thres_plus_x_degree = <0>;
		temp_neg_10_thres = <0>;

		/* battery temperature protection */
		enable_min_charge_temp;
		min_charge_temp = <0>;
		min_charge_temp_plus_x_degree = <6>;
		max_charge_temp = <50>;
		max_charge_temp_minus_x_degree = <47>;

		/* charging current */
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		charging_host_charger_current = <1500000>;

		/* dynamic mivr */
		enable_dynamic_mivr;
		min_charger_voltage_1 = <4400000>;
		min_charger_voltage_2 = <4200000>;
		max_dmivr_charger_current = <1800000>;
	};

	pd_adapter: pd_adapter {
		compatible = "mediatek,pd_adapter";
		adapter_name = "pd_adapter";
	};

	extcon_usb: extcon_usb {
		compatible = "mediatek,extcon-usb";
		charger = <&mt6370_chg>;
		vbus-supply = <&otg_vbus>;
		vbus-voltage = <5000000>;
		vbus-current = <1800000>;
		dev-conn = <&usb>;
		mediatek,bypss-typec-sink = <1>;
	};

	rt9465_slave_chr: rt9465_slave_chr {
		compatible = "richtek,rt9465";
		status = "disabled";
	};

	rt-pd-manager {
		compatible = "mediatek,rt-pd-manager";
	};

	subpmic_pmu_eint: mt6370_pmu_eint {
	};

	pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
		compatible = "mediatek,pmic_clock_buffer";
		mediatek,clkbuf-quantity = <7>;
		mediatek,clkbuf-config = <2 1 1 2 0 0 0>;
		mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
		mediatek,bblpm-support = "enable";

		pwrap-dcxo-en = <0x188 0 0x188 1 0x188 0>;
		pwrap-dcxo-cfg = <0x18c 0x19c>;

		spm-pwr-status = <0x180 0 0x180 1>;

		pwrap = <&pwrap>;
		sleep = <&sleep>;
	};

	pbm: pbm {
		compatible = "mediatek,pbm";
		io-channels = <&pmic_auxadc AUXADC_BATADC>;
		io-channel-names = "pmic_batadc";
	};

	bat_gm30: battery {
		compatible = "mediatek,bat_gm30";
	};

	pseudo_m4u {
		compatible = "mediatek,mt-pseudo_m4u";
		iommus = <&iommu M4U_PORT_DISP_RDMA0>;
	};

	pseudo_m4u-larb0 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <0>;
		iommus = <&iommu M4U_PORT_DISP_OVL0>,
			 <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>,
			 <&iommu M4U_PORT_DISP_RDMA0>,
			 <&iommu M4U_PORT_DISP_WDMA0>,
			 <&iommu M4U_PORT_MDP_RDMA0>,
			 <&iommu M4U_PORT_MDP_WDMA0>,
			 <&iommu M4U_PORT_MDP_WROT0>,
			 <&iommu M4U_PORT_DISP_FAKE0>;
	};

	pseudo_m4u-larb1 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <1>;
		iommus = <&iommu M4U_PORT_VENC_RCPU>,
			 <&iommu M4U_PORT_VENC_REC>;
	};

	pseudo_m4u-larb2 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <2>;
		iommus = <&iommu M4U_PORT_CAM_IMGO>,
			 <&iommu M4U_PORT_CAM_RRZO>;
	};

	radio_md_cfg: radio_md_cfg {
		compatible = "mediatek,radio_md_cfg";
	};

	dynamic_options: dynamic_options {
		compatible = "mediatek,dynamic_options";
	};

	cm_mgr: cm_mgr@10200000 {
		compatible = "mediatek,mt6761-cm_mgr";
		reg = <0 0x10200000 0 0x4000>;
		reg-names = "cm_mgr_base";
		required-opps = <&dvfsrc_freq_opp0>,
				<&dvfsrc_freq_opp1>,
				<&dvfsrc_freq_opp2>;
		cm_mgr,cp_down = <100 100>;
		cm_mgr,cp_up = <100 100>;
		cm_mgr,dt_down = <0 3>;
		cm_mgr,dt_up = <0 3>;
		cm_mgr,vp_down = <100 100>;
		cm_mgr,vp_up = <100 100>;

		/* use_bcpu_weight = "enable"; */
		/* cpu_power_bcpu_weight_max = <100>; */
		/* cpu_power_bcpu_weight_min = <100>; */

		use_cpu_to_dram_map = "enable";
		cm_mgr_cpu_opp_to_dram = <0 0 0 0 1 1 1 1
					1 2 2 2 2 2 2 2>;

		/* use_cpu_to_dram_map_new = "enable"; */
	};

	dram_ctrl {
		compatible = "mediatek,dram-qosctrl";
		required-opps = <&dvfsrc_freq_opp0>,
				<&dvfsrc_freq_opp1>;
	};

};

#include "cust_mt6761_msdc.dtsi"
#include "mt6357.dtsi"
#include "bat_setting/mt6761_battery_prop.dtsi"
#include "mt6370.dtsi"
#include "mt6370_pd.dtsi"