// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2019 MediaTek Inc. */ /dts-v1/; #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include / { model = "MT6873"; compatible = "mediatek,MT6873"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; /* chosen */ chosen: chosen { bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \ vmalloc=400M slub_debug=OFZPU swiotlb=noforce \ firmware_class.path=/vendor/firmware \ page_owner=on loop.max_part=7"; kaslr-seed = <0 0>; }; aliases { ovl0 = &disp_ovl0; ovl3 = &disp_ovl0_2l; ovl5 = &disp_ovl2_2l; rdma0 = &disp_rdma0; rdma4 = &disp_rdma4; dsi0 = &dsi0; }; cluster0_opp: opp_table0 { compatible = "operating-points-v2"; opp-shared; opp0 { opp-hz = /bits/ 64 <500000000>; opp-microvolt = <600000>; }; opp1 { opp-hz = /bits/ 64 <650000000>; opp-microvolt = <600000>; }; opp2 { opp-hz = /bits/ 64 <756000000>; opp-microvolt = <625000>; }; opp3 { opp-hz = /bits/ 64 <862000000>; opp-microvolt = <643750>; }; opp4 { opp-hz = /bits/ 64 <968000000>; opp-microvolt = <668750>; }; opp5 { opp-hz = /bits/ 64 <1075000000>; opp-microvolt = <693750>; }; opp6 { opp-hz = /bits/ 64 <1181000000>; opp-microvolt = <712500>; }; opp7 { opp-hz = /bits/ 64 <1358000000>; opp-microvolt = <750000>; }; opp8 { opp-hz = /bits/ 64 <1500000000>; opp-microvolt = <781250>; }; opp9 { opp-hz = /bits/ 64 <1541000000>; opp-microvolt = <800000>; }; opp10 { opp-hz = /bits/ 64 <1625000000>; opp-microvolt = <818750>; }; opp11 { opp-hz = /bits/ 64 <1687000000>; opp-microvolt = <837500>; }; opp12 { opp-hz = /bits/ 64 <1750000000>; opp-microvolt = <856250>; }; opp13 { opp-hz = /bits/ 64 <1812000000>; opp-microvolt = <868750>; }; opp14 { opp-hz = /bits/ 64 <1875000000>; opp-microvolt = <88750>; }; opp15 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <92500>; }; }; cluster1_opp: opp_table1 { compatible = "operating-points-v2"; opp-shared; opp0 { opp-hz = /bits/ 64 <774000000>; opp-microvolt = <600000>; }; opp1 { opp-hz = /bits/ 64 <841000000>; opp-microvolt = <618750>; }; opp2 { opp-hz = /bits/ 64 <925000000>; opp-microvolt = <637500>; }; opp3 { opp-hz = /bits/ 64 <1008000000>; opp-microvolt = <656250>; }; opp4 { opp-hz = /bits/ 64 <1091000000>; opp-microvolt = <675000>; }; opp5 { opp-hz = /bits/ 64 <1175000000>; opp-microvolt = <700000>; }; opp6 { opp-hz = /bits/ 64 <1258000000>; opp-microvolt = <718750>; }; opp7 { opp-hz = /bits/ 64 <1383000000>; opp-microvolt = <750000>; }; opp8 { opp-hz = /bits/ 64 <1548000000>; opp-microvolt = <800000>; }; opp9 { opp-hz = /bits/ 64 <1633000000>; opp-microvolt = <806250>; }; opp10 { opp-hz = /bits/ 64 <1716000000>; opp-microvolt = <831250>; }; opp11 { opp-hz = /bits/ 64 <1800000000>; opp-microvolt = <850000>; }; opp12 { opp-hz = /bits/ 64 <1850000000>; opp-microvolt = <868750>; }; opp13 { opp-hz = /bits/ 64 <1900000000>; opp-microvolt = <887500>; }; opp14 { opp-hz = /bits/ 64 <1950000000>; opp-microvolt = <906250>; }; opp15 { opp-hz = /bits/ 64 <2000000000>; opp-microvolt = <925000>; }; }; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@000 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; clock-frequency = <1701000000>; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <85>; capacity-dmips-mhz = <365>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &s2idle>; }; cpu1: cpu@001 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; clock-frequency = <1701000000>; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <85>; capacity-dmips-mhz = <365>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &s2idle>; }; cpu2: cpu@002 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; clock-frequency = <1701000000>; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <85>; capacity-dmips-mhz = <365>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &s2idle>; }; cpu3: cpu@003 { device_type = "cpu"; compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; clock-frequency = <1701000000>; operating-points-v2 = <&cluster0_opp>; dynamic-power-coefficient = <85>; capacity-dmips-mhz = <365>; cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff &s2idle>; }; cpu4: cpu@100 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; clock-frequency = <2171000000>; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <275>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &s2idle>; }; cpu5: cpu@101 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; clock-frequency = <2171000000>; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <275>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &s2idle>; }; cpu6: cpu@102 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0600>; enable-method = "psci"; clock-frequency = <2171000000>; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <275>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &s2idle>; }; cpu7: cpu@103 { device_type = "cpu"; compatible = "arm,cortex-a76"; reg = <0x0700>; enable-method = "psci"; clock-frequency = <2171000000>; operating-points-v2 = <&cluster1_opp>; dynamic-power-coefficient = <275>; capacity-dmips-mhz = <1024>; cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff &s2idle>; }; cpu-map { cluster0 { core0 { cpu = <&cpu0>; }; core1 { cpu = <&cpu1>; }; core2 { cpu = <&cpu2>; }; core3 { cpu = <&cpu3>; }; doe_dvfs_cl0: doe { }; }; cluster1 { core0 { cpu = <&cpu4>; }; core1 { cpu = <&cpu5>; }; core2 { cpu = <&cpu6>; }; core3 { cpu = <&cpu7>; }; doe_dvfs_cl1: doe { }; }; }; idle-states { entry-method = "arm,psci"; cpuoff_l: cpuoff_l { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <100>; min-residency-us = <1600>; }; cpuoff_b: cpuoff_b { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x00010001>; local-timer-stop; entry-latency-us = <50>; exit-latency-us = <100>; min-residency-us = <1400>; }; clusteroff_l: clusteroff_l { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <250>; min-residency-us = <2100>; }; clusteroff_b: clusteroff_b { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x01010001>; local-timer-stop; entry-latency-us = <100>; exit-latency-us = <250>; min-residency-us = <1900>; }; mcusysoff: mcusysoff { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x01010002>; local-timer-stop; entry-latency-us = <300>; exit-latency-us = <1200>; min-residency-us = <2600>; }; s2idle: s2idle { compatible = "mediatek,idle-state"; arm,psci-suspend-param = <0x01010100>; local-timer-stop; entry-latency-us = <500>; exit-latency-us = <1400>; min-residency-us = <4294967295>; }; }; }; disp_leds { compatible = "mediatek,disp-leds"; backlight { label = "lcd-backlight"; max-brightness = <255>; led-bits = <8>; default-state = "on"; }; }; psci { compatible = "arm,psci-1.0"; method = "smc"; }; pwmleds { compatible = "mediatek,disp-pwm-leds"; backlight { label = "lcd-backlight"; pwms = <&disp_pwm 0 39385>; max-brightness = <255>; pwm-names = "lcd-backlight"; }; }; mtk_lpm: mtk_lpm { compatible = "mediatek,mtk-lpm"; #address-cells = <2>; #size-cells = <2>; ranges; suspend-method = "s2idle"; irq-remain = <&edge_keypad &edge_mdwdt>, <&level_vpu_core0 &level_vpu_core1>, <&level_mali0 &level_mali1>, <&level_mali2 &level_mali3 &level_mali4>, <&level_mtk_mdla &level_edma0>; resource-ctrl = <&bus26m &infra &syspll>, <&dram_s0 &dram_s1>; constraints = <&rc_bus26m &rc_syspll &rc_dram>; lpm_sysram: lpm_sysram@0011b500 { compatible = "mediatek,lpm-sysram"; reg = <0 0x0011b500 0 0x300>; }; irq-remain-list { edge_keypad: edge_keypad { target = <&keypad>; value = <1 0 0 0x04>; }; edge_mdwdt: edge_mdwdt { target = <&mddriver>; value = <1 0 0 0x02000000>; }; level_vpu_core0: level_vpu_core0 { target = <&vpu_core0>; value = <0 0 0 0>; }; level_vpu_core1: level_vpu_core1 { target = <&vpu_core1>; value = <0 0 0 0>; }; level_mali0: level_mali0 { target = <&mali>; value = <0 0 0 0>; }; level_mali1: level_mali1 { target = <&mali>; value = <0 1 0 0>; }; level_mali2: level_mali2 { target = <&mali>; value = <0 2 0 0>; }; level_mali3: level_mali3 { target = <&mali>; value = <0 3 0 0>; }; level_mali4: level_mali4 { target = <&mali>; value = <0 4 0 0>; }; level_mtk_mdla: level_mtk_mdla { target = <&mtk_mdla>; value = <0 0 0 0>; }; level_edma0: level_edma0 { target = <&edma0>; value = <0 0 0 0>; }; }; resource-ctrl-list { bus26m: bus26m { id = <0x00000000>; value = <0>; }; infra: infra { id = <0x00000001>; value = <0>; }; syspll: syspll { id = <0x00000002>; value = <0>; }; dram_s0: dram_s0 { id = <0x00000003>; value = <0>; }; dram_s1: dram_s1 { id = <0x00000004>; value = <0>; }; }; constraint-list { rc_bus26m: rc_bus26m { id = <0x00000000>; value = <1>; }; rc_syspll: rc_syspll { id = <0x00000001>; value = <1>; }; rc_dram: rc_dram { id = <0x00000002>; value = <1>; }; }; }; cpupm_sysram: cpupm-sysram@0011b000 { compatible = "mediatek,cpupm-sysram"; reg = <0 0x0011b000 0 0x500>; }; mcusys_ctrl: mcusys-ctrl@0c53a000 { compatible = "mediatek,mcusys-ctrl"; reg = <0 0x0c53a000 0 0x1000>; }; mcucfg_mp0_counter { compatible = "mediatek,mcucfg_mp0_counter"; reg_mp0_counter_base = <&mcucfg>; }; pmu { compatible = "arm,armv8-pmuv3"; interrupt-parent = <&gic>; interrupts = ; }; dsu-pmu-0 { compatible = "arm,dsu-pmu"; interrupts = ; cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; }; memory { device_type = "memory"; reg = <0 0x40000000 0 0x3e605000>; }; reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; ssmr_cma_mem: ssmr-reserved-cma_memory { compatible = "shared-dma-pool"; reusable; size = <0 0x10000000>; alignment = <0 0x1000000>; alloc-range = <0 0xc0000000 0 0x10000000>; }; ion-carveout-heap { compatible = "mediatek,ion-carveout-heap"; no-map; #ifdef CONFIG_FPGA_EARLY_PORTING size = <0 0x10000000>; #else size = <0 0xc000>; #endif alignment = <0 0x1000>; alloc-ranges = <0 0x40000000 0 0x80000000>; }; reserve-memory-sspm_share { compatible = "mediatek,reserve-memory-sspm_share"; no-map; status = "okay"; #if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC) size = <0 0x110000>; /* 1M + 64K */ #else size = <0 0x510000>; /* 5M + 64K */ #endif alignment = <0 0x10000>; alloc-ranges = <0 0x40000000 0 0x60000000>; }; reserve-memory-adsp_share { compatible = "mediatek,reserve-memory-adsp_share"; no-map; size = <0 0x1000000>; alloc-ranges = <0 0x40000000 0 0x40000000>; alignment = <0 0x10000>; //EMI 64KB Align }; reserve-memory-scp_share { compatible = "mediatek,reserve-memory-scp_share"; no-map; size = <0 0x00300000>; /*3 MB share mem size */ alignment = <0 0x1000000>; alloc-ranges = <0 0x50000000 0 0x40000000>; }; reserve-memory-mcupm_share { compatible = "mediatek,reserve-memory-mcupm_share"; no-map; status = "okay"; #if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC) size = <0 0x210000>; /* 2M + 64K */ #else size = <0 0x610000>; /* 6M + 64K */ #endif alignment = <0 0x10000>; alloc-ranges = <0 0x40000000 0 0x60000000>; }; consys_mem: consys-reserve-memory { compatible = "mediatek,consys-reserve-memory"; no-map; size = <0 0x400000>; alignment = <0 0x1000000>; alloc-ranges = <0 0x40000000 0 0x80000000>; }; wifi_mem: wifi-reserve-memory { compatible = "shared-dma-pool"; no-map; size = <0 0x600000>; alignment = <0 0x1000000>; alloc-ranges = <0 0x40000000 0 0x80000000>; }; }; /* * dsu ecc irq (nFAULTIRQ[0]) must be at the end of * the list, due to we shouldn't force set affinity * in the driver. */ cache_parity { compatible = "mediatek,mt6873-cache-parity"; ecc-irq-support = <1>; arm_dsu_ecc_hwirq = <32>; interrupts = , , , , , , , , ; }; qos@0011bb00 { compatible = "mediatek,qos-2.0"; reg = <0 0x0011bb00 0 0x100>; }; gic: interrupt-controller { compatible = "arm,gic-v3"; #interrupt-cells = <3>; #address-cells = <2>; #size-cells = <2>; #redistributor-regions = <1>; interrupt-parent = <&gic>; interrupt-controller; reg = <0 0x0c000000 0 0x40000>, // distributor <0 0x0c040000 0 0x200000>; // redistributor interrupts = ; }; clocks { clk_null: clk_null { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; clk26m: clk26m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; }; clk12m: clk12m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <12000000>; }; clk13m: clk13m { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <13000000>; }; clk32k: clk32k { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32000>; }; }; chipid@08000000 { compatible = "mediatek,chipid"; reg = <0 0x08000000 0 0x0004>, <0 0x08000004 0 0x0004>, <0 0x08000008 0 0x0004>, <0 0x0800000c 0 0x0004>; }; apmixed: apmixed@1000c000 { compatible = "mediatek,apmixed", "syscon"; reg = <0 0x1000c000 0 0xe00>; #clock-cells = <1>; }; topckgen: topckgen@10000000 { compatible = "mediatek,topckgen", "syscon"; reg = <0 0x10000000 0 0x1000>; #clock-cells = <1>; }; infracfg_ao: infracfg_ao@10001000 { compatible = "mediatek,infracfg_ao", "mediatek,mt6853-infracfg_ao", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; infracfg_rst: reset-controller { compatible = "ti,syscon-reset"; #reset-cells = <1>; ti,reset-bits = < /* ufs reset */ 0x130 15 0x134 15 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: ufshci */ 0x140 7 0x144 7 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: unipro */ 0x150 21 0x154 21 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: ufs-crypto */ >; }; }; scpsys: scpsys@10001000 { compatible = "mediatek,scpsys"; reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */ <0 0x10006000 0 0x1000>, /* spm */ <0 0x10000000 0 0x1000>; /* topckgen */ #clock-cells = <1>; }; scp_infra: scp_infra@10001000 { compatible = "mediatek,scpinfra", "syscon"; reg = <0 0x10001000 0 0x1000>; /* infracfg_ao */ }; apu0: apu0@19030000 { compatible = "mediatek,apu0", "syscon"; reg = <0 0x19030000 0 0x1000>; #clock-cells = <1>; }; apu1: apu1@19031000 { compatible = "mediatek,apu1", "syscon"; reg = <0 0x19031000 0 0x1000>; #clock-cells = <1>; }; apu_vcore: apu_vcore@19029000 { compatible = "mediatek,apu_vcore", "syscon"; reg = <0 0x19029000 0 0x1000>; #clock-cells = <1>; }; apu_conn: apu_conn@19020000 { compatible = "mediatek,apu_conn", "syscon"; reg = <0 0x19020000 0 0x1000>; #clock-cells = <1>; }; apu_mdla0: apu_mdla0@19034000 { compatible = "mediatek,apu_mdla0", "syscon"; reg = <0 0x19034000 0 0x1000>; #clock-cells = <1>; }; audio: audio@11210000 { compatible = "mediatek,audio", "syscon"; reg = <0 0x11210000 0 0x2000>; #clock-cells = <1>; }; scp_adsp: scp_adsp@10720000 { compatible = "mediatek,scp_adsp", "syscon"; reg = <0 0x10720000 0 0x200>; #clock-cells = <1>; }; camsys_clk: camsys_clk@1a000000 { compatible = "mediatek,mt6783-camsys", "syscon"; reg = <0 0x1a000000 0 0x10000>; #clock-cells = <1>; }; camsys_rawa: camsys_rawa@1a04f000 { compatible = "mediatek,camsys_rawa", "syscon"; reg = <0 0x1a04f000 0 0x1000>; #clock-cells = <1>; }; camsys_rawb: camsys_rawb@1a06f000 { compatible = "mediatek,camsys_rawb", "syscon"; reg = <0 0x1a06f000 0 0x1000>; #clock-cells = <1>; }; camsys_rawc: camsys_rawc@1a08f000 { compatible = "mediatek,camsys_rawc", "syscon"; reg = <0 0x1a08f000 0 0x1000>; #clock-cells = <1>; }; camsys: camsys@1a000000 { compatible = "mediatek,camsys", "syscon"; reg = <0 0x1a000000 0 0x10000>; #clock-cells = <1>; /* Camera CCF */ clocks = <&scpsys SCP_SYS_MDP>, <&scpsys SCP_SYS_CAM>, <&scpsys SCP_SYS_CAM_RAWA>, <&scpsys SCP_SYS_CAM_RAWB>, <&scpsys SCP_SYS_CAM_RAWC>, <&camsys_clk CAMSYS_MAIN_CAM_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAMTG_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAMSV0_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAMSV1_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAMSV2_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAMSV3_CGPDN>, <&camsys_clk CAMSYS_MAIN_LARB13_CGPDN>, <&camsys_clk CAMSYS_MAIN_LARB14_CGPDN>, <&camsys_clk CAMSYS_MAIN_CCU0_CGPDN>, <&camsys_clk CAMSYS_MAIN_SENINF_CGPDN>, <&camsys_clk CAMSYS_MAIN_CAM2MM_GALS_CGPDN>, <&camsys_rawa CAMSYS_RAWA_LARBX_CGPDN>, <&camsys_rawa CAMSYS_RAWA_CAM_CGPDN>, <&camsys_rawa CAMSYS_RAWA_CAMTG_CGPDN>, <&camsys_rawb CAMSYS_RAWB_LARBX_CGPDN>, <&camsys_rawb CAMSYS_RAWB_CAM_CGPDN>, <&camsys_rawb CAMSYS_RAWB_CAMTG_CGPDN>, <&camsys_rawc CAMSYS_RAWC_LARBX_CGPDN>, <&camsys_rawc CAMSYS_RAWC_CAM_CGPDN>, <&camsys_rawc CAMSYS_RAWC_CAMTG_CGPDN>, <&topckgen TOP_MUX_CCU>, <&topckgen TOP_MUX_CAMTM>; clock-names = "ISP_SCP_SYS_MDP", "ISP_SCP_SYS_CAM", "ISP_SCP_SYS_RAWA", "ISP_SCP_SYS_RAWB", "ISP_SCP_SYS_RAWC", "CAMSYS_CAM_CGPDN", "CAMSYS_CAMTG_CGPDN", "CAMSYS_CAMSV0_CGPDN", "CAMSYS_CAMSV1_CGPDN", "CAMSYS_CAMSV2_CGPDN", "CAMSYS_CAMSV3_CGPDN", "CAMSYS_LARB13_CGPDN", "CAMSYS_LARB14_CGPDN", "CAMSYS_CCU0_CGPDN", "CAMSYS_SENINF_CGPDN", "CAMSYS_MAIN_CAM2MM_GALS_CGPDN", "CAMSYS_RAWALARB16_CGPDN", "CAMSYS_RAWACAM_CGPDN", "CAMSYS_RAWATG_CGPDN", "CAMSYS_RAWBLARB17_CGPDN", "CAMSYS_RAWBCAM_CGPDN", "CAMSYS_RAWBTG_CGPDN", "CAMSYS_RAWCLARB18_CGPDN", "CAMSYS_RAWCCAM_CGPDN", "CAMSYS_RAWCTG_CGPDN", "TOPCKGEN_TOP_MUX_CCU", "TOPCKGEN_TOP_MUX_CAMTM"; }; camsys_a: camsys_a@1a04f000 { compatible = "mediatek,camsys_a"; reg = <0 0x1a04f000 0 0x1000>; }; camsys_b: camsys_b@1a06f000 { compatible = "mediatek,camsys_b"; reg = <0 0x1a06f000 0 0x1000>; }; camsys_c: camsys_c@1a08f000 { compatible = "mediatek,camsys_c"; reg = <0 0x1a08f000 0 0x1000>; }; imgsys_config_clk: imgsys_config_clk@15020000 { compatible = "mediatek,mt6873-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; imgsys2_config: imgsys2_config@15820000 { compatible = "mediatek,imgsys2", "syscon"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP Center */ imp_iic_wrap_c: imp_iic_wrap_c@11007000 { compatible = "mediatek,imp_iic_wrap_c", "syscon"; reg = <0 0x11007000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP East */ imp_iic_wrap_e: imp_iic_wrap_e@11cb1000 { compatible = "mediatek,imp_iic_wrap_e", "syscon"; reg = <0 0x11cb1000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP North */ imp_iic_wrap_n: imp_iic_wrap_n@11f02000 { compatible = "mediatek,imp_iic_wrap_n", "syscon"; reg = <0 0x11f02000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP South */ imp_iic_wrap_s: imp_iic_wrap_s@11d03000 { compatible = "mediatek,imp_iic_wrap_s", "syscon"; reg = <0 0x11d03000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP WST */ imp_iic_wrap_w: imp_iic_wrap_w@11e01000 { compatible = "mediatek,imp_iic_wrap_w", "syscon"; reg = <0 0x11e01000 0 0x1000>; #clock-cells = <1>; }; /* IIC WRAP WEST */ imp_iic_wrap_ws: imp_iic_wrap_ws@11d23000 { compatible = "mediatek,imp_iic_wrap_ws", "syscon"; reg = <0 0x11d23000 0 0x1000>; #clock-cells = <1>; }; ipesys_config: ipesys_config@1b000000 { compatible = "mediatek,ipesys_config", "syscon"; reg = <0 0x1b000000 0 0x1000>; #clock-cells = <1>; }; g3d_config: g3d_config@13fbf000 { compatible = "mediatek,g3d_config", "syscon"; reg = <0 0x13fbf000 0 0x1000>; #clock-cells = <1>; }; dispsys_config_clk: dispsys_config_clk@14000000 { compatible = "mediatek,mt6873-dispsys_config","syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; }; msdcsys_top: msdcsys_top@11f10000 { compatible = "mediatek,msdcsys_top", "syscon"; reg = <0 0x11f10000 0 0x1000>; #clock-cells = <1>; }; mdpsys_config: mdpsys_config@1f000000 { compatible = "mediatek,mdpsys_config", "syscon"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; clocks = <&mdpsys_config MDP_IMG_DL_ASYNC0>, <&mdpsys_config MDP_IMG_DL_ASYNC1>, <&mdpsys_config MDP_IMG_DL_RELAY0_ASYNC0>, <&mdpsys_config MDP_IMG_DL_RELAY1_ASYNC1>, <&mdpsys_config MDP_APB_BUS>; clock-names = "MDP_IMG_DL_ASYNC0", "MDP_IMG_DL_ASYNC1", "MDP_IMG0_IMG_DL_ASYNC0", "MDP_IMG0_IMG_DL_ASYNC1", "MDP_APB_BUS"; }; pericfg:pericfg@10003000 { compatible = "mediatek,pericfg"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; }; vdec_gcon: vdec_gcon@1602f000 { compatible = "mediatek,vdec_gcon", "syscon"; reg = <0 0x1602f000 0 0x10000>; #clock-cells = <1>; }; vdec_soc_gcon: vdec_soc_gcon@1600f000 { compatible = "mediatek,vdec_soc_gcon", "syscon"; reg = <0 0x1600f000 0 0x10000>; #clock-cells = <1>; }; venc_gcon: venc_gcon@17000000 { compatible = "mediatek,venc_gcon", "syscon"; reg = <0 0x17000000 0 0x10000>; #clock-cells = <1>; }; dcm: dcm@10001000 { compatible = "mediatek,mt6873-dcm"; reg = <0 0x10001000 0 0x1000>, <0 0x10002000 0 0x1000>, <0 0x10022000 0 0x1000>, <0 0x10219000 0 0x1000>, <0 0x10230000 0 0x2000>, <0 0x10235000 0 0x1000>, <0 0x10238000 0 0x1000>, <0 0x10240000 0 0x2000>, <0 0x10248000 0 0x1000>, <0 0x10400000 0 0x1000>, <0 0x11210000 0 0x1000>, <0 0xc538000 0 0x5000>, <0 0xc53a800 0 0x1000>; reg-names = "infracfg_ao", "infracfg_ao_mem", "infra_ao_bcrm", "emi", "dramc_ch0_top0", "chn0_emi", "dramc_ch0_top5", "dramc_ch1_top0", "dramc_ch1_top5", "sspm", "audio", "mp_cpusys_top", "cpccfg_reg"; }; scp_clk_ctrl: scp_clk_ctrl@10721000 { compatible = "mediatek,scp_clk_ctrl", "syscon"; reg = <0 0x10721000 0 0x1000>; /* clk*/ }; scp_dvfs { compatible = "mediatek,scp_dvfs"; scp-dvfs-feature = "enable"; clocks = <&topckgen TOP_MUX_SCP>, <&clk26m>, <&topckgen TOP_UNIVPLL_D5>, <&topckgen TOP_MAINPLL_D6_D2>, <&topckgen TOP_MAINPLL_D6>, <&topckgen TOP_UNIVPLL_D6>, <&topckgen TOP_MAINPLL_D4_D2>, <&topckgen TOP_MAINPLL_D5_D2>, <&topckgen TOP_UNIVPLL_D4_D2>; clock-names = "clk_mux", "clk_pll_0", "clk_pll_1", "clk_pll_2", "clk_pll_3", "clk_pll_4", "clk_pll_5", "clk_pll_6", "clk_pll_7"; dvfs-opp = /* vcore vsram dvfsrc spm freq mux resource uv_index */ < 550000 750000 0 0x008 196 2 0 3>, < 600000 750000 1 0x104 260 5 0 2>, < 650000 750000 2 0x202 280 7 0 1>, < 725000 750000 3 0x301 360 3 0x3 0>, < 725000 750000 3 0x301 416 4 0x3 0>; scp-cores = <2>; pmic-sshub-support; vow-lp-en-gear = <2>; do-ulposc-cali; ccf-fmeter-support; fmeter-id-ulposc2 = <36>; fmeter-id-26M = <25>; ulposc_clksys = <&apmixed>; scp_clk_ctrl = <&scp_clk_ctrl>; scp-clk-hw-ver = "v1"; ulposc-cali-ver = "v1"; ulposc-cali-num = <3>; ulposc-cali-target = <196 280 360>; ulposc-cali-config = /* con0 con1 con2 */ <0x5aa940 0x3002900 0x40>, <0x3ca940 0x2900 0x40>, <0x52a940 0x2900 0x40>; }; infracfg_ao_mem@10002000 { compatible = "mediatek,infracfg_ao_mem"; reg = <0 0x10002000 0 0x1000>; }; iocfg_rm: iocfg_rm@11c20000 { compatible = "mediatek,iocfg_rm"; reg = <0 0x11c20000 0 0x1000>; }; iocfg_bm: iocfg_bm@11d10000 { compatible = "mediatek,iocfg_bm"; reg = <0 0x11d10000 0 0x1000>; }; iocfg_bl: iocfg_bl@11d30000 { compatible = "mediatek,iocfg_bl"; reg = <0 0x11d30000 0 0x1000>; }; iocfg_br: iocfg_br@11d40000 { compatible = "mediatek,iocfg_br"; reg = <0 0x11d40000 0 0x1000>; }; iocfg_lm: iocfg_lm@11e20000 { compatible = "mediatek,iocfg_lm"; reg = <0 0x11e20000 0 0x1000>; }; iocfg_lb: iocfg_lb@11e70000 { compatible = "mediatek,iocfg_lb"; reg = <0 0x11e70000 0 0x1000>; }; iocfg_rt: iocfg_rt@11ea0000 { compatible = "mediatek,iocfg_rt"; reg = <0 0x11ea0000 0 0x1000>; }; iocfg_lt: iocfg_lt@11f20000 { compatible = "mediatek,iocfg_lt"; reg = <0 0x11f20000 0 0x1000>; }; iocfg_tl: iocfg_tl@11f30000 { compatible = "mediatek,iocfg_tl"; reg = <0 0x11f30000 0 0x1000>; }; eint: eint@1000b000 { compatible = "mediatek,eint"; reg = <0 0x1000b000 0 0x1000>; }; gpio: gpio@10005000 { compatible = "mediatek,gpio"; reg = <0 0x10005000 0 0x1000>; }; pio: pinctrl { compatible = "mediatek,mt6873-pinctrl"; reg_bases = <&gpio>, <&iocfg_rm>, <&iocfg_bm>, <&iocfg_bl>, <&iocfg_br>, <&iocfg_lm>, <&iocfg_lb>, <&iocfg_rt>, <&iocfg_lt>, <&iocfg_tl>; reg_base_eint = <&eint>; pins-are-numbered; gpio-controller; gpio-ranges = <&pio 0 0 220>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <4>; interrupts = ; interrupt-parent = <&gic>; }; mmc0: mmc@11f60000 { compatible = "mediatek,mt6873-mmc"; reg = <0 0x11f60000 0 0x10000>, <0 0x11f50000 0 0x1000>; interrupts = ; clocks = <&topckgen TOP_MUX_MSDC50_0_HCLK>, <&infracfg_ao INFRACFG_AO_MSDC0_CG>, <&infracfg_ao INFRACFG_AO_MSDC0_SRC_CLK_CG>, <&infracfg_ao TOP_MUX_AES_MSDCFDE>; clock-names = "source", "hclk", "source_cg", "crypto_clk"; status = "disabled"; }; mmc1: mmc@11f70000 { compatible = "mediatek,mt6873-mmc"; reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; interrupts = ; clocks = <&topckgen TOP_MUX_MSDC30_1>, <&infracfg_ao INFRACFG_AO_MSDC1_CG>, <&infracfg_ao INFRACFG_AO_MSDC1_SRC_CLK_CG>; clock-names = "source", "hclk", "source_cg"; status = "disabled"; }; sleep@10006000 { compatible = "mediatek,sleep"; reg = <0 0x10006000 0 0x1000>; interrupts = ; }; spmtwam: spmtwam@10006000 { compatible = "mediatek,spmtwam"; reg = <0 0x10006000 0 0x1000>; interrupts = ; spm_twam_con = <0xa0>; spm_twam_window_len = <0xa4>; spm_twam_idle_sel = <0xa8>; spm_irq_mask = <0xb4>; spm_irq_sta = <0x128>; spm_twam_last_sta0 = <0x1d0>; spm_twam_last_sta1 = <0x1d4>; spm_twam_last_sta2 = <0x1d8>; spm_twam_last_sta3 = <0x1dc>; }; srclken@10006500 { compatible = "mediatek,srclken"; reg = <0 0x10006500 0 0x1000>; }; toprgu:toprgu@10007000 { compatible = "mediatek,mt6877-wdt", "mediatek,mt6589-wdt", "mediatek,toprgu", "syscon", "simple-mfd"; reg = <0 0x10007000 0 0x1000>; interrupts = ; mediatek,rg_dfd_timeout = <0x1ffff>; #reset-cells = <1>; reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x24>; mask = <0xf>; mode-charger = ; mode-recovery = ; mode-bootloader = ; mode-dm-verity-dev-corrupt = ; mode-kpoc = ; mode-ddr-reserve = ; mode-meta = ; mode-rpmbpk = ; }; }; apxgpt@10008000 { compatible = "mediatek,apxgpt"; reg = <0 0x10008000 0 0x1000>; interrupts = ; }; hacc@1000a000 { compatible = "mediatek,hacc"; reg = <0 0x1000a000 0 0x1000>; interrupts = ; }; fhctl-new@1000ce00 { compatible = "mediatek,mt6873-fhctl"; reg = <0 0x1000ce00 0 0x200>, <0 0x1000c000 0 0xe00>; map0 { domain = "top"; method = "fhctl-mcupm"; armpll_ll { fh-id = <0>; pll-id = <0>; perms = <0x18>; }; armpll_bl0 { fh-id = <1>; pll-id = <1>; perms = <0x18>; }; armpll_bl1 { fh-id = <2>; pll-id = <2>; perms = <0x18>; }; armpll_bl2 { fh-id = <3>; pll-id = <3>; perms = <0x18>; }; npupll { fh-id = <4>; pll-id = <4>; }; ccipll { fh-id = <5>; pll-id = <5>; perms = <0x18>; }; mfgpll { fh-id = <6>; pll-id = <6>; }; mpll { fh-id = <8>; pll-id = <8>; }; mmpll { fh-id = <9>; pll-id = <9>; }; mainpll { fh-id = <10>; pll-id = <10>; }; msdcpll { fh-id = <11>; pll-id = <11>; }; adsppll { fh-id = <12>; pll-id = <12>; }; apupll { fh-id = <13>; pll-id = <13>; }; tvdpll { fh-id = <14>; pll-id = <14>; }; }; }; efuse: efuse@11c10000 { compatible = "mediatek,devinfo"; reg = <0 0x11c10000 0 0x10000>; #address-cells = <1>; #size-cells = <1>; efuse_segment: segment@78 { reg = <0x78 0x4>; }; apu_pod19: apu_efuse2 { reg = <0x114 0x4>; }; lvts_e_data1: data1 { reg = <0x1D0 0x10>; }; lvts_e_data2: data2 { reg = <0x2F8 0x48>; }; apu_pod26: apu_efuse3 { reg = <0x344 0x4>; }; cpu_version: cpu_data { reg = <0x234 0x4>; }; u3_phy_data: u3_phy_data { reg = <0x1ac 0x4>; }; u2_phy_data: u2_phy_data { reg = <0x1b0 0x4>; }; }; pwrap: pwrap@10026000 { compatible = "mediatek,mt6873-pwrap"; reg = <0 0x10026000 0 0x1000>, <0 0x10028000 0 0x1000>; reg-names = "pwrap","spi_mst"; interrupts = ; #ifdef CONFIG_FPGA_EARLY_PORTING clocks = <&clk26m>, <&clk26m>, <&clk26m>, <&clk26m>; #else clocks = <&infracfg_ao INFRACFG_AO_PMIC_CG_AP>, <&infracfg_ao INFRACFG_AO_PMIC_CG_TMR>, <&topckgen TOP_MUX_PWRAP_ULPOSC>, <&topckgen TOP_OSC_D10>; #endif clock-names = "spi", "wrap", "ulposc", "ulposc_osc"; main_pmic: mt6359-pmic { compatible = "mediatek,mt6359-pmic"; interrupt-parent = <&pio>; interrupts = <214 IRQ_TYPE_LEVEL_HIGH 214 0>; status = "okay"; pmic_oc_debug: pmic-oc-debug { compatible = "mediatek,pmic-oc-debug"; }; }; }; pwraph: pwraphal@10026000 { compatible = "mediatek,pwraph"; mediatek,pwrap-regmap = <&pwrap>; }; pwrap_mpu@10026000 { compatible = "mediatek,pwrap_mpu"; reg = <0 0x10026000 0 0x1000>; }; topmisc@10011000 { compatible = "mediatek,topmisc"; reg = <0 0x10011000 0 0x1000>; }; dvfsrc: dvfsrc@10012000 { compatible = "mediatek,dvfsrc"; reg = <0 0x10012000 0 0x1000>, <0 0x10006000 0 0x1000>; interrupts = ; }; boot_dramboost: boot_dramboost { compatible = "mediatek,dvfsrc-boost"; boost_opp = <0>; }; mbist_ao@10013000 { compatible = "mediatek,mbist_ao"; reg = <0 0x10013000 0 0x1000>; }; dpmaif:dpmaif@10014000 { compatible = "mediatek,dpmaif"; reg = <0 0x10014000 0 0x1000>, /*AO_UL*/ <0 0x1022D000 0 0x1000>, /*PD_UL*/ <0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/ <0 0x1022E000 0 0x1000>; /*SRAM*/ interrupts = ; /*209+32=241*/ mediatek,dpmaif_capability = <14>; clocks = <&infracfg_ao INFRACFG_AO_DPMAIF_MAIN_CG>, <&infracfg_ao INFRACFG_AO_CLDMA_BCLK_CK>; clock-names = "infra-dpmaif-clk", "infra-dpmaif-blk-clk"; }; ccifdriver:ccifdriver@10209000 { compatible = "mediatek,ccci_ccif"; reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/ <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/ mediatek,sram_size = <512>; /*CCIF0 174/206, CCIF0 175/207*/ interrupts = , ; clocks = <&infracfg_ao INFRACFG_AO_CCIF_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF5_MD_CG>; clock-names = "infra-ccif-ap", "infra-ccif-md", "infra-ccif1-ap", "infra-ccif1-md", "infra-ccif2-ap", "infra-ccif2-md", "infra-ccif4-md", "infra-ccif5-md"; }; mddriver:mddriver { compatible = "mediatek,mddriver"; mediatek,mdhif_type = <6>; /* bit0~3: CLDMA|CCIF|DPMAIF */ mediatek,md_id = <0>; mediatek,offset_apon_md1 = <0x2844>; mediatek,cldma_capability = <14>; reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/ <0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/ interrupts = , /*MDWDT*/ , /*CCIF0 194/226*/ ; /*CCIF0 195/227*/ clocks = <&scpsys SCP_SYS_MD1>, <&infracfg_ao INFRACFG_AO_DPMAIF_MAIN_CG>, <&infracfg_ao INFRACFG_AO_CLDMA_BCLK_CK>, <&infracfg_ao INFRACFG_AO_CCIF_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>, <&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>, <&infracfg_ao INFRACFG_AO_CCIF5_MD_CG>; clock-names = "scp-sys-md1-main", "infra-dpmaif-clk", "infra-dpmaif-blk-clk", "infra-ccif-ap", "infra-ccif-md", "infra-ccif1-ap", "infra-ccif1-md", "infra-ccif2-ap", "infra-ccif2-md", "infra-ccif4-md", "infra-ccif5-md"; ccci-infracfg = <&infracfg_ao>; }; ssmr { compatible = "mediatek,trusted_mem"; memory-region = <&ssmr_cma_mem>; }; radio_md_cfg:radio_md_cfg { compatible = "mediatek,radio_md_cfg"; }; md_auxadc:md_auxadc { compatible = "mediatek,md_auxadc"; io-channels = <&auxadc 2>; io-channel-names = "md-channel"; }; gpio_usage_mapping: gpio_usage_mapping { compatible = "mediatek,gpio_usage_mapping"; }; aes_top0@10016000 { compatible = "mediatek,aes_top0"; reg = <0 0x10016000 0 0x1000>; }; timer: timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , , , ; clock-frequency = <13000000>; }; sys_timer@10017000 { compatible = "mediatek,mt6765-timer", "mediatek,sys_timer"; reg = <0 0x10017000 0 0x1000>; reg-names = "sys_timer_base"; interrupts = ; clocks = <&clk13m>; }; modem_temp_share@10018000 { compatible = "mediatek,modem_temp_share"; reg = <0 0x10018000 0 0x1000>; }; security_ao@1001a000 { compatible = "mediatek,security_ao"; reg = <0 0x1001a000 0 0x1000>; }; topckgen_ao@1001b000 { compatible = "mediatek,topckgen_ao"; reg = <0 0x1001b000 0 0x1000>; }; devapc_ao_mm@1001c000 { compatible = "mediatek,devapc_ao_mm"; reg = <0 0x1001c000 0 0x1000>; }; sleep_sram@1001e000 { compatible = "mediatek,sleep_sram"; reg = <0 0x1001e000 0 0x4000>; }; bcrm_ao_peri@10022000 { compatible = "mediatek,bcrm_ao_peri"; reg = <0 0x10022000 0 0x1000>; }; debug_ao_peri@10023000 { compatible = "mediatek,debug_ao_peri"; reg = <0 0x10023000 0 0x1000>; }; pmic@10026000 { compatible = "mediatek,pmic"; reg = <0 0x10026000 0 0x1000>; }; spmi_bus: spmi@10027000 { compatible = "mediatek,pmif"; reg = <0 0x10027000 0 0x000e00>, <0 0x10027f00 0 0x00008c>, <0 0x10029000 0 0x000100>; reg-names = "pmif", "pmifmpu", "spmimst"; interrupts = ; interrupt-names = "pmif_irq"; irq_event_en = <0x0 0x0 0x00300000 0x00000100 0x0>; clocks = <&infracfg_ao INFRACFG_AO_PMIC_CG_AP>, <&infracfg_ao INFRACFG_AO_PMIC_CG_TMR>, <&topckgen TOP_MUX_PWRAP_ULPOSC>, <&topckgen TOP_OSC_D10>, <&clk26m>, <&topckgen TOP_MUX_SPMI_MST>, <&clk26m>, <&topckgen TOP_OSC_D10>; clock-names = "pmif_sys_ck", "pmif_tmr_ck", "pmif_clk_mux", "pmif_clk_osc_d10", "pmif_clk26m", "spmimst_clk_mux", "spmimst_clk26m", "spmimst_clk_osc_d10"; swinf_ch_start = <4>; ap_swinf_no = <2>; #address-cells = <2>; #size-cells = <0>; }; /* ATF logger */ atf_logger { compatible = "mediatek,atf_logger"; }; mobicore { compatible = "trustonic,mobicore"; interrupts = ; }; tee_sanity { compatible = "mediatek,tee_sanity"; interrupts = ; }; /* Microtrust SW IRQ number 85(117) ~ 90(122) */ utos { compatible = "microtrust,utos"; interrupts = , ; }; utos_tester { compatible = "microtrust,tester-v1"; }; spmi_mpu@10027000 { compatible = "mediatek,spmi_mpu"; reg = <0 0x10027000 0 0x0e00>; }; bcrm_peri_ao@1002a000 { compatible = "mediatek,bcrm_peri_ao"; reg = <0 0x1002a000 0 0x1000>; }; debug_ao_peri_ctl@1002b000 { compatible = "mediatek,debug_ao_peri_ctl"; reg = <0 0x1002b000 0 0x1000>; }; bcrm_peri_ao2@1002d000 { compatible = "mediatek,bcrm_peri_ao2"; reg = <0 0x1002d000 0 0x1000>; }; debug_ao_peri2@1002e000 { compatible = "mediatek,debug_ao_peri2"; reg = <0 0x1002e000 0 0x1000>; }; devapc_ao_infra@10030000 { compatible = "mediatek,devapc_ao_infra"; reg = <0 0x10030000 0 0x4000>; }; devapc_ao_peri@10034000 { compatible = "mediatek,devapc_ao_peri"; reg = <0 0x10034000 0 0x4000>; }; devapc_ao_peri2@10038000 { compatible = "mediatek,devapc_ao_peri2"; reg = <0 0x10038000 0 0x4000>; }; devapc_ao_peri_par@1003c000 { compatible = "mediatek,devapc_ao_peri_par"; reg = <0 0x1003c000 0 0x4000>; }; debug_ao_peri_par@10040000 { compatible = "mediatek,debug_ao_peri_par"; reg = <0 0x10040000 0 0x1000>; }; bcrm_peri_par_ao@10041000 { compatible = "mediatek,bcrm_peri_par_ao"; reg = <0 0x10041000 0 0x1000>; }; debug_ao_fmem@10042000 { compatible = "mediatek,debug_ao_fmem"; reg = <0 0x10042000 0 0x1000>; }; bcrm_fmem_ao@10043000 { compatible = "mediatek,bcrm_fmem_ao"; reg = <0 0x10043000 0 0x1000>; }; devapc_ao_fmem@10044000 { compatible = "mediatek,devapc_ao_fmem"; reg = <0 0x10044000 0 0x4000>; }; pwm@10048000 { compatible = "mediatek,pwm"; reg = <0 0x10048000 0 0x1000>; interrupts = ; clocks = <&infracfg_ao INFRACFG_AO_PWM1_CG>, <&infracfg_ao INFRACFG_AO_PWM2_CG>, <&infracfg_ao INFRACFG_AO_PWM3_CG>, <&infracfg_ao INFRACFG_AO_PWM4_CG>, <&infracfg_ao INFRACFG_AO_PWM_HCLK_CG>, <&infracfg_ao INFRACFG_AO_PWM_CG>; clock-names = "PWM1-main", "PWM2-main", "PWM3-main", "PWM4-main", "PWM-HCLK-main", "PWM-main"; }; devapc@10207000 { compatible = "mediatek,mt6873-devapc"; reg = <0 0x10207000 0 0x1000>, <0 0x10274000 0 0x1000>, <0 0x10275000 0 0x1000>, <0 0x11020000 0 0x1000>, <0 0x10030000 0 0x1000>, <0 0x1020e000 0 0x1000>, <0 0x10033000 0 0x1000>, <0 0x0010c000 0 0x1000>; interrupts = ; clocks = <&infracfg_ao INFRACFG_AO_DEVICE_APC_CG>; clock-names = "devapc-infra-clock"; }; hwrng: hwrng { compatible = "mediatek,mt67xx-rng"; }; bus_dbg@10208000 { compatible = "mediatek,bus_dbg-v2"; reg = <0 0x10208000 0 0x1000>, <0 0x10001000 0 0x1000>; mediatek,bus_dbg_con_offset = <0x2fc>; interrupts = ; }; dbgtop@1000d000 { compatible = "mediatek,dbgtop"; reg = <0 0x1000d000 0 0x1000>; }; ufshci:ufshci@11270000 { compatible = "mediatek,mt8183-ufshci"; reg = <0 0x11270000 0 0x2300>; interrupts = ; clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>, <&infracfg_ao INFRACFG_AO_UNIPRO_SYSCLK_CG>, <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>, <&infracfg_ao INFRACFG_AO_AES_UFSFDE_CG>, <&topckgen TOP_MUX_AES_UFSFDE>, <&topckgen TOP_UNIVPLL_D6>, <&topckgen TOP_MAINPLL_D4>; clock-names = "ufs-clk", "ufs-unipro-clk", "ufs-mp-clk", "ufs-crypto-clk", "ufs-vendor-crypto-clk-mux", "ufs-vendor-crypto-normal-parent-clk", "ufs-vendor-crypto-perf-parent-clk"; freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>, <0 0>; vcc-supply = <&mt_pmic_vemc_ldo_reg>; vcc-fixed-regulator; resets = <&infracfg_rst 0>, <&infracfg_rst 1>, <&infracfg_rst 2>; reset-names = "hci_rst", "unipro_rst", "crypto_rst"; /* Reference clock control mode */ /* SW mode: 0, Half-HW mode: 1, HW mode: 2 */ mediatek,refclk_ctrl = <2>; /* Performance Mode */ mediatek,perf-crypto-vcore = <2>; }; ufs_mphy@11fa0000 { compatible = "mediatek,ufs_mphy"; reg = <0 0x11fa0000 0 0xc000>; }; ap_ccif0@10209000 { compatible = "mediatek,ap_ccif0"; reg = <0 0x10209000 0 0x1000>; interrupts = ; }; md_ccif0@1020a000 { compatible = "mediatek,md_ccif0"; reg = <0 0x1020a000 0 0x1000>; }; ap_ccif1@1020b000 { compatible = "mediatek,ap_ccif1"; reg = <0 0x1020b000 0 0x1000>; interrupts = ; }; md_ccif1@1020c000 { compatible = "mediatek,md_ccif1"; reg = <0 0x1020c000 0 0x1000>; }; infra_mbist@1020d000 { compatible = "mediatek,infra_mbist"; reg = <0 0x1020d000 0 0x1000>; }; infracfg@1020e000 { compatible = "mediatek,infracfg"; reg = <0 0x1020e000 0 0x1000>; }; trng@1020f000 { compatible = "mediatek,trng"; reg = <0 0x1020f000 0 0x1000>; interrupts = ; }; dxcc_sec@10210000 { compatible = "mediatek,dxcc_sec"; reg = <0 0x10210000 0 0x1000>; interrupts = ; }; md2md_md1_ccif0@10211000 { compatible = "mediatek,md2md_md1_ccif0"; reg = <0 0x10211000 0 0x1000>; }; cqdma-controller@10212000 { compatible = "mediatek,cqdma"; reg = <0 0x10212000 0 0x80>, <0 0x10212100 0 0x80>, <0 0x10212200 0 0x80>, <0 0x10212300 0 0x80>; interrupts = , , , ; clocks = <&infracfg_ao INFRACFG_AO_CQ_DMA_CG>; clock-names = "cqdma"; dma-channel-mask = <63>; dma-channels = <4>; dma-requests = <10>; #dma-cells = <1>; }; md2md_md2_ccif0@10213000 { compatible = "mediatek,md2md_md2_ccif0"; reg = <0 0x10213000 0 0x1000>; }; sramrom@10214000 { compatible = "mediatek,sramrom"; reg = <0 0x10214000 0 0x1000>; }; bcrm_infra@10215000 { compatible = "mediatek,bcrm_infra"; reg = <0 0x10215000 0 0x1000>; }; apdma@10217000 { compatible = "mediatek,apdma"; reg = <0 0x10217000 0 0x1000>; }; dbg_tracker2@10218000 { compatible = "mediatek,dbg_tracker2"; reg = <0 0x10218000 0 0x1000>; }; emicen: emicen@10219000 { compatible = "mediatek,mt6873-emicen", "mediatek,common-emicen"; reg = <0 0x10219000 0 0x1000>; mediatek,emi-reg = <&emichn>; }; emiisu { compatible = "mediatek,mt6873-emiisu", "mediatek,common-emiisu"; ctrl_intf = <1>; }; device_mpu_low@1021a000 { compatible = "mediatek,device_mpu_low"; reg = <0 0x1021a000 0 0x1000>; prot-base = <0x0 0x40000000>; prot-size = <0x4 0x00000000>; page-size = <0x200000>; interrupts = ; }; device_mpu_acp@1030d000 { compatible = "mediatek,device_mpu_acp"; reg = <0 0x1030d000 0 0x1000>; prot-base = <0x0 0x40000000>; prot-size = <0x4 0x00000000>; page-size = <0x200000>; interrupts = ; }; infracfg_mem@1021c000 { compatible = "mediatek,infracfg_mem"; reg = <0 0x1021c000 0 0x1000>; }; apcldmain@1021f000 { compatible = "mediatek,apcldmain"; reg = <0 0x1021f000 0 0x1000>; }; apcldmaout@1021b400 { compatible = "mediatek,apcldmaout"; reg = <0 0x1021b400 0 0x400>; }; apcldmamisc@1021b800 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021b800 0 0x400>; }; apcldmamisc@1021bc00 { compatible = "mediatek,apcldmamisc"; reg = <0 0x1021bc00 0 0x400>; }; mdcldmain@1021c000 { compatible = "mediatek,mdcldmain"; reg = <0 0x1021c000 0 0x400>; }; infra_md@1021d000 { compatible = "mediatek,infra_md"; reg = <0 0x1021d000 0 0x1000>; }; bpi_bsi_slv0@1021e000 { compatible = "mediatek,bpi_bsi_slv0"; reg = <0 0x1021e000 0 0x1000>; }; bpi_bsi_slv1@1021f000 { compatible = "mediatek,bpi_bsi_slv1"; reg = <0 0x1021f000 0 0x1000>; }; bpi_bsi_slv2@10225000 { compatible = "mediatek,bpi_bsi_slv2"; reg = <0 0x10225000 0 0x1000>; }; m4u0@10220000 { compatible = "mediatek,m4u0"; reg = <0 0x10220000 0 0x1000>; }; m4u1@10221000 { compatible = "mediatek,m4u1"; reg = <0 0x10221000 0 0x1000>; }; m4u2@10222000 { compatible = "mediatek,m4u2"; reg = <0 0x10222000 0 0x1000>; }; m4u3@10223000 { compatible = "mediatek,m4u3"; reg = <0 0x10223000 0 0x1000>; }; m4u4@10224000 { compatible = "mediatek,m4u4"; reg = <0 0x10224000 0 0x1000>; }; infra_device_mpu@10225000 { compatible = "mediatek,infra_device_mpu"; reg = <0 0x10225000 0 0x1000>; }; emimpu@10226000 { compatible = "mediatek,mt6873-emimpu", "mediatek,common-emimpu"; reg = <0 0x10226000 0 0x1000>; mediatek,emi-reg = <&emicen>; interrupts = ; region_cnt = <32>; domain_cnt = <16>; addr_align = <16>; ap_region = <31>; ap_apc = <0 5 5 5 2 0 6 5>, <0 0 5 0 0 0 5 5>; dump = <0x1f0 0x1f8 0x1fc>; clear = <0x160 0xffffffff 16>, <0x200 0x00000003 16>, <0x1f0 0x80000000 1>; clear_md = <0x1fc 0x80000000 1>; ctrl_intf = <1>; slverr = <0>; }; dvfsp@10227000 { compatible = "mediatek,dvfsp"; reg = <0 0x10227000 0 0x1000>; }; dvfsp: dvfsp@0011bc00 { compatible = "mediatek,mt6873-dvfsp"; reg = <0 0x0011bc00 0 0x1400>, <0 0x0011bc00 0 0x1400>; state = <1>; imax_state = <2>; change_flag = <0>; little-rise-time = <1000>; little-down-time = <750>; big-rise-time = <1000>; big-down-time = <750>; L-table = <2000 96 1 1 1933 92 1 1 1866 88 1 1 1800 83 1 1 1733 80 1 1 1666 75 1 1 1548 71 1 1 1475 66 2 1 1375 64 2 1 1275 58 2 1 1175 54 2 1 1075 49 2 1 999 46 2 1 925 43 2 1 850 40 2 1 774 38 2 1 >; B-table = <2200 100 1 1 2133 96 1 1 2066 92 1 1 2000 88 1 1 1933 84 1 1 1866 80 1 1 1800 75 1 1 1651 70 1 1 1503 64 1 1 1414 61 2 1 1295 57 2 1 1176 53 2 1 1087 49 2 1 998 46 2 1 909 43 2 1 850 40 2 1 >; CCI-table = <1400 96 2 1 1353 92 2 1 1306 88 2 1 1260 84 2 1 1190 78 2 1 1155 75 2 1 1120 71 2 1 984 64 2 1 917 62 2 1 827 58 2 1 737 54 2 2 669 51 2 2 579 47 2 2 512 44 2 2 445 41 2 2 400 38 2 2 >; }; mt_cpufreq: mt_cpufreq { compatible = "mediatek,mt-cpufreq"; #ifndef CONFIG_FPGA_EARLY_PORTING proc1-supply = <&mt6315_6_vbuck1>; proc2-supply = <&mt6315_6_vbuck3>; #endif }; gce_mbox: gce_mbox@10228000 { compatible = "mediatek,mt6873-gce"; reg = <0 0x10228000 0 0x4000>; interrupts = ; #mbox-cells = <3>; #gce-event-cells = <1>; #gce-subsys-cells = <2>; default_tokens = /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 , /bits/ 16 ; clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>, <&infracfg_ao INFRACFG_AO_GCE_26M>; clock-names = "gce", "gce-timer"; }; gce_mbox_sec: gce_mbox_sec@10228000 { compatible = "mediatek,mailbox-gce-sec"; reg = <0 0x10228000 0 0x4000>; #mbox-cells = <3>; mboxes = <&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; clock-names = "gce"; clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>; }; ktf-cmdq-test { compatible = "mediatek,ktf-cmdq-test"; mediatek,gce = <&gce_mbox>; mmsys_config = <&mmsys_config>; mboxes = <&gce_mbox 8 0 CMDQ_THR_PRIO_1>, <&gce_mbox 9 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>, <&gce_mbox 10 0 CMDQ_THR_PRIO_1>; mediatek,gce-subsys = <99>, ; gce-subsys = <&gce_mbox 0x14000000 SUBSYS_1400XXXX>, <&gce_mbox 0x14010000 SUBSYS_1401XXXX>, <&gce_mbox 0x14020000 SUBSYS_1402XXXX>; token_user0 = /bits/ 16 ; token_gpr_set4 = /bits/ 16 ; gce-event-names = "disp_rdma0_sof", "disp_rdsz0_sof", "mdp_rdma0_sof"; gce-events = <&gce_mbox CMDQ_EVENT_DISP_RDMA0_SOF>, <&gce_mbox CMDQ_EVENT_DISP_RSZ0_SOF>, <&gce_mbox CMDQ_EVENT_MDP_RDMA0_SOF>; }; cmdq-test { compatible = "mediatek,cmdq-test"; mediatek,gce = <&gce_mbox>; mmsys_config = <&dispsys_config>; mediatek,gce-subsys = <99>, ; mboxes = <&gce_mbox 21 0 CMDQ_THR_PRIO_1>, <&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>, <&gce_mbox_sec 10 0 CMDQ_THR_PRIO_1>; token_user0 = /bits/ 16 ; token_gpr_set4 = /bits/ 16 ; }; infra_dpmaif@1022c000 { compatible = "mediatek,infra_dpmaif"; reg = <0 0x1022c000 0 0x10>; }; dramc@10230000 { compatible = "mediatek,mt6873-dramc", "mediatek,common-dramc"; reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */ <0 0x10240000 0 0x2000>, /* DRAMC AO CHB */ <0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */ <0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */ <0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */ <0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */ <0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */ <0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */ <0 0x10006000 0 0x1000>; /* SLEEP BASE */ mr4_version = <1>; mr4_rg = <0x0090 0x0000ffff 0>; fmeter_version = <1>; crystal_freq = <52>; pll_id = <0x050c 0x00000100 8>; shu_lv = <0x050c 0x00030000 16>; shu_of = <0x700>; sdmpcw = <0x0704 0xffff0000 16>, <0x0724 0xffff0000 16>; prediv = <0x0708 0x000c0000 18>, <0x0728 0x000c0000 18>; posdiv = <0x0708 0x00000007 0>, <0x0728 0x00000007 0>; ckdiv4 = <0x0874 0x00000004 2>, <0x0874 0x00000004 2>; pll_md = <0x0744 0x00000100 8>, <0x0744 0x00000100 8>; cldiv2 = <0x08b4 0x00000002 1>, <0x08b4 0x00000002 1>; fbksel = <0x070c 0x00000040 6>, <0x070c 0x00000040 6>; dqsopen = <0x0870 0x00100000 20>, <0x0870 0x00100000 20>; dqopen = <0x0870 0x00200000 21>, <0x0870 0x00200000 21>; ckdiv4_ca = <0x0b74 0x00000004 2>, <0x0b74 0x00000004 2>; }; dramc_ch0_top0@10230000 { compatible = "mediatek,dramc_ch0_top0"; reg = <0 0x10230000 0 0x2000>; }; dramc_ch0_top1@10232000 { compatible = "mediatek,dramc_ch0_top1"; reg = <0 0x10232000 0 0x2000>; }; dramc_ch0_top2@10234000 { compatible = "mediatek,dramc_ch0_top2"; reg = <0 0x10234000 0 0x1000>; }; emichn: emichn@10235000 { compatible = "mediatek,mt6873-emichn", "mediatek,common-emichn"; reg = <0 0x10235000 0 0x1000>, <0 0x10245000 0 0x1000>; }; dramc_ch0_top4@10236000 { compatible = "mediatek,dramc_ch0_top4"; reg = <0 0x10236000 0 0x2000>; }; dramc_ch0_top5@10238000 { compatible = "mediatek,dramc_ch0_top5"; reg = <0 0x10238000 0 0x2000>; }; dramc_ch0_top6@1023a000 { compatible = "mediatek,dramc_ch0_top6"; reg = <0 0x1023a000 0 0x2000>; }; ap_ccif2@1023c000 { compatible = "mediatek,ap_ccif2"; reg = <0 0x1023c000 0 0x1000>; interrupts = ; }; md_ccif2@1023d000 { compatible = "mediatek,md_ccif2"; reg = <0 0x1023d000 0 0x1000>; }; ap_ccif3@1023e000 { compatible = "mediatek,ap_ccif3"; reg = <0 0x1023e000 0 0x1000>; interrupts = ; }; md_ccif3@1023f000 { compatible = "mediatek,md_ccif3"; reg = <0 0x1023f000 0 0x1000>; }; apdma: dma-controller@10217a80 { compatible = "mediatek,mt6577-uart-dma"; reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>, <0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>; interrupts = , , , ; clocks = <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "apdma"; #dma-cells = <1>; dma-bits = <34>; dma-requests = <4>; }; apuart0: serial@11002000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11002000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART0_CG>; clock-names = "baud", "bus"; dmas = <&apdma 0 &apdma 1>; dma-names = "tx", "rx"; }; apuart1: serial@11003000 { compatible = "mediatek,mt6577-uart"; reg = <0 0x11003000 0 0x1000>; interrupts = ; clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART1_CG>; clock-names = "baud", "bus"; dmas = <&apdma 2 &apdma 3>; dma-names = "tx", "rx"; }; usbphy0:usbphy { compatible = "usb-nop-xceiv"; }; ssusb: usb0@11201000 { compatible = "mediatek,mtu3"; reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x100>; reg-names = "mac", "ippc"; interrupts = ; interrupt-names = "ssusb_mac"; phy-cells = <1>; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; clocks = <&infracfg_ao INFRACFG_AO_SSUSB_CG>, <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>; clock-names = "sys_ck", "ref_ck"; #address-cells = <2>; #size-cells = <2>; ranges; dr_mode = "otg"; maximum-speed = "high-speed"; mediatek,force-vbus; mediatek,clk-mgr; mediatek,spm-mgr; mediatek,usb3-drd; mediatek,noise-still-tr; usb-role-switch; status = "okay"; usb_host: xhci0@11200000 { compatible = "mediatek,mtk-xhci"; reg = <0 0x11200000 0 0x1000>; reg-names = "mac"; interrupts = ; clocks = <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>; clock-names = "sys_ck"; status = "okay"; }; }; u3phy: usb-phy0@11e40000 { compatible = "mediatek,generic-tphy-v2"; clocks = <&clk26m>; clock-names = "u3phya_ref"; #address-cells = <2>; #size-cells = <2>; ranges; status = "okay"; u2port0: usb2-phy0@11e40000 { reg = <0 0x11e40000 0 0x700>; #phy-cells = <1>; mediatek,eye-vrt = <6>; /* 0~7 */ mediatek,eye-term = <6>; /* 0~7 */ mediatek,eye-rev6 = <1>; /* 0~3 */ mediatek,eye-disc = <7>; /* 0~8 */ mediatek,host-eye-vrt = <6>; /* 0~7 */ mediatek,host-eye-term = <6>; /* 0~7 */ mediatek,host-eye-rev6 = <1>; /* 0~3 */ mediatek,host-eye-disc = <7>; /* 0~8 */ nvmem-cells = <&u2_phy_data>; nvmem-cell-names = "intr_cal"; nvmem-cell-masks = <0x1f>; status = "okay"; }; u3port0: usb3-phy0@11e40700 { reg = <0 0x11e40700 0 0x900>; #phy-cells = <1>; nvmem-cells = <&u3_phy_data>, <&u3_phy_data>, <&u3_phy_data>; nvmem-cell-names = "iext_intr_ctrl", "rx_impsel", "tx_impsel"; nvmem-cell-masks = <0x3f0000 0x1f00 0x1f>; status = "okay"; }; }; extcon_usb: extcon_usb { compatible = "mediatek,extcon-usb"; charger = <&mt6360_chg>; dev-conn = <&ssusb>; mediatek,bypss-typec-sink = <1>; }; usb_boost_manager { compatible = "mediatek,usb_boost"; boost_period = <0>; }; dramc_ch1_top0@10240000 { compatible = "mediatek,dramc_ch1_top0"; reg = <0 0x10240000 0 0x2000>; }; dramc_ch1_top1@10242000 { compatible = "mediatek,dramc_ch1_top1"; reg = <0 0x10242000 0 0x2000>; }; dramc_ch1_top2@10244000 { compatible = "mediatek,dramc_ch1_top2"; reg = <0 0x10244000 0 0x1000>; }; dramc_ch1_top4@10246000 { compatible = "mediatek,dramc_ch1_top4"; reg = <0 0x10246000 0 0x2000>; }; dramc_ch1_top5@10248000 { compatible = "mediatek,dramc_ch1_top5"; reg = <0 0x10248000 0 0x2000>; }; dramc_ch1_top6@1024a000 { compatible = "mediatek,dramc_ch1_top6"; reg = <0 0x1024a000 0 0x2000>; }; ap_ccif4@1024c000 { compatible = "mediatek,ap_ccif4"; reg = <0 0x1024c000 0 0x1000>; }; md_ccif4@1024d000 { compatible = "mediatek,md_ccif4"; reg = <0 0x1024d000 0 0x1000>; }; md_ccif4@1024e000 { compatible = "mediatek,md_ccif4"; reg = <0 0x1024e000 0 0x1000>; }; dramc_ch2_top0@10250000 { compatible = "mediatek,dramc_ch2_top0"; reg = <0 0x10250000 0 0x2000>; }; dramc_ch2_top1@10252000 { compatible = "mediatek,dramc_ch2_top1"; reg = <0 0x10252000 0 0x2000>; }; dramc_ch2_top2@10254000 { compatible = "mediatek,dramc_ch2_top2"; reg = <0 0x10254000 0 0x1000>; }; dramc_ch2_top4@10256000 { compatible = "mediatek,dramc_ch2_top4"; reg = <0 0x10256000 0 0x2000>; }; dramc_ch2_top5@10258000 { compatible = "mediatek,dramc_ch2_top5"; reg = <0 0x10258000 0 0x2000>; }; dramc_ch2_top6@1025a000 { compatible = "mediatek,dramc_ch2_top6"; reg = <0 0x1025a000 0 0x2000>; }; ap_ccif5@1025c000 { compatible = "mediatek,ap_ccif5"; reg = <0 0x1025c000 0 0x1000>; }; md_ccif5@1025d000 { compatible = "mediatek,md_ccif5"; reg = <0 0x1025d000 0 0x1000>; }; mm_vpu_m0_sub_common@1025e000 { compatible = "mediatek,mm_vpu_m0_sub_common"; reg = <0 0x1025e000 0 0x1000>; }; mm_vpu_m1_sub_common@1025f000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1025f000 0 0x1000>; }; dramc_ch3_top0@10260000 { compatible = "mediatek,dramc_ch3_top0"; reg = <0 0x10260000 0 0x2000>; }; dramc_ch3_top1@10262000 { compatible = "mediatek,dramc_ch3_top1"; reg = <0 0x10262000 0 0x2000>; }; dramc_ch3_top2@10264000 { compatible = "mediatek,dramc_ch3_top2"; reg = <0 0x10264000 0 0x1000>; }; dramc_ch3_top4@10266000 { compatible = "mediatek,dramc_ch3_top4"; reg = <0 0x10266000 0 0x2000>; }; dramc_ch3_top5@10268000 { compatible = "mediatek,dramc_ch3_top5"; reg = <0 0x10268000 0 0x2000>; }; dramc_ch3_top6@1026a000 { compatible = "mediatek,dramc_ch3_top6"; reg = <0 0x1026a000 0 0x2000>; }; bcrm_peri@10272000 { compatible = "mediatek,bcrm_peri"; reg = <0 0x10272000 0 0x1000>; }; bcrm_peri2@10273000 { compatible = "mediatek,bcrm_peri2"; reg = <0 0x10273000 0 0x1000>; }; devapc_peri@10274000 { compatible = "mediatek,devapc_peri"; reg = <0 0x10274000 0 0x1000>; }; devapc_peri2@10275000 { compatible = "mediatek,devapc_peri2"; reg = <0 0x10275000 0 0x1000>; }; bcrm_fmem@10276000 { compatible = "mediatek,bcrm_fmem"; reg = <0 0x10276000 0 0x1000>; }; mm_vpu_m0_sub_common@10309000 { compatible = "mediatek,mm_vpu_m0_sub_common"; reg = <0 0x10309000 0 0x1000>; }; mm_vpu_m1_sub_common@1030a000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030a000 0 0x1000>; }; mm_vpu_m1_sub_common@1030b000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030b000 0 0x1000>; }; mm_vpu_m1_sub_common@1030c000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030c000 0 0x1000>; }; mm_vpu_m1_sub_common@1030d000 { compatible = "mediatek,mm_vpu_m1_sub_common"; reg = <0 0x1030d000 0 0x1000>; }; sys_cirq1@10312000 { compatible = "mediatek,sys_cirq1"; reg = <0 0x10312000 0 0x1000>; }; sys_cirq2@10313000 { compatible = "mediatek,sys_cirq2"; reg = <0 0x10313000 0 0x1000>; }; dbg_tracker@10314000 { compatible = "mediatek,dbg_tracker"; reg = <0 0x10314000 0 0x1000>; }; sspm@10400000 { compatible = "mediatek,sspm"; reg = <0 0x10400000 0 0x28000>, <0 0x10440000 0 0x10000>, <0 0x10450000 0 0x100>, <0 0x10451000 0 0x4>, <0 0x10451004 0 0x4>, <0 0x10460000 0 0x100>, <0 0x10461000 0 0x4>, <0 0x10461004 0 0x4>, <0 0x10470000 0 0x100>, <0 0x10471000 0 0x4>, <0 0x10471004 0 0x4>, <0 0x10480000 0 0x100>, <0 0x10481000 0 0x4>, <0 0x10481004 0 0x4>, <0 0x10490000 0 0x100>, <0 0x10491000 0 0x4>, <0 0x10491004 0 0x4>; reg-names = "sspm_base", "cfgreg", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox4_base", "mbox4_set", "mbox4_clr"; interrupts = , , , , , ; interrupt-names = "ipc", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; }; tinsys@10500000 { compatible = "mediatek,tinsys"; reg = <0 0x10500000 0 0x0>; }; scp: scp@10700000 { compatible = "mediatek,scp"; status = "okay"; reg = <0 0x10500000 0 0x100000>, /* tcm */ <0 0x10724000 0 0x1000>, /* cfg */ <0 0x10721000 0 0x1000>, /* clk*/ <0 0x10730000 0 0x1000>, /* cfg core0 */ <0 0x10740000 0 0x1000>, /* cfg core1 */ <0 0x10752000 0 0x1000>, /* bus tracker */ <0 0x10760000 0 0x40000>, /* llc */ <0 0x107a5000 0 0x4>, /* cfg_sec */ <0 0x107fb000 0 0x100>, /* mbox0 base */ <0 0x107fb100 0 0x4>, /* mbox0 set */ <0 0x107fb10c 0 0x4>, /* mbox0 clr */ <0 0x107a5020 0 0x4>, /* mbox0 init */ <0 0x107fc000 0 0x100>, /* mbox1 base */ <0 0x107fc100 0 0x4>, /* mbox1 set */ <0 0x107fc10c 0 0x4>, /* mbox1 clr */ <0 0x107a5024 0 0x4>, /* mbox1 init */ <0 0x107fd000 0 0x100>, /* mbox2 base */ <0 0x107fd100 0 0x4>, /* mbox2 set */ <0 0x107fd10c 0 0x4>, /* mbox2 clr */ <0 0x107a5028 0 0x4>, /* mbox2 init */ <0 0x107fe000 0 0x100>, /* mbox3 base */ <0 0x107fe100 0 0x4>, /* mbox3 set */ <0 0x107fe10c 0 0x4>, /* mbox3 clr */ <0 0x107a502c 0 0x4>, /* mbox3 init */ <0 0x107ff000 0 0x100>, /* mbox4 base */ <0 0x107ff100 0 0x4>, /* mbox4 set */ <0 0x107ff10c 0 0x4>, /* mbox4 clr */ <0 0x107a5030 0 0x4>; /* mbox4 init */ reg-names = "scp_sram_base", "scp_cfgreg", "scp_clkreg", "scp_cfgreg_core0", "scp_cfgreg_core1", "scp_bus_tracker", "scp_l1creg", "scp_cfgreg_sec", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_init"; interrupts = , , , , , , ; interrupt-names = "ipc0", "ipc1", "mbox0", "mbox1", "mbox2", "mbox3", "mbox4"; core_0 = "enable"; scp_sramSize = <0x00100000>; core_nums = <2>; /* core number */ twohart = <0>; /* two hart arch */ mbox_count = <5>; /* id, mbox, send_size*/ send_table = < 0 0 9>,/* IPI_OUT_AUDIO_VOW_1 */ < 3 1 2>,/* IPI_OUT_APCCCI_0 */ < 4 1 1>,/* IPI_OUT_DVFS_SET_FREQ_0 */ < 5 1 2>,/* IPI_OUT_C_SLEEP_0 */ < 6 1 1>,/* IPI_OUT_TEST_0 */ <26 1 9>,/* IPI_OUT_AUDIO_ULTRA_SND_0 */ <11 2 34>,/* IPI_OUT_SCP_MPOOL_0 */ <14 3 1>,/* IPI_OUT_DVFS_SET_FREQ_1 */ <15 3 2>,/* IPI_OUT_C_SLEEP_1 */ <16 3 1>,/* IPI_OUT_TEST_1 */ <17 3 6>,/* IPI_OUT_LOGGER_CTRL */ <18 3 2>,/* IPI_OUT_SCPCTL_1 */ <24 4 34>;/* IPI_OUT_SCP_MPOOL_1 */ /* id, mbox, recv_size, recv_opt */ recv_table = < 1 0 2 0>,/* IPI_IN_AUDIO_VOW_ACK_1 */ < 2 0 26 0>,/* IPI_IN_AUDIO_VOW_1 */ < 7 1 2 0>,/* IPI_IN_APCCCI_0 */ < 8 1 10 0>,/* IPI_IN_SCP_ERROR_INFO_0 */ < 9 1 1 0>,/* IPI_IN_SCP_READY_0 */ <10 1 2 0>,/* IPI_IN_SCP_RAM_DUMP_0 */ <27 1 2 0>,/* IPI_IN_AUDIO_ULTRA_SND_ACK_0 */ <28 1 5 0>,/* IPI_IN_AUDIO_ULTRA_SND_0 */ < 5 1 1 1>,/* IPI_OUT_C_SLEEP_0 */ <12 2 30 0>,/* IPI_IN_SCP_MPOOL_0 */ <20 3 10 0>,/* IPI_IN_SCP_ERROR_INFO_1 */ <21 3 6 0>,/* IPI_IN_LOGGER_CTRL */ <22 3 1 0>,/* IPI_IN_SCP_READY_1 */ <23 3 2 0>,/* IPI_IN_SCP_RAM_DUMP_1 */ <15 3 1 1>,/* IPI_OUT_C_SLEEP_1 */ <25 4 30 0>;/* IPI_IN_SCP_MPOOL_1 */ legacy_table = <11>, /* out_id_0 IPI_OUT_SCP_MPOOL_0 */ <24>, /* out_id_1 IPI_OUT_SCP_MPOOL_1 */ <12>, /* in_id_0 IPI_IN_SCP_MPOOL_0 */ <25>, /* in_id_1 IPI_IN_SCP_MPOOL_1 */ <34>, /* out_size */ <30>; /* in_size */ /* feature, frequecy, coreid */ scp_feature_tbl = <0 5 1>, /* vow */ <1 29 0>, /* sensor */ <2 26 0>, /* flp */ <3 0 0>, /* rtos */ <4 200 1>, /* speaker */ <5 0 0>, /* vcore */ <6 135 1>, /* barge in */ <7 10 1>, /* vow dump */ <8 80 1>, /* vow vendor M */ <9 43 1>, /* vow vendor A */ <10 22 1>, /* vow vendor G */ <11 20 1>, /* vow dual mic */ <12 135 1>, /* vow dual mic barge in */ <13 200 0>; /* ultrasound */ secure_dump = "disable"; /* disabled in default */ secure_dump_size = <0>; scp_mem_key = "mediatek,reserve-memory-scp_share"; scp_mem_tbl = <0 0x0>, /* secure dump, its size is in secure_dump_size */ <1 0x4E300>, /* vow */ <2 0x100000>, /* sensor main*/ <3 0x180000>, /* logger */ <4 0x19000>, /* audio */ <5 0x5A00>; /* vow bargein */ memorydump = <0x100000>, /* l2tcm */ <0x03c000>, /* l1c */ <0x003f00>, /* regdump */ <0x000100>, /* trace buffer */ <0x100000>; /* dram */ }; adsp_common: adsp_common@10800000 { compatible = "mediatek,adsp_common"; reg = <0 0x1080b000 0 0x50>, /* CFG SECURE */ <0 0x10806000 0 0x100>, /* MBOX0 base */ <0 0x10806100 0 0x4>, /* MBOX0 set */ <0 0x1080610c 0 0x4>, /* MBOX0 clr */ <0 0x1080b050 0 0x4>, /* MBOX0 init */ <0 0x10807000 0 0x100>, /* MBOX1 base */ <0 0x10807100 0 0x4>, /* MBOX1 set */ <0 0x1080710c 0 0x4>, /* MBOX1 clr */ <0 0x1080b054 0 0x4>, /* MBOX1 init */ <0 0x10808000 0 0x100>, /* MBOX2 base */ <0 0x10808100 0 0x4>, /* MBOX2 set */ <0 0x1080810c 0 0x4>, /* MBOX2 clr */ <0 0x1080b058 0 0x4>, /* MBOX2 init */ <0 0x10809000 0 0x100>, /* MBOX3 base */ <0 0x10809100 0 0x4>, /* MBOX3 set */ <0 0x1080910c 0 0x4>, /* MBOX3 clr */ <0 0x1080b05c 0 0x4>; /* MBOX3 init */ reg-names = "cfg_secure", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_init", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_init", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_init", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_init"; interrupts = , /* MBOX0 */ , /* MBOX1 */ , /* MBOX2 */ ; /* MBOX3 */ interrupt-names = "mbox0", "mbox1", "mbox2", "mbox3"; #mbox-cells = <1>; clocks = <&scpsys SCP_SYS_ADSP>, <&scp_adsp SCP_ADSP_CK_CG>, <&topckgen TOP_MUX_ADSP>, <&clk26m>, <&topckgen TOP_ADSPPLL_CK>, <&topckgen TOP_MUX_SCP>; clock-names = "scp_sys_adsp", "clk_adsp_ck_cg", "clk_top_adsp_sel", "clk_top_clk26m", "clk_top_adsppll", "clk_top_scp_sel"; adsp-rsv-ipidma-a = <0x100000>; adsp-rsv-ipidma-b = <0x100000>; adsp-rsv-logger-a = <0x80000>; adsp-rsv-logger-b = <0x80000>; adsp-rsv-c2c = <0x40000>; adsp-rsv-dbg-dump-a = <0x80000>; adsp-rsv-dbg-dump-b = <0x80000>; adsp-rsv-core-dump-a = <0x400>; adsp-rsv-core-dump-b = <0x400>; adsp-rsv-audio = <0x5c0000>; }; adsp_core0: adsp_core0@10820000 { compatible = "mediatek,adsp_core_0"; reg = <0 0x10800000 0 0x6000>, /* CFG */ <0 0x10840000 0 0x9000>, /* ITCM */ <0 0x10820000 0 0x8000>; /* DTCM */ system = <0 0x56000000 0 0x700000>; interrupts = , , ; mboxes = <&adsp_common 0>, /*channel 0*/ <&adsp_common 1>; /*channel 1*/ feature_control_bits = <0x2303ff>; }; adsp_core1: adsp_core1@10850000 { compatible = "mediatek,adsp_core_1"; reg = <0 0x10800000 0 0x6000>, /* CFG */ <0 0x10870000 0 0x9000>, /* ITCM */ <0 0x10850000 0 0x8000>; /* DTCM */ system = <0 0x56700000 0 0x700000>; interrupts = , , ; mboxes = <&adsp_common 2>, /*channel 2*/ <&adsp_common 3>; /*channel 3*/ feature_control_bits = <0x18F00F>; }; dramc_ch1_rsv0@10900000 { compatible = "mediatek,dramc_ch1_rsv0"; reg = <0 0x10900000 0 0x40000>; }; dramc_ch1_rsv1@10940000 { compatible = "mediatek,dramc_ch1_rsv1"; reg = <0 0x10940000 0 0xc0000>; }; gic500@0c000000 { compatible = "mediatek,gic500"; reg = <0 0x0c000000 0 0x400000>; }; gic_cpu@0c400000 { compatible = "mediatek,gic_cpu"; reg = <0 0x0c400000 0 0x40000>; }; dfd@0c600000 { compatible = "mediatek,dfd"; mediatek,enabled = <1>; mediatek,chain_length = <0x9c40>; mediatek,rg_dfd_timeout = <0xa0>; mediatek,check_dfd_support = <1>; mediatek,dfd_infra_base = <0x34>; mediatek,dfd_ap_addr_offset = <24>; mediatek,dfd_latch_offset = <0x44>; }; dfd_cache: dfd_cache { compatible = "mediatek,dfd_cache"; mediatek,enabled = <0>; mediatek,l2c_trigger = <0>; mediatek,rg_dfd_timeout = <0x5dc0>; }; dbg_ao@0d000000 { compatible = "mediatek,dbg_ao"; reg = <0 0x0d000000 0 0x10000>; }; dbg_cti@0d020000 { compatible = "mediatek,dbg_cti"; reg = <0 0x0d020000 0 0x10000>; }; dbg_etr@0d030000 { compatible = "mediatek,dbg_etr"; reg = <0 0x0d030000 0 0x10000>; }; bus_tracer@0d040000 { compatible = "mediatek,bus_tracer-v1"; reg = <0 0x0d040000 0 0x100>, /* dem base */ <0 0x0d01a000 0 0x1000>, /* dbgao base */ <0 0x0d041000 0 0x3000>, /* funnel/rep/etr base */ <0 0x0d010000 0 0x1000>, /* bus tracer etb base */ <0 0x0d040800 0 0x100>, /* infra bus tracer base */ <0 0x0d040900 0 0x100>, /* peri1 bus tracer base */ <0 0x0d040a00 0 0x100>; /* peri2 bus tracer base */ /* * index 0 for infra bus tracer * index 1 for peri1 bus tracer * index 2 for peri2 bus tracer */ mediatek,num_tracer = <3>; mediatek,enabled_tracer = <1 1 1>; mediatek,at_id = <0x10 0x30 0x70>; /* filters: disabled by default */ /* * mediatek,watchpoint_filter = <0x0 0x10010000 0xfffff000>; * mediatek,bypass_filter = <0x14000000 0xffff0000>; * mediatek,id_filter = <0x10 0x40>; * mediatek,rw_filter = <0x0 0x1>; */ }; dbg_dem@0d0a0000 { compatible = "mediatek,dbg_dem"; reg = <0 0x0d0a0000 0 0x10000>; interrupts = ; }; dbg_mdsys1@0d0c0000 { compatible = "mediatek,dbg_mdsys1"; reg = <0 0x0d0c0000 0 0x40000>; }; auxadc: auxadc@11001000 { compatible = "mediatek,mt6768-auxadc"; reg = <0 0x11001000 0 0x1000>; interrupts = ; clocks = <&infracfg_ao INFRACFG_AO_AUXADC_CG>; clock-names = "main"; #io-channel-cells = <1>; /* Auxadc efuse calibration */ /* 1. Auxadc cali on/off bit shift */ mediatek,cali-en-bit = <20>; /* 2. Auxadc cali ge bits shift */ mediatek,cali-ge-bit = <10>; /* 3. Auxadc cali oe bits shift */ mediatek,cali-oe-bit = <0>; /* 4. Auxadc cali efuse index */ mediatek,cali-efuse-index = <113>; }; eem_fsm: eem_fsm@11278000 { compatible = "mediatek,eem_fsm"; reg = <0 0x11278000 0 0x1000>; interrupts = ; eem-status = <1>; sn-status = <1>; eem-initmon-little = <0xff>; eem-initmon-big = <0xff>; eem-initmon-cci = <0xff>; eem-initmon-gpu = <0xff>; eem-clamp-little = <0>; eem-clamp-big = <0>; eem-clamp-cci = <0>; eem-clamp-gpu = <0>; eem-offset-little = <0xff>; eem-offset-big = <0xff>; eem-offset-cci = <0xff>; eem-offset-gpu = <0xff>; nvmem = <&efuse>; nvmem-names = "mtk_efuse"; nvmem-cells = <&efuse_segment>; nvmem-cell-names = "efuse_segment_cell"; }; eemgpu_fsm: eemgpu_fsm@1100b000 { compatible = "mediatek,eemgpu_fsm"; reg = <0 0x1100b000 0 0x1000>; interrupts = ; eemg-status = <1>; eemg-initmon-gpu = <0xf>; eemg-clamp-gpu = <0>; eemg-offset-gpu = <0xff>; }; therm_ctrl@1100b000 { compatible = "mediatek,therm_ctrl"; reg = <0 0x1100b000 0 0x26E200>; interrupts = , ; clocks = <&infracfg_ao INFRACFG_AO_THERM_CG>; clock-names = "therm-main"; }; tboard_thermistor1: thermal-sensor1 { compatible = "mediatek,mtboard-thermistor1"; io-channels = <&auxadc 0>; io-channel-names = "thermistor-ch0"; }; tboard_thermistor2: thermal-sensor2 { compatible = "mediatek,mtboard-thermistor2"; io-channels = <&auxadc 1>; io-channel-names = "thermistor-ch1"; }; tboard_thermistor3: thermal-sensor3 { compatible = "mediatek,mtboard-thermistor3"; io-channels = <&auxadc 2>; io-channel-names = "thermistor-ch2"; }; mali: mali@13000000 { compatible = "mediatek,mali", "arm,mali-valhall"; reg = <0 0x13000000 0 0x4000>; interrupts = , , , , ; interrupt-names = "GPU", "MMU", "JOB", "EVENT", "PWR"; ged-supply = <&ged>; }; gpufreq: gpufreq { compatible = "mediatek,gpufreq"; clocks = <&topckgen TOP_MUX_MFG_PLL>, <&topckgen TOP_MFGPLL_CK>, <&topckgen TOP_MUX_MFG_REF>, <&g3d_config MFGCFG_BG3D>, <&scpsys SCP_SYS_MFG0>, <&scpsys SCP_SYS_MFG1>, <&scpsys SCP_SYS_MFG2>, <&scpsys SCP_SYS_MFG3>, <&scpsys SCP_SYS_MFG4>, <&scpsys SCP_SYS_MFG5>, <&scpsys SCP_SYS_MFG6>; clock-names = "clk_mux", /* switch main/sub */ "clk_main_parent", /* main pll freq */ "clk_sub_parent", /* default 218.4 MHz */ "subsys_bg3d", "mtcmos_mfg0", /* ASYNC */ "mtcmos_mfg1", /* MFG_TOP */ "mtcmos_mfg2", /* Shader Stack0 */ "mtcmos_mfg3", /* Shader Stack2 tile 0 */ "mtcmos_mfg4", /* Shader Stack2 tile 1 */ "mtcmos_mfg5", /* Shader Stack4 */ "mtcmos_mfg6"; /* Shader Stack6 */ #ifndef CONFIG_FPGA_EARLY_PORTING _vgpu-supply = <&mt6315_7_vbuck1>; _vsram_gpu-supply = <&mt_pmic_vsram_others_ldo_reg>; #endif }; ged: ged { compatible = "mediatek,ged"; gpufreq-supply = <&gpufreq>; }; bt: bt@00000000 { compatible = "mediatek,bt"; pm_qos_support = <1>; }; btif@1100c000 { compatible = "mediatek,btif"; /*btif base*/ reg = <0 0x1100c000 0 0x1000>, /*btif tx dma base*/ <0 0x10217d80 0 0x80>, /*btif rx dma base*/ <0 0x10217e00 0 0x80>; /*btif irq, IRQS_Sync ID, btif_irq_b*/ interrupts = , /*btif tx dma irq*/ , /*btif rx dma irq*/ ; clocks = <&infracfg_ao INFRACFG_AO_BTIF_CG>, /*btif clock*/ <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; /*ap dma clock*/ clock-names = "btifc","apdmac"; }; wifi: wifi@18000000 { compatible = "mediatek,wifi"; reg = <0 0x18000000 0 0x100000>; interrupts = ; memory-region = <&wifi_mem>; }; consys: consys@18002000 { compatible = "mediatek,mt6873-consys"; #address-cells = <2>; #size-cells = <2>; /*CONN_MCU_CONFIG_BASE */ reg = <0 0x18002000 0 0x1000>, /*TOP_RGU_BASE */ <0 0x10007000 0 0x0100>, /*INFRACFG_AO_BASE */ <0 0x10001000 0 0x1000>, /*SPM_BASE */ <0 0x10006000 0 0x1000>, /*CONN_HIF_ON_BASE */ <0 0x18007000 0 0x1000>, /*CONN_TOP_MISC_OFF_BASE */ <0 0x180b1000 0 0x1000>, /*CONN_MCU_CFG_ON_BASE */ <0 0x180a3000 0 0x1000>, /*CONN_MCU_CIRQ_BASE */ <0 0x180a5000 0 0x800>, /*CONN_TOP_MISC_ON_BASE */ <0 0x180c1000 0 0x1000>, /*CONN_HIF_PDMA_BASE */ <0 0x18004000 0 0x1000>, /* INFRASYS_COMMON AP2MD_PCCIF4_BASE */ <0 0x1024C000 0 0x40>, /*INFRA_AO_PERICFG_BASE */ <0 0x10003000 0 0x1000>; /*BGF_EINT */ interrupts = , /*WDT_EINT */ , /*conn2ap_sw_irq*/ ; clocks = <&scpsys SCP_SYS_CONN>, <&infracfg_ao INFRACFG_AO_CCIF4_AP_CG>; clock-names = "conn", "ccif"; memory-region = <&consys_mem>; }; mali_dvfs_hint@13fbb000 { compatible = "mediatek,mali_dvfs_hint", "syscon"; reg = <0 0x13fbb000 0 0x1000>; #clock-cells = <1>; }; g3d_secure_reg@13fbc000 { compatible = "mediatek,g3d_secure_reg"; reg = <0 0x13fbc000 0 0x1000>; }; g3d_testbench@13fbd000 { compatible = "mediatek,g3d_testbench", "syscon"; reg = <0 0x13fbd000 0 0x1000>; #clock-cells = <1>; }; afe: mt6873-afe-pcm@11210000 { compatible = "mediatek,mt6873-sound"; reg = <0 0x11210000 0 0x2000>; interrupts = ; topckgen = <&topckgen>; apmixed = <&apmixed>; infracfg_ao = <&infracfg_ao>; clocks = <&audio AUDIO_PDN_AFE>, <&audio AUDIO_PDN_DAC>, <&audio AUDIO_PDN_DAC_PREDIS>, <&audio AUDIO_PDN_ADC>, <&audio AUDIO_PDN_ADDA6_ADC>, <&audio AUDIO_PDN_22M>, <&audio AUDIO_PDN_24M>, <&audio AUDIO_PDN_APLL_TUNER>, <&audio AUDIO_PDN_APLL2_TUNER>, <&audio AUDIO_PDN_TDM_CK>, <&audio AUDIO_PDN_TML>, <&audio AUDIO_PDN_NLE>, <&audio AUDIO_PDN_DAC_HIRES>, <&audio AUDIO_PDN_ADC_HIRES>, <&audio AUDIO_PDN_ADC_HIRES_TML>, <&audio AUDIO_PDN_ADDA6_ADC_HIRES>, <&audio AUDIO_PDN_3RD_DAC>, <&audio AUDIO_PDN_3RD_DAC_PREDIS>, <&audio AUDIO_PDN_3RD_DAC_TML>, <&audio AUDIO_PDN_3RD_DAC_HIRES>, <&scpsys SCP_SYS_AUDIO>, <&infracfg_ao INFRACFG_AO_AUDIO_CG>, <&infracfg_ao INFRACFG_AO_AUDIO_26M_BCLK_CK>, <&topckgen TOP_MUX_AUDIO>, <&topckgen TOP_MUX_AUD_INTBUS>, <&topckgen TOP_MAINPLL_D4_D4>, <&topckgen TOP_MUX_AUD_1>, <&topckgen TOP_APLL1_CK>, <&topckgen TOP_MUX_AUD_2>, <&topckgen TOP_APLL2_CK>, <&topckgen TOP_MUX_AUD_ENGEN1>, <&topckgen TOP_APLL1_D4>, <&topckgen TOP_MUX_AUD_ENGEN2>, <&topckgen TOP_APLL2_D4>, <&topckgen TOP_I2S0_M_SEL>, <&topckgen TOP_I2S1_M_SEL>, <&topckgen TOP_I2S2_M_SEL>, <&topckgen TOP_I2S3_M_SEL>, <&topckgen TOP_I2S4_M_SEL>, <&topckgen TOP_I2S5_M_SEL>, <&topckgen TOP_I2S6_M_SEL>, <&topckgen TOP_I2S7_M_SEL>, <&topckgen TOP_I2S8_M_SEL>, <&topckgen TOP_I2S9_M_SEL>, <&topckgen TOP_APLL12_DIV0>, <&topckgen TOP_APLL12_DIV1>, <&topckgen TOP_APLL12_DIV2>, <&topckgen TOP_APLL12_DIV3>, <&topckgen TOP_APLL12_DIV4>, <&topckgen TOP_APLL12_DIVB>, <&topckgen TOP_APLL12_DIV5>, <&topckgen TOP_APLL12_DIV6>, <&topckgen TOP_APLL12_DIV7>, <&topckgen TOP_APLL12_DIV8>, <&topckgen TOP_APLL12_DIV9>, <&topckgen TOP_MUX_AUDIO_H>, <&clk26m>; clock-names = "aud_afe_clk", "aud_dac_clk", "aud_dac_predis_clk", "aud_adc_clk", "aud_adda6_adc_clk", "aud_apll22m_clk", "aud_apll24m_clk", "aud_apll1_tuner_clk", "aud_apll2_tuner_clk", "aud_tdm_clk", "aud_tml_clk", "aud_nle", "aud_dac_hires_clk", "aud_adc_hires_clk", "aud_adc_hires_tml", "aud_adda6_adc_hires_clk", "aud_3rd_dac_clk", "aud_3rd_dac_predis_clk", "aud_3rd_dac_tml", "aud_3rd_dac_hires_clk", "scp_sys_audio", "aud_infra_clk", "aud_infra_26m_clk", "top_mux_audio", "top_mux_audio_int", "top_mainpll_d4_d4", "top_mux_aud_1", "top_apll1_ck", "top_mux_aud_2", "top_apll2_ck", "top_mux_aud_eng1", "top_apll1_d4", "top_mux_aud_eng2", "top_apll2_d4", "top_i2s0_m_sel", "top_i2s1_m_sel", "top_i2s2_m_sel", "top_i2s3_m_sel", "top_i2s4_m_sel", "top_i2s5_m_sel", "top_i2s6_m_sel", "top_i2s7_m_sel", "top_i2s8_m_sel", "top_i2s9_m_sel", "top_apll12_div0", "top_apll12_div1", "top_apll12_div2", "top_apll12_div3", "top_apll12_div4", "top_apll12_divb", "top_apll12_div5", "top_apll12_div6", "top_apll12_div7", "top_apll12_div8", "top_apll12_div9", "top_mux_audio_h", "top_clk26m_clk"; pinctrl-names = "aud_clk_mosi_off", "aud_clk_mosi_on", "aud_dat_mosi_off", "aud_dat_mosi_on", "aud_dat_miso_off", "aud_dat_miso_on", "vow_dat_miso_off", "vow_dat_miso_on", "vow_clk_miso_off", "vow_clk_miso_on", "aud_nle_mosi_off", "aud_nle_mosi_on", "aud_dat_miso2_off", "aud_dat_miso2_on", "aud_gpio_i2s0_off", "aud_gpio_i2s0_on", "aud_gpio_i2s1_off", "aud_gpio_i2s1_on", "aud_gpio_i2s2_off", "aud_gpio_i2s2_on", "aud_gpio_i2s3_off", "aud_gpio_i2s3_on", "aud_gpio_i2s5_off", "aud_gpio_i2s5_on", "aud_gpio_i2s6_off", "aud_gpio_i2s6_on", "aud_gpio_i2s7_off", "aud_gpio_i2s7_on", "aud_gpio_i2s8_off", "aud_gpio_i2s8_on", "aud_gpio_i2s9_off", "aud_gpio_i2s9_on", "aud_dat_mosi_ch34_off", "aud_dat_mosi_ch34_on", "aud_dat_miso_ch34_off", "aud_dat_miso_ch34_on"; pinctrl-0 = <&aud_clk_mosi_off>; pinctrl-1 = <&aud_clk_mosi_on>; pinctrl-2 = <&aud_dat_mosi_off>; pinctrl-3 = <&aud_dat_mosi_on>; pinctrl-4 = <&aud_dat_miso_off>; pinctrl-5 = <&aud_dat_miso_on>; pinctrl-6 = <&vow_dat_miso_off>; pinctrl-7 = <&vow_dat_miso_on>; pinctrl-8 = <&vow_clk_miso_off>; pinctrl-9 = <&vow_clk_miso_on>; pinctrl-10 = <&aud_nle_mosi_off>; pinctrl-11 = <&aud_nle_mosi_on>; pinctrl-12 = <&aud_dat_miso2_off>; pinctrl-13 = <&aud_dat_miso2_on>; pinctrl-14 = <&aud_gpio_i2s0_off>; pinctrl-15 = <&aud_gpio_i2s0_on>; pinctrl-16 = <&aud_gpio_i2s1_off>; pinctrl-17 = <&aud_gpio_i2s1_on>; pinctrl-18 = <&aud_gpio_i2s2_off>; pinctrl-19 = <&aud_gpio_i2s2_on>; pinctrl-20 = <&aud_gpio_i2s3_off>; pinctrl-21 = <&aud_gpio_i2s3_on>; pinctrl-22 = <&aud_gpio_i2s5_off>; pinctrl-23 = <&aud_gpio_i2s5_on>; pinctrl-24 = <&aud_gpio_i2s6_off>; pinctrl-25 = <&aud_gpio_i2s6_on>; pinctrl-26 = <&aud_gpio_i2s7_off>; pinctrl-27 = <&aud_gpio_i2s7_on>; pinctrl-28 = <&aud_gpio_i2s8_off>; pinctrl-29 = <&aud_gpio_i2s8_on>; pinctrl-30 = <&aud_gpio_i2s9_off>; pinctrl-31 = <&aud_gpio_i2s9_on>; pinctrl-32 = <&aud_dat_mosi_ch34_off>; pinctrl-33 = <&aud_dat_mosi_ch34_on>; pinctrl-34 = <&aud_dat_miso_ch34_off>; pinctrl-35 = <&aud_dat_miso_ch34_on>; }; mt6359_snd: mt6359_snd { compatible = "mediatek,mt6359-sound"; mediatek,pwrap-regmap = <&pwrap>; nvmem = <&pmic_efuse>; nvmem-names = "pmic-hp-efuse"; io-channels = <&pmic_auxadc AUXADC_HPOFS_CAL>, <&pmic_auxadc AUXADC_ACCDET>; io-channel-names = "pmic_hpofs_cal", "pmic_accdet"; }; sound: sound { compatible = "mediatek,mt6873-mt6359-sound"; mediatek,audio-codec = <&mt6359_snd>; mediatek,platform = <&afe>; mediatek,snd_audio_dsp = <&snd_audio_dsp>; mtk_spk_i2s_out = <3>; mtk_spk_i2s_in = <0>; /* mtk_spk_i2s_mck = <3>; */ mediatek,speaker-codec { sound-dai = <&speaker_amp>; }; }; /* feature : $enable $dl_mem $ul_mem $ref_mem $size */ snd_audio_dsp: snd_audio_dsp { compatible = "mediatek,snd_audio_dsp"; mtk_dsp_voip = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk_dsp_primary = <0x5 0xffffffff 0xffffffff \ 0xffffffff 0x30000>; mtk_dsp_offload = <0x1d 0xffffffff 0xffffffff \ 0xffffffff 0x400000>; mtk_dsp_deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>; mtk_dsp_playback = <0x1 0x4 0xffffffff 0x14 0x30000>; mtk_dsp_music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>; mtk_dsp_capture1 = <0x1 0xffffffff 0xd 0x13 0x20000>; mtk_dsp_a2dp = <0x0 0xffffffff 0xffffffff 0xffffffff 0x40000>; mtk_dsp_dataprovider = <0x0 0xffffffff 0xf 0xffffffff 0x30000>; mtk_dsp_call_final = <0x5 0x4 0x10 0x14 0x18000>; mtk_dsp_fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>; mtk_dsp_ktv = <0x1 0x8 0x12 0xffffffff 0x10000>; mtk_dsp_capture_raw = <0x1 0xffffffff 0xffffffff 0xffffffff 0x20000>; mtk_dsp_fm = <0x1 0xffffffff 0x10 0xffffffff 0x10000>; mtk_dsp_ver = <0x1>; swdsp_smartpa_process_enable = <0x5>; mtk_dsp_mem_afe = <0x1 0x40000>; /* always enable */ }; audio_sram@11212000 { compatible = "mediatek,audio_sram"; reg = <0 0x11212000 0 0x18000>; prefer_mode = <0>; mode_size = <0x12000 0x18000>; block_size = <0x1000>; }; btcvsd_snd: mtk-btcvsd-snd@18050000 { compatible = "mediatek,mtk-btcvsd-snd"; reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/ <0 0x18080000 0 0x14000>; /*SRAM_BANK2*/ interrupts = ; mediatek,infracfg = <&infracfg_ao>; /*INFRA MISC, conn_bt_cvsd_mask*/ /*cvsd_mcu_read, write, packet_indicator*/ mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>; disable_write_silence = <1>; }; mt_soc_playback_offload { compatible = "mediatek,mt_soc_offload_common"; }; mtk_mdla: mdla@19036000 { compatible = "mtk,mdla"; reg = <0 0x19034000 0 0x1000>, /* dla0 config */ <0 0x19036000 0 0x1000>, /* dla0 command */ <0 0x19035000 0 0x1000>, /* dla0 biu */ <0 0x1d000000 0 0x100000>,/* GSM,TODO */ <0 0x19020000 0 0x40000>; /* APU CONN */ interrupts = ; }; apusys_mnoc@1906e000 { compatible = "mediatek,apusys_mnoc"; reg = <0 0x1906e000 0 0xa000>, /* mnoc reg */ <0 0x19001000 0 0x1000>, /* apusys int */ <0 0x19020000 0 0x1000>, /* apu_conn_config */ <0 0x10001000 0 0x1000>, /* slp prot 1 */ <0 0x10215000 0 0x1000>; /* slp prot 2 */ interrupts = ; }; apusys_reviser@19021000 { compatible = "mediatek,apusys_reviser"; reg = <0 0x19021000 0 0x1000>, /* apu_sctrl_reviser */ <0 0x1d800000 0 0x200000>, /* VLM */ <0 0x1d000000 0 0x100000>, /* TCM */ <0 0x19001000 0 0x1000>; /* apusys int */ interrupts = ; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_VLM>; #endif }; apusys_devapc@19064000 { compatible = "mediatek,mt6873-apusys_devapc"; reg = <0 0x19064000 0 0x1000>; interrupts = ; }; apusys_power { compatible = "mediatek,apusys_power"; reg = <0 0x190f0000 0 0x1000>, <0 0x190f1000 0 0x1000>, <0 0x19029000 0 0x1000>; reg-names = "apusys_rpc", "apusys_pcu", "apusys_vcore"; vvpu-supply = <&mt_pmic_vproc1_buck_reg>; vmdla-supply = <&mt_pmic_vproc2_buck_reg>; vsram_apu-supply = <&mt_pmic_vsram_md_ldo_reg>; vcore-supply = <&mt_pmic_vgpu11_buck_reg>; clocks = <&topckgen TOP_MUX_DSP>, /* CONN */ <&topckgen TOP_MUX_DSP1>, /* VPU_CORE0 */ <&topckgen TOP_MUX_DSP1_NPUPLL>, /* VPU_CORE0 */ <&topckgen TOP_MUX_DSP2>, /* VPU_CORE1 */ <&topckgen TOP_MUX_DSP2_NPUPLL>, /* VPU_CORE1 */ <&topckgen TOP_MUX_DSP5>, /* MDLA0 */ <&topckgen TOP_MUX_DSP5_APUPLL>, /* MDLA0 */ <&topckgen TOP_MUX_IPU_IF>, /* VCORE */ <&apu0 APU0_JTAG_CG>, <&apu0 APU0_AXI_M_CG>, <&apu0 APU0_APU_CG>, <&apu1 APU1_JTAG_CG>, <&apu1 APU1_AXI_M_CG>, <&apu1 APU1_APU_CG>, <&apu_mdla0 APU_MDLA0_MDLA_CG0>, <&apu_mdla0 APU_MDLA0_MDLA_CG1>, <&apu_mdla0 APU_MDLA0_MDLA_CG2>, <&apu_mdla0 APU_MDLA0_MDLA_CG3>, <&apu_mdla0 APU_MDLA0_MDLA_CG4>, <&apu_mdla0 APU_MDLA0_MDLA_CG5>, <&apu_mdla0 APU_MDLA0_MDLA_CG6>, <&apu_mdla0 APU_MDLA0_MDLA_CG7>, <&apu_mdla0 APU_MDLA0_MDLA_CG8>, <&apu_mdla0 APU_MDLA0_MDLA_CG9>, <&apu_mdla0 APU_MDLA0_MDLA_CG10>, <&apu_mdla0 APU_MDLA0_MDLA_CG11>, <&apu_mdla0 APU_MDLA0_MDLA_CG12>, <&apu_mdla0 APU_MDLA0_APB_CG>, <&apu_mdla0 APU_MDLA0_AXI_M_CG>, <&apu_conn APU_CONN_AHB_CG>, <&apu_conn APU_CONN_AXI_CG>, <&apu_conn APU_CONN_ISP_CG>, <&apu_conn APU_CONN_CAM_ADL_CG>, <&apu_conn APU_CONN_IMG_ADL_CG>, <&apu_conn APU_CONN_EMI_26M_CG>, <&apu_conn APU_CONN_VPU_UDI_CG>, <&apu_conn APU_CONN_EDMA_0_CG>, <&apu_conn APU_CONN_EDMA_1_CG>, <&apu_conn APU_CONN_EDMAL_0_CG>, <&apu_conn APU_CONN_EDMAL_1_CG>, <&apu_conn APU_CONN_MNOC_CG>, <&apu_conn APU_CONN_TCM_CG>, <&apu_conn APU_CONN_MD32_CG>, <&apu_conn APU_CONN_IOMMU_0_CG>, <&apu_conn APU_CONN_MD32_32K_CG>, <&apu_vcore APUSYS_VCORE_AHB_CG>, <&apu_vcore APUSYS_VCORE_AXI_CG>, <&apu_vcore APUSYS_VCORE_ADL_CG>, <&apu_vcore APUSYS_VCORE_QOS_CG>, <&clk26m>, <&topckgen TOP_MAINPLL_D4_D2>, <&topckgen TOP_UNIVPLL_D4_D2>, <&topckgen TOP_UNIVPLL_D6_D2>, <&topckgen TOP_MMPLL_D6>, <&topckgen TOP_MMPLL_D5>, <&topckgen TOP_MMPLL_D4>, <&topckgen TOP_UNIVPLL_D5>, <&topckgen TOP_UNIVPLL_D4>, <&topckgen TOP_UNIVPLL_D3>, <&topckgen TOP_MAINPLL_D6>, <&topckgen TOP_MAINPLL_D4>, <&topckgen TOP_MAINPLL_D3>, <&topckgen TOP_TVDPLL_CK>, <&topckgen TOP_APUPLL_CK>, <&topckgen TOP_NPUPLL_CK>, <&apmixed APMIXED_APUPLL>, <&apmixed APMIXED_NPUPLL>, <&scpsys SCP_SYS_VPU>; clock-names = "clk_top_dsp_sel", "clk_top_dsp1_sel", "clk_top_dsp1_npupll_sel", "clk_top_dsp2_sel", "clk_top_dsp2_npupll_sel", "clk_top_dsp5_sel", "clk_top_dsp5_apupll_sel", "clk_top_ipu_if_sel", "clk_apu_core0_jtag_cg", "clk_apu_core0_axi_m_cg", "clk_apu_core0_apu_cg", "clk_apu_core1_jtag_cg", "clk_apu_core1_axi_m_cg", "clk_apu_core1_apu_cg", "clk_apu_mdla0_cg_b0", "clk_apu_mdla0_cg_b1", "clk_apu_mdla0_cg_b2", "clk_apu_mdla0_cg_b3", "clk_apu_mdla0_cg_b4", "clk_apu_mdla0_cg_b5", "clk_apu_mdla0_cg_b6", "clk_apu_mdla0_cg_b7", "clk_apu_mdla0_cg_b8", "clk_apu_mdla0_cg_b9", "clk_apu_mdla0_cg_b10", "clk_apu_mdla0_cg_b11", "clk_apu_mdla0_cg_b12", "clk_apu_mdla0_apb_cg", "clk_apu_mdla0_axi_m_cg", "clk_apu_conn_ahb_cg", "clk_apu_conn_axi_cg", "clk_apu_conn_isp_cg", "clk_apu_conn_cam_adl_cg", "clk_apu_conn_img_adl_cg", "clk_apu_conn_emi_26m_cg", "clk_apu_conn_vpu_udi_cg", "clk_apu_conn_edma_0_cg", "clk_apu_conn_edma_1_cg", "clk_apu_conn_edmal_0_cg", "clk_apu_conn_edmal_1_cg", "clk_apu_conn_mnoc_cg", "clk_apu_conn_tcm_cg", "clk_apu_conn_md32_cg", "clk_apu_conn_iommu_0_cg", "clk_apu_conn_md32_32k_cg", "clk_apusys_vcore_ahb_cg", "clk_apusys_vcore_axi_cg", "clk_apusys_vcore_adl_cg", "clk_apusys_vcore_qos_cg", "clk_top_clk26m", "clk_top_mainpll_d4_d2", "clk_top_univpll_d4_d2", "clk_top_univpll_d6_d2", "clk_top_mmpll_d6", "clk_top_mmpll_d5", "clk_top_mmpll_d4", "clk_top_univpll_d5", "clk_top_univpll_d4", "clk_top_univpll_d3", "clk_top_mainpll_d6", "clk_top_mainpll_d4", "clk_top_mainpll_d3", "clk_top_tvdpll_ck", "clk_top_apupll_ck", "clk_top_npupll_ck", "clk_apmixed_apupll_rate", "clk_apmixed_npupll_rate", "mtcmos_scp_sys_vpu"; }; seninf1@1a004000 { compatible = "mediatek,seninf1"; reg = <0 0x1a004000 0 0x1000>; }; seninf2@1a005000 { compatible = "mediatek,seninf2"; reg = <0 0x1a005000 0 0x1000>; }; seninf3@1a006000 { compatible = "mediatek,seninf3"; reg = <0 0x1a006000 0 0x1000>; }; seninf4@1a007000 { compatible = "mediatek,seninf4"; reg = <0 0x1a007000 0 0x1000>; }; seninf5@1a008000 { compatible = "mediatek,seninf5"; reg = <0 0x1a008000 0 0x1000>; }; seninf6@1a009000 { compatible = "mediatek,seninf6"; reg = <0 0x1a009000 0 0x1000>; }; seninf7@1a00a000 { compatible = "mediatek,seninf7"; reg = <0 0x1a00a000 0 0x1000>; }; seninf8@1a00b000 { compatible = "mediatek,seninf8"; reg = <0 0x1a00b000 0 0x1000>; }; seninf_top@1a004000 { compatible = "mediatek,seninf_top"; reg = <0 0x1a004000 0 0x1000>; #if 0 interrupts = ; #endif clocks = <&scpsys SCP_SYS_MDP>, <&scpsys SCP_SYS_CAM>, <&camsys_clk CAMSYS_MAIN_SENINF_CGPDN>, <&topckgen TOP_MUX_SENINF>, <&topckgen TOP_MUX_SENINF1>, <&topckgen TOP_MUX_SENINF2>, <&topckgen TOP_MUX_SENINF3>, <&topckgen TOP_MUX_CAMTG>, <&topckgen TOP_MUX_CAMTG2>, <&topckgen TOP_MUX_CAMTG3>, <&topckgen TOP_MUX_CAMTG4>, <&topckgen TOP_MUX_CAMTG5>, <&topckgen TOP_MUX_CAMTG6>, <&clk26m>, <&topckgen TOP_UNIVP_192M_D8>, <&topckgen TOP_UNIVPLL_D6_D8>, <&topckgen TOP_UNIVP_192M_D4>, <&topckgen TOP_F26M_CK_D2>, <&topckgen TOP_UNIVP_192M_D16>, <&topckgen TOP_UNIVP_192M_D32>; clock-names = "SCP_SYS_MDP", "SCP_SYS_CAM", "CAMSYS_SENINF_CGPDN", "TOP_MUX_SENINF", "TOP_MUX_SENINF1", "TOP_MUX_SENINF2", "TOP_MUX_SENINF3", "TOP_MUX_CAMTG", "TOP_MUX_CAMTG2", "TOP_MUX_CAMTG3", "TOP_MUX_CAMTG4", "TOP_MUX_CAMTG5", "TOP_MUX_CAMTG6", "TOP_CLK26M", "TOP_UNIVP_192M_D8", "TOP_UNIVPLL_D6_D8", "TOP_UNIVP_192M_D4", "TOP_F26M_CK_D2", "TOP_UNIVP_192M_D16", "TOP_UNIVP_192M_D32"; }; kd_camera_hw1:kd_camera_hw1@1a004000 { compatible = "mediatek,imgsensor"; }; flashlight_core: flashlight_core { compatible = "mediatek,flashlight_core"; }; flashlights_mt6360: flashlights_mt6360 { compatible = "mediatek,flashlights_mt6360"; decouple = <1>; channel@1 { type = <0>; ct = <0>; part = <0>; }; channel@2 { type = <0>; ct = <1>; part = <0>; }; }; cam_smi_subcom@1a00c000 { compatible = "mediatek,cam_smi_subcom", "mediatek,smi_common"; reg = <0 0x1a00c000 0 0x1000>; clocks = <&scpsys SCP_SYS_CAM>; clock-names = "scp-cam"; mediatek,smi-id = <27>; mediatek,smi-cnt = <30>; }; cam_smi_subcom@1a00d000 { compatible = "mediatek,cam_smi_subcom", "mediatek,smi_common"; reg = <0 0x1a00d000 0 0x1000>; clocks = <&scpsys SCP_SYS_CAM>; clock-names = "scp-cam"; mediatek,smi-id = <28>; }; cam1_inner@1a038000 { compatible = "mediatek,cam1_inner"; reg = <0 0x1a038000 0 0x8000>; }; cam2_inner@1a058000 { compatible = "mediatek,cam2_inner"; reg = <0 0x1a058000 0 0x8000>; }; cam3_inner@1a078000 { compatible = "mediatek,cam3_inner"; reg = <0 0x1a078000 0 0x8000>; }; cam1: cam1@1a030000 { compatible = "mediatek,cam1"; reg = <0 0x1a030000 0 0x8000>; interrupts = ; }; cam2: cam2@1a050000 { compatible = "mediatek,cam2"; reg = <0 0x1a050000 0 0x8000>; interrupts = ; }; cam3: cam3@1a070000 { compatible = "mediatek,cam3"; reg = <0 0x1a070000 0 0x8000>; interrupts = ; }; camsv1@1a090000 { compatible = "mediatek,camsv1"; reg = <0 0x1a090000 0 0x1000>; interrupts = ; }; camsv2@1a091000 { compatible = "mediatek,camsv2"; reg = <0 0x1a091000 0 0x1000>; interrupts = ; }; camsv3@1a092000 { compatible = "mediatek,camsv3"; reg = <0 0x1a092000 0 0x1000>; interrupts = ; }; camsv4@1a093000 { compatible = "mediatek,camsv4"; reg = <0 0x1a093000 0 0x1000>; interrupts = ; }; camsv5@1a094000 { compatible = "mediatek,camsv5"; reg = <0 0x1a094000 0 0x1000>; interrupts = ; }; camsv6@1a095000 { compatible = "mediatek,camsv6"; reg = <0 0x1a095000 0 0x1000>; interrupts = ; }; camsv7@1a096000 { compatible = "mediatek,camsv7"; reg = <0 0x1a096000 0 0x1000>; interrupts = ; }; camsv8@1a097000 { compatible = "mediatek,camsv8"; reg = <0 0x1a097000 0 0x1000>; interrupts = ; }; imgsys_config: imgsys_config@15020000 { compatible = "mediatek,imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; clocks = <&imgsys_config_clk IMGSYS1_LARB9_CGPDN>, <&imgsys_config_clk IMGSYS1_DIP_CGPDN>, <&imgsys2_config IMGSYS2_LARB11_CGPDN>, <&imgsys2_config IMGSYS2_MSS_CGPDN>, <&imgsys2_config IMGSYS2_MFB_CGPDN>; clock-names = "DIP_CG_IMG_LARB9", "DIP_CG_IMG_DIP", "DIP_CG_IMG_LARB11", "DIP_CG_IMG_DIP_MSS", "DIP_CG_IMG_MFB_DIP"; }; vdec_smi_subcom@1600a000 { compatible = "mediatek,vdec_smi_subcom", "mediatek,smi_common"; reg = <0 0x1600a000 0 0x1000>; clocks = <&scpsys SCP_SYS_VDEC>; clock-names = "scp-vdec"; mediatek,smi-id = <26>; }; vcu: vcu@16000000 { compatible = "mediatek-vcu"; mediatek,vcuid = <0>; mediatek,vcuname = "vcu"; reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */ <0 0x17020000 0 0x10000>, /* VENC_BASE */ <0 0x17820000 0 0x10000>; /* VENC_C1_BASE */ #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; #endif mediatek,mailbox-gce = <&gce_mbox>; mediatek,dec_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/ mediatek,enc_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/ #if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) mboxes = <&gce_mbox 7 0 CMDQ_THR_PRIO_1>, <&gce_mbox 12 0 CMDQ_THR_PRIO_1>, <&gce_mbox_sec 12 0 CMDQ_THR_PRIO_1>; #else mboxes = <&gce_mbox 7 0 CMDQ_THR_PRIO_1>, <&gce_mbox 12 0 CMDQ_THR_PRIO_1>; #endif gce-event-names = "venc_eof", "venc_wp_2nd_done", "venc_wp_3nd_done", "vdec_pic_start", "vdec_decode_done", "vdec_pause", "vdec_dec_error", "vdec_mc_busy_overflow_timeout", "vdec_all_dram_req_done", "vdec_ini_fetch_rdy", "vdec_process_flag", "vdec_search_start_code_done", "vdec_ref_reorder_done", "vdec_wp_tble_done", "vdec_count_sram_clr_done", "vdec_gce_cnt_op_threshold", "vdec_lat_pic_start", "vdec_lat_decode_done", "vdec_lat_pause", "vdec_lat_dec_error", "vdec_lat_mc_busy_overflow_timeout", "vdec_lat_all_dram_req_done", "vdec_lat_ini_fetch_rdy", "vdec_lat_process_flag", "vdec_lat_search_start_code_done", "vdec_lat_ref_reorder_done", "vdec_lat_wp_tble_done", "vdec_lat_count_sram_clr_done", "vdec_lat_gce_cnt_op_threshold"; gce-events = <&gce_mbox CMDQ_EVENT_VENC_CMDQ_FRAME_DONE>, <&gce_mbox CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE>, <&gce_mbox CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_SOF_0>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_0>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_1>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_2>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_3>, <&gce_mbox CMDQ_EVENT_VDEC_CORE0_ENG_EVENT_7>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_SOF_0>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_ENG_EVENT_0>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_ENG_EVENT_1>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_ENG_EVENT_2>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_ENG_EVENT_3>, <&gce_mbox CMDQ_EVENT_VDEC_LAT_ENG_EVENT_7>; gce-gpr = , ; }; vdec@16000000 { compatible = "mediatek,mt6873-vcodec-dec"; reg = <0 0x1602f000 0 0x1000>, /* VDEC_SYS */ <0 0x16000000 0 0x1000>, /* VDEC_BASE */ <0 0x16020000 0 0x1000>, /* VDEC_VLD */ <0 0x16021000 0 0x1000>, /* VDEC_MC */ <0 0x16023000 0 0x1000>, /* VDEC_MV */ <0 0x16025000 0 0x4000>, /* VDEC_MISC */ <0 0x16010000 0 0x1000>, /* VDEC_LAT_MISC */ <0 0x16011000 0 0x400>, /* VDEC_LAT_VLD */ <0 0x16004000 0 0x1000>; /* VDEC_RACING_CTRL */ #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; #endif mediatek,larb = <&smi_larb4>; interrupts = , ; mediatek,vcu = <&vcu>; clocks = <&vdec_soc_gcon VDEC_SOC_GCON_VDEC_CKEN>, <&vdec_gcon VDEC_GCON_VDEC_CKEN>, <&vdec_soc_gcon VDEC_SOC_GCON_LAT_CKEN>; clock-names = "MT_CG_SOC", "MT_CG_VDEC0", "MT_CG_VDEC1"; }; venc@17000000 { compatible = "mediatek,mt6873-vcodec-enc"; reg = <0 0x17020000 0 0x2000>, <0 0x17000000 0 0x10000>; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L7_VENC_RD_COMV>; #endif mediatek,larb = <&smi_larb7>; interrupts = ; mediatek,vcu = <&vcu>; clocks = <&venc_gcon VENC_GCON_SET1_VENC>; clock-names = "MT_CG_VENC0"; }; mtkfb: mtkfb@0 { compatible = "mediatek,mtkfb"; }; dispsys { compatible = "mediatek,dispsys"; mediatek,larb = <&smi_larb0>; clocks = <&dispsys_config_clk SCP_SYS_DIS>, <&dispsys_config_clk MM_SMI_COMMON>, <&dispsys_config_clk MM_SMI_GALS>, <&dispsys_config_clk MM_SMI_INFRA>, <&dispsys_config_clk MM_SMI_IOMMU>, <&dispsys_config_clk MM_DISP_OVL0>, <&dispsys_config_clk MM_DISP_OVL0_2L>, <&dispsys_config_clk MM_DISP_OVL2_2L>, <&dispsys_config_clk MM_DISP_RDMA0>, <&dispsys_config_clk MM_DISP_WDMA0>, <&dispsys_config_clk MM_DISP_COLOR0>, <&dispsys_config_clk MM_DISP_CCORR0>, <&dispsys_config_clk MM_DISP_AAL0>, <&dispsys_config_clk MM_MDP_AAL4>, <&dispsys_config_clk MM_DISP_GAMMA0>, <&dispsys_config_clk MM_DISP_POSTMASK0>, <&dispsys_config_clk MM_DISP_DITHER0>, <&dispsys_config_clk MM_DSI0>, <&dispsys_config_clk MM_DSI_DSI0>, <&dispsys_config_clk MM_26MHZ>, <&dispsys_config_clk MM_DISP_MUTEX0>, <&dispsys_config_clk MM_DISP_CONFIG>, <&dispsys_config_clk MM_DISP_RSZ0>, <&dispsys_config_clk MM_DISP_MUTEX0>, <&dispsys_config_clk MM_DISP_CONFIG>, <&apmixed APMIXED_MIPID0_26M>, <&topckgen TOP_MUX_DISP_PWM>, <&infracfg_ao INFRACFG_AO_DISP_PWM_CG>, <&clk26m>, <&topckgen TOP_UNIVPLL_D6_D4>, <&topckgen TOP_OSC_D2>, <&topckgen TOP_OSC_D4>, <&topckgen TOP_OSC_D16>; clock-names = "MMSYS_MTCMOS", "MMSYS_SMI_COMMON", "MMSYS_SMI_GALS", "MMSYS_SMI_INFRA", "MMSYS_SMI_IOMMU", "MMSYS_DISP_OVL0", "MMSYS_DISP_OVL0_2L", "MMSYS_DISP_OVL2_2L", "MMSYS_DISP_RDMA0", "MMSYS_DISP_WDMA0", "MMSYS_DISP_COLOR0", "MMSYS_DISP_CCORR0", "MMSYS_DISP_AAL0", "MMSYS_DISP_MDP_AAL4", "MMSYS_DISP_GAMMA0", "MMSYS_DISP_POSTMASK0", "MMSYS_DISP_DITHER0", "MMSYS_DSI0_MM_CK", "MMSYS_DSI0_IF_CK", "MMSYS_26M", "MMSYS_DISP_MUTEX0", "MMSYS_DISP_CONFIG", "MMSYS_DISP_RSZ0", "MMSYS_DISP_MUTEX0", "MMSYS_DISP_CONFIG", "APMIXED_MIPI_26M", "TOP_MUX_DISP_PWM", "DISP_PWM", "TOP_26M", "TOP_UNIVPLL_D6_D4", "TOP_OSC_D2", "TOP_OSC_D4", "TOP_OSC_D16"; }; disp_pwm: disp_pwm0@1100e000 { compatible = "mediatek,disp_pwm0", "mediatek,mt6873-disp-pwm"; reg = <0 0x1100e000 0 0x1000>; interrupts = ; #pwm-cells = <2>; clocks = <&infracfg_ao INFRACFG_AO_DISP_PWM_CG>, <&topckgen TOP_MUX_DISP_PWM>, <&topckgen TOP_OSC_D4>; clock-names = "main", "mm", "pwm_src"; }; mmsys_config: mmsys_config@14000000 { compatible = "mediatek,mmsys_config"; reg = <0 0x14000000 0 0x1000>; interrupts = ; }; dispsys_config: dispsys_config@14000000 { compatible = "mediatek,dispsys_config", "syscon", "mediatek,mt6873-mmsys"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>; mediatek,larb = <&smi_larb1>; fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE0>, <&smi_larb1 M4U_PORT_L1_DISP_FAKE1>; clocks = <&scpsys SCP_SYS_DIS>, <&dispsys_config_clk MM_26MHZ>, <&dispsys_config_clk MM_DISP_CONFIG>, <&dispsys_config_clk MM_DISP_MUTEX0>; clock-num = <4>; /* define threads, see mt6873-gce.h */ mediatek,mailbox-gce = <&gce_mbox>; mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>, <&gce_mbox 5 0 CMDQ_THR_PRIO_4>, <&gce_mbox 2 0 CMDQ_THR_PRIO_4>, <&gce_mbox 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>, <&gce_mbox 1 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_6>, #if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) <&gce_mbox 4 0 CMDQ_THR_PRIO_4>, <&gce_mbox 6 0 CMDQ_THR_PRIO_3>, <&gce_mbox_sec 8 0 CMDQ_THR_PRIO_3>, <&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>, <&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>; #else <&gce_mbox 4 0 CMDQ_THR_PRIO_4>, <&gce_mbox 6 0 CMDQ_THR_PRIO_3>; #endif gce-client-names = "CLIENT_CFG0", "CLIENT_CFG1", "CLIENT_CFG2", "CLIENT_TRIG_LOOP0", "CLIENT_SODI_LOOP0", #if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) "CLIENT_SUB_CFG0", "CLIENT_DSI_CFG0", "CLIENT_SEC_CFG0", "CLIENT_SEC_CFG1", "CLIENT_SEC_CFG2"; #else "CLIENT_SUB_CFG0", "CLIENT_DSI_CFG0"; #endif /* define subsys, see mt6873-gce.h */ gce-subsys = <&gce_mbox 0x14000000 SUBSYS_1400XXXX>, <&gce_mbox 0x14010000 SUBSYS_1401XXXX>, <&gce_mbox 0x14020000 SUBSYS_1402XXXX>; /* define subsys, see mt6873-gce.h */ gce-event-names = "disp_mutex0_eof", "disp_mutex1_eof", "disp_token_stream_dirty0", "disp_token_sodi0", "disp_wait_dsi0_te", "disp_token_stream_eof0", "disp_dsi0_eof", "disp_token_esd_eof0", "disp_rdma0_eof0", "disp_wdma0_eof0", "disp_token_stream_block0", "disp_token_cabc_eof0", "disp_wdma0_eof2", "disp_dsi0_sof0"; gce-events = <&gce_mbox CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>, <&gce_mbox CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>, <&gce_mbox CMDQ_SYNC_TOKEN_CONFIG_DIRTY>, <&gce_mbox CMDQ_SYNC_TOKEN_SODI>, <&gce_mbox CMDQ_EVENT_DSI0_TE_ENG_EVENT>, <&gce_mbox CMDQ_SYNC_TOKEN_STREAM_EOF>, <&gce_mbox CMDQ_EVENT_DSI0_FRAME_DONE>, <&gce_mbox CMDQ_SYNC_TOKEN_ESD_EOF>, <&gce_mbox CMDQ_EVENT_DISP_RDMA0_FRAME_DONE>, <&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>, <&gce_mbox CMDQ_SYNC_TOKEN_STREAM_BLOCK>, <&gce_mbox CMDQ_SYNC_TOKEN_CABC_EOF>, <&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>, <&gce_mbox CMDQ_EVENT_DSI0_SOF>; helper-name = "MTK_DRM_OPT_STAGE", "MTK_DRM_OPT_USE_CMDQ", "MTK_DRM_OPT_USE_M4U", "MTK_DRM_OPT_SODI_SUPPORT", "MTK_DRM_OPT_IDLE_MGR", "MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE", "MTK_DRM_OPT_IDLEMGR_BY_REPAINT", "MTK_DRM_OPT_IDLEMGR_ENTER_ULPS", "MTK_DRM_OPT_IDLEMGR_KEEP_LP11", "MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING", "MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ", "MTK_DRM_OPT_MET_LOG", "MTK_DRM_OPT_USE_PQ", "MTK_DRM_OPT_ESD_CHECK_RECOVERY", "MTK_DRM_OPT_ESD_CHECK_SWITCH", "MTK_DRM_OPT_PRESENT_FENCE", "MTK_DRM_OPT_RDMA_UNDERFLOW_AEE", "MTK_DRM_OPT_DSI_UNDERRUN_AEE", "MTK_DRM_OPT_HRT", "MTK_DRM_OPT_HRT_MODE", "MTK_DRM_OPT_DELAYED_TRIGGER", "MTK_DRM_OPT_OVL_EXT_LAYER", "MTK_DRM_OPT_AOD", "MTK_DRM_OPT_RPO", "MTK_DRM_OPT_DUAL_PIPE", "MTK_DRM_OPT_DC_BY_HRT", "MTK_DRM_OPT_OVL_WCG", "MTK_DRM_OPT_OVL_SBCH", "MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK", "MTK_DRM_OPT_MET", "MTK_DRM_OPT_REG_PARSER_RAW_DUMP", "MTK_DRM_OPT_VP_PQ", "MTK_DRM_OPT_GAME_PQ", "MTK_DRM_OPT_MMPATH", "MTK_DRM_OPT_HBM", "MTK_DRM_OPT_VDS_PATH_SWITCH", "MTK_DRM_OPT_LAYER_REC", "MTK_DRM_OPT_CLEAR_LAYER", "MTK_DRM_OPT_SF_PF"; helper-value = <0>, /*MTK_DRM_OPT_STAGE*/ <1>, /*MTK_DRM_OPT_USE_CMDQ*/ <1>, /*MTK_DRM_OPT_USE_M4U*/ <0>, /*MTK_DRM_OPT_SODI_SUPPORT*/ <1>, /*MTK_DRM_OPT_IDLE_MGR*/ <0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/ <1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/ <0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/ <0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/ <0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/ <1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/ <0>, /*MTK_DRM_OPT_MET_LOG*/ <1>, /*MTK_DRM_OPT_USE_PQ*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/ <1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/ <1>, /*MTK_DRM_OPT_PRESENT_FENCE*/ <0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/ <1>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/ <1>, /*MTK_DRM_OPT_HRT*/ <1>, /*MTK_DRM_OPT_HRT_MODE*/ <0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/ <1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/ <0>, /*MTK_DRM_OPT_AOD*/ <1>, /*MTK_DRM_OPT_RPO*/ <0>, /*MTK_DRM_OPT_DUAL_PIPE*/ <0>, /*MTK_DRM_OPT_DC_BY_HRT*/ <1>, /*MTK_DRM_OPT_OVL_WCG*/ <0>, /*MTK_DRM_OPT_OVL_SBCH*/ <1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/ <0>, /*MTK_DRM_OPT_MET*/ <0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/ <0>, /*MTK_DRM_OPT_VP_PQ*/ <0>, /*MTK_DRM_OPT_GAME_PQ*/ <0>, /*MTK_DRM_OPT_MMPATH*/ <0>, /*MTK_DRM_OPT_HBM*/ <0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/ <0>, /*MTK_DRM_OPT_LAYER_REC*/ <1>, /*MTK_DRM_OPT_CLEAR_LAYER*/ <1>; /*MTK_DRM_OPT_SF_PF*/ }; disp_mutex0: disp_mutex@14001000 { compatible = "mediatek,disp_mutex0", "mediatek,mt6873-disp-mutex"; reg = <0 0x14001000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_MUTEX0>; }; disp_smi_common@14002000 { compatible = "mediatek,disp_smi_common", "mediatek,smi_common"; reg = <0 0x14002000 0 0x1000>; clocks = <&scpsys SCP_SYS_DIS>, <&dispsys_config_clk MM_SMI_COMMON>, <&dispsys_config_clk MM_SMI_GALS>, <&dispsys_config_clk MM_SMI_INFRA>, <&dispsys_config_clk MM_SMI_IOMMU>; clock-names = "scp-dis", "mm-comm", "mm-gals", "mm-infra", "mm-iommu"; mediatek,smi-id = <21>; mediatek,smi-cnt = <30>; mmsys_config = <&dispsys_config>; mboxes = <&gce_mbox 23 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>; gce-event = /bits/ 16 ; }; smi_larb0: smi_larb0@14003000 { compatible = "mediatek,smi_larb0", "mediatek,smi_larb"; reg = <0 0x14003000 0 0x1000>; mediatek,larb-id = <0>; interrupts = ; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <0>; }; smi_larb1: smi_larb1@14004000 { compatible = "mediatek,smi_larb1", "mediatek,smi_larb"; reg = <0 0x14004000 0 0x1000>; mediatek,larb-id = <1>; interrupts = ; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <1>; }; smi_larb2: smi_larb2@1f002000 { compatible = "mediatek,smi_larb2", "mediatek,smi_larb"; reg = <0 0x1f002000 0 0x1000>; mediatek,larb-id = <2>; clocks = <&scpsys SCP_SYS_MDP>, <&mdpsys_config MDP_SMI0>; clock-names = "scp-mdp", "mdp-smi"; mediatek,smi-id = <2>; }; smi_larb3@1f011000 { compatible = "mediatek,smi_larb3", "mediatek,smi_larb"; reg = <0 0x1f011000 0 0x1000>; mediatek,larb-id = <3>; clocks = <&scpsys SCP_SYS_MDP>; clock-names = "scp-mdp"; mediatek,smi-id = <3>; }; smi_larb4: smi_larb4@1602e000 { compatible = "mediatek,smi_larb4", "mediatek,smi_larb"; reg = <0 0x1602e000 0 0x1000>; mediatek,larb-id = <4>; clocks = <&scpsys SCP_SYS_VDEC2>, <&vdec_gcon VDEC_GCON_LARB1_CKEN>; clock-names = "scp-vdec2", "vdec-larb"; mediatek,smi-id = <4>; }; smi_larb5: smi_larb5@1600d000 { compatible = "mediatek,smi_larb5", "mediatek,smi_larb"; reg = <0 0x1600d000 0 0x1000>; mediatek,larb-id = <5>; clocks = <&scpsys SCP_SYS_VDEC>, <&vdec_soc_gcon VDEC_SOC_GCON_LARB1_CKEN>; clock-names = "scp-vdec", "vdec-soc-larb"; mediatek,smi-id = <5>; }; smi_larb6@1600e000 { compatible = "mediatek,smi_larb6", "mediatek,smi_larb"; reg = <0 0x1600e000 0 0x1000>; mediatek,larb-id = <6>; clocks = <&scpsys SCP_SYS_VDEC>; clock-names = "scp-vdec"; mediatek,smi-id = <6>; }; smi_larb7: smi_larb7@17010000 { compatible = "mediatek,smi_larb7", "mediatek,smi_larb"; reg = <0 0x17010000 0 0x1000>; mediatek,larb-id = <7>; interrupts = ; clocks = <&scpsys SCP_SYS_VENC>, <&venc_gcon VENC_GCON_SET0_LARB>, <&venc_gcon VENC_GCON_SET1_VENC>; clock-names = "scp-venc", "venc-larb", "venc-set1"; mediatek,smi-id = <7>; }; smi_larb8@17011000 { compatible = "mediatek,smi_larb8", "mediatek,smi_larb"; reg = <0 0x17011000 0 0x1000>; mediatek,larb-id = <8>; clocks = <&scpsys SCP_SYS_VENC>; clock-names = "scp-venc"; mediatek,smi-id = <8>; }; smi_larb9: smi_larb9@1502e000 { compatible = "mediatek,smi_larb9", "mediatek,smi_larb"; reg = <0 0x1502e000 0 0x1000>; mediatek,larb-id = <9>; interrupts = ; clocks = <&scpsys SCP_SYS_ISP>, <&imgsys_config_clk IMGSYS1_LARB9_CGPDN>; clock-names = "scp-isp", "img1-larb9"; mediatek,smi-id = <9>; }; smi_larb10@1502f000 { compatible = "mediatek,smi_larb10", "mediatek,smi_larb"; reg = <0 0x1502f000 0 0x1000>; mediatek,larb-id = <10>; interrupts = ; clocks = <&scpsys SCP_SYS_ISP>; clock-names = "scp-isp"; mediatek,smi-id = <10>; }; smi_larb11: smi_larb11@1582e000 { compatible = "mediatek,smi_larb11", "mediatek,smi_larb"; reg = <0 0x1582e000 0 0x1000>; mediatek,larb-id = <11>; interrupts = ; clocks = <&scpsys SCP_SYS_ISP2>, <&imgsys2_config IMGSYS2_LARB11_CGPDN>; clock-names = "scp-isp2", "img2-larb11"; mediatek,smi-id = <11>; }; smi_larb12@1582f000 { compatible = "mediatek,smi_larb12", "mediatek,smi_larb"; reg = <0 0x1582f000 0 0x1000>; mediatek,larb-id = <12>; interrupts = ; clocks = <&scpsys SCP_SYS_ISP2>; clock-names = "scp-isp2"; mediatek,smi-id = <12>; }; smi_larb13: smi_larb13@1a001000 { compatible = "mediatek,smi_larb13", "mediatek,smi_larb"; reg = <0 0x1a001000 0 0x1000>; mediatek,larb-id = <13>; clocks = <&scpsys SCP_SYS_CAM>, <&camsys_clk CAMSYS_MAIN_CAM_CGPDN>, <&camsys_clk CAMSYS_MAIN_LARB13_CGPDN>; clock-names = "scp-cam", "cam-cg", "cam-larb13"; mediatek,smi-id = <13>; }; smi_larb14: smi_larb14@1a002000 { compatible = "mediatek,smi_larb14", "mediatek,smi_larb"; reg = <0 0x1a002000 0 0x1000>; mediatek,larb-id = <14>; clocks = <&scpsys SCP_SYS_CAM>, <&camsys_clk CAMSYS_MAIN_CAM_CGPDN>, <&camsys_clk CAMSYS_MAIN_LARB14_CGPDN>; clock-names = "scp-cam", "cam-cg", "cam-larb14"; mediatek,smi-id = <14>; }; smi_larb15@1a003000 { compatible = "mediatek,smi_larb15", "mediatek,smi_larb"; reg = <0 0x1a003000 0 0x1000>; mediatek,larb-id = <15>; clocks = <&scpsys SCP_SYS_CAM>; clock-names = "scp-cam"; mediatek,smi-id = <15>; }; smi_larb16: smi_larb16@1a00f000 { compatible = "mediatek,smi_larb16", "mediatek,smi_larb"; reg = <0 0x1a00f000 0 0x1000>; mediatek,larb-id = <16>; clocks = <&scpsys SCP_SYS_CAM_RAWA>, <&camsys_rawa CAMSYS_RAWA_CAM_CGPDN>, <&camsys_rawa CAMSYS_RAWA_LARBX_CGPDN>; clock-names = "scp-cam-rawa", "cam-rawa-cg", "cam-rawa-larb"; mediatek,smi-id = <16>; }; smi_larb17: smi_larb17@1a010000 { compatible = "mediatek,smi_larb17", "mediatek,smi_larb"; reg = <0 0x1a010000 0 0x1000>; mediatek,larb-id = <17>; clocks = <&scpsys SCP_SYS_CAM_RAWB>, <&camsys_rawb CAMSYS_RAWB_CAM_CGPDN>, <&camsys_rawb CAMSYS_RAWB_LARBX_CGPDN>; clock-names = "scp-cam-rawb", "cam-rawb-cg", "cam-rawb-larb"; mediatek,smi-id = <17>; }; smi_larb18: smi_larb18@1a011000 { compatible = "mediatek,smi_larb18", "mediatek,smi_larb"; reg = <0 0x1a011000 0 0x1000>; mediatek,larb-id = <18>; clocks = <&scpsys SCP_SYS_CAM_RAWC>, <&camsys_rawc CAMSYS_RAWC_CAM_CGPDN>, <&camsys_rawc CAMSYS_RAWC_LARBX_CGPDN>; clock-names = "scp-cam-rawc", "cam-rawc-cg", "cam-rawc-larb"; mediatek,smi-id = <18>; }; smi_larb19: smi_larb19@1b10f000 { compatible = "mediatek,smi_larb19", "mediatek,smi_larb"; reg = <0 0x1b10f000 0 0x1000>; mediatek,larb-id = <19>; clocks = <&scpsys SCP_SYS_IPE>, <&ipesys_config IPESYS_IPE_SMI_SUBCOM_CGPDN>, <&ipesys_config IPESYS_LARB19_CGPDN>; clock-names = "scp-ipe", "ipe-subcom", "ipe-larb19"; mediatek,smi-id = <19>; }; smi_larb20: smi_larb20@1b00f000 { compatible = "mediatek,smi_larb20", "mediatek,smi_larb"; reg = <0 0x1b00f000 0 0x1000>; mediatek,larb-id = <20>; clocks = <&scpsys SCP_SYS_IPE>, <&ipesys_config IPESYS_IPE_SMI_SUBCOM_CGPDN>, <&ipesys_config IPESYS_LARB20_CGPDN>; clock-names = "scp-ipe", "ipe-subcom", "ipe-larb20"; mediatek,smi-id = <20>; }; iommu0: m4u@1401d000 { cell-index = <0>; compatible = "mediatek,iommu_v0"; reg = <0 0x1401d000 0 0x1000>; mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>, <&smi_larb4 &smi_larb5 &smi_larb7>, <&smi_larb9 &smi_larb11 &smi_larb13>, <&smi_larb14 &smi_larb16 &smi_larb17>, <&smi_larb18 &smi_larb19 &smi_larb20>; interrupts = ; clocks = <&dispsys_config_clk MM_SMI_IOMMU>, <&scpsys SCP_SYS_DIS>; clock-names = "disp-iommu-ck", "power"; #iommu-cells = <1>; }; disp_ovl0: disp_ovl0@14005000 { compatible = "mediatek,disp_ovl0", "mediatek,mt6873-disp-ovl"; reg = <0 0x14005000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_OVL0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>; }; disp_ovl0_2l: disp_ovl0_2l@14006000 { compatible = "mediatek,disp_ovl0_2l", "mediatek,mt6873-disp-ovl"; reg = <0 0x14006000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_OVL0_2L>; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>; }; disp_rdma0: disp_rdma0@14007000 { compatible = "mediatek,disp_rdma0", "mediatek,mt6873-disp-rdma"; reg = <0 0x14007000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_RDMA0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; }; disp_rsz0: disp_rsz0@14008000 { compatible = "mediatek,disp_rsz0", "mediatek,mt6873-disp-rsz"; reg = <0 0x14008000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_RSZ0>; }; disp_color0: disp_color0@14009000 { compatible = "mediatek,disp_color0", "mediatek,mt6873-disp-color"; reg = <0 0x14009000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_COLOR0>; }; disp_ccorr0: disp_ccorr0@1400a000 { compatible = "mediatek,disp_ccorr0", "mediatek,mt6873-disp-ccorr"; reg = <0 0x1400a000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_CCORR0>; }; disp_aal0: disp_aal0@1400b000 { compatible = "mediatek,disp_aal0", "mediatek,mt6873-disp-aal"; reg = <0 0x1400b000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_AAL0>; aal_dre3 = <&mdp_aal4>; }; disp_gamma0: disp_gamma0@1400c000 { compatible = "mediatek,disp_gamma0", "mediatek,mt6873-disp-gamma"; reg = <0 0x1400c000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_GAMMA0>; }; disp_postmask0: disp_postmask0@1400d000 { compatible = "mediatek,disp_postmask0", "mediatek,mt6873-disp-postmask"; reg = <0 0x1400d000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_POSTMASK0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>; }; disp_dither0: disp_dither0@1400e000 { compatible = "mediatek,disp_dither0", "mediatek,mt6873-disp-dither"; reg = <0 0x1400e000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_DITHER0>; }; mmdvfs_pmqos { compatible = "mediatek,mmdvfs_pmqos"; larb_groups = <0 1 2 4 5 7 9 11 13 14 16 17 18 19 20>; larb0 = <8 7 8 8 9 8>; larb1 = <7 7 8 8 7 8 9 8>; larb2 = <7 7 7 7 8>; larb4 = <6 7 8 7 7 7 7 7 7 6 7>; larb5 = <7 7 6 7 7 8 7 7>; larb7 = <7 8 8 8 7 7 7 7 7 7 7 7 8 7 8>; larb9 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7 7 7 7 7 7 7 8 8 8 8 7>; larb11 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7 7 7 7 7 7 7 8 8 8 8 7>; larb13 = <7 8 8 8 8 8 8 8 8 7 8 7>; larb14 = <7 8 8 8 7 8>; larb16 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>; larb17 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>; larb18 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>; larb19 = <7 8 7 8>; larb20 = <7 7 8 8 7 8>; /* include SMI common CCU */ cam_larb = <13 14 16 17 18 23 24>; max_ostd_larb = <0 1>; max_ostd = <40>; comm_freq = "disp_freq"; disp_step0 = <546 1 0 10>; disp_step1 = <416 1 0 11>; disp_step2 = <312 1 0 12>; disp_step3 = <208 1 0 13>; cam_step0 = <624 1 1 14>; cam_step1 = <499 1 1 15>; cam_step2 = <392 1 1 16>; cam_step3 = <273 1 1 17>; img_step0 = <624 1 2 14>; img_step1 = <416 1 2 11>; img_step2 = <343 1 2 18>; img_step3 = <229 1 2 19>; img2_step0 = <624 1 3 14>; img2_step1 = <416 1 3 11>; img2_step2 = <343 1 3 18>; img2_step3 = <229 1 3 19>; dpe_step0 = <546 1 4 10>; dpe_step1 = <458 1 4 20>; dpe_step2 = <364 1 4 21>; dpe_step3 = <249 1 4 22>; ipe_step0 = <546 1 5 10>; ipe_step1 = <416 1 5 11>; ipe_step2 = <312 1 5 12>; ipe_step3 = <229 1 5 19>; venc_step0 = <624 1 6 14>; venc_step1 = <458 1 6 20>; venc_step2 = <364 1 6 21>; venc_step3 = <249 1 6 22>; vdec_step0 = <546 1 7 10>; vdec_step1 = <416 1 7 11>; vdec_step2 = <312 1 7 12>; vdec_step3 = <218 1 7 23>; mdp_step0 = <594 1 8 24>; mdp_step0_ext = <594 2 9 0x1A713B>; mdp_step1 = <416 1 8 11>; mdp_step1_ext = <416 2 9 0x1A713B>; mdp_step2 = <343 1 8 18>; mdp_step2_ext = <343 2 9 0x1A713B>; mdp_step3 = <229 1 8 19>; mdp_step3_ext = <229 2 9 0x1604EC>; ccu_step0 = <499 1 9 15>; ccu_step1 = <392 1 9 16>; ccu_step2 = <364 1 9 21>; ccu_step3 = <229 1 9 19>; vcore-supply = <&mt_pmic_vgpu11_buck_reg>; /* fmeter_mux_ids: Mapping to mux sequence in clocks */ vopp_steps = <0 1 2 3>; disp_freq = "disp_step0", "disp_step1", "disp_step2", "disp_step3"; cam_freq = "cam_step0", "cam_step1", "cam_step2", "cam_step3"; img_freq = "img_step0", "img_step1", "img_step2", "img_step3"; img2_freq = "img2_step0", "img2_step1", "img2_step2", "img2_step3"; dpe_freq = "dpe_step0", "dpe_step1", "dpe_step2", "dpe_step3"; ipe_freq = "ipe_step0", "ipe_step1", "ipe_step2", "ipe_step3"; venc_freq = "venc_step0", "venc_step1", "venc_step2", "venc_step3"; vdec_freq = "vdec_step0", "vdec_step1", "vdec_step2", "vdec_step3"; mdp_freq = "mdp_step0", "mdp_step1", "mdp_step2", "mdp_step3"; ccu_freq = "ccu_step0", "ccu_step1", "ccu_step2", "ccu_step3"; clocks = <&topckgen TOP_MUX_DISP>, /* 0 */ <&topckgen TOP_MUX_CAM>, /* 1 */ <&topckgen TOP_MUX_IMG1>, /* 2 */ <&topckgen TOP_MUX_IMG2>, /* 3 */ <&topckgen TOP_MUX_DPE>, /* 4 */ <&topckgen TOP_MUX_IPE>, /* 5 */ <&topckgen TOP_MUX_VENC>, /* 6 */ <&topckgen TOP_MUX_VDEC>, /* 7 */ <&topckgen TOP_MUX_MDP>, /* 8 */ <&topckgen TOP_MUX_CCU>, /* 9 */ <&topckgen TOP_MAINPLL_D4>, /* 10 */ <&topckgen TOP_UNIVPLL_D6>, /* 11 */ <&topckgen TOP_UNIVPLL_D4_D2>, /* 12 */ <&topckgen TOP_UNIVPLL_D6_D2>, /* 13 */ <&topckgen TOP_UNIVPLL_D4>, /* 14 */ <&topckgen TOP_UNIVPLL_D5>, /* 15 */ <&topckgen TOP_MMPLL_D7>, /* 16 */ <&topckgen TOP_MAINPLL_D4_D2>, /* 17 */ <&topckgen TOP_MMPLL_D4_D2>, /* 18 */ <&topckgen TOP_MMPLL_D5_D2>, /* 19 */ <&topckgen TOP_MMPLL_D6>, /* 20 */ <&topckgen TOP_MAINPLL_D6>, /* 21 */ <&topckgen TOP_UNIVPLL_D5_D2>, /* 22 */ <&topckgen TOP_MAINPLL_D5_D2>, /* 23 */ <&topckgen TOP_TVDPLL_CK>; /* 24 */ clock-names = "TOP_MUX_DISP", /* 0 */ "TOP_MUX_CAM", /* 1 */ "TOP_MUX_IMG1", /* 2 */ "TOP_MUX_IMG2", /* 3 */ "TOP_MUX_DPE", /* 4 */ "TOP_MUX_IPE", /* 5 */ "TOP_MUX_VENC", /* 6 */ "TOP_MUX_VDEC", /* 7 */ "TOP_MUX_MDP", /* 8 */ "TOP_MUX_CCU", /* 9 */ "TOP_MAINPLL_D4", /* 10 */ "TOP_UNIVPLL_D6", /* 11 */ "TOP_UNIVPLL_D4_D2", /* 12 */ "TOP_UNIVPLL_D6_D2", /* 13 */ "TOP_UNIVPLL_D4", /* 14 */ "TOP_UNIVPLL_D5", /* 15 */ "TOP_MMPLL_D7", /* 16 */ "TOP_MAINPLL_D4_D2", /* 17 */ "TOP_MMPLL_D4_D2", /* 18 */ "TOP_MMPLL_D5_D2", /* 19 */ "TOP_MMPLL_D6", /* 20 */ "TOP_MAINPLL_D6", /* 21 */ "TOP_UNIVPLL_D5_D2", /* 22 */ "TOP_MAINPLL_D5_D2", /* 23 */ "TOP_TVDPLL_CK"; /* 24 */ }; disp_dsc_wrap: disp_dsc_wrap@1400f000 { compatible = "mediatek,disp_dsc_wrap", "mediatek,mt6873-disp-dsc"; reg = <0 0x1400f000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_DSC_WRAP0>; }; mipi_tx_config0: mipi_tx_config@11e50000 { compatible = "mediatek,mipi_tx_config0", "mediatek,mt6873-mipi-tx"; reg = <0 0x11e50000 0 0x1000>; clocks = <&clk26m>; #clock-cells = <0>; #phy-cells = <0>; clock-output-names = "mipi_tx0_pll"; }; dsi0: dsi@14010000 { compatible = "mediatek,dsi0", "mediatek,mt6873-dsi"; reg = <0 0x14010000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DSI0>, <&dispsys_config_clk MM_DSI_DSI0>, <&mipi_tx_config0>; clock-names = "engine", "digital", "hs"; phys = <&mipi_tx_config0>; phy-names = "dphy"; }; dsi_te: dsi_te { compatible = "mediatek, dsi_te-eint"; status = "disabled"; }; disp_wdma0: disp_wdma0@14011000 { compatible = "mediatek,disp_wdma0", "mediatek,mt6873-disp-wdma"; reg = <0 0x14011000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_WDMA0>; mediatek,larb = <&smi_larb0>; mediatek,smi-id = <0>; iommus = <&iommu0 M4U_PORT_L0_DISP_WDMA0>; }; disp_ufbc_wdma0@14012000 { compatible = "mediatek,disp_ufbc_wdma0"; reg = <0 0x14012000 0 0x1000>; interrupts = ; mediatek,larb = <&smi_larb1>; }; disp_ovl2_2l: disp_ovl2_2l@14014000 { compatible = "mediatek,disp_ovl2_2l", "mediatek,mt6873-disp-ovl"; reg = <0 0x14014000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_OVL2_2L>; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>; }; disp_rdma4: disp_rdma4@14015000 { compatible = "mediatek,disp_rdma4", "mediatek,mt6873-disp-rdma"; reg = <0 0x14015000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_DISP_RDMA4>; mediatek,larb = <&smi_larb1>; mediatek,smi-id = <1>; iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>; }; dpi0@14016000 { compatible = "mediatek,dpi0"; reg = <0 0x14016000 0 0x1000>; interrupts = ; }; mdp_rdma4@14017000 { compatible = "mediatek,mdp_rdma4"; reg = <0 0x14017000 0 0x1000>; interrupts = ; }; mdp_hdr4@14018000 { compatible = "mediatek,mdp_hdr4"; reg = <0 0x14018000 0 0x1000>; interrupts = ; }; mdp_rsz4@14019000 { compatible = "mediatek,mdp_rsz4"; reg = <0 0x14019000 0 0x1000>; interrupts = ; }; mdp_aal4: mdp_aal4@1401a000 { compatible = "mediatek,mdp_aal4", "mediatek,mt6873-dmdp-aal"; reg = <0 0x1401a000 0 0x1000>; interrupts = ; clocks = <&dispsys_config_clk MM_MDP_AAL4>; clock-names = "DRE3_AAL0"; }; mdp_tdshp4@1401b000 { compatible = "mediatek,mdp_tdshp4"; reg = <0 0x1401b000 0 0x1000>; interrupts = ; }; mdp_color4@1401c000 { compatible = "mediatek,mdp_color4"; reg = <0 0x1401c000 0 0x1000>; interrupts = ; }; mcucfg: mcucfg@0c530000 { compatible = "mediatek,mcucfg"; reg = <0 0x0c530000 0 0x10000>; }; ion: iommu { compatible = "mediatek,ion"; iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>; }; pseudo_m4u { compatible = "mediatek,mt-pseudo_m4u"; iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>; }; pseudo_m4u-larb0 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <0>; iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>, <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>, <&iommu0 M4U_PORT_L0_OVL_RDMA0>, <&iommu0 M4U_PORT_L0_DISP_RDMA0>, <&iommu0 M4U_PORT_L0_DISP_WDMA0>, <&iommu0 M4U_PORT_L0_DISP_FAKE0>; }; pseudo_m4u-larb1 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <1>; iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>, <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>, <&iommu0 M4U_PORT_L1_DISP_MDP_RDMA4>, <&iommu0 M4U_PORT_L1_DISP_RDMA4>, <&iommu0 M4U_PORT_L1_DISP_UFBC_WDMA0>, <&iommu0 M4U_PORT_L1_DISP_FAKE1>; }; pseudo_m4u-larb2 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <2>; iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>, <&iommu0 M4U_PORT_L2_MDP_RDMA1>, <&iommu0 M4U_PORT_L2_MDP_WROT0>, <&iommu0 M4U_PORT_L2_MDP_WROT1>, <&iommu0 M4U_PORT_L2_MDP_DISP_FAKE0>; }; pseudo_m4u-larb4 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <4>; iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; }; pseudo_m4u-larb5 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <5>; iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; }; pseudo_m4u-larb7 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <7>; iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, <&iommu0 M4U_PORT_L7_VENC_REC>, <&iommu0 M4U_PORT_L7_VENC_BSDMA>, <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, <&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA>, <&iommu0 M4U_PORT_L7_JPGENC_Q_RDMA>, <&iommu0 M4U_PORT_L7_JPGENC_C_TABLE>, <&iommu0 M4U_PORT_L7_JPGENC_BSDMA>, <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; }; pseudo_m4u-larb8 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <8>; iommus = <&iommu0 M4U_PORT_L8_VENC_RCPU>, <&iommu0 M4U_PORT_L8_VENC_RECP>, <&iommu0 M4U_PORT_L8_VENC_BSDMA>, <&iommu0 M4U_PORT_L8_VENC_SUB_W_LUMA>, <&iommu0 M4U_PORT_L8_VENC_SV_COMV>, <&iommu0 M4U_PORT_L8_VENC_RD_COMV>, <&iommu0 M4U_PORT_L8_VENC_NBM_RDMA>, <&iommu0 M4U_PORT_L8_VENC_NBM_RDMA_LITE>, <&iommu0 M4U_PORT_L8_VENC_FCS_NBM_RDMA>, <&iommu0 M4U_PORT_L8_JPGENC_Y_RDMA>, <&iommu0 M4U_PORT_L8_JPGENC_C_RDMA>, <&iommu0 M4U_PORT_L8_JPGENC_Q_TABLE>, <&iommu0 M4U_PORT_L8_JPGENC_BSDMA>, <&iommu0 M4U_PORT_L8_JPGENC_HUFF_OFFSET0>, <&iommu0 M4U_PORT_L8_JPGENC_WDMA0>, <&iommu0 M4U_PORT_L8_JPGENC_BSDMA0>, <&iommu0 M4U_PORT_L8_JPGENC_HUFF_OFFSET1>, <&iommu0 M4U_PORT_L8_JPGENC_WDMA1>, <&iommu0 M4U_PORT_L8_JPGENC_BSDMA1>, <&iommu0 M4U_PORT_L8_VENC_NBM_WDMA>, <&iommu0 M4U_PORT_L8_VENC_NBM_WDMA_LITE>, <&iommu0 M4U_PORT_L8_VENC_FCS_NBM_WDMA>, <&iommu0 M4U_PORT_L8_VENC_SUB_R_LUMA>, <&iommu0 M4U_PORT_L8_VENC_CUR_LUMA>, <&iommu0 M4U_PORT_L8_VENC_CUR_CHROMA>, <&iommu0 M4U_PORT_L8_VENC_REF_LUMA>, <&iommu0 M4U_PORT_L8_VENC_REF_CHROMA>; }; pseudo_m4u-larb9 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <9>; iommus = <&iommu0 M4U_PORT_L9_IMG_IMGI_D1>, <&iommu0 M4U_PORT_L9_IMG_IMGBI_D1>, <&iommu0 M4U_PORT_L9_IMG_DMGI_D1>, <&iommu0 M4U_PORT_L9_IMG_DEPI_D1>, <&iommu0 M4U_PORT_L9_IMG_ICE_D1>, <&iommu0 M4U_PORT_L9_IMG_SMTI_D1>, <&iommu0 M4U_PORT_L9_IMG_SMTO_D2>, <&iommu0 M4U_PORT_L9_IMG_SMTO_D1>, <&iommu0 M4U_PORT_L9_IMG_CRZO_D1>, <&iommu0 M4U_PORT_L9_IMG_IMG3O_D1>, <&iommu0 M4U_PORT_L9_IMG_VIPI_D1>, <&iommu0 M4U_PORT_L9_IMG_SMTI_D5>, <&iommu0 M4U_PORT_L9_IMG_TIMGO_D1>, <&iommu0 M4U_PORT_L9_IMG_UFBC_W0>, <&iommu0 M4U_PORT_L9_IMG_UFBC_R0>, <&iommu0 M4U_PORT_L9_IMG_WPE_RDMA1>, <&iommu0 M4U_PORT_L9_IMG_WPE_RDMA0>, <&iommu0 M4U_PORT_L9_IMG_WPE_WDMA>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA0>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA1>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA2>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA3>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA4>, <&iommu0 M4U_PORT_L9_IMG_MFB_RDMA5>, <&iommu0 M4U_PORT_L9_IMG_MFB_WDMA0>, <&iommu0 M4U_PORT_L9_IMG_MFB_WDMA1>, <&iommu0 M4U_PORT_L9_IMG_RESERVE6>, <&iommu0 M4U_PORT_L9_IMG_RESERVE7>, <&iommu0 M4U_PORT_L9_IMG_RESERVE8>; }; pseudo_m4u-larb11 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <11>; iommus = <&iommu0 M4U_PORT_L11_IMG_IMGI_D1>, <&iommu0 M4U_PORT_L11_IMG_IMGBI_D1>, <&iommu0 M4U_PORT_L11_IMG_DMGI_D1>, <&iommu0 M4U_PORT_L11_IMG_DEPI_D1>, <&iommu0 M4U_PORT_L11_IMG_ICE_D1>, <&iommu0 M4U_PORT_L11_IMG_SMTI_D1>, <&iommu0 M4U_PORT_L11_IMG_SMTO_D2>, <&iommu0 M4U_PORT_L11_IMG_SMTO_D1>, <&iommu0 M4U_PORT_L11_IMG_CRZO_D1>, <&iommu0 M4U_PORT_L11_IMG_IMG3O_D1>, <&iommu0 M4U_PORT_L11_IMG_VIPI_D1>, <&iommu0 M4U_PORT_L11_IMG_SMTI_D5>, <&iommu0 M4U_PORT_L11_IMG_TIMGO_D1>, <&iommu0 M4U_PORT_L11_IMG_UFBC_W0>, <&iommu0 M4U_PORT_L11_IMG_UFBC_R0>, <&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1>, <&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0>, <&iommu0 M4U_PORT_L11_IMG_WPE_WDMA>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4>, <&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5>, <&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0>, <&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1>, <&iommu0 M4U_PORT_L11_IMG_RESERVE6>, <&iommu0 M4U_PORT_L11_IMG_RESERVE7>, <&iommu0 M4U_PORT_L11_IMG_RESERVE8>; }; pseudo_m4u-larb13 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <13>; iommus = <&iommu0 M4U_PORT_L13_CAM_MRAWI>, <&iommu0 M4U_PORT_L13_CAM_MRAWO0>, <&iommu0 M4U_PORT_L13_CAM_MRAWO1>, <&iommu0 M4U_PORT_L13_CAM_CAMSV1>, <&iommu0 M4U_PORT_L13_CAM_CAMSV2>, <&iommu0 M4U_PORT_L13_CAM_CAMSV3>, <&iommu0 M4U_PORT_L13_CAM_CAMSV4>, <&iommu0 M4U_PORT_L13_CAM_CAMSV5>, <&iommu0 M4U_PORT_L13_CAM_CAMSV6>, <&iommu0 M4U_PORT_L13_CAM_FAKE>; }; pseudo_m4u-larb14 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <14>; iommus = <&iommu0 M4U_PORT_L14_CAM_RESERVE1>, <&iommu0 M4U_PORT_L14_CAM_RESERVE2>, <&iommu0 M4U_PORT_L14_CAM_RESERVE3>, <&iommu0 M4U_PORT_L14_CAM_CAMSV0>; }; pseudo_m4u-larb16 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <16>; iommus = <&iommu0 M4U_PORT_L16_CAM_IMGO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_RRZO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_CQI_R1_A>, <&iommu0 M4U_PORT_L16_CAM_BPCI_R1_A>, <&iommu0 M4U_PORT_L16_CAM_YUVO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_UFDI_R2_A>, <&iommu0 M4U_PORT_L16_CAM_RAWI_R2_A>, <&iommu0 M4U_PORT_L16_CAM_RAWI_R3_A>, <&iommu0 M4U_PORT_L16_CAM_AAO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_AFO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_FLKO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_LCESO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_CRZO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_LTMSO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_RSSO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_AAHO_R1_A>, <&iommu0 M4U_PORT_L16_CAM_LSCI_R1_A>; }; pseudo_m4u-larb17 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <17>; iommus = <&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_CQI_R1_B>, <&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B>, <&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B>, <&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B>, <&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B>, <&iommu0 M4U_PORT_L17_CAM_AAO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_AFO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B>, <&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B>; }; pseudo_m4u-larb18 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <18>; iommus = <&iommu0 M4U_PORT_L18_CAM_IMGO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_RRZO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_CQI_R1_C>, <&iommu0 M4U_PORT_L18_CAM_BPCI_R1_C>, <&iommu0 M4U_PORT_L18_CAM_YUVO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_UFDI_R2_C>, <&iommu0 M4U_PORT_L18_CAM_RAWI_R2_C>, <&iommu0 M4U_PORT_L18_CAM_RAWI_R3_C>, <&iommu0 M4U_PORT_L18_CAM_AAO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_AFO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_FLKO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_LCESO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_CRZO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_LTMSO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_RSSO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_AAHO_R1_C>, <&iommu0 M4U_PORT_L18_CAM_LSCI_R1_C>; }; pseudo_m4u-larb19 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <19>; iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA>, <&iommu0 M4U_PORT_L19_IPE_DVS_WDMA>, <&iommu0 M4U_PORT_L19_IPE_DVP_RDMA>, <&iommu0 M4U_PORT_L19_IPE_DVP_WDMA>; }; pseudo_m4u-larb20 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = <20>; iommus = <&iommu0 M4U_PORT_L20_IPE_FDVT_RDA>, <&iommu0 M4U_PORT_L20_IPE_FDVT_RDB>, <&iommu0 M4U_PORT_L20_IPE_FDVT_WRA>, <&iommu0 M4U_PORT_L20_IPE_FDVT_WRB>, <&iommu0 M4U_PORT_L20_IPE_RSC_RDMA0>, <&iommu0 M4U_PORT_L20_IPE_RSC_WDMA>; }; pseudo_m4u-ccu0 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu0 M4U_PORT_L13_CAM_CCUI>, <&iommu0 M4U_PORT_L13_CAM_CCUO>, <&iommu0 M4U_PORT_L22_CCU0>; }; ccu@1a101000 { compatible = "mediatek,ccu"; reg = <0 0x1a101000 0 0x1000>; interrupts = ; clocks = <&camsys_clk CAMSYS_MAIN_CCU0_CGPDN>, <&topckgen TOP_MUX_CCU>, <&scpsys SCP_SYS_CAM>, <&scpsys SCP_SYS_MDP>; clock-names = "CCU_CLK_CAM_CCU", "CCU_CLK_TOP_MUX", "CAM_PWR", "MDP_PWR"; }; pseudo_m4u-ccu1 { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu0 M4U_PORT_L14_CAM_CCUI>, <&iommu0 M4U_PORT_L14_CAM_CCUO>, <&iommu0 M4U_PORT_L23_CCU1>; }; pseudo_m4u-vpu-code { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_CODE>; }; pseudo_m4u-vpu-data { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_DATA>; }; pseudo_m4u-vpu-vlm { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_VLM>; }; pseudo_m4u-misc { compatible = "mediatek,mt-pseudo_m4u-port"; mediatek,larbid = ; iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>; }; iommu0_bank1: m4u@1401e000 { cell-index = <0>; compatible = "mediatek,bank1_m4u0"; reg = <0 0x1401e000 0 0x1000>; interrupts = ; }; iommu0_bank2: m4u@1401f000 { cell-index = <0>; compatible = "mediatek,bank2_m4u0"; reg = <0 0x1401f000 0 0x1000>; interrupts = ; }; iommu0_bank3: m4u@14020000 { cell-index = <0>; compatible = "mediatek,bank3_m4u0"; reg = <0 0x14020000 0 0x1000>; interrupts = ; }; iommu0_sec: m4u@14021000 { cell-index = <0>; compatible = "mediatek,sec_m4u0"; reg = <0 0x14021000 0 0x1000>; interrupts = ; }; iommu1: m4u@19010000 { cell-index = <1>; compatible = "mediatek,iommu_v0"; reg = <0 0x19010000 0 0x1000>; interrupts = ; clocks = <&apu_conn APU_CONN_IOMMU_0_CG>, <&scpsys SCP_SYS_VPU>; clock-names = "clock", "power"; #iommu-cells = <1>; }; iommu1_bank1: m4u@19011000 { cell-index = <1>; compatible = "mediatek,bank1_m4u1"; reg = <0 0x19011000 0 0x1000>; interrupts = ; }; iommu1_bank2: m4u@19012000 { cell-index = <1>; compatible = "mediatek,bank2_m4u1"; reg = <0 0x19012000 0 0x1000>; interrupts = ; }; iommu1_bank3: m4u@19013000 { cell-index = <1>; compatible = "mediatek,bank3_m4u1"; reg = <0 0x19013000 0 0x1000>; interrupts = ; }; iommu1_sec: m4u@19014000 { cell-index = <1>; compatible = "mediatek,sec_m4u1"; reg = <0 0x19014000 0 0x1000>; interrupts = ; }; disp_smi_2x1_sub_common_u0@14022000 { compatible = "mediatek,disp_smi_2x1_sub_common_u0", "mediatek,smi_common"; reg = <0 0x14022000 0 0x1000>; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <22>; }; disp_smi_2x1_sub_common_u1@14023000 { compatible = "mediatek,disp_smi_2x1_sub_common_u1", "mediatek,smi_common"; reg = <0 0x14023000 0 0x1000>; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <23>; }; img0_smi_2x1_sub_common@14024000 { compatible = "mediatek,img0_smi_2x1_sub_common", "mediatek,smi_common"; reg = <0 0x14024000 0 0x1000>; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <24>; }; img1_smi_2x1_sub_common@14025000 { compatible = "mediatek,img1_smi_2x1_sub_common", "mediatek,smi_common"; reg = <0 0x14025000 0 0x1000>; clocks = <&scpsys SCP_SYS_DIS>; clock-names = "scp-dis"; mediatek,smi-id = <25>; }; dip_a0@15021000 { compatible = "mediatek,dip1"; reg = <0 0x15021000 0 0xc000>; interrupts = ; }; dip_a1@15022000 { compatible = "mediatek,dip_a1"; reg = <0 0x15022000 0 0x1000>; }; dip_a2@15023000 { compatible = "mediatek,dip_a2"; reg = <0 0x15023000 0 0x1000>; }; dip_a3@15024000 { compatible = "mediatek,dip_a3"; reg = <0 0x15024000 0 0x1000>; }; dip_a4@15025000 { compatible = "mediatek,dip_a4"; reg = <0 0x15025000 0 0x1000>; }; dip_a5@15026000 { compatible = "mediatek,dip_a5"; reg = <0 0x15026000 0 0x1000>; }; dip_a6@15027000 { compatible = "mediatek,dip_a6"; reg = <0 0x15027000 0 0x1000>; }; dip_a7@15028000 { compatible = "mediatek,dip_a7"; reg = <0 0x15028000 0 0x1000>; }; dip_a8@15029000 { compatible = "mediatek,dip_a8"; reg = <0 0x15029000 0 0x1000>; }; dip_a9@1502a000 { compatible = "mediatek,dip_a9"; reg = <0 0x1502a000 0 0x1000>; }; dip_a10@1502b000 { compatible = "mediatek,dip_a10"; reg = <0 0x1502b000 0 0x1000>; }; dip_a11@1502c000 { compatible = "mediatek,dip_a11"; reg = <0 0x1502c000 0 0x1000>; }; mssdl@15812000 { compatible = "mediatek,mssdl"; reg = <0 0x15812000 0 0x1000>; interrupts = ; }; msfdl@15810000 { compatible = "mediatek,msfdl"; reg = <0 0x15810000 0 0x1000>; interrupts = ; }; camera_af_hw_node: camera_af_hw_node { compatible = "mediatek,camera_af_lens"; }; mfb@15010000 { compatible = "mediatek,mfb"; reg = <0 0x15010000 0 0x1000>; interrupts = ; }; wpe_a@15811000 { compatible = "mediatek,wpe_a"; reg = <0 0x15811000 0 0x1000>; interrupts = ; clocks = <&imgsys2_config IMGSYS2_LARB11_CGPDN>, <&imgsys2_config IMGSYS2_WPE_CGPDN>; clock-names = "WPE_CLK_IMG_LARB9", "WPE_CLK_IMG_WPE_A"; }; mfb@15012000 { compatible = "mediatek,mfb"; reg = <0 0x15012000 0 0x1000>; }; dip_b0@15821000 { compatible = "mediatek,dip2"; reg = <0 0x15821000 0 0xc000>; interrupts = ; }; dip_b1@15822000 { compatible = "mediatek,dip_b1"; reg = <0 0x15822000 0 0x1000>; }; dip_b2@15823000 { compatible = "mediatek,dip_b2"; reg = <0 0x15823000 0 0x1000>; }; dip_b3@15824000 { compatible = "mediatek,dip_b3"; reg = <0 0x15824000 0 0x1000>; }; dip_b4@15825000 { compatible = "mediatek,dip_b4"; reg = <0 0x15825000 0 0x1000>; }; dip_b5@15826000 { compatible = "mediatek,dip_b5"; reg = <0 0x15826000 0 0x1000>; }; dip_b6@15827000 { compatible = "mediatek,dip_b6"; reg = <0 0x15827000 0 0x1000>; }; dip_b7@15828000 { compatible = "mediatek,dip_b7"; reg = <0 0x15828000 0 0x1000>; }; dip_b8@15829000 { compatible = "mediatek,dip_b8"; reg = <0 0x15829000 0 0x1000>; }; dip_b9@1582a000 { compatible = "mediatek,dip_b9"; reg = <0 0x1582a000 0 0x1000>; }; dip_b10@1582b000 { compatible = "mediatek,dip_b10"; reg = <0 0x1582b000 0 0x1000>; }; dip_b11@1582c000 { compatible = "mediatek,dip_b11"; reg = <0 0x1582c000 0 0x1000>; }; wpe_b@15811000 { compatible = "mediatek,wpe_b"; reg = <0 0x15811000 0 0x1000>; }; mss_b@15812000 { compatible = "mediatek,mss_b"; reg = <0 0x15812000 0 0x1000>; interrupts = ; mboxes = <&gce_mbox 17 0 CMDQ_THR_PRIO_1>; mss_frame_done = /bits/ 16 ; mss_token = /bits/ 16 ; }; msf_b@15810000 { compatible = "mediatek,msf_b"; reg = <0 0x15810000 0 0x1000>; interrupts = ; mboxes = <&gce_mbox 18 1200 CMDQ_THR_PRIO_1>; msf_frame_done = /bits/ 16 ; msf_token = /bits/ 16 ; clocks = <&imgsys2_config IMGSYS2_LARB11_CGPDN>, <&imgsys2_config IMGSYS2_MSS_CGPDN>, <&imgsys2_config IMGSYS2_MFB_CGPDN>; clock-names = "MFB_CG_IMG2_LARB11", "MFB_CG_IMG2_MSS", "MFB_CG_IMG2_MFB"; }; imgsys_mfb_b@15820000 { compatible = "mediatek,imgsys_mfb_b"; reg = <0 0x15820000 0 0x1000>; }; venc@17020000 { compatible = "mediatek,venc"; reg = <0 0x17020000 0 0x10000>; interrupts = ; }; jpgenc@17030000 { compatible = "mediatek,jpgenc"; reg = <0 0x17030000 0 0x10000>; mediatek,larb = <&smi_larb7>; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA>; #endif interrupts = ; clocks = <&venc_gcon VENC_GCON_SET2_JPGENC>; clock-names = "jpgenc"; cshot-spec = <368>; port-id = , , , ; }; mbist@17060000 { compatible = "mediatek,mbist"; reg = <0 0x17060000 0 0x10000>; }; dvs@1b100000 { compatible = "mediatek,dvs"; reg = <0 0x1b100000 0 0x1000>; interrupts = ; mboxes = <&gce_mbox 16 0 CMDQ_THR_PRIO_1>; EVENT_IPE_DVS_DONE = ; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA>; #endif clocks = <&topckgen TOP_MUX_DPE>, <&ipesys_config IPESYS_DPE_CGPDN>; clock-names = "DPE_TOP_MUX", "DPE_CLK_IPE_DPE"; }; dvp@1b100800 { compatible = "mediatek,dvp"; reg = <0 0x1b100000 0 0x1000>; interrupts = ; EVENT_IPE_DVP_DONE = ; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA>; #endif clocks = <&topckgen TOP_MUX_DPE>, <&ipesys_config IPESYS_DPE_CGPDN>; clock-names = "DPE_TOP_MUX", "DPE_CLK_IPE_DPE"; }; fdvt@1b001000 { compatible = "mediatek,fdvt"; reg = <0 0x1b001000 0 0x1000>; interrupts = ; clocks = <&ipesys_config IPESYS_FD_CGPDN>; clock-names = "FD_CLK_IPE_FD"; #if defined(CONFIG_MTK_CAM_SECURITY_SUPPORT) mboxes = <&gce_mbox 14 0 CMDQ_THR_PRIO_1>, <&gce_mbox_sec 11 0 CMDQ_THR_PRIO_1>; #else mboxes = <&gce_mbox 14 0 CMDQ_THR_PRIO_1>; #endif fdvt_frame_done = ; }; fe@1b002000 { compatible = "mediatek,fe"; reg = <0 0x1b002000 0 0x1000>; interrupts = ; }; #ifdef CONFIG_VIDEO_MEDIATEK_ISP_RSC_SUPPORT rsc@1b003000 { compatible = "mediatek,rsc"; mediatek,larb = <&smi_larb20>; mediatek,hcp = <&hcp>; reg = <0 0x1b003000 0 0x1000>; interrupts = ; mboxes = <&gce_mbox 13 0 CMDQ_THR_PRIO_1>; gce-event-names = "rsc_eof"; gce-events = <&gce_mbox CMDQ_EVENT_RSC_DONE>; clocks = <&ipesys_config IPESYS_RSC_CGPDN>; clock-names = "RSC_CLK_IPE_RSC"; }; #else rsc@1b003000 { compatible = "mediatek,rsc"; mediatek,larb = <&smi_larb20>; reg = <0 0x1b003000 0 0x1000>; interrupts = ; mboxes = <&gce_mbox 13 0 CMDQ_THR_PRIO_1>; gce-event-names = "rsc_eof"; gce-events = <&gce_mbox CMDQ_EVENT_RSC_DONE>; clocks = <&ipesys_config IPESYS_RSC_CGPDN>; clock-names = "RSC_CLK_IPE_RSC"; }; #endif ipe_smi_subcom@1b00e000 { compatible = "mediatek,ipe_smi_subcom", "mediatek,smi_common"; reg = <0 0x1b00e000 0 0x1000>; clocks = <&scpsys SCP_SYS_IPE>; clock-names = "scp-ipe"; mediatek,smi-id = <29>; }; depth@1b100000 { compatible = "mediatek,depth"; reg = <0 0x1b100000 0 0x1000>; interrupts = ; }; mdp_mutex: mdp_mutex@1f001000 { compatible = "mediatek,mdp_mutex"; reg = <0 0x1f001000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_MUTEX0>; clock-names = "MDP_MUTEX0"; }; mdp_rdma0: mdp_rdma0@1f003000 { compatible = "mediatek,mdp_rdma0", "mediatek,mdp"; reg = <0 0x1f003000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_RDMA0>, <&infracfg_ao INFRACFG_AO_GCE2_CG>, <&infracfg_ao INFRACFG_AO_GCE_26M>; clock-names = "MDP_RDMA0", "GCE", "GCE_TIMER"; mmsys_config = <&mdpsys_config>; mm_mutex = <&mdp_mutex>; mboxes = <&gce_mbox 19 0 CMDQ_THR_PRIO_1>, <&gce_mbox 20 0 CMDQ_THR_PRIO_1>, <&gce_mbox 21 0 CMDQ_THR_PRIO_1>, #if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || defined(CONFIG_MTK_CAM_SECURITY_SUPPORT) <&gce_mbox 22 0 CMDQ_THR_PRIO_1>, <&gce_mbox_sec 10 0 CMDQ_THR_PRIO_1>; #else <&gce_mbox 22 0 CMDQ_THR_PRIO_1>; #endif mdp_rdma0 = <&mdp_rdma0>; mdp_rdma1 = <&mdp_rdma1>; mdp_rsz0 = <&mdp_rsz0>; mdp_rsz1 = <&mdp_rsz1>; mdp_wrot0 = <&mdp_wrot0>; mdp_wrot1 = <&mdp_wrot1>; mdp_tdshp0 = <&mdp_tdshp0>; mdp_tdshp1 = <&mdp_tdshp1>; mdp_aal0 = <&mdp_aal0>; mdp_aal1 = <&mdp_aal1>; mdp_color0 = <&mdp_color0>; mdp_color1 = <&mdp_color1>; mdp_hdr0 = <&mdp_hdr0>; mdp_hdr1 = <&mdp_hdr1>; thread_count = <24>; mediatek,mailbox-gce = <&gce_mbox>; g3d_config_base = <0x13000000 0 0xffff0000>; mmsys_config_base = <0x14000000 1 0xffff0000>; disp_dither_base = <0x14010000 2 0xffff0000>; mm_na_base = <0x14020000 3 0xffff0000>; imgsys_base = <0x15020000 4 0xffff0000>; vdec_gcon_base = <0x18800000 5 0xffff0000>; venc_gcon_base = <0x18810000 6 0xffff0000>; conn_peri_base = <0x18820000 7 0xffff0000>; topckgen_base = <0x18830000 8 0xffff0000>; kp_base = <0x18840000 9 0xffff0000>; scp_sram_base = <0x10000000 10 0xffff0000>; infra_na3_base = <0x10010000 11 0xffff0000>; infra_na4_base = <0x10020000 12 0xffff0000>; scp_base = <0x10030000 13 0xffff0000>; mcucfg_base = <0x10040000 14 0xffff0000>; gcpu_base = <0x10050000 15 0xffff0000>; usb0_base = <0x10200000 16 0xffff0000>; usb_sif_base = <0x10280000 17 0xffff0000>; audio_base = <0x17000000 18 0xffff0000>; vdec_base = <0x17010000 19 0xffff0000>; msdc2_base = <0x17020000 20 0xffff0000>; vdec1_base = <0x17030000 21 0xffff0000>; msdc3_base = <0x18000000 22 0xffff0000>; ap_dma_base = <0x18010000 23 0xffff0000>; gce_base = <0x18020000 24 0xffff0000>; vdec2_base = <0x18040000 25 0xffff0000>; vdec3_base = <0x18050000 26 0xffff0000>; camsys_base = <0x18080000 27 0xffff0000>; camsys1_base = <0x180a0000 28 0xffff0000>; camsys2_base = <0x180b0000 29 0xffff0000>; dip_cq_thread0_frame_done = ; dip_cq_thread1_frame_done = ; dip_cq_thread2_frame_done = ; dip_cq_thread3_frame_done = ; dip_cq_thread4_frame_done = ; dip_cq_thread5_frame_done = ; dip_cq_thread6_frame_done = ; dip_cq_thread7_frame_done = ; dip_cq_thread8_frame_done = ; dip_cq_thread9_frame_done = ; dip_cq_thread10_frame_done = ; dip_cq_thread11_frame_done = ; dip_cq_thread12_frame_done = ; dip_cq_thread13_frame_done = ; dip_cq_thread14_frame_done = ; dip_cq_thread21_frame_done = ; dip_cq_thread23_frame_done = ; wpe_a_frame_done = ; dip2_cq_thread0_frame_done = ; dip2_cq_thread1_frame_done = ; dip2_cq_thread2_frame_done = ; dip2_cq_thread3_frame_done = ; dip2_cq_thread4_frame_done = ; dip2_cq_thread5_frame_done = ; dip2_cq_thread6_frame_done = ; dip2_cq_thread7_frame_done = ; dip2_cq_thread8_frame_done = ; dip2_cq_thread9_frame_done = ; dip2_cq_thread10_frame_done = ; dip2_cq_thread11_frame_done = ; dip2_cq_thread12_frame_done = ; dip2_cq_thread13_frame_done = ; dip2_cq_thread14_frame_done = ; dip2_cq_thread21_frame_done = ; dip2_cq_thread23_frame_done = ; wpe_b_frame_done = ; mdp_rdma0_sof = <256>; mdp_rdma1_sof = <257>; mdp_aal_sof = <258>; mdp_aal1_sof = <259>; mdp_hdr0_sof = <260>; mdp_hdr1_sof = <261>; mdp_rsz0_sof = <262>; mdp_rsz1_sof = <263>; mdp_wrot0_sof = <264>; mdp_wrot1_sof = <265>; mdp_tdshp_sof = <266>; mdp_tdshp1_sof = <267>; img_dl_relay_sof = <268>; img_dl_relay1_sof = <269>; mdp_color_sof = <270>; mdp_color1_sof = <271>; mdp_wrot1_write_frame_done = <290>; mdp_wrot0_write_frame_done = <291>; mdp_tdshp1_frame_done = <294>; mdp_tdshp_frame_done = <295>; mdp_rsz1_frame_done = <302>; mdp_rsz0_frame_done = <303>; mdp_rdma1_frame_done = <306>; mdp_rdma0_frame_done = <307>; mdp_hdr1_frame_done = <308>; mdp_hdr0_frame_done = <308>; mdp_color1_frame_done = <312>; mdp_color_frame_done = <313>; mdp_aal1_frame_done = <316>; mdp_aal_frame_done = <316>; dre30_hist_sram_start = <1536>; }; mdp_rdma1: mdp_rdma1@1f004000 { compatible = "mediatek,mdp_rdma1"; reg = <0 0x1f004000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_RDMA1>; clock-names = "MDP_RDMA1"; }; mdp_aal0: mdp_aal0@1f005000 { compatible = "mediatek,mdp_aal0"; reg = <0 0x1f005000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_AAL0>; clock-names = "MDP_AAL0"; }; mdp_aal1: mdp_aal0@1f006000 { compatible = "mediatek,mdp_aal1"; reg = <0 0x1f006000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_AAL1>; clock-names = "MDP_AAL1"; }; mdp_hdr0: mdp_hdr0@1f007000 { compatible = "mediatek,mdp_hdr0"; reg = <0 0x1f007000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_HDR0>; clock-names = "MDP_HDR0"; }; mdp_hdr1: mdp_hdr0@1f008000 { compatible = "mediatek,mdp_hdr1"; reg = <0 0x1f008000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_HDR1>; clock-names = "MDP_HDR1"; }; mdp_rsz0: mdp_rsz0@1f009000 { compatible = "mediatek,mdp_rsz0"; reg = <0 0x1f009000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_RSZ0>; clock-names = "MDP_RSZ0"; }; mdp_rsz1: mdp_rsz1@1f00a000 { compatible = "mediatek,mdp_rsz1"; reg = <0 0x1f00a000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_RSZ1>; clock-names = "MDP_RSZ1"; }; mdp_wrot0: mdp_wrot0@1f00b000 { compatible = "mediatek,mdp_wrot0"; reg = <0 0x1f00b000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_WROT0>; clock-names = "MDP_WROT0"; }; mdp_wrot1: mdp_wrot0@1f00c000 { compatible = "mediatek,mdp_wrot1"; reg = <0 0x1f00c000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_WROT1>; clock-names = "MDP_WROT1"; }; mdp_tdshp0: mdp_tdshp0@1f00d000 { compatible = "mediatek,mdp_tdshp0"; reg = <0 0x1f00d000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_TDSHP0>; clock-names = "MDP_TDSHP0"; }; mdp_tdshp1: mdp_tdshp1@1f00e000 { compatible = "mediatek,mdp_tdshp1"; reg = <0 0x1f00e000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_TDSHP1>; clock-names = "MDP_TDSHP1"; }; mdp_color0: mdp_color0@1f00f000 { compatible = "mediatek,mdp_color0"; reg = <0 0x1f00f000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_COLOR0>; clock-names = "MDP_COLOR0"; }; mdp_color1: mdp_color1@1f010000 { compatible = "mediatek,mdp_color1"; reg = <0 0x1f010000 0 0x1000>; clocks = <&mdpsys_config MDP_MDP_COLOR1>; clock-names = "MDP_COLOR1"; }; mcupm@0C540000 { compatible = "mediatek,mcupm"; reg =<0 0x0C540000 0 0x22000>, <0 0x0c55fb00 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fba0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fc40 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fce0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fd80 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fe20 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55fec0 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>, <0 0x0c55ff60 0 0xa0>, <0 0x0c562004 0 0x4>, <0 0x0c560074 0 0x4>, <0 0x0c562000 0 0x4>, <0 0x0c560078 0 0x4>; reg-names = "mcupm_base", "mbox0_base", "mbox0_set", "mbox0_clr", "mbox0_send", "mbox0_recv", "mbox1_base", "mbox1_set", "mbox1_clr", "mbox1_send", "mbox1_recv", "mbox2_base", "mbox2_set", "mbox2_clr", "mbox2_send", "mbox2_recv", "mbox3_base", "mbox3_set", "mbox3_clr", "mbox3_send", "mbox3_recv", "mbox4_base", "mbox4_set", "mbox4_clr", "mbox4_send", "mbox4_recv", "mbox5_base", "mbox5_set", "mbox5_clr", "mbox5_send", "mbox5_recv", "mbox6_base", "mbox6_set", "mbox6_clr", "mbox6_send", "mbox6_recv", "mbox7_base", "mbox7_set", "mbox7_clr", "mbox7_send", "mbox7_recv"; interrupts = , , , , , , , ; interrupt-names = "mbox0", "mbox1", "mbox2", "mbox3", "mbox4", "mbox5", "mbox6", "mbox7"; }; odm: odm { compatible = "simple-bus"; /* reserved for overlay by odm */ }; memory_ssmr_features: memory-ssmr-features { compatible = "mediatek,memory-ssmr-features"; svp-region-based-size = <0 0x18000000>; 2d_fr-size = <0 0>; tui-size = <0 0x4000000>; wfd-size = <0 0x4000000>; prot-region-based-size = <0 0x8000000>; ta-elf-size = <0 0x1000000>; ta-stack-heap-size = <0 0x6000000>; sdsp-tee-sharedmem-size = <0 0x1000000>; sdsp-firmware-size = <0 0x1000000>; }; spi0: spi0@1100a000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x1100a000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI0_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi1: spi1@11010000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x11010000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI1_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi2: spi2@11012000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x11012000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI2_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi3: spi3@11013000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x11013000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI3_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi4: spi4@11018000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x11018000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI4_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi5: spi5@11019000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x11019000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI5_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi6: spi6@1101d000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x1101d000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI6_CK_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; spi7: spi7@1101e000 { compatible = "mediatek,mt6765-spi"; mediatek,pad-select = <0>; reg = <0 0x1101e000 0 0x100>; interrupts = ; clocks = <&topckgen TOP_MAINPLL_D5_D4>, <&topckgen TOP_MUX_SPI>, <&infracfg_ao INFRACFG_AO_SPI7_CK_CG>; clock-names = "parent-clk", "sel-clk", "spi-clk"; }; i2c_common: i2c_common { compatible = "mediatek,i2c_common"; dma_support = /bits/ 8 <3>; idvfs = /bits/ 8 <1>; set_dt_div = /bits/ 8 <1>; check_max_freq = /bits/ 8 <1>; ver = /bits/ 8 <2>; set_ltiming = /bits/ 8 <1>; ext_time_config = /bits/ 16 <0x1801>; cnt_constraint = /bits/ 8 <1>; dma_ver = /bits/ 8 <1>; }; i2c0: i2c0@11f00000 { compatible = "mediatek,i2c"; id = <0>; reg = <0 0x11f00000 0 0x1000>, <0 0x10217080 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n IMP_IIC_WRAP_N_AP_I2C0_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <204>; sda-gpio-id = <205>; gpio_start = <0x11f20000>; mem_len = <0x200>; eh_cfg = <0x10>; pu_cfg = <0x50>; rsel_cfg = <0x70>; aed = <0x1a>; }; i2c1: i2c1@11d20000 { compatible = "mediatek,i2c"; id = <1>; reg = <0 0x11d20000 0 0x1000>, <0 0x10217100 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_ws IMP_IIC_WRAP_WS_AP_I2C1_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <118>; sda-gpio-id = <119>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; }; i2c2: i2c2@11d21000 { compatible = "mediatek,i2c"; id = <2>; reg = <0 0x11d21000 0 0x1000>, <0 0x10217180 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_ws IMP_IIC_WRAP_WS_AP_I2C2_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <141>; sda-gpio-id = <142>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; ch_offset_default = <0x100>; ch_offset_ccu = <0x200>; }; i2c3: i2c3@11cb0000 { compatible = "mediatek,i2c"; id = <3>; reg = <0 0x11cb0000 0 0x1000>, <0 0x10217300 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_e IMP_IIC_WRAP_E_AP_I2C3_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <160>; sda-gpio-id = <161>; gpio_start = <0x11ea0000>; mem_len = <0x200>; eh_cfg = <0x30>; pu_cfg = <0xa0>; rsel_cfg = <0xf0>; aed = <0x1a>; }; i2c4: i2c4@11d22000 { compatible = "mediatek,i2c"; id = <4>; reg = <0 0x11d22000 0 0x1000>, <0 0x10217380 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_ws IMP_IIC_WRAP_WS_AP_I2C4_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <139>; sda-gpio-id = <140>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; ch_offset_default = <0x100>; ch_offset_ccu = <0x200>; }; i2c5: i2c5@11e00000 { compatible = "mediatek,i2c"; id = <5>; reg = <0 0x11e00000 0 0x1000>, <0 0x10217500 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_w IMP_IIC_WRAP_W_AP_I2C5_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <202>; sda-gpio-id = <203>; gpio_start = <0x11e20000>; mem_len = <0x200>; eh_cfg = <0x20>; pu_cfg = <0x50>; rsel_cfg = <0x70>; aed = <0x1a>; }; i2c6: i2c6@11f01000 { compatible = "mediatek,i2c"; id = <6>; reg = <0 0x11f01000 0 0x1000>, <0 0x10217580 0 0x80>; interrupts = ; clocks = <&imp_iic_wrap_n IMP_IIC_WRAP_N_AP_I2C6_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <200>; sda-gpio-id = <201>; gpio_start = <0x11f20000>; mem_len = <0x200>; eh_cfg = <0x10>; pu_cfg = <0x50>; rsel_cfg = <0x70>; aed = <0x1a>; }; i2c7: i2c7@11d00000 { compatible = "mediatek,i2c"; id = <7>; reg = <0 0x11d00000 0 0x1000>, <0 0x10217600 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C7_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <124>; sda-gpio-id = <125>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; }; i2c8: i2c8@11d01000 { compatible = "mediatek,i2c"; id = <8>; reg = <0 0x11d01000 0 0x1000>, <0 0x10217780 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C8_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <122>; sda-gpio-id = <123>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; ch_offset_default = <0x100>; ch_offset_ccu = <0x200>; }; i2c9: i2c9@11d02000 { compatible = "mediatek,i2c"; id = <9>; reg = <0 0x11d02000 0 0x1000>, <0 0x10217900 0 0x180>; interrupts = ; clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C9_CG_RO>, <&infracfg_ao INFRACFG_AO_AP_DMA_CG>; clock-names = "main", "dma"; clock-div = <5>; scl-gpio-id = <120>; sda-gpio-id = <121>; gpio_start = <0x11d40000>; mem_len = <0x200>; eh_cfg = <0x40>; pu_cfg = <0xb0>; rsel_cfg = <0xe0>; aed = <0x1a>; ch_offset_default = <0x100>; ch_offset_ccu = <0x200>; }; i2c10: i2c10@11015000 { compatible = "mediatek,i2c"; id = <10>; reg = <0 0x11015000 0 0x1000>; interrupts = ; clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C10_CG_RO>; clock-names = "main"; clock-div = <5>; aed = <0x1a>; mediatek,fifo_only; }; i2c11: i2c11@11017000 { compatible = "mediatek,i2c"; id = <11>; reg = <0 0x11017000 0 0x1000>; interrupts = ; clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C11_CG_RO>; clock-names = "main"; clock-div = <5>; aed = <0x1a>; mediatek,fifo_only; }; goodix_fp: fingerprint { compatible = "mediatek,goodix-fp"; }; accdet: accdet { compatible = "mediatek,pmic-accdet"; }; mt6359_gauge { compatible = "mediatek,mt6359_gauge"; bootmode = <&chosen>; gauge_name = "gauge"; alias_name = "MT6359"; }; gauge_timer { compatible = "mediatek,gauge_timer_service"; }; #if (CONFIG_MTK_GAUGE_VERSION == 30) #include "mediatek/bat_setting/mt6873_battery_prop.dtsi" #endif edma0: edma0@19027000 { compatible = "mtk,edma-sub"; reg = <0x0 0x19027000 0x0 0x1000>; interrupts = ; }; edma: edma { compatible = "mtk,edma"; sub_nr = <1>; mediatek,edma-sub = <&edma0>; }; slbc: slbc { compatible = "mediatek,slbc"; status = "enable"; }; vpu_core0: vpu_core0@19030000 { compatible = "mediatek,vpu_core0"; reg = <0 0x19030000 0 0x1000>, <0 0x1d100000 0 0x40000>, <0 0x1d140000 0 0x30000>, <0 0x0d190000 0 0x4000>; interrupts = ; id = <0>; reset-vector = <0x7da00000 0x00100000 0x0>; main-prog = <0x7db00000 0x00300000 0x100000>; kernel-lib = <0x7de00000 0x00500000 0xffffffff>; work-buf = <0x0 0x12000 0xffffffff>; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_CODE>; #endif }; vpu_core1: vpu_core1@19031000 { compatible = "mediatek,vpu_core1"; reg = <0 0x19031000 0 0x1000>, <0 0x1d200000 0 0x40000>, <0 0x1d240000 0 0x30000>, <0 0x0d194000 0 0x4000>; interrupts = ; id = <1>; reset-vector = <0x7e300000 0x00100000 0x400000>; main-prog = <0x7e400000 0x00300000 0x500000>; kernel-lib = <0x7e700000 0x00500000 0xffffffff>; work-buf = <0x0 0x12000 0xffffffff>; #ifdef CONFIG_MTK_IOMMU_V2 iommus = <&iommu1 M4U_PORT_L21_APU_FAKE_CODE>; #endif }; irtx_pwm:irtx_pwm { compatible = "mediatek,irtx-pwm"; pwm_ch = <3>; pwm_data_invert = <0>; }; mt_charger: mt_charger { compatible = "mediatek,mt-charger"; bootmode = <&chosen>; }; lk_charger: lk_charger { compatible = "mediatek,lk_charger"; enable_anime; /* enable_pe_plus; */ enable_pd20_reset; power_path_support; max_charger_voltage = <6500000>; fast_charge_voltage = <3000000>; /* charging current */ usb_charger_current = <500000>; ac_charger_current = <2050000>; ac_charger_input_current = <3200000>; non_std_ac_charger_current = <500000>; charging_host_charger_current = <1500000>; ta_ac_charger_current = <3000000>; pd_charger_current = <500000>; /* battery temperature protection */ temp_t4_threshold = <50>; temp_t3_threshold = <45>; temp_t1_threshold = <0>; }; charger: charger { compatible = "mediatek,charger"; algorithm_name = "SwitchCharging2"; /* enable_sw_jeita; */ /* enable_pe_plus; */ /* enable_pe_2; */ /* enable_pe_3; */ /* enable_pe_4; */ enable_type_c; power_path_support; enable_dynamic_mivr; bootmode = <&chosen>; /* common */ battery_cv = <4350000>; max_charger_voltage = <6500000>; min_charger_voltage = <4600000>; /* dynamic mivr */ min_charger_voltage_1 = <4400000>; min_charger_voltage_2 = <4200000>; max_dmivr_charger_current = <1400000>; /* charging current */ usb_charger_current_suspend = <0>; usb_charger_current_unconfigured = <70000>; usb_charger_current_configured = <500000>; usb_charger_current = <500000>; ac_charger_current = <2050000>; ac_charger_input_current = <3200000>; non_std_ac_charger_current = <500000>; charging_host_charger_current = <1500000>; apple_1_0a_charger_current = <650000>; apple_2_1a_charger_current = <800000>; ta_ac_charger_current = <3000000>; /* sw jeita */ jeita_temp_above_t4_cv = <4240000>; jeita_temp_t3_to_t4_cv = <4240000>; jeita_temp_t2_to_t3_cv = <4340000>; jeita_temp_t1_to_t2_cv = <4240000>; jeita_temp_t0_to_t1_cv = <4040000>; jeita_temp_below_t0_cv = <4040000>; temp_t4_thres = <50>; temp_t4_thres_minus_x_degree = <47>; temp_t3_thres = <45>; temp_t3_thres_minus_x_degree = <39>; temp_t2_thres = <10>; temp_t2_thres_plus_x_degree = <16>; temp_t1_thres = <0>; temp_t1_thres_plus_x_degree = <6>; temp_t0_thres = <0>; temp_t0_thres_plus_x_degree = <0>; temp_neg_10_thres = <0>; /* battery temperature protection */ enable_min_charge_temp; min_charge_temp = <0>; min_charge_temp_plus_x_degree = <6>; max_charge_temp = <50>; max_charge_temp_minus_x_degree = <47>; /* PE */ ta_12v_support; ta_9v_support; pe_ichg_level_threshold = <1000000>; /* uA */ ta_ac_12v_input_current = <3200000>; ta_ac_9v_input_current = <3200000>; ta_ac_7v_input_current = <3200000>; /* PE 2.0 */ pe20_ichg_level_threshold = <1000000>; /* uA */ ta_start_battery_soc = <0>; ta_stop_battery_soc = <85>; /* PE 4.0 */ high_temp_to_leave_pe40 = <46>; high_temp_to_enter_pe40 = <39>; low_temp_to_leave_pe40 = <10>; low_temp_to_enter_pe40 = <16>; /* PE 4.0 single charger*/ pe40_single_charger_input_current = <3000000>; pe40_single_charger_current = <3000000>; /* PE 4.0 dual charger*/ pe40_dual_charger_input_current = <3000000>; pe40_dual_charger_chg1_current = <2000000>; pe40_dual_charger_chg2_current = <2000000>; pe40_stop_battery_soc = <80>; /* PE 4.0 cable impedance (mohm) */ pe40_r_cable_1a_lower = <559>; pe40_r_cable_2a_lower = <420>; pe40_r_cable_3a_lower = <279>; /* dual charger */ chg1_ta_ac_charger_current = <1500000>; chg2_ta_ac_charger_current = <1500000>; slave_mivr_diff = <100000>; dual_polling_ieoc = <750000>; /* cable measurement impedance */ cable_imp_threshold = <699>; vbat_cable_imp_threshold = <3900000>; /* uV */ /* bif */ bif_threshold1 = <4250000>; bif_threshold2 = <4300000>; bif_cv_under_threshold2 = <4450000>; /* PD */ pd_vbus_low_bound = <5000000>; pd_vbus_upper_bound = <5000000>; pd_ichg_level_threshold = <1000000>; /* uA */ pd_stop_battery_soc = <80>; ibus_err = <14>; vsys_watt = <5000000>; }; pd_adapter: pd_adapter { compatible = "mediatek,pd_adapter"; adapter_name = "pd_adapter"; }; rt-pd-manager { compatible = "mediatek,rt-pd-manager"; }; pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl { compatible = "mediatek,pmic_clock_buffer"; mediatek,clkbuf-quantity = <7>; mediatek,clkbuf-config = <2 1 1 2 0 0 1>; mediatek,clkbuf-output-impedance = <6 6 4 6 0 0 4>; mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>; }; mrdump_ext_rst: mrdump_ext_rst { compatible = "mediatek, mrdump_ext_rst-eint"; mode = "IRQ"; status = "okay"; }; gyro: gyro { }; als: als { }; touch: touch { }; nfc:nfc { compatible = "mediatek,nfc-gpio-v2"; gpio-rst = <10>; gpio-rst-std = <&pio 10 0x0>; gpio-irq = <11>; gpio-irq-std = <&pio 11 0x0>; }; irq_nfc: irq_nfc { compatible = "mediatek,irq_nfc-eint"; }; /* NFC end */ mtee_svp: mtee_svp { compatible = "medaitek,svp"; }; /* svp end */ subpmic_pmu_eint: subpmic_pmu_eint { }; tcpc_pd: tcpc_pd { }; smart_pa: smart_pa { }; keypad: kp@10010000 { compatible = "mediatek,kp"; reg = <0 0x10010000 0 0x1000>; interrupts = ; }; ses: ses { compatible = "mediatek,ses"; state = <256>; ses0_reg3 = <0>; ses1_reg3 = <0>; ses2_reg3 = <0>; ses3_reg3 = <0>; ses4_reg3 = <0>; ses5_reg3 = <0>; ses6_reg3 = <0>; ses7_reg3 = <0>; ses8_reg3 = <0>; ses0_reg2 = <0>; ses1_reg2 = <0>; ses2_reg2 = <0>; ses3_reg2 = <0>; ses4_reg2 = <0>; ses5_reg2 = <0>; ses6_reg2 = <0>; ses7_reg2 = <0>; ses8_reg2 = <0>; ses0_drphipct = <0>; ses1_drphipct = <0>; ses2_drphipct = <0>; ses3_drphipct = <0>; ses4_drphipct = <0>; ses5_drphipct = <0>; ses6_drphipct = <0>; ses7_drphipct = <0>; ses8_drphipct = <0>; ses0_drplopct = <0>; ses1_drplopct = <0>; ses2_drplopct = <0>; ses3_drplopct = <0>; ses4_drplopct = <0>; ses5_drplopct = <0>; ses6_drplopct = <0>; ses7_drplopct = <0>; ses8_drplopct = <0>; }; brisket: brisket { compatible = "mediatek,brisket"; brisket_doe_ptp = <256>; brisket_doe_pllclken = <256>; brisket_doe_bren = <256>; brisket_doe_brisket05 = <0>; brisket_doe_brisket06 = <0>; brisket_doe_brisket07 = <0>; brisket_doe_brisket08 = <0>; brisket_doe_brisket09 = <0>; }; credit_didt: credit_didt { compatible = "mediatek,credit_didt"; credit_didt_doe_ptp = <256>; credit_didt_doe_enable = <65536>; credit_didt_doe_const_mode = <256>; credit_didt_doe_ls_period = <8>; credit_didt_doe_ls_credit = <32>; credit_didt_doe_ls_low_freq_period = <8>; credit_didt_doe_ls_low_freq_enable = <2>; credit_didt_doe_vx_period = <8>; credit_didt_doe_vx_credit = <32>; credit_didt_doe_vx_low_freq_period = <8>; credit_didt_doe_vx_low_freq_enable = <2>; }; drcc: drcc { compatible = "mediatek,drcc"; state = <255>; drcc0_Vref = <255>; drcc1_Vref = <255>; drcc2_Vref = <255>; drcc3_Vref = <255>; drcc4_Vref = <255>; drcc5_Vref = <255>; drcc6_Vref = <255>; drcc7_Vref = <255>; drcc0_Hwgatepct = <255>; drcc1_Hwgatepct = <255>; drcc2_Hwgatepct = <255>; drcc3_Hwgatepct = <255>; drcc4_Hwgatepct = <255>; drcc5_Hwgatepct = <255>; drcc6_Hwgatepct = <255>; drcc7_Hwgatepct = <255>; drcc0_Code = <255>; drcc1_Code = <255>; drcc2_Code = <255>; drcc3_Code = <255>; drcc4_Code = <255>; drcc5_Code = <255>; drcc6_Code = <255>; drcc7_Code = <255>; }; cpumssv: cpumssv { compatible = "mediatek,cpumssv"; state = <0>; }; ssusb_ip_sleep: ssusb_ip_sleep { compatible = "mediatek,usb_ipsleep"; interrupt-parent = <&pio>; interrupts = <211 IRQ_TYPE_LEVEL_LOW 223 0>; }; typec_mux_switch: typec_mux_switch { compatible = "mediatek,typec_mux_switch"; status = "okay"; }; fusb304: fusb304 { compatible = "mediatek,fusb304"; status = "okay"; }; ptn36241g: ptn36241g { compatible = "mediatek,ptn36241g"; status = "okay"; }; }; &spmi_bus { #ifdef CONFIG_FPGA_EARLY_PORTING grpid = <8>; mt6315_10: mt6315@10 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0xa SPMI_USID 0x8 SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; }; mt6315_11: mt6315@11 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0xb SPMI_USID 0x8 SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; }; mt6315_12: mt6315@12 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0xc SPMI_USID 0x8 SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; }; #else grpid = <11>; mt6315_6: mt6315@6 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0x6 SPMI_USID 0xb SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; mt6315_6_regulator: mt6315_6_regulator { compatible = "mediatek,mt6315_6-regulator"; interrupt-parent = <&pio>; interrupts = <167 IRQ_TYPE_LEVEL_HIGH 167 0>; }; }; mt6315_7: mt6315@7 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0x7 SPMI_USID 0xb SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; mt6315_7_regulator: mt6315_7_regulator { compatible = "mediatek,mt6315_7-regulator"; interrupt-parent = <&pio>; interrupts = <163 IRQ_TYPE_LEVEL_HIGH 163 0>; }; }; mt6315_3: mt6315@3 { compatible = "mediatek,mt6315", "mtk,spmi-pmic"; reg = <0x3 SPMI_USID 0xb SPMI_GSID>; #address-cells = <1>; #size-cells = <0>; mt6315_3_regulator: mt6315_3_regulator { compatible = "mediatek,mt6315_3-regulator"; interrupt-parent = <&pio>; interrupts = <164 IRQ_TYPE_LEVEL_HIGH 164 0>; }; }; #endif }; &i2c6 { speaker_amp: speaker_amp@34 { compatible = "mediatek,speaker_amp"; #sound-dai-cells = <0>; reg = <0x34>; status = "okay"; }; }; &pio { aud_clk_mosi_off: aud_clk_mosi_off { pins_cmd0_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_clk_mosi_on: aud_clk_mosi_on { pins_cmd0_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_mosi_off: aud_dat_mosi_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_mosi_on: aud_dat_mosi_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_mosi_ch34_off: aud_dat_mosi_ch34_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_mosi_ch34_on: aud_dat_mosi_ch34_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso_off: aud_dat_miso_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-disable; }; }; aud_dat_miso_on: aud_dat_miso_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso_ch34_off: aud_dat_miso_ch34_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_miso_ch34_on: aud_dat_miso_ch34_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_dat_miso_off: vow_dat_miso_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; vow_dat_miso_on: vow_dat_miso_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; vow_clk_miso_off: vow_clk_miso_off { pins_cmd3_dat { pinmux = ; input-enable; bias-pull-down; }; }; vow_clk_miso_on: vow_clk_miso_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_nle_mosi_off: aud_nle_mosi_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_nle_mosi_on: aud_nle_mosi_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_dat_miso2_off: aud_dat_miso2_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_dat_miso2_on: aud_dat_miso2_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s0_off: aud_gpio_i2s0_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s0_on: aud_gpio_i2s0_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s1_off: aud_gpio_i2s1_off { }; aud_gpio_i2s1_on: aud_gpio_i2s1_on { }; aud_gpio_i2s2_off: aud_gpio_i2s2_off { }; aud_gpio_i2s2_on: aud_gpio_i2s2_on { }; aud_gpio_i2s3_off: aud_gpio_i2s3_off { pins_cmd1_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd2_dat { pinmux = ; input-enable; bias-pull-down; }; pins_cmd3_dat { pinmux = ; input-enable; bias-pull-down; }; }; aud_gpio_i2s3_on: aud_gpio_i2s3_on { pins_cmd1_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd2_dat { pinmux = ; input-schmitt-enable; bias-disable; }; pins_cmd3_dat { pinmux = ; input-schmitt-enable; bias-disable; }; }; aud_gpio_i2s5_off: aud_gpio_i2s5_off { }; aud_gpio_i2s5_on: aud_gpio_i2s5_on { }; aud_gpio_i2s6_off: aud_gpio_i2s6_off { }; aud_gpio_i2s6_on: aud_gpio_i2s6_on { }; aud_gpio_i2s7_off: aud_gpio_i2s7_off { }; aud_gpio_i2s7_on: aud_gpio_i2s7_on { }; aud_gpio_i2s8_off: aud_gpio_i2s8_off { }; aud_gpio_i2s8_on: aud_gpio_i2s8_on { }; aud_gpio_i2s9_off: aud_gpio_i2s9_off { }; aud_gpio_i2s9_on: aud_gpio_i2s9_on { }; msdc1_ins:msdc1_ins { }; md1_sim1_hot_plug_eint:md1_sim1_hot_plug_eint { }; md1_sim2_hot_plug_eint:md1_sim2_hot_plug_eint { }; }; #include "mediatek/v1/mt6360.dtsi" #ifndef CONFIG_FPGA_EARLY_PORTING #include "mediatek/mt6315_s6.dtsi" #include "mediatek/mt6315_s7.dtsi" #include "mediatek/mt6315_s3.dtsi" #endif #include "mediatek/mt6359p.dtsi" #include "mediatek/cust_mt6873_msdc.dtsi" #include "mediatek/v1/mt6360_pd.dtsi" #ifdef CONFIG_MTK_ENABLE_GENIEZONE #include "mediatek/trusty.dtsi" #endif