/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
*/

#ifndef __MPU_PLATFORM_H__
#define __MPU_PLATFORM_H__

enum {
	MT6785_M4_AXI_MST_QP_DLCH,
	MT6785_M4_AXI_MST_BR_DMA,
	MT6785_M2_AXI_MST_CCU,
	MT6785_M2_AXI_MST_SMI_LARB0,
	MT6785_M4_AXI_MST_DCXO,
	MT6785_M4_AXI_MST_MRSG0,
	MT6785_M7_AXI_MST_IPU,
	MT6785_M7_AXI_MST_CCU,
	MT6785_M4_AXI_MST_IRDMA,
	MT6785_M7_AXI_MST_MSDC0,
	MT6785_M2_AXI_MST_SMI_LARB2,
	MT6785_M4_AXI_MST_TRACE_TOP,
	MT6785_M4_AXI_MST_CSH0,
	MT6785_M4_AXI_MST_DMA_WR,
	MT6785_M7_AXI_MST_APU,
	MT6785_M7_AXI_MST_SPI1,
	MT6785_M4_AXI_MST_SSPM,
	MT6785_M2_AXI_MST_SMI_LARB6,
	MT6785_M7_AXI_MST_SPI3,
	MT6785_M3_AXI_MST_MMU,
	MT6785_M7_AXI_MST_SPI5,
	MT6785_M4_AXI_MST_IPSEC,
	MT6785_M4_AXI_MST_CNWDMA,
	MT6785_M7_AXI_MST_SPI7,
	MT6785_M5_AXI_MST_SMI_LARB1,
	MT6785_M7_AXI_MST_UFS,
	MT6785_M7_AXI_MST_DX_CC,
	MT6785_M4_AXI_MST_MMU,
	MT6785_M7_AXI_MST_APU_IOMMU_P1,
	MT6785_M1_AXI_MST_MP1,
	MT6785_M3_AXI_MST_USIP_0_DPERI,
	MT6785_M5_AXI_MST_SMI_LARB3,
	MT6785_M4_AXI_MST_HRQ_RD,
	MT6785_M4_AXI_MST_LOG_TOP_MCU,
	MT6785_M3_AXI_MST_USIP_1_I,
	MT6785_M5_AXI_MST_SMI_LARB5,
	MT6785_M5_AXI_MST_MM_IOMMU,
	MT6785_M4_AXI_MST_DBGSYS_DSP,
	MT6785_M3_AXI_MST_USIP_1_DPERI,
	MT6785_M4_AXI_MST_GDMA,
	MT6785_M4_AXI_MST_LOG_TOP_DSP,
	MT6785_M7_AXI_MST_DEVICE_MPU,
	MT6785_M7_AXI_MST_DMA_EXT,
	MT6785_M4_AXI_MST_HRQ_RD1,
	MT6785_M3_AXI_MST_USIP_0_I,
	MT6785_M4_AXI_MST_DMA_RD_DLCH,
	MT6785_M4_AXI_MST_TXBSRP,
	MT6785_M6_AXI_MST_APU_IOMMU,
	MT6785_M7_AXI_MST_CQ_DMA,
	MT6785_M2_AXI_MST_SMI_LARB1,
	MT6785_M7_AXI_MST_PWM,
	MT6785_M4_AXI_MST_,
	MT6785_M4_AXI_MST_MRSG1,
	MT6785_M2_AXI_MST_SMI_LARB3,
	MT6785_M7_AXI_MST_MSDC1,
	MT6785_M7_AXI_MST_SPI0,
	MT6785_M7_AXI_MST_NA,
	MT6785_M4_AXI_MST_IPF,
	MT6785_M4_AXI_MST_DMA_RD,
	MT6785_M4_AXI_MST_XDMA,
	MT6785_M7_AXI_MST_AUDIO,
	MT6785_M2_AXI_MST_SMI_LARB5,
	MT6785_M4_AXI_MST_TPC,
	MT6785_M7_AXI_MST_THERM,
	MT6785_M7_AXI_MST_SPI2,
	MT6785_M5_AXI_MST_CCU,
	MT6785_M4_AXI_MST_VTB,
	MT6785_M7_AXI_MST_SPM,
	MT6785_M0_AXI_MST_MP0,
	MT6785_M3_AXI_MST_MM,
	MT6785_M7_AXI_MST_MFG_M1,
	MT6785_M7_AXI_MST_SPI4,
	MT6785_M4_AXI_MST_CLDMA,
	MT6785_M4_AXI_MST_PPPHA,
	MT6785_M3_AXI_MST_USIP_1_DLONG,
	MT6785_M7_AXI_MST_SSUSB,
	MT6785_M4_AXI_MST_SCP,
	MT6785_M4_AXI_MST_HIFI3,
	MT6785_M4_AXI_MST_QP,
	MT6785_M3_AXI_MST_USIP_0_DLONG,
	MT6785_M7_AXI_MST_GCE_M,
	MT6785_M7_AXI_MST_SPI6,
	MT6785_M5_AXI_MST_SMI_LARB0,
	MT6785_M6_AXI_MST_MFG,
	MT6785_M7_AXI_MST_DEBUGTOP,
	MT6785_M5_AXI_MST_SMI_LARB2,
	MT6785_M4_AXI_MST_MCUSYS_DFD,
	MT6785_M4_AXI_MST_HRQ_WR,
	MT6785_M6_AXI_MST_APU,
	MT6785_M4_AXI_MST_TBO,
	MT6785_M2_AXI_MST_MM_IOMMU,
	MT6785_M5_AXI_MST_SMI_LARB6,
	MT6785_M4_AXI_MST_HRQ_WR1,
	MT6785_M4_AXI_MST_CONNSYS,
	MST_INVALID,
	NR_MST
};

static const struct mst_tbl_entry mst_tbl[] = {
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1EF8,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1EF8,
		.id_val = 0x20,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1E80,
		.id_val = 0x80,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DF8,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DF8,
		.id_val = 0x20,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DFF,
		.id_val = 0x40,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1DFF,
		.id_val = 0x41,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1D80,
		.id_val = 0x80,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1D00,
		.id_val = 0x100,
		.note = "",
		.name = "MT6785_M0_AXI_MST_MP0"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1EF8,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1EF8,
		.id_val = 0x20,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1E80,
		.id_val = 0x80,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DF8,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DF8,
		.id_val = 0x20,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DFF,
		.id_val = 0x40,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1DFF,
		.id_val = 0x41,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1D80,
		.id_val = 0x80,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1D00,
		.id_val = 0x100,
		.note = "",
		.name = "MT6785_M1_AXI_MST_MP1"},
	{.master = MT6785_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
		.id_val = 0xFFC,
		.note = "",
		.name = "MT6785_M2_AXI_MST_MM_IOMMU"},
	{.master = MT6785_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
		.id_val = 0xFFD,
		.note = "",
		.name = "MT6785_M2_AXI_MST_MM_IOMMU"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB0, .port = 2, .id_mask = 0x1F80,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB0"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB1, .port = 2, .id_mask = 0x1F80,
		.id_val = 0x200,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB1"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB2, .port = 2, .id_mask = 0x1F80,
		.id_val = 0x400,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB2"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB3, .port = 2, .id_mask = 0x1F80,
		.id_val = 0x600,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB3"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB5, .port = 2, .id_mask = 0x1F80,
		.id_val = 0x800,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB5"},
	{.master = MT6785_M2_AXI_MST_SMI_LARB6, .port = 2, .id_mask = 0x1F80,
		.id_val = 0xE00,
		.note = "",
		.name = "MT6785_M2_AXI_MST_SMI_LARB6"},
	{.master = MT6785_M2_AXI_MST_CCU, .port = 2, .id_mask = 0x1F80,
		.id_val = 0xC00,
		.note = "",
		.name = "MT6785_M2_AXI_MST_CCU"},
	{.master = MT6785_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
		.id_val = 0xFFC,
		.note = "",
		.name = "MT6785_M5_AXI_MST_MM_IOMMU"},
	{.master = MT6785_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
		.id_val = 0xFFD,
		.note = "",
		.name = "MT6785_M5_AXI_MST_MM_IOMMU"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB0, .port = 5, .id_mask = 0x1F80,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB0"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB1, .port = 5, .id_mask = 0x1F80,
		.id_val = 0x200,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB1"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB2, .port = 5, .id_mask = 0x1F80,
		.id_val = 0x400,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB2"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB3, .port = 5, .id_mask = 0x1F80,
		.id_val = 0x600,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB3"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB5, .port = 5, .id_mask = 0x1F80,
		.id_val = 0x800,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB5"},
	{.master = MT6785_M5_AXI_MST_SMI_LARB6, .port = 5, .id_mask = 0x1F80,
		.id_val = 0xE00,
		.note = "",
		.name = "MT6785_M5_AXI_MST_SMI_LARB6"},
	{.master = MT6785_M5_AXI_MST_CCU, .port = 5, .id_mask = 0x1F80,
		.id_val = 0xC00,
		.note = "",
		.name = "MT6785_M5_AXI_MST_CCU"},
	{.master = MT6785_M6_AXI_MST_APU_IOMMU, .port = 6, .id_mask = 0x1FFF,
		.id_val = 0x7FC,
		.note = "",
		.name = "MT6785_M6_AXI_MST_APU_IOMMU"},
	{.master = MT6785_M6_AXI_MST_APU_IOMMU, .port = 6, .id_mask = 0x1FFF,
		.id_val = 0x7FD,
		.note = "",
		.name = "MT6785_M6_AXI_MST_APU_IOMMU"},
	{.master = MT6785_M6_AXI_MST_APU, .port = 6, .id_mask = 0x1C00,
		.id_val = 0x400,
		.note = "",
		.name = "MT6785_M6_AXI_MST_APU"},
	{.master = MT6785_M6_AXI_MST_MFG, .port = 6, .id_mask = 0x1FC0,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M6_AXI_MST_MFG"},
	{.master = MT6785_M7_AXI_MST_SSUSB, .port = 7, .id_mask = 0x1FCF,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SSUSB"},
	{.master = MT6785_M7_AXI_MST_PWM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x8,
		.note = "",
		.name = "MT6785_M7_AXI_MST_PWM"},
	{.master = MT6785_M7_AXI_MST_MSDC1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x18,
		.note = "",
		.name = "MT6785_M7_AXI_MST_MSDC1"},
	{.master = MT6785_M7_AXI_MST_SPI6, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x28,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI6"},
	{.master = MT6785_M7_AXI_MST_SPI0, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x38,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI0"},
	{.master = MT6785_M7_AXI_MST_DEBUGTOP, .port = 7, .id_mask = 0x1FBF,
		.id_val = 0x4,
		.note = "",
		.name = "MT6785_M7_AXI_MST_DEBUGTOP"},
	{.master = MT6785_M7_AXI_MST_AUDIO, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x20C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_AUDIO"},
	{.master = MT6785_M7_AXI_MST_IPU, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x40C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_IPU"},
	{.master = MT6785_M7_AXI_MST_SPI1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x60C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI1"},
	{.master = MT6785_M7_AXI_MST_SPI7, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0xC,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI7"},
	{.master = MT6785_M7_AXI_MST_CCU, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x4C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_CCU"},
	{.master = MT6785_M7_AXI_MST_SPM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x24C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPM"},
	{.master = MT6785_M7_AXI_MST_NA, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x44C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_NA"},
	{.master = MT6785_M7_AXI_MST_THERM, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x64C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_THERM"},
	{.master = MT6785_M7_AXI_MST_UFS, .port = 7, .id_mask = 0x19FF,
		.id_val = 0x8C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_UFS"},
	{.master = MT6785_M7_AXI_MST_DMA_EXT, .port = 7, .id_mask = 0x1DFF,
		.id_val = 0xCC,
		.note = "",
		.name = "MT6785_M7_AXI_MST_DMA_EXT"},
	{.master = MT6785_M7_AXI_MST_SPI2, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x14C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI2"},
	{.master = MT6785_M7_AXI_MST_SPI3, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x34C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI3"},
	{.master = MT6785_M7_AXI_MST_SPI4, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x54C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI4"},
	{.master = MT6785_M7_AXI_MST_SPI5, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x74C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_SPI5"},
	{.master = MT6785_M7_AXI_MST_MSDC0, .port = 7, .id_mask = 0x11FF,
		.id_val = 0x18C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_MSDC0"},
	{.master = MT6785_M7_AXI_MST_DX_CC, .port = 7, .id_mask = 0x1C3F,
		.id_val = 0x14,
		.note = "",
		.name = "MT6785_M7_AXI_MST_DX_CC"},
	{.master = MT6785_M7_AXI_MST_CQ_DMA, .port = 7, .id_mask = 0x1E3F,
		.id_val = 0x1C,
		.note = "",
		.name = "MT6785_M7_AXI_MST_CQ_DMA"},
	{.master = MT6785_M7_AXI_MST_GCE_M, .port = 7, .id_mask = 0x1F3F,
		.id_val = 0x24,
		.note = "",
		.name = "MT6785_M7_AXI_MST_GCE_M"},
	{.master = MT6785_M7_AXI_MST_APU_IOMMU_P1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x1FF1,
		.note = "",
		.name = "MT6785_M7_AXI_MST_APU_IOMMU_P1"},
	{.master = MT6785_M7_AXI_MST_APU_IOMMU_P1, .port = 7, .id_mask = 0x1FFF,
		.id_val = 0x1FF5,
		.note = "",
		.name = "MT6785_M7_AXI_MST_APU_IOMMU_P1"},
	{.master = MT6785_M7_AXI_MST_APU, .port = 7, .id_mask = 0x1003,
		.id_val = 0x1001,
		.note = "",
		.name = "MT6785_M7_AXI_MST_APU"},
	{.master = MT6785_M7_AXI_MST_MFG_M1, .port = 7, .id_mask = 0x1F03,
		.id_val = 0x1,
		.note = "",
		.name = "MT6785_M7_AXI_MST_MFG_M1"},
	{.master = MT6785_M7_AXI_MST_DEVICE_MPU, .port = 7, .id_mask = 0x1803,
		.id_val = 0x2,
		.note = "",
		.name = "MT6785_M7_AXI_MST_DEVICE_MPU"},
	{.master = MT6785_M3_AXI_MST_MM, .port = 3, .id_mask = 0x1F83,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M3_AXI_MST_MM"},
	{.master = MT6785_M3_AXI_MST_MMU, .port = 3, .id_mask = 0x1F83,
		.id_val = 0x1,
		.note = "",
		.name = "MT6785_M3_AXI_MST_MMU"},
	{.master = MT6785_M3_AXI_MST_USIP_0_I, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0x2,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_0_I"},
	{.master = MT6785_M3_AXI_MST_USIP_0_DLONG, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0x12,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_0_DLONG"},
	{.master = MT6785_M3_AXI_MST_USIP_0_DPERI, .port = 3, .id_mask = 0x1E0F,
		.id_val = 0x6,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_0_DPERI"},
	{.master = MT6785_M3_AXI_MST_USIP_1_I, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0xA,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_1_I"},
	{.master = MT6785_M3_AXI_MST_USIP_1_DLONG, .port = 3, .id_mask = 0x1F1F,
		.id_val = 0x1A,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_1_DLONG"},
	{.master = MT6785_M3_AXI_MST_USIP_1_DPERI, .port = 3, .id_mask = 0x1E0F,
		.id_val = 0xE,
		.note = "",
		.name = "MT6785_M3_AXI_MST_USIP_1_DPERI"},
	{.master = MT6785_M4_AXI_MST_HRQ_RD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1001,
		.note = "",
		.name = "MT6785_M4_AXI_MST_HRQ_RD"},
	{.master = MT6785_M4_AXI_MST_HRQ_RD1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1009,
		.note = "",
		.name = "MT6785_M4_AXI_MST_HRQ_RD1"},
	{.master = MT6785_M4_AXI_MST_HRQ_WR, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1003,
		.note = "",
		.name = "MT6785_M4_AXI_MST_HRQ_WR"},
	{.master = MT6785_M4_AXI_MST_HRQ_WR1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x100B,
		.note = "",
		.name = "MT6785_M4_AXI_MST_HRQ_WR1"},
	{.master = MT6785_M4_AXI_MST_VTB, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1005,
		.note = "",
		.name = "MT6785_M4_AXI_MST_VTB"},
	{.master = MT6785_M4_AXI_MST_TBO, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x100D,
		.note = "",
		.name = "MT6785_M4_AXI_MST_TBO"},
	{.master = MT6785_M4_AXI_MST_BR_DMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x807,
		.note = "",
		.name = "MT6785_M4_AXI_MST_BR_DMA"},
	{.master = MT6785_M4_AXI_MST_IRDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xF,
		.note = "",
		.name = "MT6785_M4_AXI_MST_IRDMA"},
	{.master = MT6785_M4_AXI_MST_TPC, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x6F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_TPC"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xEF,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_TXBSRP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x2F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_TXBSRP"},
	{.master = MT6785_M4_AXI_MST_XDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x3F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_XDMA"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x13F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_MRSG0, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x7F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_MRSG0"},
	{.master = MT6785_M4_AXI_MST_MRSG1, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xBF,
		.note = "",
		.name = "MT6785_M4_AXI_MST_MRSG1"},
	{.master = MT6785_M4_AXI_MST_CNWDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x9F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_CNWDMA"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x19F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_CSH0, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x5F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_CSH0"},
	{.master = MT6785_M4_AXI_MST_DCXO, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1F,
		.note = "",
		.name = "MT6785_M4_AXI_MST_DCXO"},
	{.master = MT6785_M4_AXI_MST_DMA_RD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1805,
		.note = "",
		.name = "MT6785_M4_AXI_MST_DMA_RD"},
	{.master = MT6785_M4_AXI_MST_DMA_WR, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1801,
		.note = "",
		.name = "MT6785_M4_AXI_MST_DMA_WR"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1809,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_MMU, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1809,
		.note = "",
		.name = "MT6785_M4_AXI_MST_MMU"},
	{.master = MT6785_M4_AXI_MST_QP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1801,
		.note = "",
		.name = "MT6785_M4_AXI_MST_QP"},
	{.master = MT6785_M4_AXI_MST_QP_DLCH, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1803,
		.note = "",
		.name = "MT6785_M4_AXI_MST_QP_DLCH"},
	{.master = MT6785_M4_AXI_MST_DMA_RD_DLCH, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1807,
		.note = "",
		.name = "MT6785_M4_AXI_MST_DMA_RD_DLCH"},
	{.master = MT6785_M4_AXI_MST_IPF, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x180D,
		.note = "",
		.name = "MT6785_M4_AXI_MST_IPF"},
	{.master = MT6785_M4_AXI_MST_LOG_TOP_MCU, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x15,
		.note = "",
		.name = "MT6785_M4_AXI_MST_LOG_TOP_MCU"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x15,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_LOG_TOP_DSP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x7,
		.note = "",
		.name = "MT6785_M4_AXI_MST_LOG_TOP_DSP"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x7,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_TRACE_TOP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x9,
		.note = "",
		.name = "MT6785_M4_AXI_MST_TRACE_TOP"},
	{.master = MT6785_M4_AXI_MST_PPPHA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x3,
		.note = "",
		.name = "MT6785_M4_AXI_MST_PPPHA"},
	{.master = MT6785_M4_AXI_MST_IPSEC, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xB,
		.note = "",
		.name = "MT6785_M4_AXI_MST_IPSEC"},
	{.master = MT6785_M4_AXI_MST_DBGSYS_DSP, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1D,
		.note = "",
		.name = "MT6785_M4_AXI_MST_DBGSYS_DSP"},
	{.master = MT6785_M4_AXI_MST_GDMA, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xD,
		.note = "",
		.name = "MT6785_M4_AXI_MST_GDMA"},
	{.master = MT6785_M4_AXI_MST_, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0xED,
		.note = "",
		.name = "MT6785_M4_AXI_MST_"},
	{.master = MT6785_M4_AXI_MST_HIFI3, .port = 4, .id_mask = 0x1F07,
		.id_val = 0x0,
		.note = "",
		.name = "MT6785_M4_AXI_MST_HIFI3"},
	{.master = MT6785_M4_AXI_MST_CLDMA, .port = 4, .id_mask = 0x1F87,
		.id_val = 0x2,
		.note = "",
		.name = "MT6785_M4_AXI_MST_CLDMA"},
	{.master = MT6785_M4_AXI_MST_CONNSYS, .port = 4, .id_mask = 0x1FC7,
		.id_val = 0x4,
		.note = "",
		.name = "MT6785_M4_AXI_MST_CONNSYS"},
	{.master = MT6785_M4_AXI_MST_SSPM, .port = 4, .id_mask = 0x1FCF,
		.id_val = 0xE,
		.note = "",
		.name = "MT6785_M4_AXI_MST_SSPM"},
	{.master = MT6785_M4_AXI_MST_SCP, .port = 4, .id_mask = 0x1FCF,
		.id_val = 0x6,
		.note = "",
		.name = "MT6785_M4_AXI_MST_SCP"},
	{.master = MT6785_M4_AXI_MST_MCUSYS_DFD, .port = 4, .id_mask = 0x1FFF,
		.id_val = 0x1000,
		.note = "",
		.name = "MT6785_M4_AXI_MST_MCUSYS_DFD"},
};

#endif /* __MPU_PLATFORM_H__ */