/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2016 MediaTek Inc. */ #ifndef _DT_BINDINGS_CLK_MT6781_H #define _DT_BINDINGS_CLK_MT6781_H /* TOPCKGEN */ #define TOP_MUX_AXI 1 #define TOP_MUX_SCP 2 #define TOP_MUX_MFG 3 #define TOP_MUX_CAMTG 4 #define TOP_MUX_CAMTG1 5 #define TOP_MUX_CAMTG2 6 #define TOP_MUX_CAMTG3 7 #define TOP_MUX_CAMTG4 8 #define TOP_MUX_CAMTG5 9 #define TOP_MUX_CAMTG6 10 #define TOP_MUX_UART 11 #define TOP_MUX_SPI 12 #define TOP_MUX_MSDC50_0_HCLK 13 #define TOP_MUX_MSDC50_0 14 #define TOP_MUX_MSDC30_1 15 #define TOP_MUX_AUDIO 16 #define TOP_MUX_AUD_INTBUS 17 #define TOP_MUX_AUD_1 18 #define TOP_MUX_AUD_2 19 #define TOP_MUX_AUD_ENG1 20 #define TOP_MUX_AUD_ENG2 21 #define TOP_MUX_DISP_PWM 22 #define TOP_MUX_SSPM 23 #define TOP_MUX_DXCC 24 #define TOP_MUX_USB_TOP 25 #define TOP_MUX_SRCK 26 #define TOP_MUX_SPM 27 #define TOP_MUX_I2C 28 #define TOP_MUX_PWM 29 #define TOP_MUX_SENINF 30 #define TOP_MUX_SENINF1 31 #define TOP_MUX_SENINF2 32 #define TOP_MUX_SENINF3 33 #define TOP_MUX_AES_MSDCFDE 34 #define TOP_MUX_FPWRAP_ULPOSC 35 #define TOP_MUX_CAMTM 36 #define TOP_MUX_VENC 37 #define TOP_MUX_CAM 38 #define TOP_MUX_IMG1 39 #define TOP_MUX_IPE 40 #define TOP_MUX_DPMAIF 41 #define TOP_MUX_VDEC 42 #define TOP_MUX_DISP 43 #define TOP_MUX_MDP 44 #define TOP_MUX_AUDIO_H 45 #define TOP_MUX_UFS 46 #define TOP_MUX_AES_FDE 47 #define TOP_MUX_ADSP 48 #define TOP_MUX_DVFSRC 49 #define TOP_MUX_DSI_OCC 50 #define TOP_MUX_SPMI_MST 51 #define TOP_MAINPLL_CK 52 #define TOP_MAINPLL_D2 53 #define TOP_MAINPLL_D3 54 #define TOP_MAINPLL_D5 55 #define TOP_MAINPLL_D7 56 #define TOP_MAINPLL_D2_D2 57 #define TOP_MAINPLL_D2_D4 58 #define TOP_MAINPLL_D2_D8 59 #define TOP_MAINPLL_D2_D16 60 #define TOP_MAINPLL_D3_D2 61 #define TOP_MAINPLL_D3_D4 62 #define TOP_MAINPLL_D3_D8 63 #define TOP_MAINPLL_D5_D2 64 #define TOP_MAINPLL_D5_D4 65 #define TOP_MAINPLL_D7_D2 66 #define TOP_MAINPLL_D7_D4 67 #define TOP_UNIVPLL_CK 68 #define TOP_UNIVPLL_D2 69 #define TOP_UNIVPLL_D3 70 #define TOP_UNIVPLL_D5 71 #define TOP_UNIVPLL_D7 72 #define TOP_UNIVPLL_D2_D2 73 #define TOP_UNIVPLL_D2_D4 74 #define TOP_UNIVPLL_D2_D8 75 #define TOP_UNIVPLL_D3_D2 76 #define TOP_UNIVPLL_D3_D4 77 #define TOP_UNIVPLL_D3_D8 78 #define TOP_UNIVPLL_D5_D2 79 #define TOP_UNIVPLL_D5_D4 80 #define TOP_UNIVPLL_D5_D8 81 #define TOP_APLL1_CK 82 #define TOP_APLL1_D2 83 #define TOP_APLL1_D4 84 #define TOP_APLL1_D8 85 #define TOP_APLL2_CK 86 #define TOP_APLL2_D2 87 #define TOP_APLL2_D4 88 #define TOP_APLL2_D8 89 #define TOP_MSDCPLL_CK 90 #define TOP_MSDCPLL_D2 91 #define TOP_MSDCPLL_D4 92 #define TOP_MSDCPLL_D8 93 #define TOP_MSDCPLL_D16 94 #define TOP_OSC 95 #define TOP_OSC_D2 96 #define TOP_OSC_D4 97 #define TOP_OSC_D8 98 #define TOP_OSC_D10 99 #define TOP_OSC_D16 100 #define TOP_OSC_D32 101 #define TOP_F26M_CK_D2 102 #define TOP_UNIVP_192M_D2 103 #define TOP_UNIVP_192M_D4 104 #define TOP_UNIVP_192M_D8 105 #define TOP_UNIVP_192M_D16 106 #define TOP_UNIVP_192M_D32 107 #define TOP_MMPLL_CK 108 #define TOP_MMPLL_D4 109 #define TOP_MMPLL_D4_D2 110 #define TOP_MMPLL_D4_D4 111 #define TOP_MMPLL_D5 112 #define TOP_MMPLL_D5_D2 113 #define TOP_MMPLL_D5_D4 114 #define TOP_MMPLL_D6 115 #define TOP_MMPLL_D7 116 #define TOP_ADSPPLL_CK 117 #define TOP_I2S0_M_SEL 118 #define TOP_I2S1_M_SEL 119 #define TOP_I2S2_M_SEL 120 #define TOP_I2S3_M_SEL 121 #define TOP_I2S4_M_SEL 122 #define TOP_I2S5_M_SEL 123 #define TOP_APLL12_DIV0 124 #define TOP_APLL12_DIV1 125 #define TOP_APLL12_DIV2 126 #define TOP_APLL12_DIV3 127 #define TOP_APLL12_DIV4 128 #define TOP_APLL12_DIVB 129 #define TOP_APLL12_DIV5 130 #define TOP_ADSPPLL_D4 131 #define TOP_ADSPPLL_D5 132 #define TOP_ADSPPLL_D6 133 #define TOP_UNIVPLL_D3_D16 134 #define TOP_UNIVP_192M_CK 135 #define TOP_MFGPLL_CK 136 #define TOP_UNIVPLL_D3_D32 137 #define TOP_MMPLL_D2 138 #define TOP_ADSPPLL_D2 139 #define TOP_ADSPPLL_D8 140 #define TOP_NR_CLK 141 /* APMIXED */ #define APMIXED_ARMPLL_LL 1 #define APMIXED_ARMPLL_BL 2 #define APMIXED_ARMPLL_BB 3 #define APMIXED_CCIPLL 4 #define APMIXED_MAINPLL 5 #define APMIXED_UNIV2PLL 6 #define APMIXED_MSDCPLL 7 #define APMIXED_ADSPPLL 8 #define APMIXED_MMPLL 9 #define APMIXED_MFGPLL 10 #define APMIXED_APLL1 11 #define APMIXED_APLL2 12 #define APMIXED_SSUSB26M 13 #define APMIXED_APPLL26M 14 #define APMIXED_MIPIC0_26M 15 #define APMIXED_MDPLLGP26M 16 #define APMIXED_MMSYS_F26M 17 #define APMIXED_UFS26M 18 #define APMIXED_MIPIC1_26M 19 #define APMIXED_MEMPLL26M 20 #define APMIXED_CLKSQ_LVPLL_26M 21 #define APMIXED_MIPID0_26M 22 #define APMIXED_MIPID1_26M 23 #define APMIXED_NR_CLK 24 /* INFRACFG_AO */ #define INFRACFG_AO_PMIC_CG_TMR 1 #define INFRACFG_AO_PMIC_CG_AP 2 #define INFRACFG_AO_PMIC_CG_MD 3 #define INFRACFG_AO_PMIC_CG_CONN 4 #define INFRACFG_AO_SCPSYS_CG 5 #define INFRACFG_AO_SEJ_CG 6 #define INFRACFG_AO_APXGPT_CG 7 #define INFRACFG_AO_ICUSB_CG 8 #define INFRACFG_AO_GCE_CG 9 #define INFRACFG_AO_THERM_CG 10 #define INFRACFG_AO_I2C_AP_CG 11 #define INFRACFG_AO_I2C_CCU_CG 12 #define INFRACFG_AO_I2C_SSPM_CG 13 #define INFRACFG_AO_I2C_RSV_CG 14 #define INFRACFG_AO_PWM_HCLK_CG 15 #define INFRACFG_AO_PWM1_CG 16 #define INFRACFG_AO_PWM2_CG 17 #define INFRACFG_AO_PWM3_CG 18 #define INFRACFG_AO_PWM4_CG 19 #define INFRACFG_AO_PWM_CG 20 #define INFRACFG_AO_UART0_CG 21 #define INFRACFG_AO_UART1_CG 22 #define INFRACFG_AO_UART2_CG 23 #define INFRACFG_AO_UART3_CG 24 #define INFRACFG_AO_GCE_26M_CG 25 #define INFRACFG_AO_CQ_DMA_FPC_CG 26 #define INFRACFG_AO_BTIF_CG 27 #define INFRACFG_AO_SPI0_CG 28 #define INFRACFG_AO_MSDC0_CG 29 #define INFRACFG_AO_MSDC1_CG 30 #define INFRACFG_AO_MSDC2_CG 31 #define INFRACFG_AO_MSDC0_SCK_CG 32 #define INFRACFG_AO_DVFSRC_CG 33 #define INFRACFG_AO_GCPU_CG 34 #define INFRACFG_AO_TRNG_CG 35 #define INFRACFG_AO_AUXADC_CG 36 #define INFRACFG_AO_CPUM_CG 37 #define INFRACFG_AO_CCIF1_AP_CG 38 #define INFRACFG_AO_CCIF1_MD_CG 39 #define INFRACFG_AO_AUXADC_MD_CG 40 #define INFRACFG_AO_MSDC1_SCK_CG 41 #define INFRACFG_AO_MSDC2_SCK_CG 42 #define INFRACFG_AO_AP_DMA_CG 43 #define INFRACFG_AO_XIU_CG 44 #define INFRACFG_AO_DEVICE_APC_CG 45 #define INFRACFG_AO_CCIF_AP_CG 46 #define INFRACFG_AO_DEBUGSYS_CG 47 #define INFRACFG_AO_AUDIO_CG 48 #define INFRACFG_AO_CCIF_MD_CG 49 #define INFRACFG_AO_DXCC_SEC_CORE_CG 50 #define INFRACFG_AO_DXCC_AO_CG 51 #define INFRACFG_AO_DRAMC_F26M_CG 52 #define INFRACFG_AO_IRTX_CG 53 #define INFRACFG_AO_DISP_PWM_CG 54 #define INFRACFG_AO_DPMAIF_CK 55 #define INFRACFG_AO_AUDIO_26M_BCLK_CK 56 #define INFRACFG_AO_SPI1_CG 57 #define INFRACFG_AO_I2C4_CG 58 #define INFRACFG_AO_MODEM_TEMP_SHARE_CG 59 #define INFRACFG_AO_SPI2_CG 60 #define INFRACFG_AO_SPI3_CG 61 #define INFRACFG_AO_UNIPRO_SCK_CG 62 #define INFRACFG_AO_UNIPRO_TICK_CG 63 #define INFRACFG_AO_UFS_MP_SAP_BCLK_CG 64 #define INFRACFG_AO_MD32_BCLK_CG 65 #define INFRACFG_AO_SSPM_CG 66 #define INFRACFG_AO_UNIPRO_MBIST_CG 67 #define INFRACFG_AO_SSPM_BUS_HCLK_CG 68 #define INFRACFG_AO_I2C5_CG 69 #define INFRACFG_AO_I2C5_ARBITER_CG 70 #define INFRACFG_AO_I2C5_IMM_CG 71 #define INFRACFG_AO_I2C1_ARBITER_CG 72 #define INFRACFG_AO_I2C1_IMM_CG 73 #define INFRACFG_AO_I2C2_ARBITER_CG 74 #define INFRACFG_AO_I2C2_IMM_CG 75 #define INFRACFG_AO_SPI4_CG 76 #define INFRACFG_AO_SPI5_CG 77 #define INFRACFG_AO_CQ_DMA_CG 78 #define INFRACFG_AO_UFS_CG 79 #define INFRACFG_AO_AES_UFSFDE_CG 80 #define INFRACFG_AO_UFS_TICK_CG 81 #define INFRACFG_AO_MSDC0_SELF_CG 82 #define INFRACFG_AO_MSDC1_SELF_CG 83 #define INFRACFG_AO_MSDC2_SELF_CG 84 #define INFRACFG_AO_SSPM_26M_SELF_CG 85 #define INFRACFG_AO_SSPM_32K_SELF_CG 86 #define INFRACFG_AO_UFS_AXI_CG 87 #define INFRACFG_AO_I2C6_CG 88 #define INFRACFG_AO_AP_MSDC0_CG 89 #define INFRACFG_AO_MD_MSDC0_CG 90 #define INFRACFG_AO_USB_CG 91 #define INFRACFG_AO_DEVMPU_BCLK_CG 92 #define INFRACFG_AO_CCIF2_AP_CG 93 #define INFRACFG_AO_CCIF2_MD_CG 94 #define INFRACFG_AO_CCIF3_AP_CG 95 #define INFRACFG_AO_CCIF3_MD_CG 96 #define INFRACFG_AO_SEJ_F13M_CG 97 #define INFRACFG_AO_AES_BCLK_CG 98 #define INFRACFG_AO_I2C7_CG 99 #define INFRACFG_AO_I2C8_CG 100 #define INFRACFG_AO_FBIST2FPC_CG 101 #define INFRACFG_AO_CCIF4_AP_CG 102 #define INFRACFG_AO_CCIF4_MD_CG 103 #define INFRACFG_AO_FADSP_CG 104 #define INFRACFG_AO_SSUSB_XHCI_CG 105 #define INFRACFG_AO_SPI6_CG 106 #define INFRACFG_AO_SPI7_CG 107 #define INFRACFG_AO_FADSP_26M_CG 108 #define INFRACFG_AO_FADSP_32K_CG 109 #define INFRACFG_AO_DEVICE_APC_SYNC_CG 110 #define INFRACFG_AO_PWM5_CG 111 #define INFRACFG_AO_MSDCFDE_CG 112 #define INFRACFG_AO_IMP_IIC_CG 113 #define INFRACFG_AO_PWM_BCLK6_CG 114 #define INFRACFG_AO_CLDMA_BCLK_CG 115 #define INFRACFG_AO_BIST2FPC_CG 116 #define INFRACFG_AO_AES_UFS_CG 117 #define INFRACFG_AO_MSDC0_SRCLK_CG 118 #define INFRACFG_AO_MSDC1_SRCLK_CG 119 #define INFRACFG_AO_PWRAP_TMR_FO_CG 120 #define INFRACFG_AO_PWRAP_SPI_FO_CG 121 #define INFRACFG_AO_PWRAP_SYS_FO_CG 123 #define INFRACFG_AO_AES_TOP0_BCLK_CG 124 #define INFRACFG_AO_MCUPM_BCLK_CG 125 #define INFRACFG_AO_NR_CLK 126 /* MFGCFG */ #define MFGCFG_BG3D 1 #define MFGCFG_NR_CLK 2 /* MMSYS_CONFIG */ #define CLK_MM_DISP_MUTEX0 0 #define CLK_MM_APB_BUS 1 #define CLK_MM_DISP_OVL0 2 #define CLK_MM_DISP_RDMA0 3 #define CLK_MM_DISP_OVL0_2L 4 #define CLK_MM_DISP_WDMA0 5 #define CLK_MM_DISP_CCORR1 6 #define CLK_MM_DISP_RSZ0 7 #define CLK_MM_DISP_AAL0 8 #define CLK_MM_DISP_CCORR0 9 #define CLK_MM_DISP_COLOR0 10 #define CLK_MM_SMI_INFRA 11 #define CLK_MM_DISP_DSC_WRAP 12 #define CLK_MM_DISP_GAMMA0 13 #define CLK_MM_DISP_POSTMASK0 14 #define CLK_MM_DISP_SPR0 15 #define CLK_MM_DISP_DITHER0 16 #define CLK_MM_SMI_COMMON 17 #define CLK_MM_DISP_CM0 18 #define CLK_MM_DSI0 19 #define CLK_MM_DISP_FAKE_ENG0 20 #define CLK_MM_DISP_FAKE_ENG1 21 #define CLK_MM_SMI_GALS 22 #define CLK_MM_SMI_IOMMU 23 #define CLK_MM_DSI0_DSI_CK_DOMAIN 24 #define CLK_MM_DISP_26M 25 #define CLK_MM_NR_CLK 26 /* IMGSYS1 */ #define CLK_IMGSYS1_LARB9 0 #define CLK_IMGSYS1_LARB10 1 #define CLK_IMGSYS1_DIP 2 #define CLK_IMGSYS1_GALS 3 #define CLK_IMGSYS1_NR_CLK 4 /* IMGSYS2 */ #define CLK_IMGSYS2_LARB9 0 #define CLK_IMGSYS2_LARB10 1 #define CLK_IMGSYS2_MFB 2 #define CLK_IMGSYS2_WPE 3 #define CLK_IMGSYS2_MSS 4 #define CLK_IMGSYS2_GALS 5 #define CLK_IMGSYS2_NR_CLK 6 /* VDEC_GCON */ #define VDEC_VDEC 1 #define VDEC_LARB1 2 #define VDEC_LAT 3 #define VDEC_GCON_NR_CLK 4 /* VENC_GCON */ #define VENC_GCON_LARB 1 #define VENC_GCON_VENC 2 #define VENC_GCON_JPGENC 3 #define VENC_GCON_GALS 4 #define VENC_GCON_NR_CLK 5 /* AUDIO */ #define AUDIO_AFE 1 #define AUDIO_22M 2 #define AUDIO_24M 3 #define AUDIO_APLL2_TUNER 4 #define AUDIO_APLL_TUNER 5 #define AUDIO_TDM 6 #define AUDIO_ADC 7 #define AUDIO_DAC 8 #define AUDIO_DAC_PREDIS 9 #define AUDIO_TML 10 #define AUDIO_NLE 11 #define AUDIO_I2S1_BCLK_SW 12 #define AUDIO_I2S2_BCLK_SW 13 #define AUDIO_I2S3_BCLK_SW 14 #define AUDIO_I2S4_BCLK_SW 15 #define AUDIO_I2S5_BCLK_SW 16 #define AUDIO_CONN_I2S_ASRC 17 #define AUDIO_GENERAL1_ASRC 18 #define AUDIO_GENERAL2_ASRC 19 #define AUDIO_DAC_HIRES 20 #define AUDIO_PDN_ADDA6_ADC 21 #define AUDIO_ADC_HIRES 22 #define AUDIO_ADC_HIRES_TML 23 #define AUDIO_ADDA6_ADC_HIRES 24 #define AUDIO_3RD_DAC 25 #define AUDIO_3RD_DAC_PREDIS 26 #define AUDIO_3RD_DAC_TML 27 #define AUDIO_3RD_DAC_HIRES 28 #define AUDIO_ETDM_IN1_BCLK_SW 29 #define AUDIO_ETDM_OUT1_BCLK_SW 30 #define AUDIO_NR_CLK 31 /* CAMSYS_MAIN */ #define CLK_CAM_M_LARB13 0 #define CLK_CAM_M_LARB14 1 #define CLK_CAM_M_RESERVED0 2 #define CLK_CAM_M_CAM 3 #define CLK_CAM_M_CAMTG 4 #define CLK_CAM_M_SENINF 5 #define CLK_CAM_M_CAMSV1 6 #define CLK_CAM_M_CAMSV2 7 #define CLK_CAM_M_CAMSV3 8 #define CLK_CAM_M_CCU0 9 #define CLK_CAM_M_CCU1 10 #define CLK_CAM_M_MRAW0 11 #define CLK_CAM_M_RESERVED2 12 #define CLK_CAM_M_FAKE_ENG 13 #define CLK_CAM_M_CCU_GALS 14 #define CLK_CAM_M_CAM2MM_GALS 15 #define CLK_CAM_M_DFP_VAD 16 #define CLK_CAM_M_NR_CLK 17 /* CAMSYS_RAWA */ #define CLK_CAM_RA_LARBX 0 #define CLK_CAM_RA_CAM 1 #define CLK_CAM_RA_CAMTG 2 #define CLK_CAM_RA_NR_CLK 3 /* CAMSYS_RAWB */ #define CLK_CAM_RB_LARBX 0 #define CLK_CAM_RB_CAM 1 #define CLK_CAM_RB_CAMTG 2 #define CLK_CAM_RB_NR_CLK 3 /* IPESYS */ #define CLK_IPE_LARB19 0 #define CLK_IPE_LARB20 1 #define CLK_IPE_SMI_SUBCOM 2 #define CLK_IPE_FD 3 #define CLK_IPE_FE 4 #define CLK_IPE_RSC 5 #define CLK_IPE_DPE 6 #define CLK_IPE_GALS 7 #define CLK_IPE_NR_CLK 8 /* MDPSYS_CONFIG */ #define CLK_MDP_RDMA0 0 #define CLK_MDP_TDSHP0 1 #define CLK_MDP_IMG_DL_ASYNC0 2 #define CLK_MDP_IMG_DL_ASYNC1 3 #define CLK_MDP_RDMA1 4 #define CLK_MDP_TDSHP1 5 #define CLK_MDP_SMI0 6 #define CLK_MDP_APB_BUS 7 #define CLK_MDP_WROT0 8 #define CLK_MDP_RSZ0 9 #define CLK_MDP_HDR0 10 #define CLK_MDP_MUTEX0 11 #define CLK_MDP_WROT1 12 #define CLK_MDP_RSZ1 13 #define CLK_MDP_FAKE_ENG0 14 #define CLK_MDP_AAL0 15 #define CLK_MDP_AAL1 16 #define CLK_MDP_COLOR0 17 #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 18 #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 19 #define CLK_MDP_NR_CLK 20 /* IMP_IIC_WRAP */ #define CLK_IMP_AP_CLOCK_RO_I2C0 0 #define CLK_IMP_AP_CLOCK_RO_I2C1 1 #define CLK_IMP_AP_CLOCK_RO_I2C2 2 #define CLK_IMP_AP_CLOCK_RO_I2C3 3 #define CLK_IMP_AP_CLOCK_RO_I2C4 4 #define CLK_IMP_AP_CLOCK_RO_I2C5 5 #define CLK_IMP_AP_CLOCK_RO_I2C6 6 #define CLK_IMP_AP_CLOCK_RO_I2C7 7 #define CLK_IMP_AP_CLOCK_RO_I2C8 8 #define CLK_IMP_AP_CLOCK_RO_I2C9 9 #define CLK_IMP_NR_CLK 10 /* SCP_SYS */ #define SCP_SYS_MD1 1 #define SCP_SYS_CONN 2 #define SCP_SYS_DIS 3 #define SCP_SYS_MFG1 4 #define SCP_SYS_ISP 5 #define SCP_SYS_VEN 6 #define SCP_SYS_MFG0 7 #define SCP_SYS_CAM 8 #define SCP_SYS_MFG3 9 #define SCP_SYS_MFG2 10 #define SCP_SYS_ISP2 11 #define SCP_SYS_VDE 12 #define SCP_SYS_IPE 13 #define SCP_SYS_CAM_RAWA 14 #define SCP_SYS_CAM_RAWB 15 #define SCP_SYS_CSI 16 #define SCP_NR_SYSS 17 #endif /* _DT_BINDINGS_CLK_MT6781_H */