5142 lines
130 KiB
Plaintext
5142 lines
130 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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/dts-v1/;
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#include <dt-bindings/mmc/mt6781-msdc.h>
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#include <dt-bindings/clock/mt6781-clk.h>
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#include <dt-bindings/iio/mt635x-auxadc.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/memory/mt6781-larb-port.h>
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#include <dt-bindings/mfd/mt6366-irq.h>
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#include <dt-bindings/reset/ti-syscon.h>
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#include <dt-bindings/gce/mt6781-gce.h>
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#include <dt-bindings/phy/phy.h>
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#include <generated/autoconf.h>
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#include <dt-bindings/pinctrl/mt6781-pinfunc.h>
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#include <dt-bindings/soc/mediatek,boot-mode.h>
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/ {
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model = "MT6781";
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compatible = "mediatek,MT6781";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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/* chosen */
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chosen: chosen {
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bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
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vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
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initcall_debug=1 \
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firmware_class.path=/vendor/firmware \
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page_owner=on loop.max_part=7";
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kaslr-seed = <0 0>;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp0 {
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opp-hz = /bits/ 64 <500000000>;
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opp-microvolt = <600000>;
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};
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opp1 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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};
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opp2 {
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opp-hz = /bits/ 64 <875000000>;
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opp-microvolt = <700000>;
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};
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opp3 {
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opp-hz = /bits/ 64 <975000000>;
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opp-microvolt = <725000>;
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};
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opp4 {
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opp-hz = /bits/ 64 <1075000000>;
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opp-microvolt = <750000>;
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};
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opp5 {
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opp-hz = /bits/ 64 <1175000000>;
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opp-microvolt = <775000>;
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};
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opp6 {
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opp-hz = /bits/ 64 <1275000000>;
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opp-microvolt = <800000>;
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};
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opp7 {
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opp-hz = /bits/ 64 <1375000000>;
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opp-microvolt = <825000>;
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};
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opp8 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <856250>;
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};
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opp9 {
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opp-hz = /bits/ 64 <1618000000>;
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opp-microvolt = <875000>;
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};
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opp10 {
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opp-hz = /bits/ 64 <1666000000>;
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opp-microvolt = <900000>;
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};
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opp11 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <925000>;
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};
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opp12 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <950000>;
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};
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opp13 {
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opp-hz = /bits/ 64 <1866000000>;
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opp-microvolt = <981250>;
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};
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opp14 {
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opp-hz = /bits/ 64 <1933000000>;
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opp-microvolt = <1006250>;
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};
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opp15 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <1031250>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp0 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <675000>;
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};
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opp1 {
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opp-hz = /bits/ 64 <835000000>;
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opp-microvolt = <693750>;
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};
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opp2 {
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opp-hz = /bits/ 64 <919000000>;
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opp-microvolt = <718750>;
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};
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opp3 {
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opp-hz = /bits/ 64 <1002000000>;
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opp-microvolt = <743750>;
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};
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opp4 {
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opp-hz = /bits/ 64 <1085000000>;
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opp-microvolt = <775000>;
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};
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opp5 {
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opp-hz = /bits/ 64 <1169000000>;
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opp-microvolt = <800000>;
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};
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opp6 {
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opp-hz = /bits/ 64 <1308000000>;
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opp-microvolt = <843750>;
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};
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opp7 {
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opp-hz = /bits/ 64 <1419000000>;
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opp-microvolt = <875000>;
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};
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opp8 {
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opp-hz = /bits/ 64 <1530000000>;
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opp-microvolt = <912500>;
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};
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opp9 {
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opp-hz = /bits/ 64 <1670000000>;
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opp-microvolt = <956250>;
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};
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opp10 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <981250>;
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};
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opp11 {
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opp-hz = /bits/ 64 <1796000000>;
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opp-microvolt = <1012500>;
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};
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opp12 {
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opp-hz = /bits/ 64 <1860000000>;
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opp-microvolt = <1037500>;
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};
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opp13 {
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opp-hz = /bits/ 64 <1923000000>;
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opp-microvolt = <1062500>;
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};
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opp14 {
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opp-hz = /bits/ 64 <1986000000>;
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opp-microvolt = <1093750>;
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};
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opp15 {
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opp-hz = /bits/ 64 <2050000000>;
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opp-microvolt = <1118750>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@000 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0000>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu1: cpu@001 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0100>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu2: cpu@002 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0200>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu3: cpu@003 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0300>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0400>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0500>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <427>;
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cpu-idle-states = <&cpuoff_l &clusteroff_l
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&mcusysoff &s2idle>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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reg = <0x0600>;
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enable-method = "psci";
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clock-frequency = <2050000000>;
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operating-points-v2 = <&cluster1_opp>;
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dynamic-power-coefficient = <275>;
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capacity-dmips-mhz = <1024>;
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cpu-idle-states = <&cpuoff_b &clusteroff_b
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&mcusysoff &s2idle>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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reg = <0x0700>;
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enable-method = "psci";
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clock-frequency = <2050000000>;
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operating-points-v2 = <&cluster1_opp>;
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dynamic-power-coefficient = <275>;
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capacity-dmips-mhz = <1024>;
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cpu-idle-states = <&cpuoff_b &clusteroff_b
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&mcusysoff &s2idle>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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doe_dvfs_cl0: doe {
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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doe_dvfs_cl1: doe {
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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cpuoff_l: cpuoff_l {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x00010001>;
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local-timer-stop;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <1600>;
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};
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cpuoff_b: cpuoff_b {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x00010001>;
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local-timer-stop;
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entry-latency-us = <50>;
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exit-latency-us = <100>;
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min-residency-us = <1400>;
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};
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clusteroff_l: clusteroff_l {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x01010001>;
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local-timer-stop;
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entry-latency-us = <100>;
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exit-latency-us = <250>;
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min-residency-us = <2100>;
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};
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clusteroff_b: clusteroff_b {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x01010001>;
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local-timer-stop;
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entry-latency-us = <100>;
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exit-latency-us = <250>;
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min-residency-us = <1900>;
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};
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mcusysoff: mcusysoff {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x01010002>;
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local-timer-stop;
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entry-latency-us = <300>;
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exit-latency-us = <1200>;
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min-residency-us = <2600>;
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};
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s2idle: s2idle {
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compatible = "mediatek,idle-state";
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arm,psci-suspend-param = <0x01010100>;
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local-timer-stop;
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entry-latency-us = <500>;
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exit-latency-us = <1400>;
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min-residency-us = <4294967295>;
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};
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};
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};
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mtk_lpm: mtk_lpm {
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compatible = "mediatek,mtk-lpm";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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suspend-method = "s2idle";
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cpupm-method = "mcu";
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irq-remain = <&edge_keypad &edge_mdwdt>,
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<&level_btif_tx &level_btif_rx>;
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resource-ctrl = <&bus26m &infra &syspll>,
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<&dram_s0 &dram_s1>;
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constraints = <&rc_bus26m &rc_syspll &rc_dram>;
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cpupm_sysram: cpupm-sysram@0011b000 {
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compatible = "mediatek,cpupm-sysram";
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reg = <0 0x0011b000 0 0x500>;
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};
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mcusys_ctrl: mcusys-ctrl@0c53a000 {
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compatible = "mediatek,mcusys-ctrl";
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reg = <0 0x0c53a000 0 0x1000>;
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};
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lpm_sysram: lpm_sysram@0011b500 {
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compatible = "mediatek,lpm-sysram";
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reg = <0 0x0011b500 0 0x300>;
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};
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irq-remain-list {
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edge_keypad: edge_keypad {
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target = <&keypad>;
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value = <1 0 0 0x04>;
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};
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edge_mdwdt: edge_mdwdt {
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target = <&mddriver>;
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value = <1 0 0 0x02000000>;
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};
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level_btif_tx: level_btif_tx{
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target = <&btif>;
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value = <0 1 0 0>;
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};
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level_btif_rx: level_btif_rx{
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target = <&btif>;
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value = <0 2 0 0>;
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};
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};
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resource-ctrl-list {
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bus26m: bus26m {
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id = <0x00000000>;
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value = <0>;
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};
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infra: infra {
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id = <0x00000001>;
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value = <0>;
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};
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syspll: syspll {
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id = <0x00000002>;
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value = <0>;
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};
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dram_s0: dram_s0 {
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id = <0x00000003>;
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value = <0>;
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};
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dram_s1: dram_s1 {
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id = <0x00000004>;
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value = <0>;
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};
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};
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constraint-list {
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rc_bus26m: rc_bus26m {
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id = <0x00000000>;
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value = <1>;
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};
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rc_syspll: rc_syspll {
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id = <0x00000001>;
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value = <1>;
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};
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rc_dram: rc_dram {
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id = <0x00000002>;
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value = <1>;
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};
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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dsu-pmu-0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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mcucfg_mp0_counter {
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compatible = "mediatek,mcucfg_mp0_counter";
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reg_mp0_counter_base = <&mcucfg>;
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};
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memory {
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device_type = "memory";
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reg = <0 0x40000000 0 0x3e605000>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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aliases {
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ovl0 = &disp_ovl0;
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ovl3 = &disp_ovl0_2l;
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rdma0 = &disp_rdma0;
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dsi0 = &dsi0;
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ccorr0 = &disp_ccorr0;
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};
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/* Trustonic Mobicore SW IRQ number 96 = 32 + 64 */
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mobicore {
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compatible = "trustonic,mobicore";
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interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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reserve-memory-sspm_share {
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compatible = "mediatek,reserve-memory-sspm_share";
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no-map;
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status = "okay";
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#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
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size = <0 0x110000>; /* 1M + 64K */
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#else
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size = <0 0x510000>; /* 5M + 64K */
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#endif
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alignment = <0 0x10000>;
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alloc-ranges = <0 0x40000000 0 0x60000000>;
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};
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ion-carveout-heap {
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compatible = "mediatek,ion-carveout-heap";
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no-map;
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#ifdef CONFIG_FPGA_EARLY_PORTING
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size = <0 0x5000000>;
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#else
|
|
size = <0 0xc000>;
|
|
#endif
|
|
alignment = <0 0x1000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
reserve-memory-adsp_share {
|
|
compatible = "mediatek,reserve-memory-adsp_share";
|
|
no-map;
|
|
size = <0 0x1000000>;
|
|
alignment = <0 0x1000>;
|
|
alloc-ranges = <0 0x40000000 0 0x40000000>;
|
|
};
|
|
|
|
consys_mem: consys-reserve-memory {
|
|
compatible = "mediatek,consys-reserve-memory";
|
|
no-map;
|
|
size = <0 0x500000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
wifi_mem: wifi-reserve-memory {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
size = <0 0x600000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
reserve-memory-scp_share {
|
|
compatible = "mediatek,reserve-memory-scp_share";
|
|
no-map;
|
|
size = <0 0x00320000>; /*3 MB share mem size */
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x50000000 0 0x40000000>;
|
|
};
|
|
|
|
ssmr_cma_mem: ssmr-reserved-cma_memory {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0 0x10000000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-range = <0 0xc0000000 0 0x10000000>;
|
|
};
|
|
};
|
|
|
|
gic: interrupt-controller {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
#redistributor-regions = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0 0x0c000000 0 0x40000>, // distributor
|
|
<0 0x0c040000 0 0x200000>; // redistributor
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
clkitg: clkitg {
|
|
compatible = "simple-bus";
|
|
};
|
|
|
|
clocks {
|
|
clk_null: clk_null {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
clk26m: clk26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
};
|
|
|
|
clk13m: clk13m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
|
|
clk32k: clk32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
};
|
|
};
|
|
|
|
qos@0011bb80 {
|
|
compatible = "mediatek,qos-2.0";
|
|
reg = <0 0x0011bb80 0 0x80>;
|
|
};
|
|
|
|
chipid@08000000 {
|
|
compatible = "mediatek,chipid";
|
|
reg = <0 0x08000000 0 0x0004>,
|
|
<0 0x08000004 0 0x0004>,
|
|
<0 0x08000008 0 0x0004>,
|
|
<0 0x0800000c 0 0x0004>;
|
|
};
|
|
|
|
topckgen: topckgen@10000000 {
|
|
compatible = "mediatek,topckgen", "syscon";
|
|
reg = <0 0x10000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg_ao: infracfg_ao@10001000 {
|
|
compatible = "mediatek,common-infracfg_ao", "mediatek,infracfg_ao", "syscon";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
|
|
infracfg_rst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
|
|
ti,reset-bits = <
|
|
/* ufs reset */
|
|
0x130 15 0x134 15 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 0: ufshci */
|
|
0x140 7 0x144 7 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 1: unipro */
|
|
0x150 21 0x154 21 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* 2: ufs-crypto */
|
|
>;
|
|
};
|
|
};
|
|
|
|
dcm: dcm@10001000 {
|
|
compatible = "mediatek,mt6781-dcm";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0xc538000 0 0x5000>,
|
|
<0 0xc53a800 0 0x1000>;
|
|
reg-names = "infracfg_ao",
|
|
"mp_cpusys_top",
|
|
"cpccfg_reg";
|
|
};
|
|
|
|
scpsys: scpsys@10001000 {
|
|
compatible = "mediatek,scpsys";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10006000 0 0x1000>,
|
|
<0 0x1020e000 0 0x1000>,
|
|
<0 0x10000000 0 0x1000>,
|
|
<0 0x14002000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mdpsys_config: mdpsys_config@1b000000 {
|
|
compatible = "mediatek,mt6781-mdpsys", "mediatek,mdpsys_config", "syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells=<1>;
|
|
clocks = <&mdpsys_config CLK_MDP_IMG_DL_ASYNC0>,
|
|
<&mdpsys_config CLK_MDP_IMG_DL_ASYNC1>,
|
|
<&mdpsys_config CLK_MDP_IMG_DL_RELAY0_ASYNC0>,
|
|
<&mdpsys_config CLK_MDP_IMG_DL_RELAY1_ASYNC1>,
|
|
<&mdpsys_config CLK_MDP_APB_BUS>;
|
|
clock-names = "MDP_IMG_DL_ASYNC0",
|
|
"MDP_IMG_DL_ASYNC1",
|
|
"MDP_IMG_DL_RELAY0_ASYNC0",
|
|
"MDP_IMG_DL_RELAY1_ASYNC1",
|
|
"MDP_APB_BUS";
|
|
};
|
|
|
|
vdec_gcon: vdec_gcon@1602f000 {
|
|
compatible = "mediatek,vdec_gcon",
|
|
"mediatek,mt6833-vdec_gcon", "syscon";
|
|
reg = <0 0x1602f000 0 0x1000>;
|
|
pwr-regmap = <&sleep>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys: camsys@1a000000 {
|
|
compatible = "mediatek,camsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys_rawa: camsys_rawa@1a04f000 {
|
|
compatible = "mediatek,camsys_rawa", "syscon";
|
|
reg = <0 0x1a04f000 0 0x1000>;
|
|
#clock-cells=<1>;
|
|
};
|
|
|
|
camsys_rawb: camsys_rawb@1a06f000 {
|
|
compatible = "mediatek,camsys_rawb", "syscon";
|
|
reg = <0 0x1a06f000 0 0x1000>;
|
|
#clock-cells=<1>;
|
|
};
|
|
|
|
ipesys: ipesys@1c000000 {
|
|
compatible = "mediatek,ipesys", "syscon";
|
|
reg = <0 0x1c000000 0 0x1000>;
|
|
#clock-cells=<1>;
|
|
};
|
|
|
|
cache_parity {
|
|
compatible = "mediatek,mt6785-cache-parity";
|
|
reg = <0 0x0c530000 0 0x10000>;
|
|
irq_config = <0 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<1 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<2 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<3 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<4 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<5 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<6 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<7 0x8090 0x0000ff00 0x8090 68 0x8090 0x000000ff>,
|
|
<1024 0xc8c0 0x01000000 0xc8c0 12 0xc8c8 0x00000001>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
lastbus@10001000 {
|
|
compatible = "mediatek,lastbus-v1";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10003000 0 0x1000>;
|
|
};
|
|
|
|
scp_infra: scp_infra@10001000 {
|
|
compatible = "mediatek,scpinfra";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
};
|
|
|
|
scp_dvfs {
|
|
compatible = "mediatek,scp_dvfs";
|
|
clocks = <&topckgen TOP_MUX_SCP>,
|
|
<&clk26m>,
|
|
<&topckgen TOP_MAINPLL_D2_D4>,
|
|
<&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MAINPLL_D2_D2>,
|
|
<&topckgen TOP_MAINPLL_D3>,
|
|
<&topckgen TOP_UNIVPLL_D3>;
|
|
clock-names = "clk_mux",
|
|
"clk_pll_0",
|
|
"clk_pll_1",
|
|
"clk_pll_2",
|
|
"clk_pll_3",
|
|
"clk_pll_4",
|
|
"clk_pll_5";
|
|
vsram_chk_gpio = <&pio 200 0x0>;
|
|
|
|
dvfsrc-opp-num = <5>;
|
|
dvfs-opp =
|
|
/* vcore vsram uv rc spm freq mux */
|
|
< 600000 850000 0xff 0x0 0x8 125 0>,
|
|
< 650000 850000 0xff 0x0 0x4 250 2>,
|
|
< 650000 850000 2 0x0 0x4 273 3>,
|
|
< 700000 850000 1 0x1 0x102 330 3>,
|
|
< 800000 900000 0 0x2 0x201 416 5>;
|
|
|
|
/* sshub-vcore-supply = <&mt_pmic_vcore_sshub_buck_reg>;*/
|
|
/* sshub-vsram-supply = <&mt_pmic_vsram_others_sshub_ldo_reg>;*/
|
|
|
|
gpio = <&gpio 1>;
|
|
gpio-feature = "gpio-mode";
|
|
gpio-feature-cfg = <1>;
|
|
gpio-mode-reg = <0x410 0x7 24 1>;
|
|
};
|
|
|
|
iocfg_lt: iocfg_lt@10002000 {
|
|
compatible = "mediatek,iocfg_lt";
|
|
reg = <0 0x10002000 0 0x200>;
|
|
};
|
|
|
|
iocfg_lm: iocfg_lm@10002200 {
|
|
compatible = "mediatek,iocfg_lm";
|
|
reg = <0 0x10002200 0 0x200>;
|
|
};
|
|
|
|
iocfg_lb: iocfg_lb@10002400 {
|
|
compatible = "mediatek,iocfg_lb";
|
|
reg = <0 0x10002400 0 0x200>;
|
|
};
|
|
|
|
iocfg_bl: iocfg_bl@10002600 {
|
|
compatible = "mediatek,iocfg_bl";
|
|
reg = <0 0x10002600 0 0x200>;
|
|
};
|
|
|
|
iocfg_bm: iocfg_bm@10002800 {
|
|
compatible = "mediatek,iocfg_bm";
|
|
reg = <0 0x10002800 0 0x200>;
|
|
};
|
|
|
|
iocfg_rm: iocfg_rm@10002A00 {
|
|
compatible = "mediatek,iocfg_rm";
|
|
reg = <0 0x10002A00 0 0x200>;
|
|
};
|
|
|
|
iocfg_rt: iocfg_rt@10002C00 {
|
|
compatible = "mediatek,iocfg_rt";
|
|
reg = <0 0x10002C00 0 0x200>;
|
|
};
|
|
|
|
iocfg_tl: iocfg_tl@10002E00 {
|
|
compatible = "mediatek,iocfg_tl";
|
|
reg = <0 0x10002E00 0 0x200>;
|
|
};
|
|
|
|
pericfg: pericfg@10003000 {
|
|
compatible = "mediatek,pericfg", "syscon";
|
|
reg = <0 0x10003000 0 0x1000>;
|
|
};
|
|
|
|
efuse_dbg@10004000 {
|
|
compatible = "mediatek,efuse_dbg";
|
|
reg = <0 0x10004000 0 0x1000>;
|
|
};
|
|
|
|
gpio: gpio@10005000 {
|
|
compatible = "mediatek,gpio", "syscon";
|
|
reg = <0 0x10005000 0 0x1000>;
|
|
};
|
|
|
|
udi: udi@10005000 {
|
|
compatible = "mediatek,udi";
|
|
reg = <0 0x10005000 0 0x1000>;
|
|
udi_offset1 = <0x3A0>;
|
|
udi_value1 = <0x44400000>;
|
|
udi_offset2 = <0x3B0>;
|
|
udi_value2 = <0x00000044>;
|
|
ecc_debug = <1>;
|
|
};
|
|
|
|
pio: pinctrl {
|
|
compatible = "mediatek,mt6781-pinctrl";
|
|
reg_bases = <&gpio>,
|
|
<&iocfg_lt>,
|
|
<&iocfg_lm>,
|
|
<&iocfg_lb>,
|
|
<&iocfg_bl>,
|
|
<&iocfg_bm>,
|
|
<&iocfg_rm>,
|
|
<&iocfg_rt>,
|
|
<&iocfg_tl>;
|
|
reg_base_eint = <&eint>;
|
|
pins-are-numbered;
|
|
gpio-controller;
|
|
gpio-ranges = <&pio 0 0 202>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
seninf1@1a004000 {
|
|
compatible = "mediatek,seninf1";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
};
|
|
|
|
seninf2@1a005000 {
|
|
compatible = "mediatek,seninf2";
|
|
reg = <0 0x1a005000 0 0x1000>;
|
|
};
|
|
|
|
seninf3@1a006000 {
|
|
compatible = "mediatek,seninf3";
|
|
reg = <0 0x1a006000 0 0x1000>;
|
|
};
|
|
|
|
seninf4@1a007000 {
|
|
compatible = "mediatek,seninf4";
|
|
reg = <0 0x1a007000 0 0x1000>;
|
|
};
|
|
|
|
seninf5@1a008000 {
|
|
compatible = "mediatek,seninf5";
|
|
reg = <0 0x1a008000 0 0x1000>;
|
|
};
|
|
|
|
seninf6@1a009000 {
|
|
compatible = "mediatek,seninf6";
|
|
reg = <0 0x1a009000 0 0x1000>;
|
|
};
|
|
|
|
seninf7@1a00A000 {
|
|
compatible = "mediatek,seninf7";
|
|
reg = <0 0x1a00A000 0 0x1000>;
|
|
};
|
|
|
|
seninf8@1a00B000 {
|
|
compatible = "mediatek,seninf8";
|
|
reg = <0 0x1a00B000 0 0x1000>;
|
|
};
|
|
|
|
seninf_top@1a004000 {
|
|
compatible = "mediatek,seninf_top";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&scpsys SCP_SYS_CSI>,
|
|
<&camsys CLK_CAM_M_SENINF>,
|
|
<&topckgen TOP_MUX_SENINF>,
|
|
<&topckgen TOP_MUX_SENINF1>,
|
|
<&topckgen TOP_MUX_SENINF2>,
|
|
<&topckgen TOP_MUX_SENINF3>,
|
|
<&topckgen TOP_MUX_CAMTG>,
|
|
<&topckgen TOP_MUX_CAMTG1>,
|
|
<&topckgen TOP_MUX_CAMTG2>,
|
|
<&topckgen TOP_MUX_CAMTG3>,
|
|
<&topckgen TOP_MUX_CAMTG4>,
|
|
<&topckgen TOP_MUX_CAMTG5>,
|
|
<&topckgen TOP_MUX_CAMTG6>,
|
|
<&topckgen TOP_UNIVP_192M_D32>,
|
|
<&topckgen TOP_UNIVP_192M_D16>,
|
|
<&topckgen TOP_UNIVPLL_D3_D32>,
|
|
<&topckgen TOP_UNIVP_192M_D8>,
|
|
<&clk26m>,
|
|
<&topckgen TOP_UNIVP_192M_D4>,
|
|
<&topckgen TOP_UNIVPLL_D3_D8>;
|
|
|
|
clock-names = "SCP_SYS_CAM",
|
|
"SCP_SYS_CSI",
|
|
"CAMSYS_SENINF_CGPDN",
|
|
"TOP_MUX_SENINF",
|
|
"TOP_MUX_SENINF1",
|
|
"TOP_MUX_SENINF2",
|
|
"TOP_MUX_SENINF3",
|
|
"TOP_MUX_CAMTG",
|
|
"TOP_MUX_CAMTG1",
|
|
"TOP_MUX_CAMTG2",
|
|
"TOP_MUX_CAMTG3",
|
|
"TOP_MUX_CAMTG4",
|
|
"TOP_MUX_CAMTG5",
|
|
"TOP_MUX_CAMTG6",
|
|
"TOP_UNIVP_192M_D32",
|
|
"TOP_UNIVP_192M_D16",
|
|
"TOP_UNIVPLL_D3_D32",
|
|
"TOP_UNIVP_192M_D8",
|
|
"TOP_CLK26M",
|
|
"TOP_UNIVP_192M_D4",
|
|
"TOP_UNIVPLL_D3_D8";
|
|
};
|
|
|
|
|
|
kd_camera_hw1:kd_camera_hw1@1a004000 {
|
|
compatible = "mediatek,imgsensor";
|
|
};
|
|
|
|
seninf_n3d_top: seninf_n3d_top@1a004000 {
|
|
compatible = "mediatek,seninf_n3d_top";
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
reg = <0 0x1a004000 0 0x100>,
|
|
<0 0x1a004100 0 0x100>,
|
|
<0 0x1a004200 0 0x100>;
|
|
reg-names = "seninf_top",
|
|
"seninf_n3d_a",
|
|
"seninf_n3d_b";
|
|
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CLK_CAM_M_SENINF>,
|
|
<&camsys CLK_CAM_M_CAMTG>;
|
|
clock-names = "SCP_SYS_CAM",
|
|
"CAMSYS_SENINF_CGPDN",
|
|
"CAMSYS_CAMTG_CGPDN";
|
|
};
|
|
|
|
sleep: sleep@10006000 {
|
|
compatible = "mediatek,sleep";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
};
|
|
|
|
spmtwam: spmtwam@10006000 {
|
|
compatible = "mediatek,spmtwam";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
|
|
spm_twam_con = <0x970>;
|
|
spm_twam_window_len = <0x974>;
|
|
spm_twam_idle_sel = <0x978>;
|
|
spm_irq_mask = <0xb4>;
|
|
spm_irq_sta = <0x128>;
|
|
spm_twam_last_sta0 = <0x1d0>;
|
|
spm_twam_last_sta1 = <0x1d4>;
|
|
spm_twam_last_sta2 = <0x1d8>;
|
|
spm_twam_last_sta3 = <0x1dc>;
|
|
};
|
|
|
|
toprgu:toprgu@10007000 {
|
|
compatible = "mediatek,mt6781-wdt",
|
|
"mediatek,mt6589-wdt",
|
|
"mediatek,toprgu",
|
|
"syscon", "simple-mfd";
|
|
reg = <0 0x10007000 0 0x1000>;
|
|
mediatek,rg_dfd_timeout = <0xa0>;
|
|
#reset-cells = <1>;
|
|
reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x24>;
|
|
mask = <0xf>;
|
|
mode-charger = <BOOT_CHARGER>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_BOOTLOADER>;
|
|
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
|
|
mode-kpoc = <BOOT_KPOC>;
|
|
mode-ddr-reserve = <BOOT_DDR_RSVD>;
|
|
mode-meta = <BOOT_META>;
|
|
mode-rpmbpk = <BOOT_RPMBPK>;
|
|
};
|
|
};
|
|
|
|
apxgpt@10008000 {
|
|
compatible = "mediatek,apxgpt";
|
|
reg = <0 0x10008000 0 0x1000>;
|
|
mediatek,kick_off = <0xb4>;
|
|
};
|
|
|
|
hacc@1000a000 {
|
|
compatible = "mediatek,hacc";
|
|
reg = <0 0x1000a000 0 0x1000>;
|
|
};
|
|
|
|
eint: eint@1000b000 {
|
|
compatible = "mediatek,eint";
|
|
reg = <0 0x1000b000 0 0x1000>;
|
|
};
|
|
|
|
apmixed: apmixed@1000c000 {
|
|
compatible = "mediatek,apmixed", "syscon";
|
|
reg = <0 0x1000c000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
fhctl@1000ce00 {
|
|
compatible = "mediatek,fhctl";
|
|
reg = <0 0x1000ce00 0 0x200>;
|
|
};
|
|
|
|
pwrap: pwrap@1000d000 {
|
|
compatible = "mediatek,mt6781-pwrap";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
reg-names = "pwrap";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk26m>, <&clk26m>;
|
|
clock-names = "spi", "wrap";
|
|
|
|
main_pmic: mt6358-pmic {
|
|
compatible = "mediatek,mt6358-pmic";
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <144 IRQ_TYPE_LEVEL_HIGH 144 0>;
|
|
status = "okay";
|
|
|
|
pmic_oc_debug: pmic-oc-debug {
|
|
compatible = "mediatek,pmic-oc-debug";
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
pwraph: pwraphal@ {
|
|
compatible = "mediatek,pwraph";
|
|
mediatek,pwrap-regmap = <&pwrap>;
|
|
};
|
|
|
|
pwrap_mpu@1000d000 {
|
|
compatible = "mediatek,pwrap_mpu";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
};
|
|
|
|
pwrap_p2p@1005cb000 {
|
|
compatible = "mediatek,pwrap_p2p";
|
|
reg = <0 0x105cb000 0 0x1000>;
|
|
};
|
|
|
|
pwrap_md32@10448000 {
|
|
compatible = "mediatek,pwrap_md32";
|
|
reg = <0 0x10448000 0 0x1000>;
|
|
};
|
|
|
|
|
|
devapc_ao_infra_peri@1000e000 {
|
|
compatible = "mediatek,devapc_ao_infra_peri";
|
|
reg = <0 0x1000e000 0 0x1000>;
|
|
};
|
|
|
|
sleep_reg_md@1000f000 {
|
|
compatible = "mediatek,sleep_reg_md";
|
|
reg = <0 0x1000f000 0 0x1000>;
|
|
};
|
|
|
|
keypad:kp@10010000 {
|
|
compatible = "mediatek,kp";
|
|
reg = <0 0x10010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "kpd";
|
|
};
|
|
|
|
/* Microtrust SW IRQ number 88(120) ~ 93(125) */
|
|
utos {
|
|
compatible = "microtrust,utos";
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
utos_tester {
|
|
compatible = "microtrust,tester-v1";
|
|
};
|
|
|
|
|
|
amms_control {
|
|
compatible = "mediatek,amms";
|
|
interrupts = <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
topmisc@10011000 {
|
|
compatible = "mediatek,topmisc";
|
|
reg = <0 0x10011000 0 0x1000>;
|
|
};
|
|
|
|
dvfsrc: dvfsrc@10012000 {
|
|
compatible = "mediatek,dvfsrc";
|
|
reg = <0 0x10012000 0 0x1000>,
|
|
<0 0x10006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
boot_dramboost: boot_dramboost {
|
|
compatible = "mediatek,dvfsrc-boost";
|
|
boost_opp = <0>;
|
|
};
|
|
|
|
mbist_ao@10013000 {
|
|
compatible = "mediatek,mbist_ao";
|
|
reg = <0 0x10013000 0 0x1000>;
|
|
};
|
|
|
|
apcldmain_ao@10014000 {
|
|
compatible = "mediatek,apcldmain_ao";
|
|
reg = <0 0x10014000 0 0x400>;
|
|
};
|
|
|
|
apcldmaout_ao@10014400 {
|
|
compatible = "mediatek,apcldmaout_ao";
|
|
reg = <0 0x10014400 0 0x400>;
|
|
};
|
|
|
|
apcldmamisc_ao@10014800 {
|
|
compatible = "mediatek,apcldmamisc_ao";
|
|
reg = <0 0x10014800 0 0x400>;
|
|
};
|
|
|
|
apcldmamisc_ao@10014c00 {
|
|
compatible = "mediatek,apcldmamisc_ao";
|
|
reg = <0 0x10014c00 0 0x400>;
|
|
};
|
|
|
|
dpmaif:dpmaif@10014000 {
|
|
compatible = "mediatek,dpmaif";
|
|
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
|
|
<0 0x10014400 0 0x1000>, /*AO_DL*/
|
|
<0 0x1021d000 0 0x1000>, /*PD_UL*/
|
|
<0 0x1021d100 0 0x1000>, /*PD_DL*/
|
|
<0 0x1021d400 0 0x1000>, /*PD_MISC*/
|
|
<0 0x1021c000 0 0x1000>, /*PD_MD_MISC*/
|
|
<0 0x1022e000 0 0x1000>; /*SRAM*/
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; /*GIC Interrupt ID-32*/
|
|
mediatek,dpmaif_capability = <6>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_CLDMA_BCLK_CG>;
|
|
clock-names = "infra-dpmaif-clk";
|
|
};
|
|
|
|
ccifdriver:ccifdriver@10209000 {
|
|
compatible = "mediatek,ccci_ccif";
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
mediatek,sram_size = <512>;
|
|
/*CCIF_IRQ0 164, CCIF_IRQ1 165*/
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_CCIF_AP_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF_MD_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>;
|
|
clock-names = "infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif2-ap",
|
|
"infra-ccif2-md",
|
|
"infra-ccif4-md",
|
|
"infra-ccif5-md";
|
|
};
|
|
|
|
mddriver:mddriver {
|
|
compatible = "mediatek,mddriver";
|
|
mediatek,mdhif_type = <6>; /* bit0~3: CLDMA|CCIF|DPMAIF */
|
|
mediatek,md_id = <0>;
|
|
mediatek,ap_plat_info = <6781>;
|
|
mediatek,md_generation = <6295>;
|
|
mediatek,cldma_capability = <6>;
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, /*MDWDT*/
|
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, /*CCIF0 GIC Interrupt ID 196-32*/
|
|
<GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; /*CCIF0 GIC Interrupt ID 197-32*/
|
|
clocks = <&scpsys SCP_SYS_MD1>;
|
|
clock-names = "scp-sys-md1-main";
|
|
ccci-infracfg = <&infracfg_ao>;
|
|
};
|
|
|
|
radio_md_cfg:radio_md_cfg {
|
|
compatible = "mediatek,radio_md_cfg";
|
|
};
|
|
|
|
ddrphy@10015000 {
|
|
compatible = "mediatek,ddrphy";
|
|
reg = <0 0x10015000 0 0x1000>;
|
|
};
|
|
|
|
aes_top0@10016000 {
|
|
compatible = "mediatek,aes_top0";
|
|
reg = <0 0x10016000 0 0x1000>;
|
|
};
|
|
|
|
sys_timer@10017000 {
|
|
compatible = "mediatek,sys_timer",
|
|
"mediatek,mt6765-timer";
|
|
reg = <0 0x10017000 0 0x1000>;
|
|
reg-names = "sys_timer_base";
|
|
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk13m>;
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
|
|
scp@10500000 {
|
|
compatible = "mediatek,scp";
|
|
status = "okay";
|
|
reg = <0 0x10500000 0 0xc0000>,
|
|
<0 0x105c0000 0 0x3000>,
|
|
<0 0x105c4000 0 0x1000>,
|
|
<0 0x105d4000 0 0x6000>;
|
|
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
|
core_1 = "enable";
|
|
scp_sramSize = <0x000c0000>;
|
|
scp_mpuRegionId = <7>;
|
|
scp_feature_tbl = <0 5>, /* vow */
|
|
<1 356>, /* dsp */
|
|
<2 62>, /* sensor */
|
|
<3 47>, /* mp3 */
|
|
<4 26>, /* flp */
|
|
<5 0>, /* rtos */
|
|
<6 200>, /* speaker */
|
|
<7 0>, /* vcore */
|
|
<8 120>, /* barge in */
|
|
<9 10>, /* vow dump */
|
|
<10 43>, /* vow vendor m */
|
|
<11 43>, /* vow vendor_a */
|
|
<12 22>, /* vow vendor_g */
|
|
<13 200>; /* ultrasound */
|
|
|
|
scp_mem_key = "mediatek,reserve-memory-scp_share";
|
|
scp_mem_tbl = <0 0x49200>, /* vow */
|
|
<1 0x100000>, /* sensor */
|
|
<3 0x001000>, /* flp */
|
|
<4 0x180000>, /* logger */
|
|
<5 0x19000>, /* audio */
|
|
<8 0x4600>, /* barge in */
|
|
<10 0x19000>; /* ultrasound */
|
|
};
|
|
|
|
modem_temp_share@10018000 {
|
|
compatible = "mediatek,modem_temp_share";
|
|
reg = <0 0x10018000 0 0x1000>;
|
|
};
|
|
|
|
devapc_ao_md@10019000 {
|
|
compatible = "mediatek,devapc_ao_md";
|
|
reg = <0 0x10019000 0 0x1000>;
|
|
};
|
|
|
|
security_ao@1001a000 {
|
|
compatible = "mediatek,security_ao";
|
|
reg = <0 0x1001a000 0 0x1000>;
|
|
};
|
|
|
|
topckgen_ao@1001b000 {
|
|
compatible = "mediatek,topckgen_ao";
|
|
reg = <0 0x1001b000 0 0x1000>;
|
|
};
|
|
|
|
devapc_ao_mm@1001c000 {
|
|
compatible = "mediatek,devapc_ao_mm";
|
|
reg = <0 0x1001c000 0 0x1000>;
|
|
};
|
|
|
|
dramc@10220000 {
|
|
compatible = "mediatek,dramc";
|
|
reg = <0 0x10220000 0 0x2000>,
|
|
<0 0x10230000 0 0x2000>,
|
|
<0 0x10224000 0 0x1000>,
|
|
<0 0x10234000 0 0x1000>,
|
|
<0 0x10228000 0 0x2000>,
|
|
<0 0x10238000 0 0x2000>,
|
|
<0 0x10226000 0 0x1000>,
|
|
<0 0x10236000 0 0x1000>;
|
|
};
|
|
|
|
ddrphy@1001e000 {
|
|
compatible = "mediatek,ddrphy";
|
|
reg = <0 0x1001e000 0 0x1000>;
|
|
};
|
|
|
|
iocfg_0@10002000 {
|
|
compatible = "mediatek,iocfg_0";
|
|
reg = <0 0x10002000 0 0x200>;
|
|
};
|
|
|
|
iocfg_1@10002200 {
|
|
compatible = "mediatek,iocfg_1";
|
|
reg = <0 0x10002200 0 0x200>;
|
|
};
|
|
|
|
iocfg_2@10002400 {
|
|
compatible = "mediatek,iocfg_2";
|
|
reg = <0 0x10002400 0 0x200>;
|
|
};
|
|
|
|
iocfg_3@10002600 {
|
|
compatible = "mediatek,iocfg_3";
|
|
reg = <0 0x10002600 0 0x200>;
|
|
};
|
|
|
|
iocfg_4@10002800 {
|
|
compatible = "mediatek,iocfg_4";
|
|
reg = <0 0x10002800 0 0x200>;
|
|
};
|
|
|
|
iocfg_5@10002a00 {
|
|
compatible = "mediatek,iocfg_5";
|
|
reg = <0 0x10002a00 0 0x200>;
|
|
};
|
|
|
|
sys_cirq@10204000 {
|
|
compatible = "mediatek,sys_cirq";
|
|
reg = <0 0x10204000 0 0x1000>;
|
|
};
|
|
|
|
devapc@10207000 {
|
|
compatible = "mediatek,mt6781-devapc";
|
|
reg = <0 0x10207000 0 0x1000>,
|
|
<0 0x1000e000 0 0x1000>,
|
|
<0 0x10033000 0 0x1000>,
|
|
<0 0x0011a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_DEVICE_APC_CG>;
|
|
clock-names = "devapc-infra-clock";
|
|
};
|
|
|
|
hwrng: hwrng {
|
|
compatible = "mediatek,mt67xx-rng";
|
|
};
|
|
|
|
bus_dbg@10208000 {
|
|
compatible = "mediatek,bus_dbg-v2";
|
|
reg = <0 0x10208000 0 0x1000>,
|
|
<0 0x10001000 0 0x1000>;
|
|
mediatek,bus_dbg_con_offset = <0x2fc>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ap_ccif0@10209000 {
|
|
compatible = "mediatek,ap_ccif0";
|
|
reg = <0 0x10209000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif0@1020a000 {
|
|
compatible = "mediatek,md_ccif0";
|
|
reg = <0 0x1020a000 0 0x1000>;
|
|
};
|
|
|
|
ap_ccif1@1020b000 {
|
|
compatible = "mediatek,ap_ccif1";
|
|
reg = <0 0x1020b000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif1@1020c000 {
|
|
compatible = "mediatek,md_ccif1";
|
|
reg = <0 0x1020c000 0 0x1000>;
|
|
};
|
|
|
|
infra_mbist@1020d000 {
|
|
compatible = "mediatek,infra_mbist";
|
|
reg = <0 0x1020d000 0 0x1000>;
|
|
};
|
|
|
|
infracfg@1020e000 {
|
|
compatible = "mediatek,infracfg";
|
|
reg = <0 0x1020e000 0 0x1000>;
|
|
};
|
|
|
|
dxcc_sec@10210000 {
|
|
compatible = "mediatek,dxcc_sec";
|
|
reg = <0 0x10210000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_sram2@10211000 {
|
|
compatible = "mediatek,mcupm_sram2";
|
|
reg = <0 0x10211000 0 0x1000>;
|
|
};
|
|
|
|
cqdma-controller@10212000 {
|
|
compatible = "mediatek,cqdma";
|
|
reg = <0 0x10212000 0 0x80>,
|
|
<0 0x10212100 0 0x80>,
|
|
<0 0x10212200 0 0x80>,
|
|
<0 0x10212300 0 0x80>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
|
|
nr_channel = <4>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_CQ_DMA_CG>;
|
|
clock-names = "cqdma";
|
|
dma-channel-mask = <63>;
|
|
dma-requests = <10>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
mcupm_sram3@10213000 {
|
|
compatible = "mediatek,mcupm_sram3";
|
|
reg = <0 0x10213000 0 0x1000>;
|
|
};
|
|
|
|
sramrom@10214000 {
|
|
compatible = "mediatek,sramrom";
|
|
reg = <0 0x10214000 0 0x1000>;
|
|
};
|
|
|
|
mipi_tx0@10215000 {
|
|
compatible = "mediatek,mipi_tx0";
|
|
reg = <0 0x10215000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_reg@10216000 {
|
|
compatible = "mediatek,mcupm_reg";
|
|
reg = <0 0x10216000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_sram0@10217000 {
|
|
compatible = "mediatek,mcupm_sram0";
|
|
reg = <0 0x10217000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_sram1@10218000 {
|
|
compatible = "mediatek,mcupm_sram1";
|
|
reg = <0 0x10218000 0 0x1000>;
|
|
};
|
|
|
|
emichn: emichn@10225000 {
|
|
compatible = "mediatek,mt6781-emichn",
|
|
"mediatek,common-emichn";
|
|
reg = <0 0x10225000 0 0x1000>,
|
|
<0 0x10235000 0 0x1000>;
|
|
};
|
|
|
|
emicen: emicen@10219000 {
|
|
compatible = "mediatek,mt6781-emicen",
|
|
"mediatek,common-emicen";
|
|
reg = <0 0x10219000 0 0x1000>;
|
|
mediatek,emi-reg = <&emichn>;
|
|
};
|
|
|
|
emiisu {
|
|
compatible = "mediatek,mt6781-emiisu",
|
|
"mediatek,common-emiisu";
|
|
ctrl_intf = <1>;
|
|
};
|
|
|
|
emimpu@1021b000 {
|
|
compatible = "mediatek,mt6781-emimpu",
|
|
"mediatek,common-emimpu";
|
|
reg = <0 0x1021b000 0 0x1000>;
|
|
mediatek,emi-reg = <&emicen>;
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
region_cnt = <32>;
|
|
domain_cnt = <16>;
|
|
addr_align = <16>;
|
|
ap_region = <31>;
|
|
ap_apc = <0 5 5 5 2 0 6 5>,
|
|
<0 0 5 0 0 0 5 5>;
|
|
dump = <0x1f0 0x1f8 0x1fc>;
|
|
clear = <0x160 0xffffffff 16>,
|
|
<0x200 0x00000003 16>,
|
|
<0x1f0 0x80000000 1>;
|
|
clear_md = <0x1fc 0x80000000 1>;
|
|
ctrl_intf = <1>;
|
|
slverr = <0>;
|
|
};
|
|
|
|
device_mpu_low@1021a000 {
|
|
compatible = "mediatek,device_mpu_low";
|
|
reg = <0 0x1021a000 0 0x1000>;
|
|
prot-base = <0x0 0x40000000>;
|
|
prot-size = <0x4 0x00000000>;
|
|
page-size = <0x200000>;
|
|
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dvfsp@10227000 {
|
|
compatible = "mediatek,dvfsp";
|
|
reg = <0 0x10227000 0 0x1000>;
|
|
};
|
|
|
|
dvfsp: dvfsp@0011bc00 {
|
|
compatible = "mediatek,mt6781-dvfsp";
|
|
reg = <0 0x0011bc00 0 0x1400>,
|
|
<0 0x0011bc00 0 0x1400>;
|
|
state = <1>;
|
|
imax_state = <2>;
|
|
change_flag = <0>;
|
|
little-rise-time = <1000>;
|
|
little-down-time = <750>;
|
|
big-rise-time = <1000>;
|
|
big-down-time = <750>;
|
|
L-table = <2000 85 1 1
|
|
1933 81 1 1
|
|
1866 77 1 1
|
|
1800 72 1 1
|
|
1733 68 1 1
|
|
1666 64 2 1
|
|
1618 60 2 1
|
|
1500 57 2 1
|
|
1375 52 2 1
|
|
1275 48 2 1
|
|
1175 44 2 1
|
|
1075 40 2 1
|
|
975 36 2 1
|
|
875 32 2 1
|
|
774 28 4 1
|
|
500 16 4 1 >;
|
|
|
|
B-table = <2050 99 1 1
|
|
1986 95 1 1
|
|
1923 90 1 1
|
|
1860 86 1 1
|
|
1796 82 1 1
|
|
1733 77 1 1
|
|
1670 73 1 1
|
|
1530 66 2 1
|
|
1419 60 2 1
|
|
1308 55 2 1
|
|
1169 48 2 1
|
|
1085 44 2 1
|
|
1002 39 2 1
|
|
919 35 2 1
|
|
835 31 2 1
|
|
774 28 4 1 >;
|
|
|
|
CCI-table = <1400 85 2 1
|
|
1330 79 2 1
|
|
1260 72 2 1
|
|
1190 65 2 1
|
|
1155 62 2 1
|
|
1120 58 2 1
|
|
1050 55 2 1
|
|
980 51 2 1
|
|
927 48 2 1
|
|
875 45 2 1
|
|
822 43 2 1
|
|
752 39 2 1
|
|
682 35 4 1
|
|
612 31 4 1
|
|
560 28 4 1
|
|
500 16 4 1 >;
|
|
};
|
|
|
|
mt_cpufreq: mt_cpufreq {
|
|
compatible = "mediatek,mt-cpufreq";
|
|
proc1-supply = <&mt_pmic_vproc11_buck_reg>;
|
|
proc2-supply = <&mt_pmic_vproc12_buck_reg>;
|
|
sram_proc1-supply = <&mt_pmic_vsram_proc11_ldo_reg>;
|
|
sram_proc2-supply = <&mt_pmic_vsram_proc12_ldo_reg>;
|
|
};
|
|
|
|
mcucfg: mcucfg@0c530000 {
|
|
compatible = "mediatek,mcucfg";
|
|
reg = <0 0x0c530000 0 0x10000>;
|
|
};
|
|
|
|
gce_mbox: gce_mbox@1022c000 {
|
|
compatible = "mediatek,mt6781-gce";
|
|
reg = <0 0x1022c000 0 0x4000>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
#mbox-cells = <3>;
|
|
#gce-event-cells = <1>;
|
|
#gce-subsys-cells = <2>;
|
|
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
|
|
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
|
|
clock-names = "gce", "gce-timer";
|
|
};
|
|
|
|
gce_mbox_sec: gce_mbox_sec@1022c000 {
|
|
compatible = "mediatek,mailbox-gce-sec";
|
|
reg = <0 0x1022c000 0 0x4000>;
|
|
#mbox-cells = <3>;
|
|
mboxes = <&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>;
|
|
clock-names = "gce";
|
|
};
|
|
|
|
cmdq-test {
|
|
compatible = "mediatek,cmdq-test";
|
|
mediatek,gce = <&gce_mbox>;
|
|
mmsys_config = <&mmsys_config>;
|
|
mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
|
|
mboxes = <&gce_mbox 21 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox_sec 11 0 CMDQ_THR_PRIO_1>;
|
|
token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
|
|
token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
|
|
};
|
|
|
|
ap_ccif2@1023c000 {
|
|
compatible = "mediatek,ap_ccif2";
|
|
reg = <0 0x1023c000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif2@1023d000 {
|
|
compatible = "mediatek,md_ccif2";
|
|
reg = <0 0x1023d000 0 0x1000>;
|
|
};
|
|
|
|
ap_ccif3@1023e000 {
|
|
compatible = "mediatek,ap_ccif3";
|
|
reg = <0 0x1023e000 0 0x1000>;
|
|
};
|
|
|
|
goodix_fp: fingerprint {
|
|
compatible = "mediatek,goodix-fp";
|
|
};
|
|
|
|
accdet: accdet {
|
|
compatible = "mediatek,pmic-accdet";
|
|
mediatek,accdet-pmic = <0x66>;
|
|
};
|
|
|
|
irtx_pwm:irtx_pwm {
|
|
compatible = "mediatek,irtx-pwm";
|
|
pwm_ch = <1>;
|
|
pwm_data_invert = <0>;
|
|
};
|
|
|
|
mt6358_gauge {
|
|
compatible = "mediatek,mt6358_gauge";
|
|
bootmode = <&chosen>;
|
|
gauge_name = "gauge";
|
|
alias_name = "MT6358";
|
|
vbif28-supply = <&mt_pmic_vbif28_ldo_reg>;
|
|
};
|
|
|
|
#if (CONFIG_MTK_GAUGE_VERSION == 30)
|
|
#include "mediatek/bat_setting/mt6781_battery_prop.dtsi"
|
|
#endif
|
|
|
|
md_ccif3@1023f000 {
|
|
compatible = "mediatek,md_ccif3";
|
|
reg = <0 0x1023f000 0 0x1000>;
|
|
};
|
|
|
|
ap_ccif4@10211000 {
|
|
compatible = "mediatek,ap_ccif4";
|
|
reg = <0 0x10211000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif4@10213000 {
|
|
compatible = "mediatek,md_ccif4";
|
|
reg = <0 0x10213000 0 0x1000>;
|
|
};
|
|
|
|
sspm@10400000 {
|
|
compatible = "mediatek,sspm";
|
|
reg = <0 0x10400000 0 0x28000>,
|
|
<0 0x10440000 0 0x10000>,
|
|
<0 0x10450000 0 0x100>,
|
|
<0 0x10451000 0 0x4>,
|
|
<0 0x10451004 0 0x4>,
|
|
<0 0x10460000 0 0x100>,
|
|
<0 0x10461000 0 0x4>,
|
|
<0 0x10461004 0 0x4>,
|
|
<0 0x10470000 0 0x100>,
|
|
<0 0x10471000 0 0x4>,
|
|
<0 0x10471004 0 0x4>,
|
|
<0 0x10480000 0 0x100>,
|
|
<0 0x10481000 0 0x4>,
|
|
<0 0x10481004 0 0x4>,
|
|
<0 0x10490000 0 0x100>,
|
|
<0 0x10491000 0 0x4>,
|
|
<0 0x10491004 0 0x4>;
|
|
|
|
reg-names = "sspm_base",
|
|
"cfgreg",
|
|
"mbox0_base",
|
|
"mbox0_set",
|
|
"mbox0_clr",
|
|
"mbox1_base",
|
|
"mbox1_set",
|
|
"mbox1_clr",
|
|
"mbox2_base",
|
|
"mbox2_set",
|
|
"mbox2_clr",
|
|
"mbox3_base",
|
|
"mbox3_set",
|
|
"mbox3_clr",
|
|
"mbox4_base",
|
|
"mbox4_set",
|
|
"mbox4_clr";
|
|
|
|
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "ipc",
|
|
"mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4";
|
|
};
|
|
|
|
adsp_common: adsp_common@10600000 {
|
|
compatible = "mediatek,adsp_common";
|
|
reg = <0 0x10001000 0 0x1000>, /* infracfg_ao */
|
|
<0 0x10003000 0 0x1000>; /* pericfg */
|
|
clocks = <&infracfg_ao INFRACFG_AO_FADSP_26M_CG>, /* subsys_cg */
|
|
<&infracfg_ao INFRACFG_AO_FADSP_32K_CG>, /* subsys_cg */
|
|
<&infracfg_ao INFRACFG_AO_FADSP_CG>, /* subsys_cg */
|
|
<&topckgen TOP_MUX_ADSP>, /* mux */
|
|
<&clk26m>,
|
|
<&topckgen TOP_ADSPPLL_CK>;
|
|
clock-names = "clk_adsp_infra_26m",
|
|
"clk_adsp_infra_32k",
|
|
"clk_adsp_infra",
|
|
"clk_top_adsp_sel",
|
|
"clk_adsp_clk26m",
|
|
"clk_top_adsppll_ck";
|
|
adsp-rsv-ipidma-a = <0x200000>;
|
|
adsp-rsv-logger-a = <0x80000>;
|
|
adsp-rsv-dbg-dump-a = <0x80000>;
|
|
adsp-rsv-core-dump-a = <0x400>;
|
|
adsp-rsv-audio = <0x5c0000>;
|
|
};
|
|
|
|
adsp_core0: adsp_core0@10610000 {
|
|
compatible = "mediatek,adsp_core_0";
|
|
reg = <0 0x10600000 0 0x10000>, /* CFG */
|
|
<0 0x10630000 0 0x9000>, /* ITCM */
|
|
<0 0x10610000 0 0x8000>; /* DTCM */
|
|
system = <0 0x56000000 0 0x700000>;
|
|
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, /* ADSP_WDT0_IRQ_BIT */
|
|
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; /* ADSP_CIRQ_C0_IRQ_BIT */
|
|
};
|
|
|
|
imp_iic_wrap: imp_iic_wrap@11017000 {
|
|
compatible = "mediatek,imp_iic_wrap",
|
|
"mediatek,mt6781-imp_iic_wrap", "syscon";
|
|
reg = <0 0x11017000 0 0x1000>;
|
|
pwr-regmap = <&topckgen>;
|
|
#clock-cells=<1>;
|
|
};
|
|
|
|
auxadc: auxadc@11001000 {
|
|
compatible = "mediatek,mt6768-auxadc";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_AUXADC_CG>;
|
|
clock-names = "main";
|
|
#io-channel-cells = <1>;
|
|
/* Auxadc efuse calibration */
|
|
/* 1. Auxadc cali on/off bit shift */
|
|
mediatek,cali-en-bit = <20>;
|
|
/* 2. Auxadc cali ge bits shift */
|
|
mediatek,cali-ge-bit = <10>;
|
|
/* 3. Auxadc cali oe bits shift */
|
|
mediatek,cali-oe-bit = <0>;
|
|
/* 4. Auxadc cali efuse reg offset */
|
|
mediatek,cali-efuse-reg-offset = <0x1a8>;
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
apdma: dma-controller@10200d80 {
|
|
compatible = "mediatek,mt6577-uart-dma";
|
|
reg = <0 0x10200d80 0 0x80>,
|
|
<0 0x10200e00 0 0x80>,
|
|
<0 0x10200e80 0 0x80>,
|
|
<0 0x10200f00 0 0x80>;
|
|
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "apdma";
|
|
#dma-cells = <1>;
|
|
dma-bits = <34>;
|
|
dma-requests = <4>;
|
|
};
|
|
|
|
apuart0: serial@11002000 {
|
|
compatible = "mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART0_CG>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 0
|
|
&apdma 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
apuart1: serial@11003000 {
|
|
compatible = "mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART1_CG>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 2
|
|
&apdma 3>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
i2c_common: i2c_common {
|
|
compatible = "mediatek,i2c_common";
|
|
dma_support = /bits/ 8 <3>;
|
|
idvfs = /bits/ 8 <1>;
|
|
set_dt_div = /bits/ 8 <1>;
|
|
check_max_freq = /bits/ 8 <1>;
|
|
ver = /bits/ 8 <2>;
|
|
set_ltiming = /bits/ 8 <1>;
|
|
ext_time_config = /bits/ 16 <0x1801>;
|
|
cnt_constraint = /bits/ 8 <1>;
|
|
};
|
|
|
|
i2c0: i2c0@11007000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <0>;
|
|
reg = <0 0x11007000 0 0x1000>,
|
|
<0 0x10200100 0 0x100>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C0>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <144>;
|
|
sda-gpio-id = <145>;
|
|
gpio_start = <0x10002200>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x10>;
|
|
pu_cfg = <0x40>;
|
|
rsel_cfg = <0x60>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
i2c1: i2c1@11008000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <1>;
|
|
reg = <0 0x11008000 0 0x1000>,
|
|
<0 0x10200200 0 0x100>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C1>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <146>;
|
|
sda-gpio-id = <147>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x40>;
|
|
pu_cfg = <0xb0>;
|
|
rsel_cfg = <0xe0>;
|
|
aed = <0x1a>;
|
|
};
|
|
|
|
i2c2: i2c2@11009000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <2>;
|
|
reg = <0 0x11009000 0 0x1000>,
|
|
<0 0x10200300 0 0x180>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C2>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <148>;
|
|
sda-gpio-id = <149>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x40>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xe0>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
i2c3: i2c3@1100f000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <3>;
|
|
reg = <0 0x1100f000 0 0x1000>,
|
|
<0 0x10200480 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C3>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <150>;
|
|
sda-gpio-id = <151>;
|
|
gpio_start = <0x10002000>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x90>;
|
|
rsel_cfg = <0xc0>;
|
|
aed = <0x1a>;
|
|
};
|
|
|
|
i2c4: i2c4@11011000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <4>;
|
|
reg = <0 0x11011000 0 0x1000>,
|
|
<0 0x10200580 0 0x180>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C4>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <152>;
|
|
sda-gpio-id = <153>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x40>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xe0>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
i2c5: i2c5@11016000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <5>;
|
|
reg = <0 0x11016000 0 0x1000>,
|
|
<0 0x10200700 0 0x100>;
|
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C5>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <154>;
|
|
sda-gpio-id = <155>;
|
|
gpio_start = <0x10002000>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x90>;
|
|
rsel_cfg = <0xc0>;
|
|
aed = <0x1a>;
|
|
};
|
|
|
|
i2c6: i2c6@1100d000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <6>;
|
|
reg = <0 0x1100d000 0 0x1000>,
|
|
<0 0x10200800 0 0x100>;
|
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C6>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <156>;
|
|
sda-gpio-id = <157>;
|
|
gpio_start = <0x10002000>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x90>;
|
|
rsel_cfg = <0xc0>;
|
|
aed = <0x1a>;
|
|
};
|
|
|
|
i2c7: i2c7@11004000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <7>;
|
|
reg = <0 0x11004000 0 0x1000>,
|
|
<0 0x10200900 0 0x180>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C7>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <158>;
|
|
sda-gpio-id = <159>;
|
|
gpio_start = <0x10002200>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x10>;
|
|
pu_cfg = <0x40>;
|
|
rsel_cfg = <0x60>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
i2c8: i2c8@11005000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <8>;
|
|
reg = <0 0x11005000 0 0x1000>,
|
|
<0 0x10200a80 0 0x180>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C8>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <160>;
|
|
sda-gpio-id = <161>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x40>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xe0>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
i2c9: i2c9@11019000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <9>;
|
|
reg = <0 0x11019000 0 0x1000>,
|
|
<0 0x10200c00 0 0x180>;
|
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&imp_iic_wrap CLK_IMP_AP_CLOCK_RO_I2C9>,
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <162>;
|
|
sda-gpio-id = <163>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x40>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xe0>;
|
|
aed = <0x1a>;
|
|
apdma_size = <255>;
|
|
};
|
|
|
|
pwm@11006000 {
|
|
compatible = "mediatek,pwm";
|
|
reg = <0 0x11006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_PWM1_CG>,
|
|
<&infracfg_ao INFRACFG_AO_PWM2_CG>,
|
|
<&infracfg_ao INFRACFG_AO_PWM3_CG>,
|
|
<&infracfg_ao INFRACFG_AO_PWM_HCLK_CG>,
|
|
<&infracfg_ao INFRACFG_AO_PWM_CG>;
|
|
|
|
clock-names = "PWM1-main",
|
|
"PWM2-main",
|
|
"PWM3-main",
|
|
"PWM-HCLK-main",
|
|
"PWM-main";
|
|
};
|
|
|
|
spi0: spi0@1100a000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI0_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
wifi: wifi@18000000 {
|
|
compatible = "mediatek,wifi";
|
|
reg = <0 0x18000000 0 0x100000>;
|
|
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
|
|
memory-region = <&wifi_mem>;
|
|
};
|
|
|
|
therm_ctrl@1100b000 {
|
|
compatible = "mediatek,therm_ctrl";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_THERM_CG>;
|
|
clock-names = "therm-main";
|
|
};
|
|
|
|
tboard_thermistor1: thermal-sensor1 {
|
|
compatible = "mediatek,mtboard-thermistor1";
|
|
io-channels = <&auxadc 0>;
|
|
io-channel-names = "thermistor-ch0";
|
|
};
|
|
|
|
tboard_thermistor2: thermal-sensor2 {
|
|
compatible = "mediatek,mtboard-thermistor2";
|
|
io-channels = <&auxadc 1>;
|
|
io-channel-names = "thermistor-ch1";
|
|
};
|
|
|
|
cpumssv: cpumssv {
|
|
compatible = "mediatek,cpumssv";
|
|
state = <0>;
|
|
};
|
|
|
|
eem_fsm: eem_fsm@1100b000 {
|
|
compatible = "mediatek,eem_fsm";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
eem-status = <1>;
|
|
eem-initmon-little = <0xf>;
|
|
eem-initmon-big = <0xf>;
|
|
eem-initmon-cci = <0xf>;
|
|
eem-initmon-gpu = <0xf>;
|
|
eem-clamp-little = <0>;
|
|
eem-clamp-big = <0>;
|
|
eem-clamp-cci = <0>;
|
|
eem-clamp-gpu = <0>;
|
|
eem-offset-little = <0xff>;
|
|
eem-offset-big = <0xff>;
|
|
eem-offset-cci = <0xff>;
|
|
eem-offset-gpu = <0xff>;
|
|
};
|
|
|
|
bt: bt@00000000 {
|
|
compatible = "mediatek,bt";
|
|
pm_qos_support = <1>;
|
|
};
|
|
|
|
btif: btif@1100c000 {
|
|
compatible = "mediatek,btif";
|
|
/*btif base*/
|
|
reg = <0 0x1100c000 0 0x1000>,
|
|
/*btif tx dma base*/
|
|
<0 0x10201080 0 0x80>,
|
|
/*btif rx dma base*/
|
|
<0 0x10201100 0 0x80>;
|
|
/*btif irq, IRQS_Sync ID, btif_irq_b*/
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
|
/*btif tx dma irq*/
|
|
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
|
|
/*btif rx dma irq*/
|
|
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_BTIF_CG>,
|
|
/*btif clock*/
|
|
<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
|
|
/*ap dma clock*/
|
|
clock-names = "btifc","apdmac";
|
|
};
|
|
|
|
spi1: spi1@11010000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI1_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi2: spi2@11012000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI2_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi3: spi3@11013000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI3_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi4: spi4@11014000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI4_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi5: spi5@11015000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <1>;
|
|
reg = <0 0x11015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MAINPLL_D5>,
|
|
<&topckgen TOP_MUX_SPI>,
|
|
<&infracfg_ao INFRACFG_AO_SPI5_CG>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
imp_iic@11017000 {
|
|
compatible = "mediatek,imp_iic";
|
|
reg = <0 0x11017000 0 0x1000>;
|
|
};
|
|
|
|
ap_uart2@11018000 {
|
|
compatible = "mediatek,ap_uart2";
|
|
reg = <0 0x11018000 0 0x1000>;
|
|
};
|
|
|
|
usb1p@11200000 {
|
|
compatible = "mediatek,usb1p";
|
|
reg = <0 0x11200000 0 0x10000>;
|
|
};
|
|
|
|
audio: audio@11210000 {
|
|
compatible = "mediatek,audio", "syscon";
|
|
reg = <0 0x11210000 0 0x2000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
afe: mt6781-afe-pcm@11210000 {
|
|
compatible = "mediatek,mt6781-sound";
|
|
reg = <0 0x11210000 0 0x2000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
topckgen = <&topckgen>;
|
|
apmixed = <&apmixed>;
|
|
infracfg_ao = <&infracfg_ao>;
|
|
|
|
clocks = <&audio AUDIO_AFE>,
|
|
<&audio AUDIO_DAC>,
|
|
<&audio AUDIO_DAC_PREDIS>,
|
|
<&audio AUDIO_ADC>,
|
|
<&audio AUDIO_PDN_ADDA6_ADC>,
|
|
<&audio AUDIO_22M>,
|
|
<&audio AUDIO_24M>,
|
|
<&audio AUDIO_APLL_TUNER>,
|
|
<&audio AUDIO_APLL2_TUNER>,
|
|
<&audio AUDIO_TDM>,
|
|
<&audio AUDIO_TML>,
|
|
<&audio AUDIO_NLE>,
|
|
<&audio AUDIO_DAC_HIRES>,
|
|
<&audio AUDIO_ADC_HIRES>,
|
|
<&audio AUDIO_ADC_HIRES_TML>,
|
|
<&audio AUDIO_ADDA6_ADC_HIRES>,
|
|
<&audio AUDIO_3RD_DAC>,
|
|
<&audio AUDIO_3RD_DAC_PREDIS>,
|
|
<&audio AUDIO_3RD_DAC_TML>,
|
|
<&audio AUDIO_3RD_DAC_HIRES>,
|
|
<&infracfg_ao INFRACFG_AO_AUDIO_CG>,
|
|
<&infracfg_ao INFRACFG_AO_AUDIO_26M_BCLK_CK>,
|
|
<&topckgen TOP_MUX_AUDIO>,
|
|
<&topckgen TOP_MUX_AUD_INTBUS>,
|
|
<&topckgen TOP_MAINPLL_D2_D4>,
|
|
<&topckgen TOP_MUX_AUD_1>,
|
|
<&topckgen TOP_APLL1_CK>,
|
|
<&topckgen TOP_MUX_AUD_2>,
|
|
<&topckgen TOP_APLL2_CK>,
|
|
<&topckgen TOP_MUX_AUD_ENG1>,
|
|
<&topckgen TOP_APLL1_D8>,
|
|
<&topckgen TOP_MUX_AUD_ENG2>,
|
|
<&topckgen TOP_APLL2_D8>,
|
|
<&topckgen TOP_I2S0_M_SEL>,
|
|
<&topckgen TOP_I2S1_M_SEL>,
|
|
<&topckgen TOP_I2S2_M_SEL>,
|
|
<&topckgen TOP_I2S3_M_SEL>,
|
|
<&topckgen TOP_I2S4_M_SEL>,
|
|
<&topckgen TOP_I2S5_M_SEL>,
|
|
<&topckgen TOP_APLL12_DIV0>,
|
|
<&topckgen TOP_APLL12_DIV1>,
|
|
<&topckgen TOP_APLL12_DIV2>,
|
|
<&topckgen TOP_APLL12_DIV3>,
|
|
<&topckgen TOP_APLL12_DIV4>,
|
|
<&topckgen TOP_APLL12_DIVB>,
|
|
<&topckgen TOP_APLL12_DIV5>,
|
|
<&topckgen TOP_MUX_AUDIO_H>,
|
|
<&clk26m>;
|
|
|
|
clock-names = "aud_afe_clk",
|
|
"aud_dac_clk",
|
|
"aud_dac_predis_clk",
|
|
"aud_adc_clk",
|
|
"aud_adda6_adc_clk",
|
|
"aud_apll22m_clk",
|
|
"aud_apll24m_clk",
|
|
"aud_apll1_tuner_clk",
|
|
"aud_apll2_tuner_clk",
|
|
"aud_tdm_clk",
|
|
"aud_tml_clk",
|
|
"aud_nle",
|
|
"aud_dac_hires_clk",
|
|
"aud_adc_hires_clk",
|
|
"aud_adc_hires_tml",
|
|
"aud_adda6_adc_hires_clk",
|
|
"aud_3rd_dac_clk",
|
|
"aud_3rd_dac_predis_clk",
|
|
"aud_3rd_dac_tml",
|
|
"aud_3rd_dac_hires_clk",
|
|
"aud_infra_clk",
|
|
"mtkaif_26m_clk",
|
|
"top_mux_audio",
|
|
"top_mux_audio_int",
|
|
"top_mainpll_d2_d4",
|
|
"top_mux_aud_1",
|
|
"top_apll1_ck",
|
|
"top_mux_aud_2",
|
|
"top_apll2_ck",
|
|
"top_mux_aud_eng1",
|
|
"top_apll1_d8",
|
|
"top_mux_aud_eng2",
|
|
"top_apll2_d8",
|
|
"top_i2s0_m_sel",
|
|
"top_i2s1_m_sel",
|
|
"top_i2s2_m_sel",
|
|
"top_i2s3_m_sel",
|
|
"top_i2s4_m_sel",
|
|
"top_i2s5_m_sel",
|
|
"top_apll12_div0",
|
|
"top_apll12_div1",
|
|
"top_apll12_div2",
|
|
"top_apll12_div3",
|
|
"top_apll12_div4",
|
|
"top_apll12_divb",
|
|
"top_apll12_div5",
|
|
"top_mux_audio_h",
|
|
"top_clk26m_clk";
|
|
|
|
pinctrl-names = "aud_clk_mosi_off",
|
|
"aud_clk_mosi_on",
|
|
"aud_dat_mosi_off",
|
|
"aud_dat_mosi_on",
|
|
"aud_dat_miso0_off",
|
|
"aud_dat_miso0_on",
|
|
"aud_dat_miso1_off",
|
|
"aud_dat_miso1_on",
|
|
"vow_dat_miso_off",
|
|
"vow_dat_miso_on",
|
|
"vow_clk_miso_off",
|
|
"vow_clk_miso_on",
|
|
"aud_gpio_i2s0_off",
|
|
"aud_gpio_i2s0_on",
|
|
"aud_gpio_i2s1_off",
|
|
"aud_gpio_i2s1_on",
|
|
"aud_gpio_i2s2_off",
|
|
"aud_gpio_i2s2_on",
|
|
"aud_gpio_i2s3_off",
|
|
"aud_gpio_i2s3_on";
|
|
|
|
pinctrl-0 = <&aud_clk_mosi_off>;
|
|
pinctrl-1 = <&aud_clk_mosi_on>;
|
|
pinctrl-2 = <&aud_dat_mosi_off>;
|
|
pinctrl-3 = <&aud_dat_mosi_on>;
|
|
pinctrl-4 = <&aud_dat_miso0_off>;
|
|
pinctrl-5 = <&aud_dat_miso0_on>;
|
|
pinctrl-6 = <&aud_dat_miso1_off>;
|
|
pinctrl-7 = <&aud_dat_miso1_on>;
|
|
pinctrl-8 = <&vow_dat_miso_off>;
|
|
pinctrl-9 = <&vow_dat_miso_on>;
|
|
pinctrl-10 = <&vow_clk_miso_off>;
|
|
pinctrl-11 = <&vow_clk_miso_on>;
|
|
pinctrl-12 = <&aud_gpio_i2s0_off>;
|
|
pinctrl-13 = <&aud_gpio_i2s0_on>;
|
|
pinctrl-14 = <&aud_gpio_i2s1_off>;
|
|
pinctrl-15 = <&aud_gpio_i2s1_on>;
|
|
pinctrl-16 = <&aud_gpio_i2s2_off>;
|
|
pinctrl-17 = <&aud_gpio_i2s2_on>;
|
|
pinctrl-18 = <&aud_gpio_i2s3_off>;
|
|
pinctrl-19 = <&aud_gpio_i2s3_on>;
|
|
};
|
|
|
|
mt6366_snd: mt6366_snd {
|
|
compatible = "mediatek,mt6366-sound";
|
|
mediatek,pwrap-regmap = <&pwrap>;
|
|
};
|
|
|
|
sound: sound {
|
|
compatible = "mediatek,mt6781-mt6366-sound";
|
|
mediatek,audio-codec = <&mt6366_snd>;
|
|
mediatek,platform = <&afe>;
|
|
mediatek,snd_audio_dsp = <&snd_audio_dsp>;
|
|
mtk_spk_i2s_out = <3>;
|
|
mtk_spk_i2s_in = <0>;
|
|
/* mtk_spk_i2s_mck = <3>; */
|
|
mediatek,speaker-codec {
|
|
sound-dai = <&speaker_amp>;
|
|
};
|
|
};
|
|
|
|
snd_scp_ultra: snd_scp_ultra {
|
|
compatible = "mediatek,snd_scp_ultra";
|
|
scp_ultra_dl_memif_id = <0x7>;
|
|
scp_ultra_ul_memif_id = <0xe>;
|
|
};
|
|
|
|
audio_sram@11212000 {
|
|
compatible = "mediatek,audio_sram";
|
|
reg = <0 0x11212000 0 0xd000>;
|
|
prefer_mode = <0>;
|
|
mode_size = <0x9c00 0xd000>;
|
|
block_size = <0x1000>;
|
|
};
|
|
|
|
btcvsd_snd: mtk-btcvsd-snd@18050000 {
|
|
compatible = "mediatek,mtk-btcvsd-snd";
|
|
reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
|
|
<0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
|
|
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
/*INFRA MISC, conn_bt_cvsd_mask*/
|
|
/*cvsd_mcu_read, write, packet_indicator*/
|
|
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
|
|
disable_write_silence = <1>;
|
|
};
|
|
|
|
mt_soc_playback_offload {
|
|
compatible = "mediatek,mt_soc_offload_common";
|
|
};
|
|
|
|
/* feature : $enable $dl_mem $ul_mem $ref_mem $size */
|
|
snd_audio_dsp: snd_audio_dsp {
|
|
compatible = "mediatek,snd_audio_dsp";
|
|
mtk_dsp_voip = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk_dsp_primary = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk_dsp_offload = <0x0 0xffffffff 0xffffffff 0xffffffff 0x400000>;
|
|
mtk_dsp_deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
|
|
mtk_dsp_playback = <0x1 0x4 0xffffffff 0x13 0x30000>;
|
|
mtk_dsp_music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>;
|
|
mtk_dsp_capture1 = <0x0 0xffffffff 0xc 0x12 0x20000>;
|
|
mtk_dsp_a2dp = <0x0 0xffffffff 0xffffffff 0xffffffff 0x40000>;
|
|
mtk_dsp_dataprovider = <0x0 0xffffffff 0xf 0xffffffff 0x30000>;
|
|
mtk_dsp_call_final = <0x5 0x4 0xf 0x13 0x18000>;
|
|
mtk_dsp_fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>;
|
|
mtk_dsp_ktv = <0x1 0x8 0x11 0xffffffff 0x10000>;
|
|
mtk_dsp_capture_raw = <0x0 0xffffffff 0xffffffff 0xffffffff 0x20000>;
|
|
mtk_dsp_fm = <0x1 0xffffffff 0xf 0xffffffff 0x10000>;
|
|
mtk_dsp_ver = <0x1>;
|
|
swdsp_smartpa_process_enable = <0x5>;
|
|
mtk_dsp_mem_afe = <0x1 0x40000>; /* always enable */
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt6781-mmc";
|
|
reg = <0 0x11230000 0 0x10000>,
|
|
<0 0x11cd0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MUX_MSDC50_0_HCLK>,
|
|
<&infracfg_ao INFRACFG_AO_MSDC0_CG>,
|
|
<&infracfg_ao INFRACFG_AO_MSDC0_SCK_CG>,
|
|
<&infracfg_ao INFRACFG_AO_MSDCFDE_CG>;
|
|
clock-names = "source", "hclk", "source_cg",
|
|
"crypto_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt6781-mmc";
|
|
reg = <0 0x11240000 0 0x10000>,
|
|
<0 0x11c90000 0 0x10000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&topckgen TOP_MUX_MSDC30_1>,
|
|
<&infracfg_ao INFRACFG_AO_MSDC1_CG>,
|
|
<&infracfg_ao INFRACFG_AO_MSDC1_SCK_CG>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
|
|
ufshci:ufshci@11270000 {
|
|
compatible = "mediatek,mt8183-ufshci";
|
|
reg = <0 0x11270000 0 0x2300>;
|
|
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy>;
|
|
|
|
clocks = <&infracfg_ao INFRACFG_AO_UFS_CG>,
|
|
<&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>,
|
|
<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>,
|
|
<&infracfg_ao INFRACFG_AO_AES_UFS_CG>;
|
|
clock-names = "ufs0-clock", "ufs0-unipro-clk", "ufs0-mp-clk",
|
|
"ufs0-aes-clk";
|
|
freq-table-hz = <0 0>, <0 0>, <0 0>,
|
|
<0 0>;
|
|
|
|
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
|
|
vcc-fixed-regulator;
|
|
|
|
resets = <&infracfg_rst 0>, <&infracfg_rst 1>,
|
|
<&infracfg_rst 2>;
|
|
reset-names = "hci_rst", "unipro_rst", "crypto_rst";
|
|
|
|
/* Reference clock control mode */
|
|
/* SW mode: 0, Half-HW mode: 1, HW mode: 2 */
|
|
mediatek,refclk_ctrl = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi0@11c10000 {
|
|
compatible = "mediatek,mipi_rx_ana_csi0";
|
|
reg = <0 0x11c10000 0 0x10000>;
|
|
};
|
|
|
|
mipi_tx0@11c80000 {
|
|
compatible = "mediatek,mipi_tx0";
|
|
reg = <0 0x11c80000 0 0x10000>;
|
|
};
|
|
|
|
msdc1_top@11c90000 {
|
|
compatible = "mediatek,msdc1_top";
|
|
reg = <0 0x11c90000 0 0x10000>;
|
|
};
|
|
|
|
usb_phy@11ca0000 {
|
|
compatible = "mediatek,usb_phy";
|
|
reg = <0 0x11ca0000 0 0x10000>;
|
|
};
|
|
|
|
efuse: efuse@11cb0000 {
|
|
compatible = "mediatek,devinfo";
|
|
reg = <0 0x11cb0000 0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
efuse_segment: segment@78 {
|
|
reg = <0x78 0x4>;
|
|
};
|
|
|
|
u2_phy_data: u2_phy_data {
|
|
reg = <0x1b0 0x4>;
|
|
};
|
|
|
|
};
|
|
|
|
ufsphy: phy@11cc0000 {
|
|
compatible = "mediatek,mt8183-ufsphy";
|
|
reg = <0 0x11cc0000 0 0xc000>;
|
|
#phy-cells = <0>;
|
|
};
|
|
|
|
msdc0_top@11cd0000 {
|
|
compatible = "mediatek,msdc0_top";
|
|
reg = <0 0x11cd0000 0 0x10000>;
|
|
};
|
|
|
|
dbg_cti@0d020000 {
|
|
compatible = "mediatek,dbg_cti";
|
|
reg = <0 0x0d020000 0 0x10000>;
|
|
};
|
|
|
|
dbg_etr@0d030000 {
|
|
compatible = "mediatek,dbg_etr";
|
|
reg = <0 0x0d030000 0 0x10000>;
|
|
};
|
|
|
|
dbg_funnel@0d040000 {
|
|
compatible = "mediatek,dbg_funnel";
|
|
reg = <0 0x0d040000 0 0x10000>;
|
|
};
|
|
|
|
dbg_dem@0d0a0000 {
|
|
compatible = "mediatek,dbg_dem";
|
|
reg = <0 0x0d0a0000 0 0x10000>;
|
|
};
|
|
|
|
dbg_mdsys1@0d0c0000 {
|
|
compatible = "mediatek,dbg_mdsys1";
|
|
reg = <0 0x0d0c0000 0 0x40000>;
|
|
};
|
|
|
|
usb: usb0@11200000 {
|
|
compatible = "mediatek,mt6781-usb20";
|
|
reg = <0 0x11200000 0 0x10000>,
|
|
<0 0x11ca0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_ICUSB_CG>,
|
|
<&topckgen TOP_MUX_USB_TOP>,
|
|
<&topckgen TOP_UNIVPLL_D5_D2>;
|
|
clock-names = "usb0",
|
|
"usb0_clk_top_sel",
|
|
"usb0_clk_univpll5_d2";
|
|
mode = <2>;
|
|
multipoint = <1>;
|
|
num_eps = <16>;
|
|
pericfg= <&pericfg>;
|
|
interrupt-names = "mc";
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
dr_mode = "otg";
|
|
usb-role-switch;
|
|
};
|
|
|
|
u2phy0: usb-phy@11210000 {
|
|
compatible = "mediatek,generic-tphy-v1";
|
|
reg = <0 0x11ca0000 0 0x0300>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "okay";
|
|
u2port0: usb-phy@11210000 {
|
|
reg = <0 0x11ca0300 0 0x100>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
mediatek,rx-sqth = <2>;
|
|
mediatek,fsrxlvl = <1>;
|
|
nvmem-cells = <&u2_phy_data>;
|
|
nvmem-cell-names = "intr_cal";
|
|
nvmem-cell-masks = <0x1f>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
infra_dbgsystop_cpu0@0e000000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu0";
|
|
reg = <0 0x0e000000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu1@0e100000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu1";
|
|
reg = <0 0x0e100000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu2@0e200000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu2";
|
|
reg = <0 0x0e200000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu3@0e300000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu3";
|
|
reg = <0 0x0e300000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu4@0e400000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu4";
|
|
reg = <0 0x0e400000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu5@0e500000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu5";
|
|
reg = <0 0x0e500000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu6@0e600000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu6";
|
|
reg = <0 0x0e600000 0 0x100000>;
|
|
};
|
|
|
|
infra_dbgsystop_cpu7@0e700000 {
|
|
compatible = "mediatek,infra_dbgsystop_cpu7";
|
|
reg = <0 0x0e700000 0 0x100000>;
|
|
};
|
|
|
|
mali: mali@13000000 {
|
|
compatible = "mediatek,mali", "arm,mali-valhall";
|
|
reg = <0 0x13000000 0 0x4000>;
|
|
interrupts =
|
|
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names =
|
|
"GPU",
|
|
"MMU",
|
|
"JOB",
|
|
"EVENT",
|
|
"PWR";
|
|
ged-supply = <&ged>;
|
|
};
|
|
|
|
gpufreq: gpufreq {
|
|
compatible = "mediatek,gpufreq";
|
|
clocks =
|
|
<&topckgen TOP_MUX_MFG>,
|
|
<&topckgen TOP_MFGPLL_CK>,
|
|
<&topckgen TOP_MAINPLL_D5>,
|
|
<&mfgcfg MFGCFG_BG3D>,
|
|
<&scpsys SCP_SYS_MFG0>,
|
|
<&scpsys SCP_SYS_MFG1>,
|
|
<&scpsys SCP_SYS_MFG2>,
|
|
<&scpsys SCP_SYS_MFG3>;
|
|
clock-names =
|
|
"clk_mux", /* switch main/sub */
|
|
"clk_main_parent", /* main pll freq */
|
|
"clk_sub_parent", /* default 218.4 MHz */
|
|
"subsys_mfg_cg",
|
|
"mtcmos_mfg_async", /* ASYNC MFG0 */
|
|
"mtcmos_mfg", /* MFG_TOP MFG1 */
|
|
"mtcmos_mfg_core0", /* Shader Stack0 MFG2*/
|
|
"mtcmos_mfg_core1"; /* Shader Stack2 MFG3*/
|
|
#ifndef CONFIG_FPGA_EARLY_PORTING
|
|
_vgpu-supply = <&mt_pmic_vgpu_buck_reg>;
|
|
_vsram_gpu-supply = <&mt_pmic_vsram_gpu_ldo_reg>;
|
|
#endif
|
|
};
|
|
|
|
ged: ged {
|
|
compatible = "mediatek,ged";
|
|
gpufreq-supply = <&gpufreq>;
|
|
};
|
|
|
|
dfd: dfd {
|
|
compatible = "mediatek,dfd";
|
|
mediatek,enabled = <1>;
|
|
mediatek,chain_length = <0xa7f8>;
|
|
mediatek,rg_dfd_timeout = <0xa0>;
|
|
|
|
mediatek,check_dfd_support = <1>;
|
|
mediatek,dfd_infra_base = <0x390>;
|
|
mediatek,dfd_ap_addr_offset = <24>;
|
|
mediatek,dfd_latch_offset = <0x48>;
|
|
};
|
|
|
|
dfd_cache: dfd_cache {
|
|
compatible = "mediatek,dfd_cache";
|
|
mediatek,enabled = <0>;
|
|
mediatek,l2c_trigger = <0>;
|
|
mediatek,rg_dfd_timeout = <0x3e80>;
|
|
};
|
|
|
|
g3d_secure_reg@13fbc000 {
|
|
compatible = "mediatek,g3d_secure_reg";
|
|
reg = <0 0x13fbc000 0 0x1000>;
|
|
};
|
|
|
|
g3d_testbench@13fbd000 {
|
|
compatible = "mediatek,g3d_testbench", "syscon";
|
|
reg = <0 0x13fbd000 0 0x1000>;
|
|
};
|
|
|
|
mfgcfg: mfgcfg@13fbf000 {
|
|
compatible = "mediatek,mfgcfg",
|
|
"mediatek,mt6781-mfgsys", "syscon",
|
|
"mediatek,g3d_config";
|
|
reg = <0 0x13fbf000 0 0x1000>;
|
|
pwr-regmap = <&sleep>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mmsys_config: syson@14000000 {
|
|
compatible = "mediatek,mmsys_config",
|
|
"mediatek,mt6781-mmsys_config", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
pwr-regmap = <&sleep>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
disp_pwm: disp_pwm0@1100e000 {
|
|
compatible = "mediatek,disp_pwm0",
|
|
"mediatek,mt6781-disp-pwm";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <2>;
|
|
pwm_src_base = <&sleep>;
|
|
pwm_src_addr = <0x420>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_DISP_PWM_CG>,
|
|
<&topckgen TOP_MUX_DISP_PWM>,
|
|
<&topckgen TOP_OSC_D8>;
|
|
clock-names = "main", "mm", "pwm_src";
|
|
};
|
|
|
|
mtkfb: mtkfb@0 {
|
|
compatible = "mediatek,mtkfb";
|
|
};
|
|
|
|
dispsys_config: dispsys_config@14000000 {
|
|
compatible = "mediatek,dispsys_config",
|
|
"syscon",
|
|
"mediatek,mt6781-mmsys";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE0>,
|
|
<&smi_larb1 M4U_PORT_L1_DISP_FAKE1>;
|
|
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys_config CLK_MM_DISP_26M>,
|
|
<&mmsys_config CLK_MM_APB_BUS>,
|
|
<&mmsys_config CLK_MM_DISP_MUTEX0>;
|
|
clock-num = <4>;
|
|
|
|
/* define threads, see mt6781-gce.h */
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 5 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 2 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
<&gce_mbox 1 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_6>,
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
|
|
<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 6 0 CMDQ_THR_PRIO_3>,
|
|
<&gce_mbox_sec 8 0 CMDQ_THR_PRIO_3>,
|
|
<&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>,
|
|
<&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>;
|
|
#else
|
|
<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 6 0 CMDQ_THR_PRIO_3>;
|
|
#endif
|
|
|
|
gce-client-names = "CLIENT_CFG0",
|
|
"CLIENT_CFG1",
|
|
"CLIENT_CFG2",
|
|
"CLIENT_TRIG_LOOP0",
|
|
"CLIENT_SODI_LOOP0",
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
|
|
"CLIENT_SUB_CFG0",
|
|
"CLIENT_DSI_CFG0",
|
|
"CLIENT_SEC_CFG0",
|
|
"CLIENT_SEC_CFG1",
|
|
"CLIENT_SEC_CFG2";
|
|
#else
|
|
"CLIENT_SUB_CFG0",
|
|
"CLIENT_DSI_CFG0";
|
|
#endif
|
|
/* define subsys, see mt6781-gce.h */
|
|
gce-subsys = <&gce_mbox 0x14000000 SUBSYS_1400XXXX>,
|
|
<&gce_mbox 0x14010000 SUBSYS_1401XXXX>,
|
|
<&gce_mbox 0x14020000 SUBSYS_1402XXXX>;
|
|
|
|
/* define subsys, see mt6781-gce.h */
|
|
gce-event-names = "disp_mutex0_eof",
|
|
"disp_token_stream_dirty0",
|
|
"disp_token_sodi0",
|
|
"disp_wait_dsi0_te",
|
|
"disp_token_stream_eof0",
|
|
"disp_dsi0_eof",
|
|
"disp_token_esd_eof0",
|
|
"disp_rdma0_eof0",
|
|
"disp_wdma0_eof0",
|
|
"disp_token_stream_block0",
|
|
"disp_token_cabc_eof0",
|
|
"disp_wdma0_eof2",
|
|
"disp_dsi0_sof0";
|
|
|
|
gce-events =
|
|
<&gce_mbox CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_CONFIG_DIRTY>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_SODI>,
|
|
<&gce_mbox CMDQ_EVENT_DSI0_TE_ENG_EVENT>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_STREAM_EOF>,
|
|
<&gce_mbox CMDQ_EVENT_DSI0_FRAME_DONE>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_ESD_EOF>,
|
|
<&gce_mbox CMDQ_EVENT_DISP_RDMA0_FRAME_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_STREAM_BLOCK>,
|
|
<&gce_mbox CMDQ_SYNC_TOKEN_CABC_EOF>,
|
|
<&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_DSI0_SOF>;
|
|
|
|
helper-name = "MTK_DRM_OPT_STAGE",
|
|
"MTK_DRM_OPT_USE_CMDQ",
|
|
"MTK_DRM_OPT_USE_M4U",
|
|
"MTK_DRM_OPT_SODI_SUPPORT",
|
|
"MTK_DRM_OPT_IDLE_MGR",
|
|
"MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE",
|
|
"MTK_DRM_OPT_IDLEMGR_BY_REPAINT",
|
|
"MTK_DRM_OPT_IDLEMGR_ENTER_ULPS",
|
|
"MTK_DRM_OPT_IDLEMGR_KEEP_LP11",
|
|
"MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING",
|
|
"MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ",
|
|
"MTK_DRM_OPT_MET_LOG",
|
|
"MTK_DRM_OPT_USE_PQ",
|
|
"MTK_DRM_OPT_ESD_CHECK_RECOVERY",
|
|
"MTK_DRM_OPT_ESD_CHECK_SWITCH",
|
|
"MTK_DRM_OPT_PRESENT_FENCE",
|
|
"MTK_DRM_OPT_RDMA_UNDERFLOW_AEE",
|
|
"MTK_DRM_OPT_DSI_UNDERRUN_AEE",
|
|
"MTK_DRM_OPT_HRT",
|
|
"MTK_DRM_OPT_HRT_MODE",
|
|
"MTK_DRM_OPT_DELAYED_TRIGGER",
|
|
"MTK_DRM_OPT_OVL_EXT_LAYER",
|
|
"MTK_DRM_OPT_AOD",
|
|
"MTK_DRM_OPT_RPO",
|
|
"MTK_DRM_OPT_DUAL_PIPE",
|
|
"MTK_DRM_OPT_DC_BY_HRT",
|
|
"MTK_DRM_OPT_OVL_WCG",
|
|
"MTK_DRM_OPT_OVL_SBCH",
|
|
"MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK",
|
|
"MTK_DRM_OPT_MET",
|
|
"MTK_DRM_OPT_REG_PARSER_RAW_DUMP",
|
|
"MTK_DRM_OPT_VP_PQ",
|
|
"MTK_DRM_OPT_GAME_PQ",
|
|
"MTK_DRM_OPT_MMPATH",
|
|
"MTK_DRM_OPT_HBM",
|
|
"MTK_DRM_OPT_VDS_PATH_SWITCH",
|
|
"MTK_DRM_OPT_LAYER_REC",
|
|
"MTK_DRM_OPT_CLEAR_LAYER",
|
|
"MTK_DRM_OPT_LFR",
|
|
"MTK_DRM_OPT_DYN_MIPI_CHANGE",
|
|
"MTK_DRM_OPT_SF_PF";
|
|
|
|
helper-value = <0>, /*MTK_DRM_OPT_STAGE*/
|
|
<1>, /*MTK_DRM_OPT_USE_CMDQ*/
|
|
<1>, /*MTK_DRM_OPT_USE_M4U*/
|
|
<0>, /*MTK_DRM_OPT_SODI_SUPPORT*/
|
|
<1>, /*MTK_DRM_OPT_IDLE_MGR*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/
|
|
<1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/
|
|
<0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/
|
|
<0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/
|
|
<1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/
|
|
<0>, /*MTK_DRM_OPT_MET_LOG*/
|
|
<1>, /*MTK_DRM_OPT_USE_PQ*/
|
|
<1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/
|
|
<1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/
|
|
<1>, /*MTK_DRM_OPT_PRESENT_FENCE*/
|
|
<0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/
|
|
<1>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/
|
|
<1>, /*MTK_DRM_OPT_HRT*/
|
|
<1>, /*MTK_DRM_OPT_HRT_MODE*/
|
|
<0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/
|
|
<1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/
|
|
<0>, /*MTK_DRM_OPT_AOD*/
|
|
<1>, /*MTK_DRM_OPT_RPO*/
|
|
<0>, /*MTK_DRM_OPT_DUAL_PIPE*/
|
|
<0>, /*MTK_DRM_OPT_DC_BY_HRT*/
|
|
<0>, /*MTK_DRM_OPT_OVL_WCG*/
|
|
<0>, /*MTK_DRM_OPT_OVL_SBCH*/
|
|
<1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/
|
|
<0>, /*MTK_DRM_OPT_MET*/
|
|
<0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/
|
|
<0>, /*MTK_DRM_OPT_VP_PQ*/
|
|
<0>, /*MTK_DRM_OPT_GAME_PQ*/
|
|
<0>, /*MTK_DRM_OPT_MMPATH*/
|
|
<0>, /*MTK_DRM_OPT_HBM*/
|
|
<0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/
|
|
<0>, /*MTK_DRM_OPT_LAYER_REC*/
|
|
<1>, /*MTK_DRM_OPT_CLEAR_LAYER*/
|
|
<1>, /*MTK_DRM_OPT_LFR*/
|
|
<1>, /*MTK_DRM_OPT_DYN_MIPI_CHANGE*/
|
|
<1>; /*MTK_DRM_OPT_SF_PF*/
|
|
};
|
|
|
|
disp_mutex0: disp_mutex@14001000 {
|
|
compatible = "mediatek,disp_mutex0",
|
|
"mediatek,mt6781-disp-mutex";
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_MUTEX0>;
|
|
};
|
|
|
|
smi_common@14002000 {
|
|
compatible = "mediatek,disp_smi_common", "mediatek,smi_common";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys_config CLK_MM_SMI_COMMON>,
|
|
<&mmsys_config CLK_MM_SMI_GALS>,
|
|
<&mmsys_config CLK_MM_SMI_INFRA>,
|
|
<&mmsys_config CLK_MM_SMI_IOMMU>;
|
|
clock-names = "scp-dis", "mm-comm", "mm-gals",
|
|
"mm-infra", "mm-iommu";
|
|
mediatek,smi-id = <21>;
|
|
mediatek,smi-cnt = <29>;
|
|
mmsys_config = <&mmsys_config>;
|
|
};
|
|
|
|
smi_larb0: smi_larb0@14003000 {
|
|
compatible = "mediatek,smi_larb0", "mediatek,smi_larb";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
mediatek,larb-id = <0>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <0>;
|
|
};
|
|
|
|
smi_larb1: smi_larb1@14004000 {
|
|
compatible = "mediatek,smi_larb1", "mediatek,smi_larb";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
mediatek,larb-id = <1>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <1>;
|
|
};
|
|
|
|
smi_larb2: smi_larb2@1b002000 {
|
|
compatible = "mediatek,smi_larb2", "mediatek,smi_larb";
|
|
reg = <0 0x1b002000 0 0x1000>;
|
|
mediatek,larb-id = <2>;
|
|
clocks = <&scpsys SCP_SYS_DIS>, <&mdpsys_config CLK_MDP_SMI0>;
|
|
clock-names = "scp-dis", "mdp-smi";
|
|
mediatek,smi-id = <2>;
|
|
};
|
|
|
|
smi_larb3@1f00f000 {
|
|
compatible = "mediatek,smi_larb3", "mediatek,smi_larb";
|
|
reg = <0 0x1f00f000 0 0x1000>;
|
|
mediatek,larb-id = <3>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <3>;
|
|
};
|
|
|
|
smi_larb4: smi_larb4@1602e000 {
|
|
compatible = "mediatek,smi_larb4", "mediatek,smi_larb";
|
|
reg = <0 0x1602e000 0 0x1000>;
|
|
mediatek,larb-id = <4>;
|
|
clocks = <&scpsys SCP_SYS_VDE>, <&vdec_gcon VDEC_VDEC>;
|
|
clock-names = "scp-vdec", "vdec-larb";
|
|
mediatek,smi-id = <4>;
|
|
};
|
|
|
|
smi_larb5@16030000 {
|
|
compatible = "mediatek,smi_larb5", "mediatek,smi_larb";
|
|
reg = <0 0x16030000 0 0x1000>;
|
|
mediatek,larb-id = <5>;
|
|
clocks = <&scpsys SCP_SYS_VDE>;
|
|
clock-names = "scp-vdec";
|
|
mediatek,smi-id = <5>;
|
|
};
|
|
|
|
smi_larb6@16031000 {
|
|
compatible = "mediatek,smi_larb6", "mediatek,smi_larb";
|
|
reg = <0 0x16031000 0 0x1000>;
|
|
mediatek,larb-id = <6>;
|
|
clocks = <&scpsys SCP_SYS_VDE>;
|
|
clock-names = "scp-vdec";
|
|
mediatek,smi-id = <6>;
|
|
};
|
|
|
|
smi_larb13: smi_larb13@1a001000 {
|
|
compatible = "mediatek,smi_larb13", "mediatek,smi_larb";
|
|
reg = <0 0x1a001000 0 0x1000>;
|
|
mediatek,larb-id = <13>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CLK_CAM_M_LARB13>;
|
|
clock-names = "scp-cam", "cam-larb13";
|
|
mediatek,smi-id = <13>;
|
|
};
|
|
|
|
smi_larb14: smi_larb14@1a002000 {
|
|
compatible = "mediatek,smi_larb14", "mediatek,smi_larb";
|
|
reg = <0 0x1a002000 0 0x1000>;
|
|
mediatek,larb-id = <14>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CLK_CAM_M_LARB14>;
|
|
clock-names = "scp-cam", "cam-larb14";
|
|
mediatek,smi-id = <14>;
|
|
};
|
|
|
|
smi_larb15@1a003000 {
|
|
compatible = "mediatek,smi_larb15", "mediatek,smi_larb";
|
|
reg = <0 0x1a003000 0 0x1000>;
|
|
mediatek,larb-id = <15>;
|
|
clocks = <&scpsys SCP_SYS_CAM>;
|
|
clock-names = "scp-cam";
|
|
mediatek,smi-id = <15>;
|
|
};
|
|
|
|
smi_larb16: smi_larb16@1a00f000 {
|
|
compatible = "mediatek,smi_larb16", "mediatek,smi_larb";
|
|
reg = <0 0x1a00f000 0 0x1000>;
|
|
mediatek,larb-id = <16>;
|
|
clocks = <&scpsys SCP_SYS_CAM_RAWA>,
|
|
<&camsys_rawa CLK_CAM_RA_LARBX>;
|
|
clock-names = "scp-cam-rawa", "cam-rawa-larbx";
|
|
mediatek,smi-id = <16>;
|
|
power-reset = <0x1a04f00c 0>;
|
|
common-reset = <0x1a00c000 2>;
|
|
};
|
|
|
|
smi_larb17: smi_larb17@1a010000 {
|
|
compatible = "mediatek,smi_larb17", "mediatek,smi_larb";
|
|
reg = <0 0x1a010000 0 0x1000>;
|
|
mediatek,larb-id = <17>;
|
|
clocks = <&scpsys SCP_SYS_CAM_RAWB>,
|
|
<&camsys_rawb CLK_CAM_RB_LARBX>;
|
|
clock-names = "scp-cam-rawb", "cam-rawb-larbx";
|
|
mediatek,smi-id = <17>;
|
|
power-reset = <0x1a06f00c 0>;
|
|
common-reset = <0x1a00d000 3>;
|
|
};
|
|
|
|
smi_larb18: smi_larb18@1a011000 {
|
|
compatible = "mediatek,smi_larb18", "mediatek,smi_larb";
|
|
reg = <0 0x1a011000 0 0x1000>;
|
|
mediatek,larb-id = <18>;
|
|
clocks = <&scpsys SCP_SYS_CAM_RAWB>;
|
|
clock-names = "scp-cam-rawb";
|
|
mediatek,smi-id = <18>;
|
|
};
|
|
|
|
smi_larb19: smi_larb19@1c10f000 {
|
|
compatible = "mediatek,smi_larb19", "mediatek,smi_larb";
|
|
reg = <0 0x1c10f000 0 0x1000>;
|
|
mediatek,larb-id = <19>;
|
|
clocks = <&scpsys SCP_SYS_IPE>,
|
|
<&ipesys CLK_IPE_LARB19>;
|
|
clock-names = "scp-ipe", "ipe-larb19";
|
|
mediatek,smi-id = <19>;
|
|
};
|
|
|
|
smi_larb20: smi_larb20@1c00f000 {
|
|
compatible = "mediatek,smi_larb20", "mediatek,smi_larb";
|
|
reg = <0 0x1c00f000 0 0x1000>;
|
|
mediatek,larb-id = <20>;
|
|
clocks = <&scpsys SCP_SYS_IPE>,
|
|
<&ipesys CLK_IPE_LARB20>;
|
|
clock-names = "scp-ipe", "ipe-larb20";
|
|
mediatek,smi-id = <20>;
|
|
};
|
|
|
|
mmdvfs: mmdvfs_pmqos {
|
|
compatible = "mediatek,mmdvfs";
|
|
disp_step0 = <560 1 0 7>;
|
|
disp_step0_ext = <560 2 9 0x1589d8>;
|
|
disp_step1 = <450 1 0 7>;
|
|
disp_step1_ext = <450 2 9 0x114ec4>;
|
|
disp_step2 = <312 1 0 10>;
|
|
cam_step0 = <546 1 1 8>;
|
|
cam_step1 = <416 1 1 9>;
|
|
cam_step2 = <312 1 1 10>;
|
|
img_step0 = <546 1 2 8>;
|
|
img_step1 = <364 1 2 11>;
|
|
img_step2 = <312 1 2 10>;
|
|
ipe_step0 = <546 1 3 8>;
|
|
ipe_step1 = <364 1 3 11>;
|
|
ipe_step2 = <312 1 3 10>;
|
|
venc_step0 = <560 1 4 7>;
|
|
venc_step1 = <450 1 4 7>;
|
|
venc_step2 = <364 1 4 11>;
|
|
vdec_step0 = <546 1 5 8>;
|
|
vdec_step1 = <416 1 5 9>;
|
|
vdec_step2 = <312 1 5 10>;
|
|
mdp_step0 = <560 1 6 7>;
|
|
mdp_step1 = <450 1 6 7>;
|
|
mdp_step2 = <312 1 6 10>;
|
|
|
|
vcore-supply = <&mt_pmic_vcore_buck_reg>;
|
|
|
|
/* fmeter_mux_ids: Mapping to mux sequence in clocks */
|
|
vopp_steps = <0 1 2>;
|
|
disp_freq = "disp_step0", "disp_step1", "disp_step2";
|
|
cam_freq = "cam_step0", "cam_step1", "cam_step2";
|
|
img_freq = "img_step0", "img_step1", "img_step2";
|
|
ipe_freq = "ipe_step0", "ipe_step1", "ipe_step2";
|
|
venc_freq = "venc_step0", "venc_step1", "venc_step2";
|
|
vdec_freq = "vdec_step0", "vdec_step1", "vdec_step2";
|
|
mdp_freq = "mdp_step0", "mdp_step1", "mdp_step2";
|
|
|
|
clocks = <&topckgen TOP_MUX_DISP>, /* 0 */
|
|
<&topckgen TOP_MUX_CAM>, /* 1 */
|
|
<&topckgen TOP_MUX_IMG1>, /* 2 */
|
|
<&topckgen TOP_MUX_IPE>, /* 3 */
|
|
<&topckgen TOP_MUX_VENC>, /* 4 */
|
|
<&topckgen TOP_MUX_VDEC>, /* 5 */
|
|
<&topckgen TOP_MUX_MDP>, /* 6 */
|
|
<&topckgen TOP_MMPLL_CK>, /* 7 */
|
|
<&topckgen TOP_MAINPLL_D2>, /* 8 */
|
|
<&topckgen TOP_UNIVPLL_D3>, /* 9 */
|
|
<&topckgen TOP_UNIVPLL_D2_D2>, /* 10 */
|
|
<&topckgen TOP_MAINPLL_D3>; /* 11 */
|
|
|
|
clock-names = "TOP_MUX_DISP", /* 0 */
|
|
"TOP_MUX_CAM", /* 1 */
|
|
"TOP_MUX_IMG1", /* 2 */
|
|
"TOP_MUX_IPE", /* 3 */
|
|
"TOP_MUX_VENC", /* 4 */
|
|
"TOP_MUX_VDEC", /* 5 */
|
|
"TOP_MUX_MDP", /* 6 */
|
|
"TOP_MMPLL_CK", /* 7 */
|
|
"TOP_MAINPLL_D2", /* 8 */
|
|
"TOP_UNIVPLL_D3", /* 9 */
|
|
"TOP_UNIVPLL_D2_D2", /* 10 */
|
|
"TOP_MAINPLL_D3"; /* 11 */
|
|
};
|
|
|
|
mmqos: mmqos {
|
|
compatible = "mediatek,mmqos";
|
|
larb_groups = <0 1 2 4 7 9 11 13 14 16 17 19 20>;
|
|
larb0 = <8 7 8 8>;
|
|
larb1 = <7 8 8 9 8>;
|
|
larb2 = <7 7 7 7 8>;
|
|
larb4 = <6 7 8 7 7 7 7 7 7 6 6 7 8 9>;
|
|
larb7 = <7 8 8 8 7 7 7 7 7 7 7 7 8>;
|
|
larb9 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7
|
|
7 7 7 7 7 7 8 8 8 8 7>;
|
|
larb11 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7
|
|
7 7 7 7 7 7 8 8 8 8 7>;
|
|
larb13 = <7 8 8 8 8 8 8 8 8 7 8 7>;
|
|
larb14 = <7 8 8 8 7 8>;
|
|
larb16 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>;
|
|
larb17 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>;
|
|
larb19 = <7 8 7 8>;
|
|
larb20 = <7 7 8 8 6 7>;
|
|
/* include SMI common CCU */
|
|
cam_larb = <13 14 16 17>;
|
|
max_ostd_larb = <0 1>;
|
|
max_ostd = <40>;
|
|
comm_freq = <0>;
|
|
};
|
|
|
|
disp_ovl0: disp_ovl0@14005000 {
|
|
compatible = "mediatek,disp_ovl0",
|
|
"mediatek,mt6781-disp-ovl";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_OVL0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
|
|
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
|
|
};
|
|
|
|
disp_ovl0_2l: disp_ovl0_2l@14006000 {
|
|
compatible = "mediatek,disp_ovl0_2l",
|
|
"mediatek,mt6781-disp-ovl";
|
|
reg = <0 0x14006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_OVL0_2L>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
mediatek,smi-id = <1>;
|
|
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
|
|
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
|
|
};
|
|
|
|
disp_rdma0: disp_rdma0@14007000 {
|
|
compatible = "mediatek,disp_rdma0",
|
|
"mediatek,mt6781-disp-rdma";
|
|
reg = <0 0x14007000 0 0x1000>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_RDMA0>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
mediatek,smi-id = <1>;
|
|
iommus = <&iommu0 M4U_PORT_L1_DISP_RDMA0>;
|
|
};
|
|
|
|
disp_rsz0: disp_rsz0@14008000 {
|
|
compatible = "mediatek,disp_rsz0",
|
|
"mediatek,mt6781-disp-rsz";
|
|
reg = <0 0x14008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_RSZ0>;
|
|
};
|
|
|
|
disp_color0: disp_color0@14009000 {
|
|
compatible = "mediatek,disp_color0",
|
|
"mediatek,mt6781-disp-color";
|
|
reg = <0 0x14009000 0 0x1000>;
|
|
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_COLOR0>;
|
|
};
|
|
|
|
reserved@1400a000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
};
|
|
|
|
disp_ccorr0: disp_ccorr0@1400b000 {
|
|
compatible = "mediatek,disp_ccorr0",
|
|
"mediatek,mt6781-disp-ccorr";
|
|
reg = <0 0x1400b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_CCORR0>;
|
|
};
|
|
|
|
disp_aal0: disp_aal0@1400c000 {
|
|
compatible = "mediatek,disp_aal0",
|
|
"mediatek,mt6781-disp-aal";
|
|
reg = <0 0x1400c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_AAL0>;
|
|
};
|
|
|
|
disp_gamma0: disp_gamma0@1400d000 {
|
|
compatible = "mediatek,disp_gamma0",
|
|
"mediatek,mt6781-disp-gamma";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_GAMMA0>;
|
|
};
|
|
|
|
disp_postmask0: disp_postmask0@1400e000 {
|
|
compatible = "mediatek,disp_postmask0",
|
|
"mediatek,mt6781-disp-postmask";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_POSTMASK0>;
|
|
mediatek,larb = <&smi_larb0>;
|
|
mediatek,smi-id = <0>;
|
|
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
|
|
};
|
|
|
|
disp_dither0: disp_dither0@1400f000 {
|
|
compatible = "mediatek,disp_dither0",
|
|
"mediatek,mt6781-disp-dither";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_DITHER0>;
|
|
};
|
|
|
|
reserved@14010000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
};
|
|
|
|
reserved@14011000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x14011000 0 0x1000>;
|
|
};
|
|
|
|
disp_dsc_wrap: disp_dsc_wrap@14012000 {
|
|
compatible = "mediatek,disp_dsc_wrap",
|
|
"mediatek,mt6781-disp-dsc";
|
|
reg = <0 0x14012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_DSC_WRAP>;
|
|
};
|
|
|
|
mipi_tx_config0: mipi_tx_config@11c80000 {
|
|
compatible = "mediatek,mipi_tx_config0",
|
|
"mediatek,mt6781-mipi-tx";
|
|
reg = <0 0x11c80000 0 0x1000>;
|
|
clocks = <&clk26m>;
|
|
#clock-cells = <0>;
|
|
#phy-cells = <0>;
|
|
clock-output-names = "mipi_tx0_pll";
|
|
};
|
|
dsi0: dsi@14013000 {
|
|
compatible = "mediatek,dsi0",
|
|
"mediatek,mt6781-dsi";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DSI0>,
|
|
<&mmsys_config CLK_MM_DSI0_DSI_CK_DOMAIN>,
|
|
<&mipi_tx_config0>;
|
|
clock-names = "engine", "digital", "hs";
|
|
phys = <&mipi_tx_config0>;
|
|
phy-names = "dphy";
|
|
};
|
|
|
|
dsi_te: dsi_te {
|
|
compatible = "mediatek, dsi_te-eint";
|
|
status = "disabled";
|
|
};
|
|
|
|
disp_wdma0: disp_wdma0@14014000 {
|
|
compatible = "mediatek,disp_wdma0",
|
|
"mediatek,mt6781-disp-wdma";
|
|
reg = <0 0x14014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_WDMA0>;
|
|
mediatek,larb = <&smi_larb1>;
|
|
mediatek,smi-id = <1>;
|
|
iommus = <&iommu0 M4U_PORT_L1_DISP_WDMA0>;
|
|
};
|
|
|
|
reserved@14015000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x14015000 0 0x1000>;
|
|
};
|
|
|
|
disp_leds {
|
|
compatible = "mediatek,disp-leds";
|
|
|
|
backlight {
|
|
label = "lcd-backlight";
|
|
max-brightness = <255>;
|
|
led-bits = <8>;
|
|
default-state = "on";
|
|
};
|
|
};
|
|
|
|
pwmleds {
|
|
compatible = "mediatek,disp-pwm-leds";
|
|
|
|
backlight {
|
|
label = "lcd-backlight";
|
|
pwms = <&disp_pwm 0 39385>;
|
|
max-brightness = <255>;
|
|
led-bits = <8>;
|
|
default-state = "on";
|
|
pwm-names = "lcd-backlight";
|
|
};
|
|
};
|
|
|
|
ion: iommu {
|
|
compatible = "mediatek,ion";
|
|
iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
pseudo_m4u {
|
|
compatible = "mediatek,mt-pseudo_m4u";
|
|
iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
pseudo_m4u-larb0 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <0>;
|
|
iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>,
|
|
<&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>,
|
|
<&iommu0 M4U_PORT_L0_OVL_RDMA0>,
|
|
<&iommu0 M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
pseudo_m4u-larb1 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <1>;
|
|
iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>,
|
|
<&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
|
|
<&iommu0 M4U_PORT_L1_DISP_RDMA0>,
|
|
<&iommu0 M4U_PORT_L1_DISP_WDMA0>,
|
|
<&iommu0 M4U_PORT_L1_DISP_FAKE1>;
|
|
};
|
|
|
|
pseudo_m4u-larb2 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <2>;
|
|
iommus = <&iommu0 M4U_PORT_L2_MDP_RDMA0>,
|
|
<&iommu0 M4U_PORT_L2_MDP_RDMA1>,
|
|
<&iommu0 M4U_PORT_L2_MDP_WROT0>,
|
|
<&iommu0 M4U_PORT_L2_MDP_WROT1>,
|
|
<&iommu0 M4U_PORT_L2_MDP_DISP_FAKE0>;
|
|
};
|
|
|
|
pseudo_m4u-larb4 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <4>;
|
|
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_UFO_ENC_EXT>,
|
|
<&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>,
|
|
<&iommu0 M4U_PORT_L4_MINI_MDP_R0_EXT>,
|
|
<&iommu0 M4U_PORT_L4_MINI_MDP_W0_EXT>;
|
|
};
|
|
|
|
pseudo_m4u-larb7 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <7>;
|
|
iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>,
|
|
<&iommu0 M4U_PORT_L7_VENC_REC>,
|
|
<&iommu0 M4U_PORT_L7_VENC_BSDMA>,
|
|
<&iommu0 M4U_PORT_L7_VENC_SV_COMV>,
|
|
<&iommu0 M4U_PORT_L7_VENC_RD_COMV>,
|
|
<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>,
|
|
<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>,
|
|
<&iommu0 M4U_PORT_L7_VENC_REF_LUMA>,
|
|
<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>,
|
|
<&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA>,
|
|
<&iommu0 M4U_PORT_L7_JPGENC_C_RDMA>,
|
|
<&iommu0 M4U_PORT_L7_JPGENC_Q_TABLE>,
|
|
<&iommu0 M4U_PORT_L7_JPGENC_BSDMA>;
|
|
};
|
|
|
|
pseudo_m4u-larb9 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <9>;
|
|
iommus = <&iommu0 M4U_PORT_L9_IMG_IMGI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_IMGBI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_DMGI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_DEPI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_ICE_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_SMTI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_SMTO_D2>,
|
|
<&iommu0 M4U_PORT_L9_IMG_SMTO_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_CRZO_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_IMG3O_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_VIPI_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_SMTI_D5>,
|
|
<&iommu0 M4U_PORT_L9_IMG_TIMGO_D1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_UFBC_W0>,
|
|
<&iommu0 M4U_PORT_L9_IMG_UFBC_R0>,
|
|
<&iommu0 M4U_PORT_L9_IMG_WPE_RDMA1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_WPE_RDMA0>,
|
|
<&iommu0 M4U_PORT_L9_IMG_WPE_WDMA>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA0>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA2>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA3>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA4>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_RDMA5>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_WDMA0>,
|
|
<&iommu0 M4U_PORT_L9_IMG_MFB_WDMA1>,
|
|
<&iommu0 M4U_PORT_L9_IMG_RESERVE6>,
|
|
<&iommu0 M4U_PORT_L9_IMG_RESERVE7>,
|
|
<&iommu0 M4U_PORT_L9_IMG_RESERVE8>;
|
|
};
|
|
|
|
|
|
pseudo_m4u-larb11 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <11>;
|
|
iommus = <&iommu0 M4U_PORT_L11_IMG_IMGI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_IMGBI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_DMGI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_DEPI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_ICE_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_SMTI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_SMTO_D2>,
|
|
<&iommu0 M4U_PORT_L11_IMG_SMTO_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_CRZO_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_IMG3O_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_VIPI_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_SMTI_D5>,
|
|
<&iommu0 M4U_PORT_L11_IMG_TIMGO_D1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_UFBC_W0>,
|
|
<&iommu0 M4U_PORT_L11_IMG_UFBC_R0>,
|
|
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0>,
|
|
<&iommu0 M4U_PORT_L11_IMG_WPE_WDMA>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0>,
|
|
<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1>,
|
|
<&iommu0 M4U_PORT_L11_IMG_RESERVE6>,
|
|
<&iommu0 M4U_PORT_L11_IMG_RESERVE7>,
|
|
<&iommu0 M4U_PORT_L11_IMG_RESERVE8>;
|
|
};
|
|
|
|
|
|
pseudo_m4u-larb13 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <13>;
|
|
iommus = <&iommu0 M4U_PORT_L13_CAM_MRAWI>,
|
|
<&iommu0 M4U_PORT_L13_CAM_MRAWO0>,
|
|
<&iommu0 M4U_PORT_L13_CAM_MRAWO1>,
|
|
<&iommu0 M4U_PORT_L13_CAM_RESERVE1>,
|
|
<&iommu0 M4U_PORT_L13_CAM_RESERVE2>,
|
|
<&iommu0 M4U_PORT_L13_CAM_RESERVE3>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CAMSV4>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CAMSV5>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CAMSV6>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CCUI>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CCUO>,
|
|
<&iommu0 M4U_PORT_L13_CAM_FAKE>;
|
|
};
|
|
|
|
pseudo_m4u-larb14 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <14>;
|
|
iommus = <&iommu0 M4U_PORT_L14_CAM_RESERVE1>,
|
|
<&iommu0 M4U_PORT_L14_CAM_RESERVE2>,
|
|
<&iommu0 M4U_PORT_L14_CAM_RESERVE3>,
|
|
<&iommu0 M4U_PORT_L14_CAM_RESERVE4>,
|
|
<&iommu0 M4U_PORT_L14_CAM_CCUI>,
|
|
<&iommu0 M4U_PORT_L14_CAM_CCUO>;
|
|
};
|
|
|
|
|
|
pseudo_m4u-larb16 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <16>;
|
|
iommus = <&iommu0 M4U_PORT_L16_CAM_IMGO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_RRZO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_CQI_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_BPCI_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_YUVO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_UFDI_R2_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_RAWI_R2_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_RAWI_R3_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_AAO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_AFO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_FLKO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_LCESO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_CRZO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_LTMSO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_RSSO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_AAHO_R1_A>,
|
|
<&iommu0 M4U_PORT_L16_CAM_LSCI_R1_A>;
|
|
};
|
|
|
|
pseudo_m4u-larb17 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <17>;
|
|
iommus = <&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_CQI_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_AAO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_AFO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B>,
|
|
<&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B>;
|
|
};
|
|
|
|
pseudo_m4u-larb18 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <18>;
|
|
iommus = <&iommu0 M4U_PORT_L18_CAM_IMGO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_RRZO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_CQI_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_BPCI_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_YUVO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_UFDI_R2_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_RAWI_R2_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_RAWI_R3_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_AAO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_AFO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_FLKO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_LCESO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_CRZO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_LTMSO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_RSSO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_AAHO_R1_C>,
|
|
<&iommu0 M4U_PORT_L18_CAM_LSCI_R1_C>;
|
|
};
|
|
|
|
pseudo_m4u-larb19 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <19>;
|
|
iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA>,
|
|
<&iommu0 M4U_PORT_L19_IPE_DVS_WDMA>,
|
|
<&iommu0 M4U_PORT_L19_IPE_DVP_RDMA>,
|
|
<&iommu0 M4U_PORT_L19_IPE_DVP_WDMA>;
|
|
};
|
|
|
|
pseudo_m4u-larb20 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <20>;
|
|
iommus = <&iommu0 M4U_PORT_L20_IPE_FDVT_RDA>,
|
|
<&iommu0 M4U_PORT_L20_IPE_FDVT_RDB>,
|
|
<&iommu0 M4U_PORT_L20_IPE_FDVT_WRA>,
|
|
<&iommu0 M4U_PORT_L20_IPE_FDVT_WRB>,
|
|
<&iommu0 M4U_PORT_L20_IPE_RSC_RDMA0>,
|
|
<&iommu0 M4U_PORT_L20_IPE_RSC_WDMA>;
|
|
};
|
|
|
|
pseudo_m4u-ccu0 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <CCU0_PSEUDO_LARBID>;
|
|
iommus = <&iommu0 M4U_PORT_L13_CAM_CCUI>,
|
|
<&iommu0 M4U_PORT_L13_CAM_CCUO>,
|
|
<&iommu0 M4U_PORT_L22_CCU0>;
|
|
};
|
|
|
|
pseudo_m4u-ccu1 {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <CCU1_PSEUDO_LARBID>;
|
|
iommus = <&iommu0 M4U_PORT_L14_CAM_CCUI>,
|
|
<&iommu0 M4U_PORT_L14_CAM_CCUO>,
|
|
<&iommu0 M4U_PORT_L23_CCU1>;
|
|
};
|
|
|
|
pseudo_m4u-misc {
|
|
compatible = "mediatek,mt-pseudo_m4u-port";
|
|
mediatek,larbid = <MISC_PSEUDO_LARBID>;
|
|
iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
|
|
};
|
|
|
|
iommu0: m4u@14016000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,iommu_v0";
|
|
reg = <0 0x14016000 0 0x1000>;
|
|
mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2>,
|
|
<&smi_larb4 &smi_larb7 &smi_larb9>,
|
|
<&smi_larb11 &smi_larb13 &smi_larb14>,
|
|
<&smi_larb16 &smi_larb17 &smi_larb18>,
|
|
<&smi_larb19 &smi_larb20>;
|
|
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mmsys_config CLK_MM_SMI_IOMMU>,
|
|
<&scpsys SCP_SYS_DIS>;
|
|
clock-names = "disp-iommu-ck", "power";
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
iommu0_bank1: m4u@14017000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,bank1_m4u0";
|
|
reg = <0 0x14017000 0 0x1000>;
|
|
interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iommu0_bank2: m4u@14018000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,bank2_m4u0";
|
|
reg = <0 0x14018000 0 0x1000>;
|
|
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iommu0_bank3: m4u@14019000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,bank3_m4u0";
|
|
reg = <0 0x14019000 0 0x1000>;
|
|
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
iommu0_sec: m4u@1401a000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,sec_m4u0";
|
|
reg = <0 0x1401a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
disp_smi_2x1_sub_common_u0@1401b000 {
|
|
compatible = "mediatek,disp_smi_2x1_sub_common_u0", "mediatek,smi_common";
|
|
reg = <0 0x1401b000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <22>;
|
|
};
|
|
|
|
disp_smi_2x1_sub_common_u1@1401c000 {
|
|
compatible = "mediatek,disp_smi_2x1_sub_common_u1", "mediatek,smi_common";
|
|
reg = <0 0x1401c000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <23>;
|
|
};
|
|
|
|
reserved@1401d000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1401d000 0 0x1000>;
|
|
};
|
|
|
|
img1_smi_2x1_sub_common@1401e000 {
|
|
compatible = "mediatek,img1_smi_2x1_sub_common", "mediatek,smi_common";
|
|
reg = <0 0x1401e000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "scp-dis";
|
|
mediatek,smi-id = <24>;
|
|
};
|
|
|
|
reserved@1401f000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1401f000 0 0xe1000>;
|
|
};
|
|
|
|
imgsys_config: imgsys_config@15020000 {
|
|
compatible = "mediatek,imgsys", "syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
clocks =
|
|
<&imgsys1 CLK_IMGSYS1_LARB9>,
|
|
<&imgsys1 CLK_IMGSYS1_DIP>,
|
|
<&imgsys2 CLK_IMGSYS2_LARB9>,
|
|
<&imgsys2 CLK_IMGSYS2_MSS>,
|
|
<&imgsys2 CLK_IMGSYS2_MFB>;
|
|
clock-names =
|
|
"DIP_CG_IMG_LARB9",
|
|
"DIP_CG_IMG_DIP",
|
|
"DIP_CG_IMG_LARB11",
|
|
"DIP_CG_IMG_DIP_MSS",
|
|
"DIP_CG_IMG_MFB_DIP";
|
|
};
|
|
|
|
imgsys1: imgsys1@15020000 {
|
|
compatible = "mediatek,imgsys1", "syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dip_a0@15021000 {
|
|
compatible = "mediatek,dip1";
|
|
reg = <0 0x15021000 0 0xc000>;
|
|
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dip_a1@15022000 {
|
|
compatible = "mediatek,dip_a1";
|
|
reg = <0 0x15022000 0 0x1000>;
|
|
};
|
|
|
|
dip_a2@15023000 {
|
|
compatible = "mediatek,dip_a2";
|
|
reg = <0 0x15023000 0 0x1000>;
|
|
};
|
|
|
|
dip_a3@15024000 {
|
|
compatible = "mediatek,dip_a3";
|
|
reg = <0 0x15024000 0 0x1000>;
|
|
};
|
|
|
|
dip_a4@15025000 {
|
|
compatible = "mediatek,dip_a4";
|
|
reg = <0 0x15025000 0 0x1000>;
|
|
};
|
|
|
|
dip_a5@15026000 {
|
|
compatible = "mediatek,dip_a5";
|
|
reg = <0 0x15026000 0 0x1000>;
|
|
};
|
|
|
|
dip_a6@15027000 {
|
|
compatible = "mediatek,dip_a6";
|
|
reg = <0 0x15027000 0 0x1000>;
|
|
};
|
|
|
|
dip_a7@15028000 {
|
|
compatible = "mediatek,dip_a7";
|
|
reg = <0 0x15028000 0 0x1000>;
|
|
};
|
|
|
|
dip_a8@15029000 {
|
|
compatible = "mediatek,dip_a8";
|
|
reg = <0 0x15029000 0 0x1000>;
|
|
};
|
|
|
|
dip_a9@1502a000 {
|
|
compatible = "mediatek,dip_a9";
|
|
reg = <0 0x1502a000 0 0x1000>;
|
|
};
|
|
|
|
dip_a10@1502b000 {
|
|
compatible = "mediatek,dip_a10";
|
|
reg = <0 0x1502b000 0 0x1000>;
|
|
};
|
|
|
|
dip_a11@1502c000 {
|
|
compatible = "mediatek,dip_a11";
|
|
reg = <0 0x1502c000 0 0x1000>;
|
|
};
|
|
|
|
smi_larb9: smi_larb9@1502e000 {
|
|
compatible = "mediatek,smi_larb9", "mediatek,smi_larb";
|
|
reg = <0 0x1502e000 0 0x1000>;
|
|
mediatek,larb-id = <9>;
|
|
clocks = <&scpsys SCP_SYS_ISP>,
|
|
<&imgsys1 CLK_IMGSYS1_LARB9>;
|
|
clock-names = "scp-isp", "img1-larb9";
|
|
mediatek,smi-id = <9>;
|
|
};
|
|
|
|
smi_larb10@15030000 {
|
|
compatible = "mediatek,smi_larb10", "mediatek,smi_larb";
|
|
reg = <0 0x15030000 0 0x1000>;
|
|
mediatek,larb-id = <10>;
|
|
clocks = <&scpsys SCP_SYS_ISP>;
|
|
clock-names = "scp-isp";
|
|
mediatek,smi-id = <10>;
|
|
};
|
|
|
|
|
|
2x1_sub_common@1502f000 {
|
|
compatible = "mediatek,2x1_sub_common", "mediatek,smi_common";
|
|
reg = <0 0x1502f000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_ISP>;
|
|
clock-names = "scp-isp";
|
|
mediatek,smi-id = <28>;
|
|
common-clamp = <1>;
|
|
};
|
|
|
|
mfb@15010000 {
|
|
compatible = "mediatek,mfb";
|
|
reg = <0 0x15010000 0 0x1000>;
|
|
};
|
|
|
|
wpe_a@15011000 {
|
|
compatible = "mediatek,wpe_a";
|
|
reg = <0 0x15011000 0 0x1000>;
|
|
};
|
|
|
|
mfb@15012000 {
|
|
compatible = "mediatek,mfb";
|
|
reg = <0 0x15012000 0 0x1000>;
|
|
};
|
|
|
|
imgsys2_config@15820000 {
|
|
compatible = "mediatek,imgsys2_config", "syscon";
|
|
reg = <0 0x15820000 0 0x1000>;
|
|
};
|
|
|
|
imgsys2: imgsys2@15820000 {
|
|
compatible = "mediatek,imgsys2", "syscon";
|
|
reg = <0 0x15820000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dip_b0@15821000 {
|
|
compatible = "mediatek,dip_b0";
|
|
reg = <0 0x15821000 0 0x1000>;
|
|
};
|
|
|
|
dip_b1@15822000 {
|
|
compatible = "mediatek,dip_b1";
|
|
reg = <0 0x15822000 0 0x1000>;
|
|
};
|
|
|
|
dip_b2@15823000 {
|
|
compatible = "mediatek,dip_b2";
|
|
reg = <0 0x15823000 0 0x1000>;
|
|
};
|
|
|
|
dip_b3@15824000 {
|
|
compatible = "mediatek,dip_b3";
|
|
reg = <0 0x15824000 0 0x1000>;
|
|
};
|
|
|
|
dip_b4@15825000 {
|
|
compatible = "mediatek,dip_b4";
|
|
reg = <0 0x15825000 0 0x1000>;
|
|
};
|
|
|
|
dip_b5@15826000 {
|
|
compatible = "mediatek,dip_b5";
|
|
reg = <0 0x15826000 0 0x1000>;
|
|
};
|
|
|
|
dip_b6@15827000 {
|
|
compatible = "mediatek,dip_b6";
|
|
reg = <0 0x15827000 0 0x1000>;
|
|
};
|
|
|
|
dip_b7@15828000 {
|
|
compatible = "mediatek,dip_b7";
|
|
reg = <0 0x15828000 0 0x1000>;
|
|
};
|
|
|
|
dip_b8@15829000 {
|
|
compatible = "mediatek,dip_b8";
|
|
reg = <0 0x15829000 0 0x1000>;
|
|
};
|
|
|
|
dip_b9@1582a000 {
|
|
compatible = "mediatek,dip_b9";
|
|
reg = <0 0x1582a000 0 0x1000>;
|
|
};
|
|
|
|
dip_b10@1582b000 {
|
|
compatible = "mediatek,dip_b10";
|
|
reg = <0 0x1582b000 0 0x1000>;
|
|
};
|
|
|
|
dip_b11@1582c000 {
|
|
compatible = "mediatek,dip_b11";
|
|
reg = <0 0x1582c000 0 0x1000>;
|
|
};
|
|
|
|
smi_larb11: smi_larb11@1582e000 {
|
|
compatible = "mediatek,smi_larb11", "mediatek,smi_larb";
|
|
reg = <0 0x1582e000 0 0x1000>;
|
|
mediatek,larb-id = <11>;
|
|
clocks = <&scpsys SCP_SYS_ISP2>,
|
|
<&imgsys2 CLK_IMGSYS2_LARB9>;
|
|
clock-names = "scp-isp2", "img2-larb9";
|
|
mediatek,smi-id = <11>;
|
|
power-reset = <0x1502000c 2>,
|
|
<0x1582000c 0>;
|
|
common-reset = <0x1502f000 1>;
|
|
};
|
|
|
|
smi_larb12@15830000 {
|
|
compatible = "mediatek,smi_larb12", "mediatek,smi_larb";
|
|
reg = <0 0x15830000 0 0x1000>;
|
|
mediatek,larb-id = <12>;
|
|
clocks = <&scpsys SCP_SYS_ISP2>;
|
|
clock-names = "scp-isp2";
|
|
mediatek,smi-id = <12>;
|
|
};
|
|
|
|
msfdl@15810000 {
|
|
compatible = "mediatek,msfdl";
|
|
reg = <0 0x15810000 0 0x1000>;
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
wpe_b@15811000 {
|
|
compatible = "mediatek,wpe_b";
|
|
reg = <0 0x15811000 0 0x1000>;
|
|
};
|
|
|
|
mssdl@15812000 {
|
|
compatible = "mediatek,mssdl";
|
|
reg = <0 0x15812000 0 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
mss_b@15812000 {
|
|
compatible = "mediatek,mss_b";
|
|
reg = <0 0x15812000 0 0x1000>;
|
|
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
|
|
mboxes = <&gce_mbox 17 0 CMDQ_THR_PRIO_1>;
|
|
mss_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_GCE_IMG2_EVENT23>;
|
|
mss_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_MSS>;
|
|
};
|
|
|
|
msf_b@15810000 {
|
|
compatible = "mediatek,msf_b";
|
|
reg = <0 0x15810000 0 0x1000>;
|
|
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
|
|
mboxes = <&gce_mbox 18 0 CMDQ_THR_PRIO_1>;
|
|
msf_frame_done =
|
|
/bits/ 16 <CMDQ_EVENT_GCE_IMG2_EVENT21>;
|
|
msf_token =
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_MSF>;
|
|
clocks =
|
|
<&imgsys2 CLK_IMGSYS2_LARB9>,
|
|
<&imgsys2 CLK_IMGSYS2_MSS>,
|
|
<&imgsys2 CLK_IMGSYS2_MFB>,
|
|
<&scpsys SCP_SYS_ISP>;
|
|
clock-names =
|
|
"MFB_CG_IMG2_LARB11",
|
|
"MFB_CG_IMG2_MSS",
|
|
"MFB_CG_IMG2_MFB",
|
|
"MFB_CG_IMG1_GALS";
|
|
};
|
|
|
|
imgsys_mfb_b@15820000 {
|
|
compatible = "mediatek,imgsys_mfb_b";
|
|
reg = <0 0x15820000 0 0x1000>;
|
|
};
|
|
|
|
vdec_fmt: vdec_fmt@16080000 {
|
|
compatible = "mediatek-vdec-fmt";
|
|
mediatek,fmtname = "vdec-fmt";
|
|
reg = <0 0x16080000 0 0x1000>, /* VDEC_MINI_MDP_TOP_MDP_RDMA */
|
|
<0 0x16081000 0 0x1000>, /* VDEC_MINI_MDP_TOP_MDP_WDMA */
|
|
<0 0x1602f000 0 0x10000>; /* VDEC_SOC_GCON */
|
|
clocks = <&vdec_gcon VDEC_VDEC>;
|
|
clock-names = "MT_CG_VDEC";
|
|
mediatek,fmt_gce_th_num = <1>; /* FMT GCE HW THREAD NUM*/
|
|
mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>;
|
|
/* rdma_sw_rst_done_eng_event */
|
|
rdma0_sw_rst_done_eng = /bits/ 16 <CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0>;
|
|
/* rdma_tile_done */
|
|
rdma0_tile_done = /bits/ 16 <CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1>;
|
|
/* wdma_sw_rst_done_eng_event */
|
|
wdma0_sw_rst_done_eng = /bits/ 16 <CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2>;
|
|
/* wdma_tile_done */
|
|
wdma0_tile_done = /bits/ 16 <CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3>;
|
|
gce-gpr = <GCE_GPR_R10>;
|
|
};
|
|
|
|
vcu: vcu@16000000 {
|
|
compatible = "mediatek-vcu";
|
|
mediatek,vcuid = <0>;
|
|
mediatek,vcuname = "vcu";
|
|
reg = <0 0x16000000 0 0x40000>, /* VDEC_BASE */
|
|
<0 0x17020000 0 0x10000>, /* VENC_BASE */
|
|
<0 0x17820000 0 0x10000>; /* VENC_C1_BASE */
|
|
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
mediatek,dec_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/
|
|
mediatek,enc_gce_th_num = <1>; /* VDEC GCE HW THREAD NUM*/
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
|
|
mboxes = <&gce_mbox 7 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox_sec 12 0 CMDQ_THR_PRIO_1>;
|
|
#else
|
|
mboxes = <&gce_mbox 7 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 12 0 CMDQ_THR_PRIO_1>;
|
|
#endif
|
|
gce-event-names = "venc_eof",
|
|
"venc_cmdq_pause_done",
|
|
"venc_mb_done",
|
|
"venc_sps_done",
|
|
"venc_pps_done",
|
|
"venc_128B_cnt_done",
|
|
"vdec_pic_start",
|
|
"vdec_decode_done",
|
|
"vdec_pause",
|
|
"vdec_dec_error",
|
|
"vdec_mc_busy_overflow_timeout",
|
|
"vdec_all_dram_req_done",
|
|
"vdec_ini_fetch_rdy",
|
|
"vdec_process_flag",
|
|
"vdec_search_start_code_done",
|
|
"vdec_ref_reorder_done",
|
|
"vdec_wp_tble_done",
|
|
"vdec_count_sram_clr_done",
|
|
"vdec_gce_cnt_op_threshold";
|
|
gce-events = <&gce_mbox CMDQ_EVENT_VENC_CMDQ_FRAME_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_MB_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_SPS_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_PPS_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_INT>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_PAUSE>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_DEC_ERROR>,
|
|
<&gce_mbox CMDQ_EVENT_MDEC_TIMEOUT>,
|
|
<&gce_mbox CMDQ_EVENT_DRAM_ACCESS_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_INI_FETCH_RDY>,
|
|
<&gce_mbox CMDQ_EVENT_PROCESS_FLAG>,
|
|
<&gce_mbox CMDQ_EVENT_SEARCH_START_CODE_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_REF_REORDER_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_WP_TBLE_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_COUNT_SRAM_CLR_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_GCE_CNT_OP_THRESHOLD>;
|
|
gce-gpr = <GCE_GPR_R10>, <GCE_GPR_R11>;
|
|
};
|
|
|
|
vdec@16000000 {
|
|
compatible = "mediatek,mt6781-vcodec-dec";
|
|
reg = <0 0x1602f000 0 0x1000>, /* VDEC_SYS */
|
|
<0 0x16029800 0 0x400>, /* VDEC_UFO */
|
|
<0 0x16020000 0 0x400>, /* VDEC_VLD */
|
|
<0 0x16021000 0 0x1000>, /* VDEC_MC */
|
|
<0 0x16023000 0 0x1000>, /* VDEC_MV */
|
|
<0 0x16025000 0 0x1000>; /* VDEC_MISC */
|
|
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
|
|
mediatek,larb = <&smi_larb4>;
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
|
mediatek,vcu = <&vcu>;
|
|
clocks =
|
|
<&vdec_gcon VDEC_VDEC>;
|
|
clock-names =
|
|
"MT_CG_VDEC";
|
|
};
|
|
|
|
vdec_gcon_clk: vdec_gcon@16010000 {
|
|
compatible = "mediatek,vdec_gcon";
|
|
reg = <0 0x16010000 0 0x8000>;
|
|
};
|
|
|
|
vdec_gcon@16018000 {
|
|
compatible = "mediatek,vdec_gcon";
|
|
reg = <0 0x16018000 0 0x8000>;
|
|
};
|
|
|
|
venc_gcon: venc_gcon@17000000 {
|
|
compatible = "mediatek,venc_gcon",
|
|
"mediatek,mt6833-venc_gcon", "syscon";
|
|
reg = <0 0x17000000 0 0x10000>;
|
|
pwr-regmap = <&sleep>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
venc@17000000 {
|
|
compatible = "mediatek,mt6781-vcodec-enc";
|
|
reg = <0 0x17020000 0 0x2000>;
|
|
iommus = <&iommu0 M4U_PORT_L7_VENC_RD_COMV>;
|
|
mediatek,larb = <&smi_larb7>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
mediatek,vcu = <&vcu>;
|
|
clocks =
|
|
<&venc_gcon VENC_GCON_VENC>;
|
|
clock-names =
|
|
"MT_CG_VENC";
|
|
};
|
|
|
|
smi_larb7: smi_larb7@17010000 {
|
|
compatible = "mediatek,smi_larb7", "mediatek,smi_larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
mediatek,larb-id = <7>;
|
|
clocks = <&scpsys SCP_SYS_VEN>,
|
|
<&venc_gcon VENC_GCON_VENC>,
|
|
<&venc_gcon VENC_GCON_JPGENC>;
|
|
clock-names = "scp-venc", "venc-set1", "venc-set2";
|
|
mediatek,smi-id = <7>;
|
|
};
|
|
|
|
venc@17020000 {
|
|
compatible = "mediatek,venc";
|
|
reg = <0 0x17020000 0 0x10000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
jpgenc@17030000 {
|
|
compatible = "mediatek,jpgenc";
|
|
reg = <0 0x17030000 0 0x10000>;
|
|
mediatek,larb = <&smi_larb7>;
|
|
#ifdef CONFIG_MTK_IOMMU_V2
|
|
iommus = <&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA>;
|
|
#endif
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&venc_gcon VENC_GCON_JPGENC>;
|
|
clock-names = "jpgenc";
|
|
cshot-spec = <368>;
|
|
port-id = <M4U_PORT_L7_JPGENC_Y_RDMA>,
|
|
<M4U_PORT_L7_JPGENC_C_RDMA>,
|
|
<M4U_PORT_L7_JPGENC_Q_TABLE>,
|
|
<M4U_PORT_L7_JPGENC_BSDMA>;
|
|
};
|
|
|
|
mbist@17060000 {
|
|
compatible = "mediatek,mbist";
|
|
reg = <0 0x17060000 0 0x10000>;
|
|
};
|
|
|
|
consys: consys@18002000 {
|
|
compatible = "mediatek,mt6781-consys";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
/*CONN_MCU_CONFIG_BASE */
|
|
reg = <0 0x18002000 0 0x1000>,
|
|
/*TOP_RGU_BASE */
|
|
<0 0x10007000 0 0x0100>,
|
|
/*INFRACFG_AO_BASE */
|
|
<0 0x10001000 0 0x1000>,
|
|
/*SPM_BASE */
|
|
<0 0x10006000 0 0x1000>,
|
|
/*ONN_HIF_ON_BASE */
|
|
<0 0x18007000 0 0x1000>,
|
|
/*CONN_TOP_MISC_OFF_BASE */
|
|
<0 0x180b1000 0 0x1000>,
|
|
/*CONN_MCU_CFG_ON_BASE */
|
|
<0 0x180a3000 0 0x1000>,
|
|
/*CONN_MCU_CIRQ_BASE */
|
|
<0 0x180a5000 0 0x800>,
|
|
/*CONN_TOP_MISC_ON_BASE */
|
|
<0 0x180c1000 0 0x1000>,
|
|
/*CONN_HIF_PDMA_BASE */
|
|
<0 0x18004000 0 0x1000>,
|
|
/* INFRASYS_COMMON AP2MD_PCCIF4_BASE */
|
|
<0 0x10211000 0 0x40>,
|
|
/*INFRA_AO_PERICFG_BASE */
|
|
<0 0x10003000 0 0x1000>;
|
|
/*BGF_EINT */
|
|
interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
|
|
/*WDT_EINT */
|
|
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
|
/*conn2ap_sw_irq*/
|
|
<GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&scpsys SCP_SYS_CONN>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF4_AP_CG>;
|
|
clock-names = "conn", "ccif";
|
|
memory-region = <&consys_mem>;
|
|
};
|
|
|
|
cam_smi_subcom@1a00c000 {
|
|
compatible = "mediatek,cam_smi_subcom", "mediatek,smi_common";
|
|
reg = <0 0x1a00c000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_CAM>;
|
|
clock-names = "scp-cam";
|
|
mediatek,smi-id = <26>;
|
|
common-clamp = <2>;
|
|
};
|
|
|
|
cam_smi_subcom@1a00d000 {
|
|
compatible = "mediatek,cam_smi_subcom", "mediatek,smi_common";
|
|
reg = <0 0x1a00d000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_CAM>;
|
|
clock-names = "scp-cam";
|
|
mediatek,smi-id = <27>;
|
|
common-clamp = <3>;
|
|
};
|
|
|
|
flashlight_core: flashlight_core {
|
|
compatible = "mediatek,flashlight_core";
|
|
};
|
|
|
|
flashlights_mt6370: flashlights_mt6370 {
|
|
compatible = "mediatek,flashlights_mt6370";
|
|
decouple = <1>;
|
|
channel@1 {
|
|
type = <0>;
|
|
ct = <0>;
|
|
part = <0>;
|
|
};
|
|
channel@2 {
|
|
type = <0>;
|
|
ct = <1>;
|
|
part = <0>;
|
|
};
|
|
};
|
|
|
|
camera_af_hw_node: camera_af_hw_node {
|
|
compatible = "mediatek,camera_af_lens";
|
|
};
|
|
|
|
camisp: camisp@1a000000 {
|
|
compatible = "mediatek,camisp", "syscon";
|
|
reg = <0 0x1a000000 0 0x10000>;
|
|
/* Camera CCF */
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&scpsys SCP_SYS_CAM_RAWA>,
|
|
<&scpsys SCP_SYS_CAM_RAWB>,
|
|
<&camsys CLK_CAM_M_CAM>,
|
|
<&camsys CLK_CAM_M_CAMTG>,
|
|
<&camsys CLK_CAM_M_CAMSV1>,
|
|
<&camsys CLK_CAM_M_CAMSV2>,
|
|
<&camsys CLK_CAM_M_CAMSV3>,
|
|
<&camsys CLK_CAM_M_LARB13>,
|
|
<&camsys CLK_CAM_M_LARB14>,
|
|
<&camsys CLK_CAM_M_SENINF>,
|
|
<&camsys CLK_CAM_M_CAM2MM_GALS>,
|
|
<&camsys_rawa CLK_CAM_RA_LARBX>,
|
|
<&camsys_rawa CLK_CAM_RA_CAM>,
|
|
<&camsys_rawa CLK_CAM_RA_CAMTG>,
|
|
<&camsys_rawb CLK_CAM_RB_LARBX>,
|
|
<&camsys_rawb CLK_CAM_RB_CAM>,
|
|
<&camsys_rawb CLK_CAM_RB_CAMTG>,
|
|
<&topckgen TOP_MUX_CAMTM>;
|
|
clock-names = "ISP_SCP_SYS_CAM",
|
|
"ISP_SCP_SYS_RAWA",
|
|
"ISP_SCP_SYS_RAWB",
|
|
"CAMSYS_CAM_CGPDN",
|
|
"CAMSYS_CAMTG_CGPDN",
|
|
"CAMSYS_CAMSV0_CGPDN",
|
|
"CAMSYS_CAMSV1_CGPDN",
|
|
"CAMSYS_CAMSV2_CGPDN",
|
|
"CAMSYS_LARB13_CGPDN",
|
|
"CAMSYS_LARB14_CGPDN",
|
|
"CAMSYS_SENINF_CGPDN",
|
|
"CAMSYS_MAIN_CAM2MM_GALS_CGPDN",
|
|
"CAMSYS_RAWALARB16_CGPDN",
|
|
"CAMSYS_RAWACAM_CGPDN",
|
|
"CAMSYS_RAWATG_CGPDN",
|
|
"CAMSYS_RAWBLARB17_CGPDN",
|
|
"CAMSYS_RAWBCAM_CGPDN",
|
|
"CAMSYS_RAWBTG_CGPDN",
|
|
"TOPCKGEN_TOP_MUX_CAMTM";
|
|
};
|
|
|
|
camsys_a: camsys_a@1a04f000 {
|
|
compatible = "mediatek,camsys_a";
|
|
reg = <0 0x1a04f000 0 0x1000>;
|
|
};
|
|
|
|
camsys_b: camsys_b@1a06f000 {
|
|
compatible = "mediatek,camsys_b";
|
|
reg = <0 0x1a06f000 0 0x1000>;
|
|
};
|
|
|
|
camsys_c: camsys_c@1a08f000 {
|
|
compatible = "mediatek,camsys_c";
|
|
reg = <0 0x1a08f000 0 0x1000>;
|
|
};
|
|
|
|
cam1_inner@1a038000 {
|
|
compatible = "mediatek,cam1_inner";
|
|
reg = <0 0x1a038000 0 0x8000>;
|
|
};
|
|
|
|
cam2_inner@1a058000 {
|
|
compatible = "mediatek,cam2_inner";
|
|
reg = <0 0x1a058000 0 0x8000>;
|
|
};
|
|
|
|
cam3_inner@1a078000 {
|
|
compatible = "mediatek,cam3_inner";
|
|
reg = <0 0x1a078000 0 0x8000>;
|
|
};
|
|
|
|
cam1: cam1@1a030000 {
|
|
compatible = "mediatek,cam1";
|
|
reg = <0 0x1a030000 0 0x8000>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cam2: cam2@1a050000 {
|
|
compatible = "mediatek,cam2";
|
|
reg = <0 0x1a050000 0 0x8000>;
|
|
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cam3@1a070000 {
|
|
compatible = "mediatek,cam3";
|
|
reg = <0 0x1a070000 0 0x8000>;
|
|
};
|
|
|
|
camsv3@1a092000 {
|
|
compatible = "mediatek,camsv3";
|
|
reg = <0 0x1a092000 0 0x1000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
camsv4@1a093000 {
|
|
compatible = "mediatek,camsv4";
|
|
reg = <0 0x1a093000 0 0x1000>;
|
|
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
camsv5@1a094000 {
|
|
compatible = "mediatek,camsv5";
|
|
reg = <0 0x1a094000 0 0x1000>;
|
|
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
camsv6@1a095000 {
|
|
compatible = "mediatek,camsv6";
|
|
reg = <0 0x1a095000 0 0x1000>;
|
|
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
camsv7@1a096000 {
|
|
compatible = "mediatek,camsv7";
|
|
reg = <0 0x1a096000 0 0x1000>;
|
|
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
camsv8@1a097000 {
|
|
compatible = "mediatek,camsv8";
|
|
reg = <0 0x1a097000 0 0x1000>;
|
|
interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
mdp_mutex: mdp_mutex@1b001000 {
|
|
compatible = "mediatek,mdp_mutex";
|
|
reg = <0 0x1b001000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_MUTEX0>;
|
|
clock-names = "MDP_MUTEX0";
|
|
};
|
|
|
|
mdp_smi_larb0@1b002000 {
|
|
compatible = "mediatek,mdp_smi_larb0";
|
|
reg = <0 0x1b002000 0 0x1000>;
|
|
};
|
|
|
|
mdp_rdma0: mdp_rdma0@1b003000 {
|
|
compatible = "mediatek,mdp_rdma0", "mediatek,mdp";
|
|
reg = <0 0x1b003000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_RDMA0>,
|
|
<&infracfg_ao INFRACFG_AO_GCE_CG>,
|
|
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
|
|
clock-names = "MDP_RDMA0", "GCE", "GCE_TIMER";
|
|
mmsys_config = <&mdpsys_config>;
|
|
mm_mutex = <&mdp_mutex>;
|
|
mboxes =
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
<&gce_mbox_sec 10 0 CMDQ_THR_PRIO_1>,
|
|
#endif
|
|
<&gce_mbox 19 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 20 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 21 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 22 0 CMDQ_THR_PRIO_1>;
|
|
mdp_rdma0 = <&mdp_rdma0>;
|
|
mdp_rsz0 = <&mdp_rsz0>;
|
|
mdp_rsz1 = <&mdp_rsz1>;
|
|
mdp_wrot0 = <&mdp_wrot0>;
|
|
mdp_wrot1 = <&mdp_wrot1>;
|
|
mdp_tdshp0 = <&mdp_tdshp0>;
|
|
mdp_aal0 = <&mdp_aal0>;
|
|
mdp_hdr0 = <&mdp_hdr0>;
|
|
thread_count = <24>;
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
g3d_config_base = <0x13000000 0 0xffff0000>;
|
|
mmsys_config_base = <0x14000000 1 0xffff0000>;
|
|
disp_dither_base = <0x14010000 2 0xffff0000>;
|
|
mm_na_base = <0x14020000 3 0xffff0000>;
|
|
imgsys_base = <0x15020000 4 0xffff0000>;
|
|
vdec_gcon_base = <0x18800000 5 0xffff0000>;
|
|
venc_gcon_base = <0x18810000 6 0xffff0000>;
|
|
conn_peri_base = <0x18820000 7 0xffff0000>;
|
|
topckgen_base = <0x18830000 8 0xffff0000>;
|
|
kp_base = <0x18840000 9 0xffff0000>;
|
|
scp_sram_base = <0x10000000 10 0xffff0000>;
|
|
infra_na3_base = <0x10010000 11 0xffff0000>;
|
|
infra_na4_base = <0x10020000 12 0xffff0000>;
|
|
scp_base = <0x10030000 13 0xffff0000>;
|
|
mcucfg_base = <0x10040000 14 0xffff0000>;
|
|
gcpu_base = <0x10050000 15 0xffff0000>;
|
|
usb0_base = <0x10200000 16 0xffff0000>;
|
|
usb_sif_base = <0x10280000 17 0xffff0000>;
|
|
audio_base = <0x17000000 18 0xffff0000>;
|
|
vdec_base = <0x17010000 19 0xffff0000>;
|
|
msdc2_base = <0x17020000 20 0xffff0000>;
|
|
vdec1_base = <0x17030000 21 0xffff0000>;
|
|
msdc3_base = <0x18000000 22 0xffff0000>;
|
|
ap_dma_base = <0x18010000 23 0xffff0000>;
|
|
gce_base = <0x18020000 24 0xffff0000>;
|
|
vdec2_base = <0x18040000 25 0xffff0000>;
|
|
vdec3_base = <0x18050000 26 0xffff0000>;
|
|
camsys_base = <0x18080000 27 0xffff0000>;
|
|
camsys1_base = <0x180a0000 28 0xffff0000>;
|
|
camsys2_base = <0x180b0000 29 0xffff0000>;
|
|
dip_cq_thread0_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT0>;
|
|
dip_cq_thread1_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT1>;
|
|
dip_cq_thread2_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT2>;
|
|
dip_cq_thread3_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT3>;
|
|
dip_cq_thread4_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT4>;
|
|
dip_cq_thread5_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT5>;
|
|
dip_cq_thread6_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT6>;
|
|
dip_cq_thread7_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT7>;
|
|
dip_cq_thread8_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT8>;
|
|
dip_cq_thread9_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT9>;
|
|
dip_cq_thread10_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT10>;
|
|
dip_cq_thread11_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT11>;
|
|
dip_cq_thread12_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT12>;
|
|
dip_cq_thread13_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT13>;
|
|
dip_cq_thread14_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT14>;
|
|
dip_cq_thread15_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT15>;
|
|
dip_cq_thread16_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT16>;
|
|
dip_cq_thread17_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT17>;
|
|
dip_cq_thread18_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG1_EVENT18>;
|
|
dip2_cq_thread21_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG2_EVENT21>;
|
|
dip2_cq_thread23_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG2_EVENT23>;
|
|
wpe_b_frame_done =
|
|
<CMDQ_EVENT_GCE_IMG2_EVENT22>;
|
|
mdp_rdma0_sof = <256>;
|
|
mdp_aal_sof = <258>;
|
|
mdp_hdr0_sof = <260>;
|
|
mdp_rsz0_sof = <261>;
|
|
mdp_rsz1_sof = <262>;
|
|
mdp_wrot0_sof = <263>;
|
|
mdp_wrot1_sof = <264>;
|
|
mdp_tdshp_sof = <265>;
|
|
img_dl_relay_sof = <267>;
|
|
img_dl_relay1_sof = <268>;
|
|
mdp_wrot1_write_frame_done = <290>;
|
|
mdp_wrot0_write_frame_done = <291>;
|
|
mdp_tdshp_frame_done = <295>;
|
|
mdp_rsz1_frame_done = <298>;
|
|
mdp_rsz0_frame_done = <299>;
|
|
mdp_rdma0_frame_done = <303>;
|
|
mdp_hdr0_frame_done = <305>;
|
|
mdp_aal_frame_done = <310>;
|
|
dre30_hist_sram_start = <1536>;
|
|
};
|
|
|
|
reserved@1b004000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1b004000 0 0x1000>;
|
|
};
|
|
|
|
mdp_aal0: mdp_aal0@1b005000 {
|
|
compatible = "mediatek,mdp_aal0";
|
|
reg = <0 0x1b005000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_AAL0>;
|
|
clock-names = "MDP_AAL0";
|
|
};
|
|
|
|
reserved@1b006000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1b006000 0 0x1000>;
|
|
};
|
|
|
|
mdp_hdr0: mdp_hdr0@1b007000 {
|
|
compatible = "mediatek,mdp_hdr0";
|
|
reg = <0 0x1b007000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_HDR0>;
|
|
clock-names = "MDP_HDR0";
|
|
};
|
|
|
|
mdp_rsz0: mdp_rsz@1b008000 {
|
|
compatible = "mediatek,mdp_rsz0";
|
|
reg = <0 0x1b008000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_RSZ0>;
|
|
clock-names = "MDP_RSZ0";
|
|
};
|
|
|
|
mdp_rsz1: mdp_rsz1@1bf009000 {
|
|
compatible = "mediatek,mdp_rsz1";
|
|
reg = <0 0x1b009000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_RSZ1>;
|
|
clock-names = "MDP_RSZ1";
|
|
};
|
|
|
|
mdp_wrot0: mdp_wrot0@1b00a000 {
|
|
compatible = "mediatek,mdp_wrot0";
|
|
reg = <0 0x1b00a000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_WROT0>;
|
|
clock-names = "MDP_WROT0";
|
|
};
|
|
|
|
mdp_wrot1: mdp_wrot1@1b00b000 {
|
|
compatible = "mediatek,mdp_wrot1";
|
|
reg = <0 0x1b00b000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_WROT1>;
|
|
clock-names = "MDP_WROT1";
|
|
};
|
|
|
|
mdp_tdshp0: mdp_tdshp0@1b00c000 {
|
|
compatible = "mediatek,mdp_tdshp0";
|
|
reg = <0 0x1b00c000 0 0x1000>;
|
|
clocks = <&mdpsys_config CLK_MDP_TDSHP0>;
|
|
clock-names = "MDP_TDSHP0";
|
|
};
|
|
|
|
reserved@1b00d000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1b00d000 0 0x1000>;
|
|
};
|
|
|
|
reserved@1b00e000 {
|
|
compatible = "mediatek,reserved";
|
|
reg = <0 0x1b00e000 0 0x1000>;
|
|
};
|
|
|
|
ipesys_config@1c000000 {
|
|
compatible = "mediatek,ipesys_config";
|
|
reg = <0 0x1c000000 0 0x1000>;
|
|
};
|
|
|
|
fdvt@1c001000 {
|
|
compatible = "mediatek,fdvt";
|
|
reg = <0 0x1c001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ipesys CLK_IPE_FD>;
|
|
clock-names = "FD_CLK_IPE_FD";
|
|
#if defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
mboxes = <&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox_sec 11 0 CMDQ_THR_PRIO_1>;
|
|
#else
|
|
mboxes = <&gce_mbox 14 0 CMDQ_THR_PRIO_1>;
|
|
#endif
|
|
fdvt_frame_done = <CMDQ_EVENT_FDVT_DONE>;
|
|
};
|
|
|
|
fe@1c002000 {
|
|
compatible = "mediatek,fe";
|
|
reg = <0 0x1c002000 0 0x1000>;
|
|
};
|
|
|
|
rsc@1c003000 {
|
|
compatible = "mediatek,rsc";
|
|
reg = <0 0x1c003000 0 0x1000>;
|
|
mediatek,larb = <&smi_larb20>;
|
|
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
|
|
mboxes = <&gce_mbox 13 0 CMDQ_THR_PRIO_1>;
|
|
gce-event-names = "rsc_eof";
|
|
gce-events = <&gce_mbox CMDQ_EVENT_RSC_DONE>;
|
|
clocks = <&ipesys CLK_IPE_RSC>;
|
|
clock-names = "RSC_CLK_IPE_RSC";
|
|
};
|
|
|
|
ipe_smi_subcom@1c00e000 {
|
|
compatible = "mediatek,ipe_smi_subcom", "mediatek,smi_common";
|
|
reg = <0 0x1c00e000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_IPE>,
|
|
<&ipesys CLK_IPE_SMI_SUBCOM>;
|
|
clock-names = "scp-ipe", "ipe-smisubcom";
|
|
mediatek,smi-id = <25>;
|
|
};
|
|
|
|
smi_larb8@17011000 {
|
|
compatible = "mediatek,smi_larb8", "mediatek,smi_larb";
|
|
reg = <0 0x17011000 0 0x1000>;
|
|
mediatek,larb-id = <8>;
|
|
clocks = <&scpsys SCP_SYS_VEN>;
|
|
clock-names = "scp-venc";
|
|
mediatek,smi-id = <8>;
|
|
};
|
|
|
|
depth@1c100000 {
|
|
compatible = "mediatek,depth";
|
|
reg = <0 0x1c100000 0 0x1000>;
|
|
};
|
|
|
|
subpmic_pmu_eint: mt6370_pmu_eint {
|
|
};
|
|
|
|
gps: gps@18c00000 {
|
|
compatible = "mediatek,gps";
|
|
};
|
|
|
|
odm: odm {
|
|
compatible = "simple-bus";
|
|
/* reserved for overlay by odm */
|
|
};
|
|
|
|
ssmr {
|
|
compatible = "mediatek,trusted_mem";
|
|
memory-region = <&ssmr_cma_mem>;
|
|
};
|
|
|
|
memory_ssmr_features: memory-ssmr-features {
|
|
compatible = "mediatek,memory-ssmr-features";
|
|
svp-region-based-size = <0 0x10000000>;
|
|
iris-recognition-size = <0 0x10000000>;
|
|
2d_fr-size = <0 0>;
|
|
tui-size = <0 0x4000000>;
|
|
wfd-size = <0 0x4000000>;
|
|
prot-region-based-size = <0 0x8000000>;
|
|
ta-elf-size = <0 0x1000000>;
|
|
ta-stack-heap-size = <0 0x6000000>;
|
|
sdsp-tee-sharedmem-size = <0 0x1000000>;
|
|
sdsp-firmware-size = <0 0x1000000>;
|
|
};
|
|
|
|
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
|
|
compatible = "mediatek,pmic_clock_buffer";
|
|
mediatek,clkbuf-quantity = <7>;
|
|
mediatek,clkbuf-config = <2 1 1 2 0 0 0>;
|
|
mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
|
|
};
|
|
|
|
/* ATF logger */
|
|
atf_logger {
|
|
compatible = "mediatek,atf_logger";
|
|
};
|
|
|
|
md_auxadc:md_auxadc {
|
|
compatible = "mediatek,md_auxadc";
|
|
io-channels = <&auxadc 2>;
|
|
io-channel-names = "md-channel";
|
|
};
|
|
|
|
gpio_usage_mapping: gpio_usage_mapping {
|
|
compatible = "mediatek,gpio_usage_mapping";
|
|
};
|
|
|
|
mrdump_ext_rst: mrdump_ext_rst {
|
|
compatible = "mediatek, mrdump_ext_rst-eint";
|
|
mode = "IRQ";
|
|
status = "okay";
|
|
};
|
|
|
|
gyro:gyro {
|
|
};
|
|
|
|
msdc1_ins: msdc1_ins {
|
|
};
|
|
|
|
touch: touch {
|
|
compatible = "goodix,touch", "mediatek,touch";
|
|
};
|
|
|
|
smart_pa: smart_pa {
|
|
};
|
|
|
|
md1_sim1_hot_plug_eint:md1_sim1_hot_plug_eint{
|
|
};
|
|
|
|
md1_sim2_hot_plug_eint:md1_sim2_hot_plug_eint{
|
|
};
|
|
|
|
mt_charger: mt_charger {
|
|
compatible = "mediatek,mt-charger";
|
|
bootmode = <&chosen>;
|
|
};
|
|
|
|
lk_charger: lk_charger {
|
|
compatible = "mediatek,lk_charger";
|
|
enable_anime;
|
|
/* enable_pe_plus; */
|
|
enable_pd20_reset;
|
|
power_path_support;
|
|
max_charger_voltage = <6500000>;
|
|
fast_charge_voltage = <3000000>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
non_std_ac_charger_current = <500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
ta_ac_charger_current = <3000000>;
|
|
pd_charger_current = <500000>;
|
|
|
|
/* battery temperature protection */
|
|
temp_t4_threshold = <50>;
|
|
temp_t3_threshold = <45>;
|
|
temp_t1_threshold = <0>;
|
|
};
|
|
|
|
charger: charger {
|
|
compatible = "mediatek,charger";
|
|
algorithm_name = "SwitchCharging2";
|
|
/* enable_sw_jeita; */
|
|
/* enable_pe_plus; */
|
|
/* enable_pe_2; */
|
|
/* enable_pe_3; */
|
|
/* enable_pe_4; */
|
|
enable_type_c;
|
|
power_path_support;
|
|
enable_dynamic_mivr;
|
|
bootmode = <&chosen>;
|
|
|
|
/* common */
|
|
battery_cv = <4350000>;
|
|
max_charger_voltage = <6500000>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* dynamic mivr */
|
|
min_charger_voltage_1 = <4400000>;
|
|
min_charger_voltage_2 = <4200000>;
|
|
max_dmivr_charger_current = <1400000>;
|
|
|
|
/* charging current */
|
|
usb_charger_current_suspend = <0>;
|
|
usb_charger_current_unconfigured = <70000>;
|
|
usb_charger_current_configured = <500000>;
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
non_std_ac_charger_current = <500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
apple_1_0a_charger_current = <650000>;
|
|
apple_2_1a_charger_current = <800000>;
|
|
ta_ac_charger_current = <3000000>;
|
|
|
|
/* sw jeita */
|
|
jeita_temp_above_t4_cv = <4240000>;
|
|
jeita_temp_t3_to_t4_cv = <4240000>;
|
|
jeita_temp_t2_to_t3_cv = <4340000>;
|
|
jeita_temp_t1_to_t2_cv = <4240000>;
|
|
jeita_temp_t0_to_t1_cv = <4040000>;
|
|
jeita_temp_below_t0_cv = <4040000>;
|
|
temp_t4_thres = <50>;
|
|
temp_t4_thres_minus_x_degree = <47>;
|
|
temp_t3_thres = <45>;
|
|
temp_t3_thres_minus_x_degree = <39>;
|
|
temp_t2_thres = <10>;
|
|
temp_t2_thres_plus_x_degree = <16>;
|
|
temp_t1_thres = <0>;
|
|
temp_t1_thres_plus_x_degree = <6>;
|
|
temp_t0_thres = <0>;
|
|
temp_t0_thres_plus_x_degree = <0>;
|
|
temp_neg_10_thres = <0>;
|
|
|
|
/* battery temperature protection */
|
|
enable_min_charge_temp;
|
|
min_charge_temp = <0>;
|
|
min_charge_temp_plus_x_degree = <6>;
|
|
max_charge_temp = <50>;
|
|
max_charge_temp_minus_x_degree = <47>;
|
|
|
|
/* PE */
|
|
ta_12v_support;
|
|
ta_9v_support;
|
|
pe_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_ac_12v_input_current = <3200000>;
|
|
ta_ac_9v_input_current = <3200000>;
|
|
ta_ac_7v_input_current = <3200000>;
|
|
|
|
/* PE 2.0 */
|
|
pe20_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
|
|
/* PE 4.0 */
|
|
high_temp_to_leave_pe40 = <46>;
|
|
high_temp_to_enter_pe40 = <39>;
|
|
low_temp_to_leave_pe40 = <10>;
|
|
low_temp_to_enter_pe40 = <16>;
|
|
|
|
/* PE 4.0 single charger*/
|
|
pe40_single_charger_input_current = <3000000>;
|
|
pe40_single_charger_current = <3000000>;
|
|
|
|
/* PE 4.0 dual charger*/
|
|
pe40_dual_charger_input_current = <3000000>;
|
|
pe40_dual_charger_chg1_current = <2000000>;
|
|
pe40_dual_charger_chg2_current = <2000000>;
|
|
pe40_stop_battery_soc = <80>;
|
|
|
|
/* PE 4.0 cable impedance (mohm) */
|
|
pe40_r_cable_1a_lower = <559>;
|
|
pe40_r_cable_2a_lower = <420>;
|
|
pe40_r_cable_3a_lower = <279>;
|
|
|
|
/* dual charger */
|
|
chg1_ta_ac_charger_current = <1500000>;
|
|
chg2_ta_ac_charger_current = <1500000>;
|
|
slave_mivr_diff = <100000>;
|
|
dual_polling_ieoc = <750000>;
|
|
|
|
/* cable measurement impedance */
|
|
cable_imp_threshold = <699>;
|
|
vbat_cable_imp_threshold = <3900000>; /* uV */
|
|
|
|
/* bif */
|
|
bif_threshold1 = <4250000>;
|
|
bif_threshold2 = <4300000>;
|
|
bif_cv_under_threshold2 = <4450000>;
|
|
|
|
/* PD */
|
|
pd_vbus_low_bound = <5000000>;
|
|
pd_vbus_upper_bound = <5000000>;
|
|
pd_ichg_level_threshold = <1000000>; /* uA */
|
|
pd_stop_battery_soc = <80>;
|
|
|
|
ibus_err = <14>;
|
|
vsys_watt = <5000000>;
|
|
};
|
|
|
|
pd_adapter: pd_adapter {
|
|
compatible = "mediatek,pd_adapter";
|
|
adapter_name = "pd_adapter";
|
|
};
|
|
|
|
extcon_usb: extcon_usb {
|
|
compatible = "mediatek,extcon-usb";
|
|
charger = <&mt6370_chg>;
|
|
dev-conn = <&usb>;
|
|
mediatek,bypss-typec-sink = <1>;
|
|
};
|
|
|
|
rt-pd-manager {
|
|
compatible = "mediatek,rt-pd-manager";
|
|
};
|
|
|
|
mtee_svp: mtee_svp {
|
|
compatible = "medaitek,svp";
|
|
};
|
|
/* svp end */
|
|
};
|
|
|
|
&i2c6 {
|
|
speaker_amp: speaker_amp@34 {
|
|
compatible = "mediatek,speaker_amp";
|
|
#sound-dai-cells = <0>;
|
|
reg = <0x34>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&pio {
|
|
aud_clk_mosi_off: aud_clk_mosi_off {
|
|
pins_cmd0_dat {
|
|
pinmux = <PINMUX_GPIO183__FUNC_GPIO183>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO184__FUNC_GPIO184>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_clk_mosi_on: aud_clk_mosi_on {
|
|
pins_cmd0_dat {
|
|
pinmux = <PINMUX_GPIO183__FUNC_AUD_CLK_MOSI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO184__FUNC_AUD_SYNC_MOSI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_mosi_off: aud_dat_mosi_off {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO185__FUNC_GPIO185>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO186__FUNC_GPIO186>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_mosi_on: aud_dat_mosi_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO185__FUNC_AUD_DAT_MOSI0>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO186__FUNC_AUD_DAT_MOSI1>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso0_off: aud_dat_miso0_off {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO189__FUNC_GPIO189>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_miso0_on: aud_dat_miso0_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO189__FUNC_AUD_DAT_MISO0>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_dat_miso1_off: aud_dat_miso1_off {
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO190__FUNC_GPIO190>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_dat_miso1_on: aud_dat_miso1_on {
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO190__FUNC_AUD_DAT_MISO1>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
vow_dat_miso_off: vow_dat_miso_off {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO189__FUNC_GPIO189>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
vow_dat_miso_on: vow_dat_miso_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO189__FUNC_VOW_DAT_MISO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
vow_clk_miso_off: vow_clk_miso_off {
|
|
pins_cmd3_dat {
|
|
pinmux = <PINMUX_GPIO190__FUNC_GPIO190>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
vow_clk_miso_on: vow_clk_miso_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO190__FUNC_VOW_CLK_MISO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_gpio_i2s0_off: aud_gpio_i2s0_off {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO59__FUNC_GPIO59>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_gpio_i2s0_on: aud_gpio_i2s0_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO59__FUNC_I2S0_DI>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
aud_gpio_i2s1_off: aud_gpio_i2s1_off {
|
|
};
|
|
aud_gpio_i2s1_on: aud_gpio_i2s1_on {
|
|
};
|
|
aud_gpio_i2s2_off: aud_gpio_i2s2_off {
|
|
};
|
|
aud_gpio_i2s2_on: aud_gpio_i2s2_on {
|
|
};
|
|
aud_gpio_i2s3_off: aud_gpio_i2s3_off {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
pins_cmd3_dat {
|
|
pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
|
|
input-enable;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
aud_gpio_i2s3_on: aud_gpio_i2s3_on {
|
|
pins_cmd1_dat {
|
|
pinmux = <PINMUX_GPIO56__FUNC_I2S3_DO>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins_cmd2_dat {
|
|
pinmux = <PINMUX_GPIO57__FUNC_I2S3_BCK>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
pins_cmd3_dat {
|
|
pinmux = <PINMUX_GPIO58__FUNC_I2S3_LRCK>;
|
|
input-schmitt-enable;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "mediatek/mt6366.dtsi"
|
|
#include "mediatek/cust_mt6781_msdc.dtsi"
|
|
#include "mediatek/mt6370.dtsi"
|
|
#include "mediatek/mt6370_pd.dtsi"
|
|
#include "mediatek/mt6781-clkitg.dtsi"
|
|
#include "mediatek/rt5133_for_6781.dtsi"
|
|
#ifdef CONFIG_MTK_ENABLE_GENIEZONE
|
|
#include "mediatek/trusty.dtsi"
|
|
#endif
|
|
|