764 lines
14 KiB
C
764 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/syscore_ops.h>
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#include <linux/version.h>
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#define WARN_ON_CHECK_PLL_FAIL 0
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#define CLKDBG_CCF_API_4_4 1
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#include "clk-mt6781-pg.h"
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#define TAG "[clkchk] "
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#if !CLKDBG_CCF_API_4_4
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/* backward compatible */
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static const char *clk_hw_get_name(const struct clk_hw *hw)
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{
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return __clk_get_name(hw->clk);
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}
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static bool clk_hw_is_prepared(const struct clk_hw *hw)
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{
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return __clk_is_prepared(hw->clk);
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}
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static bool clk_hw_is_enabled(const struct clk_hw *hw)
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{
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return __clk_is_enabled(hw->clk);
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}
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#endif /* !CLKDBG_CCF_API_4_4 */
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static const char * const *get_all_clk_names(void)
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{
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static const char * const clks[] = {
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/* plls */
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"mainpll",
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"univ2pll",
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"mfgpll",
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"msdcpll",
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"adsppll",
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"mmpll",
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"apll1",
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"apll2",
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/* apmixedsys */
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"apmixed_ssusb26m",
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"apmixed_appll26m",
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"apmixed_mipic026m",
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"apmixed_mdpll26m",
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"apmixed_mmsys26m",
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"apmixed_ufs26m",
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"apmixed_mipic126m",
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"apmixed_mempll26m",
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"apmixed_lvpll26m",
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"apmixed_mipid026m",
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"apmixed_mipid126m",
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/* TOP */
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"fpwrap_ulposc_sel",
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"aud_intbus_sel",
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"audio_h_sel",
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"aud_2_sel",
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"aud_eng2_sel",
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"aud_1_sel",
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"aud_eng1_sel",
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"mdp_sel",
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"disp_sel",
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"venc_sel",
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"adsp_sel",
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"msdc50_0_sel",
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"msdc30_1_sel",
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"mfg_sel",
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"i2c_sel",
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"usb_top_sel",
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"aes_fde_sel",
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"aes_msdcfde_sel",
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"seninf3_sel",
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"seninf2_sel",
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"seninf1_sel",
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"seninf_sel",
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"camtg6_sel",
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"camtg5_sel",
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"camtg4_sel",
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"camtg3_sel",
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"camtg2_sel",
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"camtg1_sel",
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"camtg_sel",
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"vdec_sel",
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"ipe_sel",
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"img1_sel",
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"cam_sel",
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"ufs_sel",
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"dxcc_sel",
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"msdc50_0_hclk_sel",
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"dpmaif_sel",
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"spi_sel",
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"axi_sel",
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"spm_sel",
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"spmi_mst_sel",
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"dsi_occ_sel",
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"dvfsrc_sel",
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"camtm_sel",
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"pwm_sel",
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"sspm_sel",
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"disppwm_sel",
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"audio_sel",
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"uart_sel",
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"scp_sel",
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"srck_sel",
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/* INFRACFG */
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"infra_pmic_tmr",
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"infra_pmic_ap",
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"infra_pmic_md",
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"infra_pmic_conn",
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"infra_scp",
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"infra_sej",
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"infra_apxgpt",
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"infra_icusb",
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"infra_gce",
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"infra_therm",
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"infra_i2c_ap",
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"infra_i2c_ccu",
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"infra_i2c_sspm",
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"infra_i2c_rsv",
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"infra_pwm_hclk",
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"infra_pwm1",
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"infra_pwm2",
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"infra_pwm3",
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"infra_pwm4",
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"infra_pwm5",
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"infra_pwm",
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"infra_uart0",
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"infra_uart1",
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"infra_uart2",
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"infra_uart3",
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"infra_gce_26m",
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"infra_cqdma_fpc",
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"infra_btif",
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"infra_spi0",
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"infra_msdc0",
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"infra_msdcfde",
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"infra_msdc1",
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"infra_msdc2",
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"infra_msdc0_sck",
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"infra_dvfsrc",
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"infra_gcpu",
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"infra_trng",
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"infra_auxadc",
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"infra_cpum",
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"infra_ccif1_ap",
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"infra_ccif1_md",
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"infra_auxadc_md",
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"infra_msdc1_sck",
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"infra_msdc2_sck",
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"infra_apdma",
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"infra_xiu",
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"infra_devapc",
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"infra_ccif_ap",
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"infra_debugsys",
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"infra_audio",
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"infra_ccif_md",
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"infra_dxcc_sec_core",
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"infra_dxcc_ao",
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"infra_imp_iic",
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"infra_devmpu_bclk",
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"infra_dramc_f26m",
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"infra_pwm_bclk6",
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"infra_usb",
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"infra_disppwm",
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"infra_cldma_bclk",
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"infra_spi1",
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"infra_i2c4",
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"infra_spi2",
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"infra_spi3",
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"infra_unipro_sck",
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"infra_unipro_tick",
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"infra_md32_bclk",
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"infra_sspm",
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"infra_unipro_mbist",
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"infra_sspm_bus_hclk",
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"infra_i2c5",
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"infra_i2c5_arbiter",
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"infra_i2c5_imm",
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"infra_i2c1_arbiter",
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"infra_i2c1_imm",
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"infra_i2c2_arbiter",
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"infra_i2c2_imm",
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"infra_spi4",
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"infra_spi5",
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"infra_cqdma",
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"infra_bist2fpc",
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"infra_aes_ufs",
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"infra_ufs",
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"infra_ufs_tick",
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"infra_msdc0_self",
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"infra_msdc1_self",
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"infra_msdc2_self",
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"infra_sspm_26m_self",
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"infra_sspm_32k_self",
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"infra_ufs_axi",
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"infra_i2c6",
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"infra_ap_msdc0",
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"infra_md_msdc0",
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"infra_msdc0_srclk",
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"infra_msdc1_srclk",
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"infra_pwrap_tmr_fo",
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"infra_pwrap_spi_fo",
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"infra_pwrap_sys_fo",
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"infra_sej_f13m",
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"infra_aes_top0_bclk",
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"infra_mcupm_bclk",
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"infra_ccif2_ap",
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"infra_ccif2_md",
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"infra_ccif3_ap",
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"infra_ccif3_md",
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"infra_fadsp_26m",
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"infra_fadsp_32k",
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"infra_ccif4_ap",
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"infra_ccif4_md",
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"infra_dpmaif",
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"infra_fadsp",
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/* AUDIO */
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"aud_afe",
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"aud_22m",
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"aud_24m",
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"aud_apll2_tuner",
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"aud_apll_tuner",
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"aud_tdm",
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"aud_adc",
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"aud_dac",
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"aud_dac_predis",
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"aud_tml",
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"aud_nle",
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"aud_i2s1_bclk",
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"aud_i2s2_bclk",
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"aud_i2s3_bclk",
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"aud_i2s4_bclk",
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"aud_i2s5_bclk",
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"aud_conn_i2s",
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"aud_general1",
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"aud_general2",
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"aud_dac_hires",
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"aud_adc_hires",
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"aud_adc_hires_tml",
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"aud_pdn_adda6_adc",
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"aud_adda6_adc_hires",
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"aud_3rd_dac",
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"aud_3rd_dac_predis",
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"aud_3rd_dac_tml",
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"aud_3rd_dac_hires",
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"aud_etdm_out1_bclk",
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"aud_etdm_in1_bclk",
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/* CAM */
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"cam_m_larb13",
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"cam_m_dfpvad",
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"cam_m_larb14",
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"cam_m_cam",
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"cam_m_camtg",
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"cam_m_seninf",
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"cam_m_camsv1",
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"cam_m_camsv2",
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"cam_m_camsv3",
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"cam_m_ccu0",
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"cam_m_ccu1",
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"cam_m_mraw0",
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"cam_m_fake_eng",
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"cam_m_ccu_gals",
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"cam_m_cam2mm_gals",
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/* CAM_RAWA */
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"cam_ra_larbx",
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"cam_ra_cam",
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"cam_ra_camtg",
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/* CAM_RAWB */
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"cam_rb_larbx",
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"cam_rb_cam",
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"cam_rb_camtg",
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/* IMG */
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"imgsys1_larb9",
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"imgsys1_larb10",
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"imgsys1_dip",
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"imgsys1_gals",
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/* IMG2 */
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"imgsys2_larb9",
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"imgsys2_larb10",
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"imgsys2_mfb",
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"imgsys2_wpe",
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"imgsys2_mss",
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"imgsys2_gals",
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/* IPE */
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"ipe_larb19",
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"ipe_larb20",
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"ipe_smi_subcom",
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"ipe_fd",
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"ipe_fe",
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"ipe_rsc",
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"ipe_dpe",
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"ipe_gals",
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/* MFG */
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"mfg_cfg_bg3d",
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/* MM0 */
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"mm_disp_mutex0",
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"mm_apb_bus",
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"mm_disp_ovl0",
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"mm_disp_rdma0",
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"mm_disp_ovl0_2l",
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"mm_disp_wdma0",
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"mm_disp_ccorr1",
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"mm_disp_rsz0",
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"mm_disp_aal0",
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"mm_disp_ccorr0",
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"mm_disp_color0",
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"mm_smi_infra",
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"mm_disp_dsc_wrap",
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"mm_disp_gamma0",
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"mm_disp_postmask0",
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"mm_disp_spr0",
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"mm_disp_dither0",
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"mm_smi_common",
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"mm_disp_cm0",
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"mm_dsi0",
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"mm_disp_fake_eng0",
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"mm_disp_fake_eng1",
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"mm_smi_gals",
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"mm_smi_iommu",
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/* MM1 */
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"mm_dsi0_dsi_domain",
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"mm_disp_26m_ck",
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/* MDP0 */
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"mdp_rdma0",
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"mdp_tdshp0",
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"mdp_img_dl_async0",
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"mdp_img_dl_async1",
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"mdp_rdma1",
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"mdp_tdshp1",
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"mdp_smi0",
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"mdp_apb_bus",
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"mdp_wrot0",
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"mdp_rsz0",
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"mdp_hdr0",
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"mdp_mutex0",
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"mdp_wrot1",
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"mdp_rsz1",
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"mdp_fake_eng0",
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"mdp_aal0",
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"mdp_aal1",
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"mdp_color0",
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/* MDP1 */
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"mdp_img_dl_rel0_as0",
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"mdp_img_dl_rel1_as1",
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/* VDEC */
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"vdec_cken",
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"vdec_larb1_cken",
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"vdec_lat_cken",
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/* VENC */
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"venc_larb",
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"venc_venc",
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"venc_jpgenc",
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"venc_gals",
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/* SCPSYS */
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"pg_md1",
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"pg_conn",
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"pg_dis",
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"pg_cam",
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"pg_cam_rawa",
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"pg_cam_rawb",
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"pg_isp",
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"pg_isp2",
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"pg_ipe",
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"pg_ven",
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"pg_vde",
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"pg_mfg0",
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"pg_mfg1",
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"pg_mfg2",
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"pg_mfg3",
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"pg_csi",
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/* end */
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NULL
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};
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return clks;
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}
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static const char *ccf_state(struct clk_hw *hw)
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{
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if (__clk_get_enable_count(hw->clk))
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return "enabled";
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if (clk_hw_is_prepared(hw))
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return "prepared";
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return "disabled";
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}
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static void print_enabled_clks(void)
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{
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const char * const *cn = get_all_clk_names();
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pr_notice("enabled clks:\n");
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for (; *cn; cn++) {
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struct clk *c = __clk_lookup(*cn);
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struct clk_hw *c_hw = __clk_get_hw(c);
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struct clk_hw *p_hw;
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if (IS_ERR_OR_NULL(c) || !c_hw)
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continue;
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p_hw = clk_hw_get_parent(c_hw);
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if (!p_hw)
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continue;
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/*if (!clk_hw_is_prepared(c_hw) && !__clk_get_enable_count(c))*/
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if (!__clk_get_enable_count(c))
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continue;
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pr_notice("[%-17s: %8s, %3d, %3d, %10ld, %17s]\n",
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clk_hw_get_name(c_hw),
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ccf_state(c_hw),
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clk_hw_is_prepared(c_hw),
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__clk_get_enable_count(c),
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clk_hw_get_rate(c_hw),
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p_hw ? clk_hw_get_name(p_hw) : "- ");
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}
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}
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static void check_pll_off(void)
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{
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static const char * const off_pll_names[] = {
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"univ2pll",
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"mfgpll",
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"msdcpll",
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"tvdpll",
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"adsppll",
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"mmpll",
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"apll1",
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"apll2",
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NULL
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};
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static struct clk *off_plls[ARRAY_SIZE(off_pll_names)];
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struct clk **c;
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int invalid = 0;
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char buf[128] = {0};
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int n = 0;
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if (!off_plls[0]) {
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const char * const *pn;
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for (pn = off_pll_names, c = off_plls; *pn; pn++, c++)
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*c = __clk_lookup(*pn);
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}
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for (c = off_plls; *c; c++) {
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struct clk_hw *c_hw = __clk_get_hw(*c);
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if (!c_hw)
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continue;
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/*if (!clk_hw_is_prepared(c_hw) && !clk_hw_is_enabled(c_hw))*/
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if (!clk_hw_is_enabled(c_hw))
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continue;
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n += snprintf(buf + n, sizeof(buf) - n, "%s ",
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clk_hw_get_name(c_hw));
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invalid++;
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}
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if (invalid) {
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pr_notice("unexpected unclosed PLL: %s\n", buf);
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print_enabled_clks();
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#if WARN_ON_CHECK_PLL_FAIL
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WARN_ON(1);
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#endif
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}
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}
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void print_enabled_clks_once(void)
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{
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static bool first_flag = true;
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if (first_flag) {
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first_flag = false;
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print_enabled_clks();
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}
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}
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static int clkchk_syscore_suspend(void)
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{
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check_pll_off();
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return 0;
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}
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static void clkchk_syscore_resume(void)
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{
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}
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static struct syscore_ops clkchk_syscore_ops = {
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.suspend = clkchk_syscore_suspend,
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.resume = clkchk_syscore_resume,
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};
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static int __init clkchk_init(void)
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{
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if (!of_machine_is_compatible("mediatek,mt6781"))
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return -ENODEV;
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register_syscore_ops(&clkchk_syscore_ops);
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return 0;
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}
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subsys_initcall(clkchk_init);
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/*
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* Before MTCMOS off procedure, perform the Subsys CGs sanity check.
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*/
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struct pg_check_swcg {
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struct clk *c;
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const char *name;
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};
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#define SWCG(_name) { \
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.name = _name, \
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}
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struct subsys_cgs_check {
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enum subsys_id id; /* the Subsys id */
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struct pg_check_swcg *swcgs; /* those CGs that would be checked */
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char *subsys_name; /*
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* subsys_name is used in
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* print_subsys_reg() and can be NULL
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* if not porting ready yet.
|
|
*/
|
|
};
|
|
|
|
/*
|
|
* The clk names in Mediatek CCF.
|
|
*/
|
|
struct pg_check_swcg mm_mdp_swcgs[] = {
|
|
SWCG("mm_disp_mutex0"),
|
|
SWCG("mm_apb_bus"),
|
|
SWCG("mm_disp_ovl0"),
|
|
SWCG("mm_disp_rdma0"),
|
|
SWCG("mm_disp_ovl0_2l"),
|
|
SWCG("mm_disp_wdma0"),
|
|
SWCG("mm_disp_ccorr1"),
|
|
SWCG("mm_disp_rsz0"),
|
|
SWCG("mm_disp_aal0"),
|
|
SWCG("mm_disp_ccorr0"),
|
|
SWCG("mm_disp_color0"),
|
|
SWCG("mm_smi_infra"),
|
|
SWCG("mm_disp_dsc_wrap"),
|
|
SWCG("mm_disp_gamma0"),
|
|
SWCG("mm_disp_postmask0"),
|
|
SWCG("mm_disp_spr0"),
|
|
SWCG("mm_disp_dither0"),
|
|
SWCG("mm_smi_common"),
|
|
SWCG("mm_disp_cm0"),
|
|
SWCG("mm_dsi0"),
|
|
SWCG("mm_disp_fake_eng0"),
|
|
SWCG("mm_disp_fake_eng1"),
|
|
SWCG("mm_smi_gals"),
|
|
SWCG("mm_smi_iommu"),
|
|
SWCG("mm_dsi0_dsi_domain"),
|
|
SWCG("mm_disp_26m_ck"),
|
|
SWCG("mdp_rdma0"),
|
|
SWCG("mdp_tdshp0"),
|
|
SWCG("mdp_img_dl_async0"),
|
|
SWCG("mdp_img_dl_async1"),
|
|
SWCG("mdp_rdma1"),
|
|
SWCG("mdp_tdshp1"),
|
|
SWCG("mdp_smi0"),
|
|
SWCG("mdp_apb_bus"),
|
|
SWCG("mdp_wrot0"),
|
|
SWCG("mdp_rsz0"),
|
|
SWCG("mdp_hdr0"),
|
|
SWCG("mdp_mutex0"),
|
|
SWCG("mdp_wrot1"),
|
|
SWCG("mdp_rsz1"),
|
|
SWCG("mdp_fake_eng0"),
|
|
SWCG("mdp_aal0"),
|
|
SWCG("mdp_aal1"),
|
|
SWCG("mdp_color0"),
|
|
SWCG("mdp_img_dl_rel0_as0"),
|
|
SWCG("mdp_img_dl_rel1_as1"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg vdec_swcgs[] = {
|
|
SWCG("vdec_cken"),
|
|
SWCG("vdec_larb1_cken"),
|
|
SWCG("vdec_lat_cken"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg venc_swcgs[] = {
|
|
SWCG("venc_larb"),
|
|
SWCG("venc_venc"),
|
|
SWCG("venc_jpgenc"),
|
|
SWCG("venc_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct pg_check_swcg img1_swcgs[] = {
|
|
SWCG("imgsys1_larb9"),
|
|
SWCG("imgsys1_larb10"),
|
|
SWCG("imgsys1_dip"),
|
|
SWCG("imgsys1_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg img2_swcgs[] = {
|
|
SWCG("imgsys2_larb9"),
|
|
SWCG("imgsys2_larb10"),
|
|
SWCG("imgsys2_mfb"),
|
|
SWCG("imgsys2_wpe"),
|
|
SWCG("imgsys2_mss"),
|
|
SWCG("imgsys2_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg ipe_swcgs[] = {
|
|
SWCG("ipe_larb19"),
|
|
SWCG("ipe_larb20"),
|
|
SWCG("ipe_smi_subcom"),
|
|
SWCG("ipe_fd"),
|
|
SWCG("ipe_fe"),
|
|
SWCG("ipe_rsc"),
|
|
SWCG("ipe_dpe"),
|
|
SWCG("ipe_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg cam_swcgs[] = {
|
|
SWCG("cam_m_larb13"),
|
|
SWCG("cam_m_dfpvad"),
|
|
SWCG("cam_m_larb14"),
|
|
SWCG("cam_m_cam"),
|
|
SWCG("cam_m_camtg"),
|
|
SWCG("cam_m_seninf"),
|
|
SWCG("cam_m_camsv1"),
|
|
SWCG("cam_m_camsv2"),
|
|
SWCG("cam_m_camsv3"),
|
|
SWCG("cam_m_ccu0"),
|
|
SWCG("cam_m_ccu1"),
|
|
SWCG("cam_m_mraw0"),
|
|
SWCG("cam_m_fake_eng"),
|
|
SWCG("cam_m_ccu_gals"),
|
|
SWCG("cam_m_cam2mm_gals"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg cam_rawa_swcgs[] = {
|
|
SWCG("cam_ra_larbx"),
|
|
SWCG("cam_ra_cam"),
|
|
SWCG("cam_ra_camtg"),
|
|
SWCG(NULL),
|
|
};
|
|
struct pg_check_swcg cam_rawb_swcgs[] = {
|
|
SWCG("cam_rb_larbx"),
|
|
SWCG("cam_rb_cam"),
|
|
SWCG("cam_rb_camtg"),
|
|
SWCG(NULL),
|
|
};
|
|
|
|
struct subsys_cgs_check mtk_subsys_check[] = {
|
|
/*{SYS_DIS, mm_swcgs, NULL}, */
|
|
{SYS_DIS, mm_mdp_swcgs, "mmsys"},
|
|
{SYS_VDE, vdec_swcgs, "vdecsys"},
|
|
{SYS_VEN, venc_swcgs, "vencsys"},
|
|
{SYS_ISP, img1_swcgs, "img1sys"},
|
|
{SYS_ISP2, img2_swcgs, "img2sys"},
|
|
{SYS_IPE, ipe_swcgs, "ipesys"},
|
|
{SYS_CAM, cam_swcgs, "camsys"},
|
|
{SYS_CAM_RAWA, cam_rawa_swcgs, "cam_rawa_sys"},
|
|
{SYS_CAM_RAWB, cam_rawb_swcgs, "cam_rawb_sys"},
|
|
};
|
|
|
|
static unsigned int check_cg_state(struct pg_check_swcg *swcg)
|
|
{
|
|
int enable_count = 0;
|
|
|
|
if (!swcg)
|
|
return 0;
|
|
|
|
while (swcg->name) {
|
|
if (!IS_ERR_OR_NULL(swcg->c)) {
|
|
if (__clk_get_enable_count(swcg->c) > 0) {
|
|
pr_notice("%s[%-17s: %3d]\n",
|
|
__func__,
|
|
__clk_get_name(swcg->c),
|
|
__clk_get_enable_count(swcg->c));
|
|
enable_count++;
|
|
}
|
|
}
|
|
swcg++;
|
|
}
|
|
|
|
return enable_count;
|
|
}
|
|
|
|
void mtk_check_subsys_swcg(enum subsys_id id)
|
|
{
|
|
int i;
|
|
unsigned int ret = 0;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++) {
|
|
if (mtk_subsys_check[i].id != id)
|
|
continue;
|
|
|
|
/* check if Subsys CGs are still on */
|
|
ret = check_cg_state(mtk_subsys_check[i].swcgs);
|
|
if (ret) {
|
|
pr_notice("%s:(%d) warning!\n", __func__, id);
|
|
|
|
/* print registers dump */
|
|
if (mtk_subsys_check[i].subsys_name)
|
|
print_subsys_reg(
|
|
mtk_subsys_check[i].subsys_name);
|
|
}
|
|
break;
|
|
}
|
|
|
|
if (ret) {
|
|
pr_notice("%s(%d): %d\n", __func__, id, ret);
|
|
BUG_ON(1);
|
|
}
|
|
}
|
|
|
|
static void __init pg_check_swcg_init_common(struct pg_check_swcg *swcg)
|
|
{
|
|
if (!swcg)
|
|
return;
|
|
|
|
while (swcg->name) {
|
|
struct clk *c = __clk_lookup(swcg->name);
|
|
|
|
if (IS_ERR_OR_NULL(c))
|
|
pr_notice("[%17s: NULL]\n", swcg->name);
|
|
else
|
|
swcg->c = c;
|
|
swcg++;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Init procedure for CG checking before MTCMOS off.
|
|
*/
|
|
static int __init pg_check_swcg_init_mt6781(void)
|
|
{
|
|
/* fill the 'struct clk *' ptr of every CGs*/
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(mtk_subsys_check); i++)
|
|
pg_check_swcg_init_common(mtk_subsys_check[i].swcgs);
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(pg_check_swcg_init_mt6781);
|
|
|