513 lines
13 KiB
C
513 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#ifdef CONFIG_MTK_DEVAPC
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#include <mt-plat/devapc_public.h>
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#endif
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#include "clkdbg.h"
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#include "clkchk.h"
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#include "clk-fmeter.h"
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#define ALL_CLK_ON 0
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#define DUMP_INIT_STATE 0
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/*
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* clkdbg dump_regs
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*/
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enum {
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topckgen,
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infracfg,
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scpsys,
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apmixed,
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audio,
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mfgsys,
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mmsys,
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mdpsys,
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img1sys,
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img2sys,
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ipesys,
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camsys,
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cam_rawa_sys,
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cam_rawb_sys,
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cam_rawc_sys,
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vencsys,
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vdecsys,
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vdec_soc_sys,
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ipu_vcore,
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ipu_conn,
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ipu0,
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ipu1,
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};
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#define REGBASE_V(_phys, _id_name) { .phys = _phys, .name = #_id_name }
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/*
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* checkpatch.pl ERROR:COMPLEX_MACRO
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*
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* #define REGBASE(_phys, _id_name) [_id_name] = REGBASE_V(_phys, _id_name)
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*/
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static struct regbase rb[] = {
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[topckgen] = REGBASE_V(0x10000000, topckgen),
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[infracfg] = REGBASE_V(0x10001000, infracfg),
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[scpsys] = REGBASE_V(0x10006000, scpsys),
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[apmixed] = REGBASE_V(0x1000c000, apmixed),
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[audio] = REGBASE_V(0x11210000, audio),
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[mfgsys] = REGBASE_V(0x13fbf000, mfgsys),
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[mmsys] = REGBASE_V(0x14000000, mmsys),
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[mdpsys] = REGBASE_V(0x1F000000, mdpsys),
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[img1sys] = REGBASE_V(0x15020000, img1sys),
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[img2sys] = REGBASE_V(0x15820000, img2sys),
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[ipesys] = REGBASE_V(0x1b000000, ipesys),
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[camsys] = REGBASE_V(0x1a000000, camsys),
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[cam_rawa_sys] = REGBASE_V(0x1a04f000, cam_rawa_sys),
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[cam_rawb_sys] = REGBASE_V(0x1a06f000, cam_rawb_sys),
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[cam_rawc_sys] = REGBASE_V(0x1a08f000, cam_rawc_sys),
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[vencsys] = REGBASE_V(0x17000000, vencsys),
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[vdecsys] = REGBASE_V(0x1602f000, vdecsys),
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[vdec_soc_sys] = REGBASE_V(0x1600f000, vdec_soc_sys),
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[ipu_vcore] = REGBASE_V(0x19029000, ipu_vcore),
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[ipu_conn] = REGBASE_V(0x19020000, ipu_conn),
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[ipu0] = REGBASE_V(0x19030000, ipu0),
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[ipu1] = REGBASE_V(0x19031000, ipu1),
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{},
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};
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#define REGNAME(_base, _ofs, _name) \
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{ .base = &rb[_base], .ofs = _ofs, .name = #_name }
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static struct regname rn[] = {
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REGNAME(topckgen, 0x010, CLK_CFG_0),
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REGNAME(topckgen, 0x020, CLK_CFG_1),
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REGNAME(topckgen, 0x030, CLK_CFG_2),
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REGNAME(topckgen, 0x040, CLK_CFG_3),
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REGNAME(topckgen, 0x050, CLK_CFG_4),
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REGNAME(topckgen, 0x060, CLK_CFG_5),
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REGNAME(topckgen, 0x070, CLK_CFG_6),
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REGNAME(topckgen, 0x080, CLK_CFG_7),
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REGNAME(topckgen, 0x090, CLK_CFG_8),
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REGNAME(topckgen, 0x0A0, CLK_CFG_9),
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REGNAME(topckgen, 0x0B0, CLK_CFG_10),
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REGNAME(topckgen, 0x0C0, CLK_CFG_11),
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REGNAME(topckgen, 0x0D0, CLK_CFG_12),
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REGNAME(topckgen, 0x0E0, CLK_CFG_13),
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REGNAME(topckgen, 0x0F0, CLK_CFG_14),
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REGNAME(topckgen, 0x100, CLK_CFG_15),
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REGNAME(topckgen, 0x110, CLK_CFG_16),
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REGNAME(apmixed, 0x050, PLLON_CON0),
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REGNAME(apmixed, 0x054, PLLON_CON1),
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REGNAME(apmixed, 0x058, PLLON_CON2),
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REGNAME(apmixed, 0x05C, PLLON_CON3),
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REGNAME(apmixed, 0x208, ARMPLL_LL_CON0),
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REGNAME(apmixed, 0x20C, ARMPLL_LL_CON1),
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REGNAME(apmixed, 0x210, ARMPLL_LL_CON2),
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REGNAME(apmixed, 0x214, ARMPLL_LL_CON3),
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REGNAME(apmixed, 0x218, ARMPLL_BL0_CON0),
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REGNAME(apmixed, 0x21C, ARMPLL_BL0_CON1),
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REGNAME(apmixed, 0x220, ARMPLL_BL0_CON2),
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REGNAME(apmixed, 0x224, ARMPLL_BL0_CON3),
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REGNAME(apmixed, 0x228, ARMPLL_BL1_CON0),
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REGNAME(apmixed, 0x22C, ARMPLL_BL1_CON1),
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REGNAME(apmixed, 0x230, ARMPLL_BL1_CON2),
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REGNAME(apmixed, 0x234, ARMPLL_BL1_CON3),
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REGNAME(apmixed, 0x238, ARMPLL_BL2_CON0),
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REGNAME(apmixed, 0x23C, ARMPLL_BL2_CON1),
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REGNAME(apmixed, 0x240, ARMPLL_BL2_CON2),
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REGNAME(apmixed, 0x244, ARMPLL_BL2_CON3),
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REGNAME(apmixed, 0x248, ARMPLL_BL3_CON0),
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REGNAME(apmixed, 0x24C, ARMPLL_BL3_CON1),
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REGNAME(apmixed, 0x250, ARMPLL_BL3_CON2),
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REGNAME(apmixed, 0x254, ARMPLL_BL3_CON3),
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REGNAME(apmixed, 0x258, CCIPLL_CON0),
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REGNAME(apmixed, 0x25C, CCIPLL_CON1),
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REGNAME(apmixed, 0x260, CCIPLL_CON2),
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REGNAME(apmixed, 0x264, CCIPLL_CON3),
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REGNAME(apmixed, 0x268, MFGPLL_CON0),
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REGNAME(apmixed, 0x26C, MFGPLL_CON1),
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REGNAME(apmixed, 0x274, MFGPLL_CON3),
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REGNAME(apmixed, 0x308, UNIVPLL_CON0),
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REGNAME(apmixed, 0x30C, UNIVPLL_CON1),
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REGNAME(apmixed, 0x314, UNIVPLL_CON3),
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REGNAME(apmixed, 0x318, APLL1_CON0),
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REGNAME(apmixed, 0x31C, APLL1_CON1),
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REGNAME(apmixed, 0x320, APLL1_CON2),
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REGNAME(apmixed, 0x324, APLL1_CON3),
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REGNAME(apmixed, 0x328, APLL1_CON4),
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REGNAME(apmixed, 0x32C, APLL2_CON0),
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REGNAME(apmixed, 0x330, APLL2_CON1),
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REGNAME(apmixed, 0x334, APLL2_CON2),
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REGNAME(apmixed, 0x338, APLL2_CON3),
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REGNAME(apmixed, 0x33C, APLL2_CON4),
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REGNAME(apmixed, 0x340, MAINPLL_CON0),
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REGNAME(apmixed, 0x344, MAINPLL_CON1),
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REGNAME(apmixed, 0x34C, MAINPLL_CON3),
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REGNAME(apmixed, 0x350, MSDCPLL_CON0),
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REGNAME(apmixed, 0x354, MSDCPLL_CON1),
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REGNAME(apmixed, 0x35C, MSDCPLL_CON3),
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REGNAME(apmixed, 0x360, MMPLL_CON0),
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REGNAME(apmixed, 0x364, MMPLL_CON1),
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REGNAME(apmixed, 0x36C, MMPLL_CON3),
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REGNAME(apmixed, 0x370, ADSPPLL_CON0),
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REGNAME(apmixed, 0x374, ADSPPLL_CON1),
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REGNAME(apmixed, 0x37C, ADSPPLL_CON3),
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REGNAME(apmixed, 0x380, TVDPLL_CON0),
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REGNAME(apmixed, 0x384, TVDPLL_CON1),
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REGNAME(apmixed, 0x38C, TVDPLL_CON3),
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REGNAME(apmixed, 0x390, MPLL_CON0),
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REGNAME(apmixed, 0x394, MPLL_CON1),
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REGNAME(apmixed, 0x39C, MPLL_CON3),
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REGNAME(apmixed, 0x3A0, APUPLL_CON0),
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REGNAME(apmixed, 0x3A4, APUPLL_CON1),
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REGNAME(apmixed, 0x3AC, APUPLL_CON3),
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REGNAME(scpsys, 0x0000, POWERON_CONFIG_EN),
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REGNAME(scpsys, 0x016C, PWR_STATUS),
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REGNAME(scpsys, 0x0170, PWR_STATUS_2ND),
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REGNAME(scpsys, 0x0178, OTHER_PWR_STATUS),
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REGNAME(scpsys, 0x300, MD1_PWR_CON),
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REGNAME(scpsys, 0x304, CONN_PWR_CON),
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REGNAME(scpsys, 0x308, MFG0_PWR_CON),
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REGNAME(scpsys, 0x30C, MFG1_PWR_CON),
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REGNAME(scpsys, 0x310, MFG2_PWR_CON),
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REGNAME(scpsys, 0x314, MFG3_PWR_CON),
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REGNAME(scpsys, 0x318, MFG4_PWR_CON),
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REGNAME(scpsys, 0x31C, MFG5_PWR_CON),
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REGNAME(scpsys, 0x320, MFG6_PWR_CON),
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REGNAME(scpsys, 0x324, IFR_PWR_CON),
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REGNAME(scpsys, 0x328, IFR_SUB_PWR_CON),
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REGNAME(scpsys, 0x32C, DPY_PWR_CON),
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REGNAME(scpsys, 0x330, ISP_PWR_CON),
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REGNAME(scpsys, 0x334, ISP2_PWR_CON),
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REGNAME(scpsys, 0x338, IPE_PWR_CON),
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REGNAME(scpsys, 0x33C, VDE_PWR_CON),
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REGNAME(scpsys, 0x340, VDE2_PWR_CON),
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REGNAME(scpsys, 0x344, VEN_PWR_CON),
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REGNAME(scpsys, 0x348, VEN_CORE1_PWR_CON),
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REGNAME(scpsys, 0x34C, MDP_PWR_CON),
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REGNAME(scpsys, 0x350, DIS_PWR_CON),
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REGNAME(scpsys, 0x354, AUDIO_PWR_CON),
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REGNAME(scpsys, 0x358, ADSP_PWR_CON),
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REGNAME(scpsys, 0x35C, CAM_PWR_CON),
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REGNAME(scpsys, 0x360, CAM_RAWA_PWR_CON),
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REGNAME(scpsys, 0x364, CAM_RAWB_PWR_CON),
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REGNAME(scpsys, 0x368, CAM_RAWC_PWR_CON),
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REGNAME(scpsys, 0x3AC, DP_TX_PWR_CON),
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REGNAME(scpsys, 0x3C4, DPY2_PWR_CON),
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REGNAME(scpsys, 0x398, MD_EXT_BUCK_ISO_CON),
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REGNAME(scpsys, 0x39C, EXT_BUCK_ISO),
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REGNAME(scpsys, 0x3A4, MSDC_PWR_CON),
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REGNAME(audio, 0x0000, AUDIO_TOP_CON0),
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REGNAME(audio, 0x0004, AUDIO_TOP_CON1),
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REGNAME(audio, 0x0008, AUDIO_TOP_CON2),
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REGNAME(camsys, 0x0000, CAMSYS_CG_CON),
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REGNAME(cam_rawa_sys, 0x0000, CAMSYS_RAWA_CG_CON),
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REGNAME(cam_rawb_sys, 0x0000, CAMSYS_RAWB_CG_CON),
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REGNAME(cam_rawc_sys, 0x0000, CAMSYS_RAWC_CG_CON),
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REGNAME(img1sys, 0x0000, IMG1_CG_CON),
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REGNAME(img2sys, 0x0000, IMG2_CG_CON),
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REGNAME(ipesys, 0x0000, IPE_CG_CON),
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REGNAME(infracfg, 0x090, MODULE_SW_CG_0),
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REGNAME(infracfg, 0x094, MODULE_SW_CG_1),
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REGNAME(infracfg, 0x0ac, MODULE_SW_CG_2),
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REGNAME(infracfg, 0x0c8, MODULE_SW_CG_3),
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#if 0
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/*
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* REGNAME(ipu0, 0x000, IPU0_CORE_CG),
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* REGNAME(ipu1, 0x000, IPU1_CORE_CG),
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* REGNAME(ipu2, 0x000, IPU2_CORE_CG),
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* REGNAME(ipu_conn, 0x000, IPU_CONN_CG),
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* REGNAME(ipu_vcore, 0x000, IPU_VCORE_CG),
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*/
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#endif
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REGNAME(mfgsys, 0x0000, MFG_CG_CON),
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REGNAME(mmsys, 0x100, MM_CG_CON0),
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REGNAME(mmsys, 0x110, MM_CG_CON1),
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REGNAME(mmsys, 0x1a0, MM_CG_CON2),
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REGNAME(mdpsys, 0x100, MDP_CG_CON0),
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REGNAME(mdpsys, 0x104, MDP_CG_SET0),
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REGNAME(mdpsys, 0x114, MDP_CG_SET1),
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REGNAME(mdpsys, 0x124, MDP_CG_SET2),
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REGNAME(vdecsys, 0x0000, VDEC_CKEN_SET),
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REGNAME(vdecsys, 0x0008, VDEC_LARB1_CKEN_SET),
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REGNAME(vdecsys, 0x0200, VDEC_LAT_CKEN_SET),
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REGNAME(vdec_soc_sys, 0x0000, VDEC_SOC_CKEN_SET),
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REGNAME(vdec_soc_sys, 0x0008, VDEC_SOC_LARB1_CKEN_SET),
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REGNAME(vdec_soc_sys, 0x0200, VDEC_SOC_LAT_CKEN_SET),
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REGNAME(vencsys, 0x0000, VENC_CG_CON),
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{}
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};
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static const struct regname *get_all_regnames(void)
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{
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return rn;
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}
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static void init_regbase(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(rb) - 1; i++)
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rb[i].virt = ioremap_nocache(rb[i].phys, PAGE_SIZE);
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}
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#ifndef GENMASK
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#define GENMASK(h, l) (((1U << ((h) - (l) + 1)) - 1) << (l))
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#endif
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#define clk_readl(addr) readl(addr)
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#define clk_writel(addr, val) \
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do { writel(val, addr); wmb(); } while (0) /* sync write */
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#define _CKGEN(x) (rb[topckgen].virt + (x))
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#define CLK_CFG_0 _CKGEN(0x10)
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#define _SCPSYS(x) (rb[scpsys].virt + (x))
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#define SPM_PWR_STATUS _SCPSYS(0x16C)
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#define SPM_PWR_STATUS_2ND _SCPSYS(0x170)
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#ifdef CONFIG_MTK_DEVAPC
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static void devapc_dump_regs(void)
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{
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int i = 0;
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pr_notice("[devapc] CLK_CFG_0-16\r\n");
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for (i = 0; i < 17; i++)
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pr_notice("[%d]0x%08x\r\n", i, clk_readl(CLK_CFG_0 + (i << 4)));
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pr_notice("[devapc] PWR_STATUS(0x16C,0x170) = 0x%08x 0x%08x\n",
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clk_readl(SPM_PWR_STATUS), clk_readl(SPM_PWR_STATUS_2ND));
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}
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static struct devapc_vio_callbacks devapc_vio_handle = {
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.id = DEVAPC_SUBSYS_CLKMGR,
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.debug_dump = devapc_dump_regs,
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};
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#endif
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static const struct fmeter_clk *get_all_fmeter_clks(void)
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{
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return get_fmeter_clks();
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}
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static u32 fmeter_freq_op(const struct fmeter_clk *fclk)
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{
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if (fclk->type == ABIST)
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return mt_get_abist_freq(fclk->id);
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else if (fclk->type == CKGEN)
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return mt_get_ckgen_freq(fclk->id);
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return 0;
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}
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/*
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* clkdbg dump_state
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*/
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extern const char * const *get_mt6873_all_clk_names(void);
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static const char * const *get_all_clk_names(void)
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{
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return get_mt6873_all_clk_names();
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}
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/*
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* clkdbg pwr_status
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*/
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static const char * const *get_pwr_names(void)
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{
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static const char * const pwr_names[] = {
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[0] = "MD",
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[1] = "CONN",
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[2] = "MFG0",
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[3] = "MFG1",
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[4] = "MFG2",
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[5] = "MFG3",
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[6] = "MFG4",
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[7] = "MFG5",
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[8] = "MFG6",
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[9] = "INFRA",
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[10] = "SUB_INFRA",
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[11] = "DDRPHY",
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[12] = "ISP",
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[13] = "ISP2",
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[14] = "IPE",
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[15] = "VDEC",
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[16] = "VDEC2",
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[17] = "VEN",
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[18] = "VEN_CORE1",
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[19] = "MDP",
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[20] = "DISP",
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[21] = "AUDIO",
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[22] = "ADSP",
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[23] = "CAM",
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[24] = "CAM_RAWA",
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[25] = "CAM_RAWB",
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[26] = "CAM_RAWC",
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[27] = "DP_TX",
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[28] = "DDRPHY2",
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[29] = "MCUPM",
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[30] = "MSDC",
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[31] = "PERI",
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};
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return pwr_names;
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}
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/*
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* clkdbg dump_clks
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*/
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void setup_provider_clk(struct provider_clk *pvdck)
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{
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static const struct {
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const char *pvdname;
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u32 pwr_mask;
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} pvd_pwr_mask[] = {
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};
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int i;
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const char *pvdname = pvdck->provider_name;
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if (!pvdname)
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return;
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for (i = 0; i < ARRAY_SIZE(pvd_pwr_mask); i++) {
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if (strcmp(pvdname, pvd_pwr_mask[i].pvdname) == 0) {
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pvdck->pwr_mask = pvd_pwr_mask[i].pwr_mask;
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return;
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}
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}
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}
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/*
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* chip_ver functions
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*/
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#include <linux/seq_file.h>
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#if 0
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#include <mt-plat/mtk_chip.h>
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#endif
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static int clkdbg_chip_ver(struct seq_file *s, void *v)
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{
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static const char * const sw_ver_name[] = {
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"CHIP_SW_VER_01",
|
|
"CHIP_SW_VER_02",
|
|
"CHIP_SW_VER_03",
|
|
"CHIP_SW_VER_04",
|
|
};
|
|
|
|
#if 0 /*no support*/
|
|
enum chip_sw_ver ver = mt_get_chip_sw_ver();
|
|
|
|
seq_printf(s, "mt_get_chip_sw_ver(): %d (%s)\n", ver, sw_ver_name[ver]);
|
|
#else
|
|
seq_printf(s, "mt_get_chip_sw_ver(): %d (%s)\n", 0, sw_ver_name[0]);
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* init functions
|
|
*/
|
|
|
|
static struct clkdbg_ops clkdbg_mt6873_ops = {
|
|
.get_all_fmeter_clks = get_all_fmeter_clks,
|
|
.prepare_fmeter = NULL,
|
|
.unprepare_fmeter = NULL,
|
|
.fmeter_freq = fmeter_freq_op,
|
|
.get_all_regnames = get_all_regnames,
|
|
.get_all_clk_names = get_all_clk_names,
|
|
.get_pwr_names = get_pwr_names,
|
|
.setup_provider_clk = setup_provider_clk,
|
|
};
|
|
|
|
static void __init init_custom_cmds(void)
|
|
{
|
|
static const struct cmd_fn cmds[] = {
|
|
CMDFN("chip_ver", clkdbg_chip_ver),
|
|
{}
|
|
};
|
|
|
|
set_custom_cmds(cmds);
|
|
}
|
|
|
|
static int __init clkdbg_mt6873_init(void)
|
|
{
|
|
init_regbase();
|
|
|
|
init_custom_cmds();
|
|
set_clkdbg_ops(&clkdbg_mt6873_ops);
|
|
|
|
#ifdef CONFIG_MTK_DEVAPC
|
|
register_devapc_vio_callback(&devapc_vio_handle);
|
|
#endif
|
|
|
|
#if ALL_CLK_ON
|
|
prepare_enable_provider("topckgen");
|
|
reg_pdrv("all");
|
|
prepare_enable_provider("all");
|
|
#endif
|
|
|
|
#if DUMP_INIT_STATE
|
|
print_regs();
|
|
print_fmeter_all();
|
|
#endif /* DUMP_INIT_STATE */
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(clkdbg_mt6873_init);
|
|
|
|
static struct regbase *lookup_regbase(char *name)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(rb) - 1; i++) {
|
|
if (!strcmp(name, rb[i].name))
|
|
return &rb[i];
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
void print_subsys_reg(char *subsys_name)
|
|
{
|
|
struct regbase *rb_dump;
|
|
const struct regname *rns = &rn[0];
|
|
|
|
if (rns == NULL)
|
|
return;
|
|
|
|
rb_dump = lookup_regbase(subsys_name);
|
|
if (rb_dump == NULL) {
|
|
pr_info("wrong regbase name:%s\n", subsys_name);
|
|
return;
|
|
}
|
|
|
|
for (; rns->base != NULL; rns++) {
|
|
if (!is_valid_reg(ADDR(rns)))
|
|
return;
|
|
|
|
/* filter out the subsys that we don't want */
|
|
if (rns->base != rb_dump)
|
|
continue;
|
|
|
|
pr_info("%-18s: [0x%08x] = 0x%08x\n",
|
|
rns->name, PHYSADDR(rns), clk_readl(ADDR(rns)));
|
|
}
|
|
}
|