4544 lines
119 KiB
Plaintext
4544 lines
119 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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*/
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/dts-v1/;
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#include <dt-bindings/mmc/mt6779-msdc.h>
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#include <dt-bindings/iio/mt635x-auxadc.h>
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#include <generated/autoconf.h>
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#include <dt-bindings/clock/mt6779-clk.h>
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#include <dt-bindings/power/mt6779-power.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/memory/mt6779-larb-port.h>
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#include <dt-bindings/power/mt6779-power.h>
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#include <dt-bindings/gce/mt6779-gce.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
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#include <dt-bindings/soc/mediatek,boot-mode.h>
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#include <dt-bindings/interconnect/mtk,mt6779-emi.h>
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#include <dt-bindings/usb/pd.h>
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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model = "MT6779";
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compatible = "mediatek,MT6779";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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/* chosen */
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chosen: chosen {
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bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
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vmalloc=400M slub_debug=OFZPU page_owner=on \
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swiotlb=noforce cma=0 \
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firmware_class.path=/vendor/firmware loop.max_part=7";
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kaslr-seed = <0 0>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
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};
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dsu-pmu-0 {
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compatible = "arm,dsu-pmu";
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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cluster0_opp: opp_table0 {
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compatible = "operating-points-v2";
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opp-shared;
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opp0 {
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opp-hz = /bits/ 64 <774000000>;
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opp-microvolt = <637500>;
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};
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opp1 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <662500>;
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};
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opp2 {
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opp-hz = /bits/ 64 <925000000>;
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opp-microvolt = <681250>;
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};
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opp3 {
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opp-hz = /bits/ 64 <999000000>;
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opp-microvolt = <700000>;
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};
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opp4 {
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opp-hz = /bits/ 64 <1075000000>;
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opp-microvolt = <718750>;
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};
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opp5 {
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opp-hz = /bits/ 64 <1175000000>;
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opp-microvolt = <750000>;
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};
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opp6 {
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opp-hz = /bits/ 64 <1275000000>;
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opp-microvolt = <775000>;
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};
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opp7 {
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opp-hz = /bits/ 64 <1375000000>;
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opp-microvolt = <800000>;
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};
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opp8 {
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opp-hz = /bits/ 64 <1475000000>;
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opp-microvolt = <825000>;
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};
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opp9 {
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opp-hz = /bits/ 64 <1548000000>;
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opp-microvolt = <843750>;
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};
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opp10 {
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opp-hz = /bits/ 64 <1666000000>;
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opp-microvolt = <887500>;
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};
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opp11 {
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opp-hz = /bits/ 64 <1733000000>;
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opp-microvolt = <912500>;
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};
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opp12 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <931250>;
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};
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opp13 {
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opp-hz = /bits/ 64 <1866000000>;
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opp-microvolt = <956250>;
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};
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opp14 {
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opp-hz = /bits/ 64 <1933000000>;
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opp-microvolt = <981250>;
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};
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opp15 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <1000000>;
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};
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};
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cluster1_opp: opp_table1 {
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compatible = "operating-points-v2";
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opp-shared;
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opp0 {
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opp-hz = /bits/ 64 <850000000>;
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opp-microvolt = <675000>;
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};
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opp1 {
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opp-hz = /bits/ 64 <909000000>;
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opp-microvolt = <693750>;
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};
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opp2 {
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opp-hz = /bits/ 64 <998000000>;
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opp-microvolt = <712500>;
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};
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opp3 {
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opp-hz = /bits/ 64 <1087000000>;
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opp-microvolt = <731250>;
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};
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opp4 {
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opp-hz = /bits/ 64 <1176000000>;
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opp-microvolt = <756250>;
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};
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opp5 {
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opp-hz = /bits/ 64 <1295000000>;
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opp-microvolt = <781250>;
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};
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opp6 {
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opp-hz = /bits/ 64 <1414000000>;
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opp-microvolt = <800000>;
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};
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opp7 {
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opp-hz = /bits/ 64 <1503000000>;
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opp-microvolt = <831250>;
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};
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opp8 {
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opp-hz = /bits/ 64 <1651000000>;
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opp-microvolt = <868750>;
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};
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opp9 {
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opp-hz = /bits/ 64 <1800000000>;
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opp-microvolt = <900000>;
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};
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opp10 {
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opp-hz = /bits/ 64 <1866000000>;
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opp-microvolt = <931250>;
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};
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opp11 {
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opp-hz = /bits/ 64 <1933000000>;
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opp-microvolt = <956250>;
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};
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opp12 {
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opp-hz = /bits/ 64 <2000000000>;
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opp-microvolt = <987500>;
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};
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opp13 {
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opp-hz = /bits/ 64 <2066000000>;
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opp-microvolt = <1012500>;
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};
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opp14 {
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opp-hz = /bits/ 64 <2133000000>;
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opp-microvolt = <1043750>;
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};
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opp15 {
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opp-hz = /bits/ 64 <2200000000>;
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opp-microvolt = <1068750>;
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};
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};
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cci_opp: opp_table2 {
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compatible = "operating-points-v2";
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opp-shared;
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opp00 {
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opp-hz = /bits/ 64 <400000000>;
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opp-microvolt = <637500>;
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};
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opp01 {
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opp-hz = /bits/ 64 <445000000>;
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opp-microvolt = <656250>;
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};
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opp02 {
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opp-hz = /bits/ 64 <512000000>;
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opp-microvolt = <675000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <579000000>;
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opp-microvolt = <693750>;
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};
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opp04 {
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opp-hz = /bits/ 64 <669000000>;
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opp-microvolt = <718750>;
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};
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opp05 {
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opp-hz = /bits/ 64 <737000000>;
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opp-microvolt = <737500>;
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};
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opp06 {
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opp-hz = /bits/ 64 <827000000>;
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opp-microvolt = <762500>;
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};
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opp07 {
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opp-hz = /bits/ 64 <917000000>;
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opp-microvolt = <787500>;
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};
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opp08 {
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opp-hz = /bits/ 64 <98400000>;
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opp-microvolt = <800000>;
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};
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opp09 {
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opp-hz = /bits/ 64 <112000000>;
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opp-microvolt = <843750>;
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};
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opp10 {
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opp-hz = /bits/ 64 <115500000>;
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opp-microvolt = <868750>;
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};
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opp11 {
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opp-hz = /bits/ 64 <119000000>;
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opp-microvolt = <887500>;
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};
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opp12 {
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opp-hz = /bits/ 64 <1260000000>;
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opp-microvolt = <925000>;
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};
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opp13 {
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opp-hz = /bits/ 64 <1306000000>;
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opp-microvolt = <950000>;
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};
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opp14 {
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opp-hz = /bits/ 64 <1353000000>;
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opp-microvolt = <975000>;
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};
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opp15 {
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opp-hz = /bits/ 64 <1400000000>;
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opp-microvolt = <1000000>;
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};
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};
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cci: cci {
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compatible = "mediatek,mtk-cci";
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clocks = <&apmixed CLK_APMIXED_CCIPLL>;
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clock-names = "dsu_clock";
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operating-points-v2 = <&cci_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0000>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu1: cpu@001 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0100>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu2: cpu@002 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0200>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu3: cpu@003 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0300>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0400>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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reg = <0x0500>;
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enable-method = "psci";
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clock-frequency = <2000000000>;
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operating-points-v2 = <&cluster0_opp>;
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proc-supply = <&mt_pmic_vproc2_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc2_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_LL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <85>;
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capacity-dmips-mhz = <578>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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reg = <0x0600>;
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enable-method = "psci";
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clock-frequency = <2200000000>;
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operating-points-v2 = <&cluster1_opp>;
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proc-supply = <&mt_pmic_vproc1_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc1_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_BL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <275>;
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capacity-dmips-mhz = <1024>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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reg = <0x0700>;
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enable-method = "psci";
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clock-frequency = <2200000000>;
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operating-points-v2 = <&cluster1_opp>;
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proc-supply = <&mt_pmic_vproc1_buck_reg>;
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sram-supply = <&mt_pmic_vsram_proc1_ldo_reg>;
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clocks = <&apmixed CLK_APMIXED_ARMPLL_BL>;
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clock-names = "cpu";
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dynamic-power-coefficient = <275>;
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capacity-dmips-mhz = <1024>;
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cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
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<&SODI &SODI3 &DPIDLE &SUSPEND>;
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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core4 {
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cpu = <&cpu4>;
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};
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core5 {
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cpu = <&cpu5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu6>;
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};
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core1 {
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cpu = <&cpu7>;
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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STANDBY: standby {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x00000001>;
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entry-latency-us = <600>;
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exit-latency-us = <600>;
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min-residency-us = <1200>;
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};
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MCDI_CPU: mcdi-cpu {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x00010001>;
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entry-latency-us = <600>;
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exit-latency-us = <600>;
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min-residency-us = <1200>;
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};
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MCDI_CLUSTER: mcdi-cluster {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010001>;
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entry-latency-us = <600>;
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exit-latency-us = <600>;
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min-residency-us = <1200>;
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};
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SODI: sodi {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010002>;
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entry-latency-us = <800>;
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exit-latency-us = <1000>;
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min-residency-us = <2000>;
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status = "okay";
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};
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SODI3: sodi3 {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010003>;
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entry-latency-us = <800>;
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exit-latency-us = <1000>;
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min-residency-us = <2000>;
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status = "okay";
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};
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DPIDLE: dpidle {
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compatible = "arm,idle-state";
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arm,psci-suspend-param = <0x01010004>;
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entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
status = "okay";
|
|
};
|
|
|
|
SUSPEND: suspend {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010005>;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
mtk_lpm: mtk_lpm {
|
|
compatible = "mediatek,mtk-lpm";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
suspend-method = "system";
|
|
|
|
irq-remain = <&edge_keypad>;
|
|
irq-remain-list {
|
|
edge_keypad: edge_keypad {
|
|
target = <&keypad>;
|
|
value = <1 0 0 0x40>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dvfsp@10227000 {
|
|
compatible = "mediatek,dvfsp";
|
|
reg = <0 0x10227000 0 0x1000>;
|
|
};
|
|
|
|
dvfsp: dvfsp@0011bc00 {
|
|
compatible = "mediatek,sspm-dvfsp";
|
|
reg = <0 0x0011bc00 0 0x1400>,
|
|
<0 0x0011bc00 0 0x1400>;
|
|
state = <1>;
|
|
change_flag = <0>;
|
|
little-rise-time = <1000>;
|
|
little-down-time = <750>;
|
|
big-rise-time = <1000>;
|
|
big-down-time = <750>;
|
|
nvmem-cells = <&efuse_segment>;
|
|
nvmem-cell-names = "efuse_segment_cell";
|
|
L-table = <2000 96 1 1
|
|
1933 92 1 1
|
|
1866 88 1 1
|
|
1800 83 1 1
|
|
1733 80 1 1
|
|
1666 75 1 1
|
|
1548 71 1 1
|
|
1475 66 2 1
|
|
1375 64 2 1
|
|
1275 58 2 1
|
|
1175 54 2 1
|
|
1075 49 2 1
|
|
999 46 2 1
|
|
925 43 2 1
|
|
850 40 2 1
|
|
774 38 2 1 >;
|
|
|
|
B-table = <2200 100 1 1
|
|
2133 96 1 1
|
|
2066 92 1 1
|
|
2000 88 1 1
|
|
1933 84 1 1
|
|
1866 80 1 1
|
|
1800 75 1 1
|
|
1651 70 1 1
|
|
1503 64 1 1
|
|
1414 61 2 1
|
|
1295 57 2 1
|
|
1176 53 2 1
|
|
1087 49 2 1
|
|
998 46 2 1
|
|
909 43 2 1
|
|
850 40 2 1 >;
|
|
|
|
CCI-table = <1400 96 2 1
|
|
1353 92 2 1
|
|
1306 88 2 1
|
|
1260 84 2 1
|
|
1190 78 2 1
|
|
1155 75 2 1
|
|
1120 71 2 1
|
|
984 64 2 1
|
|
917 62 2 1
|
|
827 58 2 1
|
|
737 54 2 2
|
|
669 51 2 2
|
|
579 47 2 2
|
|
512 44 2 2
|
|
445 41 2 2
|
|
400 38 2 2 >;
|
|
};
|
|
|
|
mt_cpufreq: mt_cpufreq {
|
|
compatible = "mediatek,mt-cpufreq";
|
|
};
|
|
|
|
eem_fsm@1100b000 {
|
|
compatible = "mediatek,eem_fsm";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_LOW>;
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
nvmem-cells = <&efuse_segment>;
|
|
nvmem-cell-names = "efuse_segment_cell";
|
|
eem-ct = <1>;
|
|
};
|
|
|
|
reserved_memory: reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
reserve-memory-sspm_share {
|
|
compatible = "mediatek,reserve-memory-sspm_share";
|
|
no-map;
|
|
status = "okay";
|
|
size = <0 0x510000>; /* 5M + 64K */
|
|
alignment = <0 0x10000>;
|
|
alloc-ranges = <0 0x40000000 0 0x60000000>;
|
|
};
|
|
|
|
consys_mem: consys-reserve-memory {
|
|
compatible = "mediatek,consys-reserve-memory";
|
|
no-map;
|
|
size = <0 0x400000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
reserve-memory-adsp_share {
|
|
compatible = "mediatek,reserve-memory-adsp_share";
|
|
no-map;
|
|
size = <0 0x1000000>;
|
|
alignment = <0 0x10000>;
|
|
alloc-ranges = <0 0x40000000 0 0x40000000>;
|
|
};
|
|
|
|
reserve-memory-scp_share {
|
|
compatible = "mediatek,reserve-memory-scp_share";
|
|
no-map;
|
|
size = <0 0x00380000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x50000000>;
|
|
};
|
|
|
|
wifi_mem: wifi-reserve-memory {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
size = <0 0x600000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
ssmr_cma_mem: ssmr-reserved-cma_memory {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0 0x10000000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-range = <0 0xc0000000 0 0x10000000>;
|
|
};
|
|
};
|
|
|
|
clk26m: oscillator@0 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
clock-output-names = "clk26m";
|
|
};
|
|
|
|
clk32k: oscillator@1 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "clk32k";
|
|
};
|
|
|
|
clk13m: oscillator@2 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <13000000>;
|
|
clock-output-names = "clk13m";
|
|
};
|
|
|
|
uart_clk: dummy26m {
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <26000000>;
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 14
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10
|
|
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
soc {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
compatible = "simple-bus";
|
|
ranges;
|
|
|
|
cpupm_sysram: cpupm-sysram@0011b000 {
|
|
compatible = "mediatek,cpupm-sysram";
|
|
reg = <0 0x0011b000 0 0x500>;
|
|
};
|
|
|
|
gic: interrupt-controller@0c000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
#redistributor-regions = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0 0x0c000000 0 0x40000>, // distributor
|
|
<0 0x0c040000 0 0x200000>, // redistributor
|
|
<0 0x0c53a650 0 0x50>; //INTPOL
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cm_mgr: cm_mgr@0c530000 {
|
|
compatible = "mediatek,mt6779-cm_mgr";
|
|
reg = <0 0x0c530000 0 0x9000>;
|
|
reg-names = "cm_mgr_base";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>,
|
|
<&dvfsrc_freq_opp3>,
|
|
<&dvfsrc_freq_opp4>,
|
|
<&dvfsrc_freq_opp5>;
|
|
cm_mgr,cp_down = <120 120 20 20>;
|
|
cm_mgr,cp_up = <100 100 40 40>;
|
|
cm_mgr,dt_down = <3 0 0 0>;
|
|
cm_mgr,dt_up = <0 0 0 0>;
|
|
cm_mgr,vp_down = <100 100 100 100>;
|
|
cm_mgr,vp_up = <100 100 100 100>;
|
|
|
|
/* use_bcpu_weight = "enable"; */
|
|
/* cpu_power_bcpu_weight_max = <100>; */
|
|
/* cpu_power_bcpu_weight_min = <100>; */
|
|
|
|
/* use_cpu_to_dram_map = "enable"; */
|
|
/* cm_mgr_cpu_opp_to_dram = <0 0 0 0 1 1 1 1 */
|
|
/* 1 2 2 2 2 2 2 2>; */
|
|
|
|
/* use_cpu_to_dram_map_new = "enable"; */
|
|
};
|
|
|
|
mcusys_ctrl: mcusys-ctrl@0c53a000 {
|
|
compatible = "mediatek,mcusys-ctrl";
|
|
reg = <0 0x0c53a000 0 0x1000>;
|
|
};
|
|
|
|
sysirq: intpol-controller@0c53a650 {
|
|
compatible = "mediatek,mt6779-sysirq",
|
|
"mediatek,mt6577-sysirq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0 0x0c53a650 0 0x50>;
|
|
};
|
|
|
|
topckgen: clock-controller@10000000 {
|
|
compatible = "mediatek,mt6779-topckgen", "syscon";
|
|
reg = <0 0x10000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
infracfg_ao: clock-reset-controller@10001000 {
|
|
compatible = "mediatek,common-infracfg_ao",
|
|
"mediatek,infracfg_ao",
|
|
"mediatek,mt6779-infracfg_ao", "syscon", "simple-mfd";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
|
|
infracfg_rst: reset-controller {
|
|
compatible = "ti,syscon-reset";
|
|
#reset-cells = <1>;
|
|
|
|
ti,reset-bits = <
|
|
/* 0: ufs: hci_rst */
|
|
0x130 15 0x134 15 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
/* 1: ufs: unipro_rst */
|
|
0x140 7 0x144 7 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
/* 2: ufs: crypto_rst */
|
|
0x150 21 0x154 21 0 0
|
|
(ASSERT_SET | DEASSERT_SET | STATUS_NONE)
|
|
>;
|
|
};
|
|
};
|
|
|
|
lastbus@10001000 {
|
|
compatible = "mediatek,lastbus-v1";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10003000 0 0x1000>;
|
|
};
|
|
|
|
scp_infra: scp_infra@10001000 {
|
|
compatible = "mediatek,scpinfra";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
};
|
|
|
|
mcucfg: mcucfg@0c530000 {
|
|
compatible = "mediatek,mcucfg";
|
|
reg = <0 0x0c530000 0 0x10000>;
|
|
};
|
|
|
|
dcm: dcm@10001000 {
|
|
compatible = "mediatek,mt6779-dcm";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10002000 0 0x1000>,
|
|
<0 0x0c538000 0 0x5000>,
|
|
<0 0x0c53a800 0 0x1000>,
|
|
<0 0x10230000 0 0x1000>,
|
|
<0 0x10240000 0 0x1000>,
|
|
<0 0x10238000 0 0x1000>,
|
|
<0 0x10248000 0 0x1000>,
|
|
<0 0x10219000 0 0x1000>,
|
|
<0 0x10235000 0 0x1000>;
|
|
reg-names = "infra_ao",
|
|
"infra_ao_mem",
|
|
"mcucfg",
|
|
"cpc",
|
|
"dramc0",
|
|
"dramc1",
|
|
"dramc4",
|
|
"dramc5",
|
|
"emi0",
|
|
"emi2";
|
|
};
|
|
|
|
pericfg: pericfg@10003000 {
|
|
compatible = "mediatek,pericfg",
|
|
"mediatek,mt6779-pericfg", "syscon";
|
|
reg = <0 0x10003000 0 0x1000>;
|
|
#clock-cells=<1>;
|
|
};
|
|
|
|
gpio: gpio@10005000 {
|
|
compatible = "mediatek,gpio";
|
|
reg = <0 0x10005000 0 0x1000>;
|
|
};
|
|
|
|
pio: pinctrl@10005000 {
|
|
compatible = "mediatek,mt6779-pinctrl", "syscon";
|
|
reg = <0 0x10005000 0 0x1000>,
|
|
<0 0x11c20000 0 0x1000>,
|
|
<0 0x11d10000 0 0x1000>,
|
|
<0 0x11e20000 0 0x1000>,
|
|
<0 0x11e70000 0 0x1000>,
|
|
<0 0x11ea0000 0 0x1000>,
|
|
<0 0x11f20000 0 0x1000>,
|
|
<0 0x11f30000 0 0x1000>,
|
|
<0 0x1000b000 0 0x1000>;
|
|
reg-names = "gpio", "iocfg_rm",
|
|
"iocfg_br", "iocfg_lm",
|
|
"iocfg_lb", "iocfg_rt",
|
|
"iocfg_lt", "iocfg_tl",
|
|
"eint";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
gpio-ranges = <&pio 0 0 209>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
spm: spm@10006000 {
|
|
compatible = "mediatek,spm";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
};
|
|
|
|
sleep_reg_md@1000f000 {
|
|
compatible = "mediatek,sleep_reg_md";
|
|
reg = <0 0x1000f000 0 0x1000>;
|
|
};
|
|
|
|
infracfg: infracfg@1020e000 {
|
|
compatible = "syscon";
|
|
reg = <0 0x1020e000 0 0x1000>;
|
|
};
|
|
|
|
mcdi:mcdi@0011b000 {
|
|
compatible = "mediatek,mt6779-mcdi";
|
|
mediatek,enabled = <1>;
|
|
reg = <0 0x0011b000 0 0x800>,
|
|
<0 0x0c53a000 0 0x1000>;
|
|
};
|
|
|
|
scpsys: scpsys@10006000 {
|
|
compatible = "mediatek,mt6779-scpsys";
|
|
#power-domain-cells = <1>;
|
|
reg = <0 0x10001000 0 0x1000>, /* infracfg */
|
|
<0 0x10006000 0 0x1000>, /* spm */
|
|
<0 0x1020e000 0 0x1000>, /* infra */
|
|
<0 0x10000000 0 0x1000>, /* ckgen */
|
|
<0 0x14019000 0 0x1000>; /* smi common */
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
spmtwam: spmtwam@10006000 {
|
|
compatible = "mediatek,spmtwam";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_LOW>;
|
|
spm_twam_con = <0x194>;
|
|
spm_twam_window_len = <0x198>;
|
|
spm_twam_idle_sel = <0x19c>;
|
|
spm_irq_mask = <0xb4>;
|
|
spm_irq_sta = <0x130>;
|
|
spm_twam_last_sta0 = <0x170>;
|
|
spm_twam_last_sta1 = <0x174>;
|
|
spm_twam_last_sta2 = <0x178>;
|
|
spm_twam_last_sta3 = <0x17c>;
|
|
};
|
|
|
|
srclken: srclken@10006500 {
|
|
compatible = "mediatek,srclken";
|
|
reg = <0 0x10006500 0 0x1000>,
|
|
<0 0x105c4000 0 0x1000>,
|
|
<0 0x10005000 0 0x1000>;
|
|
reg-names = "srclken", "scpdvfs", "gpio";
|
|
srclken-mode = "full-set";
|
|
|
|
srclken-rst-cfg = <0x0>;
|
|
srclken-central-cfg = <0x4 0x8 0x1C>;
|
|
srclken-cmd-cfg = <0xC>;
|
|
srclken-pmic-cfg = <0x10 0x14>;
|
|
srclken-dcxo-fpm-cfg = <0x18>;
|
|
srclken-subsys-cfg = <0x20>;
|
|
srclken-misc-cfg = <0xB4>;
|
|
srclken-spm-cfg = <0xB8>;
|
|
srclken-subsys-if-cfg = <0xBC>;
|
|
srclken-fsm-sta = <0x60>;
|
|
srclken-cmd-sta = <0x64 0x68>;
|
|
srclken-spi-sta = <0x6C>;
|
|
srclken-pipo-sta = <0x70>;
|
|
srclken-subsys-sta = <0x80>;
|
|
srclken-dbg-trace-sta = <0xC0 0xC4>;
|
|
|
|
scp-vreq-cfg = <0x54>;
|
|
scp-rc-vreq-bit = <27 28>;
|
|
gpio-dir-cfg = <0x0>;
|
|
gpio-dout-cfg = <0x100>;
|
|
gpio-pull-bit = <6>;
|
|
};
|
|
|
|
toprgu: toprgu@10007000 {
|
|
compatible = "mediatek,mt6779-wdt",
|
|
"mediatek,mt6589-wdt",
|
|
"mediatek,toprgu",
|
|
"syscon", "simple-mfd";
|
|
reg = <0 0x10007000 0 0x1000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,rg_dfd_timeout = <0xa0>;
|
|
reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
regmap = <&toprgu>;
|
|
offset = <0x24>;
|
|
mask = <0xF>;
|
|
mode-charger = <BOOT_CHARGER>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_BOOTLOADER>;
|
|
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
|
|
mode-kpoc = <BOOT_KPOC>;
|
|
mode-ddr-reserve = <BOOT_DDR_RSVD>;
|
|
mode-meta = <BOOT_META>;
|
|
mode-rpmbpk = <BOOT_RPMBPK>;
|
|
};
|
|
};
|
|
|
|
hacc@1000a000 {
|
|
compatible = "mediatek,hacc";
|
|
reg = <0 0x1000a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
apmixed: clock-controller@1000c000 {
|
|
compatible = "mediatek,mt6779-apmixed", "syscon";
|
|
reg = <0 0x1000c000 0 0xe00>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
fhctl: fhctl@1000ce00 {
|
|
compatible = "mediatek,mt6779-fhctl";
|
|
reg = <0 0x1000ce00 0 0x200>;
|
|
mediatek,apmixed = <&apmixed>;
|
|
|
|
armpll_ll {
|
|
mediatek,fh-id = <0>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_LL>;
|
|
mediatek,fh-cpu-pll;
|
|
};
|
|
|
|
armpll_bl {
|
|
mediatek,fh-id = <1>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_BL>;
|
|
mediatek,fh-cpu-pll;
|
|
};
|
|
|
|
ccipll {
|
|
mediatek,fh-id = <3>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_CCIPLL>;
|
|
};
|
|
|
|
mfgpll {
|
|
mediatek,fh-id = <4>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
|
|
};
|
|
|
|
mpll {
|
|
mediatek,fh-id = <5>;
|
|
};
|
|
|
|
mainpll {
|
|
mediatek,fh-id = <7>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
|
|
};
|
|
|
|
msdcpll {
|
|
mediatek,fh-id = <8>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
|
|
};
|
|
|
|
mmpll {
|
|
mediatek,fh-id = <9>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
|
|
};
|
|
|
|
adsppll {
|
|
mediatek,fh-id = <10>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_ADSPPLL>;
|
|
};
|
|
|
|
tvdpll {
|
|
mediatek,fh-id = <11>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_TVDPLL>;
|
|
};
|
|
};
|
|
|
|
pwrap: pwrap@1000d000 {
|
|
compatible = "mediatek,mt6779-pwrap",
|
|
"mediatek,pwrap_mpu", "syscon";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
reg-names = "pwrap";
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_PMIC_AP>,
|
|
<&topckgen CLK_TOP_FPWRAP_ULPOSC>;
|
|
clock-names = "spi", "wrap", "ulposc";
|
|
|
|
main_pmic: main_pmic {
|
|
compatible = "mediatek,mt6359";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <193 IRQ_TYPE_LEVEL_HIGH 193 0>;
|
|
|
|
mtk_battery_oc_throttling {
|
|
compatible =
|
|
"mediatek,mt6359-battery_oc_throttling";
|
|
oc-thd-h = <5800>;
|
|
oc-thd-l = <6300>;
|
|
};
|
|
};
|
|
};
|
|
|
|
keypad: kp@10010000 {
|
|
compatible = "mediatek,kp";
|
|
reg = <0 0x10010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "kpd";
|
|
};
|
|
|
|
dvfsrc: dvfsrc@10012000 {
|
|
compatible = "mediatek,mt6779-dvfsrc";
|
|
reg = <0 0x10012000 0 0x1000>,
|
|
<0 0x10006000 0 0x1000>;
|
|
reg-names = "dvfsrc", "spm";
|
|
clocks = <&infracfg_ao CLK_INFRA_DVFSRC>;
|
|
clock-names = "dvfsrc";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
dvfsrc_freq_opp5: opp5 {
|
|
opp-level = <5>;
|
|
};
|
|
|
|
dvfsrc_freq_opp4: opp4 {
|
|
opp-level = <4>;
|
|
};
|
|
|
|
dvfsrc_freq_opp3: opp3 {
|
|
opp-level = <3>;
|
|
};
|
|
|
|
dvfsrc_freq_opp2: opp2 {
|
|
opp-level = <2>;
|
|
};
|
|
|
|
dvfsrc_freq_opp1: opp1 {
|
|
opp-level = <1>;
|
|
};
|
|
|
|
dvfsrc_freq_opp0: opp0 {
|
|
opp-level = <0>;
|
|
};
|
|
|
|
dvfsrc-up {
|
|
compatible = "mediatek,mt6779-dvfsrc-up";
|
|
};
|
|
|
|
dvfsrc-debug {
|
|
compatible = "mediatek,mt6779-dvfsrc-debug";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>,
|
|
<&dvfsrc_freq_opp3>,
|
|
<&dvfsrc_freq_opp4>,
|
|
<&dvfsrc_freq_opp5>;
|
|
};
|
|
|
|
dvfsrc-met {
|
|
compatible = "mediatek,mt6779-dvfsrc-met";
|
|
};
|
|
|
|
qos@0011bb80 {
|
|
compatible = "mediatek,mt6779-qos";
|
|
reg = <0 0x0011bb80 0 0x80>;
|
|
};
|
|
};
|
|
|
|
dpmaif:dpmaif@10014000 {
|
|
compatible = "mediatek,dpmaif";
|
|
reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
|
|
<0 0x10014400 0 0x1000>, /*AO_DL*/
|
|
<0 0x1022D000 0 0x1000>, /*PD_UL*/
|
|
<0 0x1022D100 0 0x1000>, /*PD_DL*/
|
|
<0 0x1022D400 0 0x1000>, /*PD_MISC*/
|
|
<0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
|
|
<0 0x1022E000 0 0x1000>; /*SRAM*/
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
|
mediatek,dpmaif_capability = <6>;
|
|
clocks = <&infracfg_ao CLK_INFRA_DPMAIF_CK>;
|
|
clock-names = "infra-dpmaif-clk";
|
|
};
|
|
|
|
dfd@10200b00 {
|
|
compatible = "mediatek,dfd";
|
|
reg = <0 0x10200b00 0 0x10000>;
|
|
|
|
mediatek,enabled = <1>;
|
|
mediatek,chain_length = <0xa7f8>;
|
|
mediatek,rg_dfd_timeout = <0xa0>;
|
|
mediatek,check_dfd_support = <1>;
|
|
mediatek,dfd_infra_base = <0x390>;
|
|
mediatek,dfd_ap_addr_offset = <24>;
|
|
mediatek,dfd_latch_offset = <0x48>;
|
|
reg_base = <&toprgu>;
|
|
};
|
|
|
|
dfd_cache: dfd_cache {
|
|
compatible = "mediatek,dfd_cache";
|
|
mediatek,enabled = <0>;
|
|
mediatek,rg_dfd_timeout = <0x3e80>;
|
|
};
|
|
|
|
sys_cirq@10204000 {
|
|
compatible = "mediatek,sys_cirq";
|
|
reg = <0 0x10204000 0 0x1000>;
|
|
mediatek,cirq_num = <271>;
|
|
mediatek,spi_start_offset = <64>;
|
|
sw_reset = <1>;
|
|
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
devapc: devapc@10207000 {
|
|
compatible = "mediatek,mt6779-devapc";
|
|
reg = <0 0x10207000 0 0x1000>,
|
|
<0 0x1001c000 0 0x1000>,
|
|
<0 0x0011a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_DEVICE_APC>;
|
|
clock-names = "devapc-infra-clock";
|
|
};
|
|
|
|
devmpu@1021a000 {
|
|
compatible = "mediatek,device_mpu_low";
|
|
reg = <0 0x1021a000 0 0x1000>;
|
|
prot-base = <0x0 0x40000000>;
|
|
prot-size = <0x4 0x00000000>;
|
|
page-size = <0x200000>;
|
|
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
bus_dbg@10208000 {
|
|
compatible = "mediatek,bus_dbg-v2";
|
|
reg = <0 0x10208000 0 0x1000>,
|
|
<0 0x10001000 0 0x1000>;
|
|
mediatek,bus_dbg_con_offset = <0x2fc>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
ccifdriver:ccifdriver@10209000 {
|
|
compatible = "mediatek,ccci_ccif";
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
mediatek,sram_size = <512>;
|
|
/*CCIF0 174/206, CCIF0 175/207*/
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_CCIF_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF1_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF1_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF2_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF2_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF4_MD>;
|
|
clock-names = "infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif2-ap",
|
|
"infra-ccif2-md",
|
|
"infra-ccif4-md";
|
|
};
|
|
|
|
iommu0: m4u@10220000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,iommu_v0";
|
|
reg = <0 0x10220000 0 0x1000>;
|
|
mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb2
|
|
&smi_larb3 &smi_larb5 &smi_larb7
|
|
&smi_larb8 &smi_larb9 &smi_larb10>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
iommu1: m4u@1024f000 {
|
|
cell-index = <1>;
|
|
compatible = "mediatek,iommu_v0";
|
|
reg = <0 0x1024f000 0 0x1000>;
|
|
mediatek,larbs = <&smi_larb6 &smi_larb11>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
m4u@10224000 {
|
|
cell-index = <2>;
|
|
compatible = "mediatek,sec_mm_m4u";
|
|
reg = <0 0x10224000 0 0x1000>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
m4u@10253000 {
|
|
cell-index = <3>;
|
|
compatible = "mediatek,sec_vpu_m4u";
|
|
reg = <0 0x10253000 0 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
gce_mbox: gce_mbox@10228000 {
|
|
compatible = "mediatek,mt6779-gce";
|
|
reg = <0 0x10228000 0 0x4000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
|
|
#mbox-cells = <3>;
|
|
#gce-event-cells = <1>;
|
|
#gce-subsys-cells = <2>;
|
|
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
|
|
clocks = <&infracfg_ao CLK_INFRA_GCE>,
|
|
<&infracfg_ao CLK_INFRA_GCE_26M>;
|
|
clock-names = "gce", "gce-timer";
|
|
};
|
|
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
|
|
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
gce_mbox_svp: gce_mbox_svp@10228000 {
|
|
compatible = "mediatek,mailbox-gce-svp";
|
|
reg = <0 0x10228000 0 0x4000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
|
#mbox-cells = <3>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
|
|
<&infracfg_ao INFRACFG_AO_GCE_26M_CG>;
|
|
clock-names = "gce", "GCE_TIMER";
|
|
};
|
|
#endif
|
|
|
|
mtk-cmdq-mdp@10228000 {
|
|
compatible = "mediatek,mdp";
|
|
|
|
iommus = <&iommu0 M4U_PORT_MDP_PVRIC0>,
|
|
<&iommu0 M4U_PORT_MDP_PVRIC1>,
|
|
<&iommu0 M4U_PORT_MDP_RDMA0>,
|
|
<&iommu0 M4U_PORT_MDP_RDMA1>,
|
|
<&iommu0 M4U_PORT_MDP_WROT0_R>,
|
|
<&iommu0 M4U_PORT_MDP_WROT0_W>,
|
|
<&iommu0 M4U_PORT_MDP_WROT1_R>,
|
|
<&iommu0 M4U_PORT_MDP_WROT1_W>;
|
|
};
|
|
|
|
gce: gce@10228000 {
|
|
compatible = "mediatek,gce";
|
|
reg = <0 0x10228000 0 0x4000>;
|
|
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
|
|
disp_mutex_reg = <0x14016000 0x1000>;
|
|
g3d_config_base = <0x13000000 0 0xffff0000>;
|
|
mmsys_config_base = <0x14000000 1 0xffff0000>;
|
|
disp_dither_base = <0x14010000 2 0xffff0000>;
|
|
mm_na_base = <0x14020000 3 0xffff0000>;
|
|
imgsys_base = <0x15020000 4 0xffff0000>;
|
|
vdec_gcon_base = <0x18800000 5 0xffff0000>;
|
|
venc_gcon_base = <0x18810000 6 0xffff0000>;
|
|
conn_peri_base = <0x18820000 7 0xffff0000>;
|
|
topckgen_base = <0x18830000 8 0xffff0000>;
|
|
kp_base = <0x18840000 9 0xffff0000>;
|
|
scp_sram_base = <0x10000000 10 0xffff0000>;
|
|
infra_na3_base = <0x10010000 11 0xffff0000>;
|
|
infra_na4_base = <0x10020000 12 0xffff0000>;
|
|
scp_base = <0x10030000 13 0xffff0000>;
|
|
mcucfg_base = <0x10040000 14 0xffff0000>;
|
|
gcpu_base = <0x10050000 15 0xffff0000>;
|
|
usb0_base = <0x10200000 16 0xffff0000>;
|
|
usb_sif_base = <0x10280000 17 0xffff0000>;
|
|
audio_base = <0x17000000 18 0xffff0000>;
|
|
vdec_base = <0x17010000 19 0xffff0000>;
|
|
msdc2_base = <0x17020000 20 0xffff0000>;
|
|
vdec1_base = <0x17030000 21 0xffff0000>;
|
|
msdc3_base = <0x18000000 22 0xffff0000>;
|
|
ap_dma_base = <0x18010000 23 0xffff0000>;
|
|
gce_base = <0x18020000 24 0xffff0000>;
|
|
vdec2_base = <0x18040000 25 0xffff0000>;
|
|
vdec3_base = <0x18050000 26 0xffff0000>;
|
|
camsys_base = <0x18080000 27 0xffff0000>;
|
|
camsys1_base = <0x180a0000 28 0xffff0000>;
|
|
camsys2_base = <0x180b0000 29 0xffff0000>;
|
|
pwm_sw_base = <0x11000000 99 0xffff0000>;
|
|
imgsys2_base = <0x15010000 99 0xffff0000>;
|
|
ipesys_base = <0x1b000000 99 0xffff0000>;
|
|
dpe_base = <0x1b100000 99 0xffff0000>;
|
|
mipitx0_base = <0x11e50000 99 0xffff0000>;
|
|
disp_rdma0_sof = <0>;
|
|
disp_rdma1_sof = <1>;
|
|
mdp_rdma0_sof = <2>;
|
|
mdp_rdma1_sof = <3>;
|
|
mdp_rsz0_sof = <4>;
|
|
mdp_rsz1_sof = <5>;
|
|
mdp_tdshp_sof = <6>;
|
|
mdp_wrot0_sof = <7>;
|
|
mdp_wrot1_sof = <8>;
|
|
disp_ovl0_sof = <9>;
|
|
disp_2l_ovl0_sof = <10>;
|
|
disp_2l_ovl1_sof = <11>;
|
|
disp_wdma0_sof = <12>;
|
|
disp_color0_sof = <13>;
|
|
disp_ccorr0_sof = <14>;
|
|
disp_aal0_sof = <15>;
|
|
disp_gamma0_sof = <16>;
|
|
disp_dither0_sof = <17>;
|
|
disp_pwm0_sof = <18>;
|
|
disp_dsi0_sof = <19>;
|
|
disp_dpi0_sof = <20>;
|
|
disp_postmask0_sof = <21>;
|
|
disp_rsz0_sof = <22>;
|
|
mdp_aal_sof = <23>;
|
|
mdp_ccorr_sof = <24>;
|
|
disp_dbi0_sof = <25>;
|
|
isp_relay_sof = <26>;
|
|
ipu_relay_sof = <27>;
|
|
disp_rdma0_frame_done = <28>;
|
|
disp_rdma1_frame_done = <29>;
|
|
mdp_rdma0_frame_done = <30>;
|
|
mdp_rdma1_frame_done = <31>;
|
|
mdp_rsz0_frame_done = <32>;
|
|
mdp_rsz1_frame_done = <33>;
|
|
mdp_tdshp_frame_done = <34>;
|
|
mdp_wrot0_write_frame_done = <35>;
|
|
mdp_wrot1_write_frame_done = <36>;
|
|
disp_ovl0_frame_done = <37>;
|
|
disp_2l_ovl0_frame_done = <38>;
|
|
disp_2l_ovl1_frame_done = <39>;
|
|
disp_wdma0_frame_done = <40>;
|
|
disp_color0_frame_done = <41>;
|
|
disp_ccorr0_frame_done = <42>;
|
|
disp_aal0_frame_done = <43>;
|
|
disp_gamma0_frame_done = <44>;
|
|
disp_dither0_frame_done = <45>;
|
|
disp_dsi0_frame_done = <46>;
|
|
disp_dpi0_frame_done = <47>;
|
|
disp_rsz0_frame_done = <49>;
|
|
mdp_aal_frame_done = <50>;
|
|
mdp_ccorr_frame_done = <51>;
|
|
disp_postmask0_frame_done = <52>;
|
|
stream_done_0 = <130>;
|
|
stream_done_1 = <131>;
|
|
stream_done_2 = <132>;
|
|
stream_done_3 = <133>;
|
|
stream_done_4 = <134>;
|
|
stream_done_5 = <135>;
|
|
stream_done_6 = <136>;
|
|
stream_done_7 = <137>;
|
|
stream_done_8 = <138>;
|
|
stream_done_9 = <139>;
|
|
stream_done_10 = <140>;
|
|
stream_done_11 = <141>;
|
|
buf_underrun_event_0 = <142>;
|
|
buf_underrun_event_1 = <143>;
|
|
buf_underrun_event_2 = <144>;
|
|
buf_underrun_event_3 = <145>;
|
|
dsi0_te_event = <146>;
|
|
dsi0_irq_event = <147>;
|
|
dsi0_done_event = <148>;
|
|
disp_postmask0_frame_rst_done_pulse = <150>;
|
|
disp_wdma0_rst_done = <151>;
|
|
mdp_wrot0_rst_done = <153>;
|
|
mdp_rdma0_rst_done = <154>;
|
|
disp_ovl0_frame_rst_done_pusle = <155>;
|
|
disp_ovl0_2l_frame_rst_done_pusle = <156>;
|
|
disp_ovl1_2l_frame_rst_done_pusle = <157>;
|
|
dip_cq_thread0_frame_done = <257>;
|
|
dip_cq_thread1_frame_done = <258>;
|
|
dip_cq_thread2_frame_done = <259>;
|
|
dip_cq_thread3_frame_done = <260>;
|
|
dip_cq_thread4_frame_done = <261>;
|
|
dip_cq_thread5_frame_done = <262>;
|
|
dip_cq_thread6_frame_done = <263>;
|
|
dip_cq_thread7_frame_done = <264>;
|
|
dip_cq_thread8_frame_done = <265>;
|
|
dip_cq_thread9_frame_done = <266>;
|
|
dip_cq_thread10_frame_done = <267>;
|
|
dip_cq_thread11_frame_done = <268>;
|
|
dip_cq_thread12_frame_done = <269>;
|
|
dip_cq_thread13_frame_done = <270>;
|
|
dip_cq_thread14_frame_done = <271>;
|
|
dip_cq_thread15_frame_done = <272>;
|
|
dip_cq_thread16_frame_done = <273>;
|
|
dip_cq_thread17_frame_done = <274>;
|
|
dip_cq_thread18_frame_done = <275>;
|
|
dip_dma_err_event = <276>;
|
|
amd_frame_done = <277>;
|
|
mfb_done = <278>;
|
|
wpe_a_frame_done = <279>;
|
|
venc_done = <289>;
|
|
venc_cmdq_pause_done = <290>;
|
|
jpgenc_done = <291>;
|
|
venc_mb_done = <292>;
|
|
venc_128byte_cnt_done = <293>;
|
|
isp_frame_done_a = <321>;
|
|
isp_frame_done_b = <322>;
|
|
isp_frame_done_c = <323>;
|
|
camsv_0_pass1_done = <324>;
|
|
camsv_0_2_pass1_done = <325>;
|
|
camsv_1_pass1_done = <326>;
|
|
camsv_2_pass1_done = <327>;
|
|
camsv_3_pass1_done = <328>;
|
|
tsf_done = <329>;
|
|
seninf_0_fifo_full = <330>;
|
|
seninf_1_fifo_full = <331>;
|
|
seninf_2_fifo_full = <332>;
|
|
seninf_3_fifo_full = <333>;
|
|
seninf_4_fifo_full = <334>;
|
|
seninf_5_fifo_full = <335>;
|
|
seninf_6_fifo_full = <336>;
|
|
seninf_7_fifo_full = <337>;
|
|
tg_ovrun_a_int_dly = <338>;
|
|
tg_ovrun_b_int_dly = <339>;
|
|
tg_ovrun_c_int = <340>;
|
|
tg_graberr_a_int_dly = <341>;
|
|
tg_graberr_b_int_dly = <342>;
|
|
tg_graberr_c_int = <343>;
|
|
cq_vr_snap_a_int_dly = <344>;
|
|
cq_vr_snap_b_int_dly = <345>;
|
|
cq_vr_snap_c_int = <346>;
|
|
dma_r1_error_a_int_dly = <347>;
|
|
dma_r1_error_b_int_dly = <348>;
|
|
dma_r1_error_c_int = <349>;
|
|
apu_gce_core0_event_0 = <353>;
|
|
apu_gce_core0_event_1 = <354>;
|
|
apu_gce_core0_event_2 = <355>;
|
|
apu_gce_core0_event_3 = <356>;
|
|
apu_gce_core1_event_0 = <385>;
|
|
apu_gce_core1_event_1 = <386>;
|
|
apu_gce_core1_event_2 = <387>;
|
|
apu_gce_core1_event_3 = <388>;
|
|
vdec_event_0 = <416>;
|
|
vdec_event_1 = <417>;
|
|
vdec_event_2 = <418>;
|
|
vdec_event_3 = <419>;
|
|
vdec_event_4 = <420>;
|
|
vdec_event_5 = <421>;
|
|
vdec_event_6 = <422>;
|
|
vdec_event_7 = <423>;
|
|
vdec_event_8 = <424>;
|
|
vdec_event_9 = <425>;
|
|
vdec_event_10 = <426>;
|
|
vdec_event_11 = <427>;
|
|
vdec_event_12 = <428>;
|
|
vdec_event_13 = <429>;
|
|
vdec_event_14 = <430>;
|
|
vdec_event_15 = <431>;
|
|
fdvt_done = <449>;
|
|
fe_done = <450>;
|
|
rsc_frame_done = <451>;
|
|
dvs_done_async_shot = <452>;
|
|
dvp_done_async_shot = <453>;
|
|
dsi0_te_from_infra = <898>;
|
|
sram_size_cpr_64 = <656>;
|
|
mmsys_config = <&mmsys>;
|
|
mm_mutex = <&mm_mutex>;
|
|
mdp_rdma0 = <&mdp_rdma0>;
|
|
mdp_rdma1 = <&mdp_rdma1>;
|
|
mdp_rsz0 = <&mdp_rsz0>;
|
|
mdp_rsz1 = <&mdp_rsz1>;
|
|
mdp_wrot0 = <&mdp_wrot0>;
|
|
mdp_wrot1 = <&mdp_wrot1>;
|
|
mdp_tdshp0 = <&mdp_tdshp>;
|
|
mdp_aal0 = <&mdp_aal>;
|
|
mdp_hdr0 = <&mdp_hdr>;
|
|
mdp_color0 = <&disp_color0>;
|
|
smi_larb0 = <&smi_larb0>;
|
|
sram_share_cnt = <2>;
|
|
sram_share_engine = <21>, <22>;
|
|
sram_share_event = <710>, <711>;
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
thread_count = <24>;
|
|
secure_thread = <8 10>;
|
|
mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 1 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 2 0 CMDQ_THR_PRIO_5>,
|
|
<&gce_mbox 3 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 5 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 6 0 CMDQ_THR_PRIO_3>,
|
|
<&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
|
|
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
<&gce_mbox_svp 8 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox_svp 9 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox_svp 10 0 CMDQ_THR_PRIO_1>,
|
|
#else
|
|
<&gce_mbox 8 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 9 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 10 0 CMDQ_THR_PRIO_1>,
|
|
#endif
|
|
<&gce_mbox 11 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 13 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
|
|
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
<&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
|
|
#else
|
|
<&gce_mbox 15 0 CMDQ_THR_PRIO_1>,
|
|
#endif
|
|
<&gce_mbox 18 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 19 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 20 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 21 0 CMDQ_THR_PRIO_1>;
|
|
clocks = <&infracfg_ao CLK_INFRA_GCE>,
|
|
<&infracfg_ao CLK_INFRA_GCE_26M>;
|
|
clock-names = "GCE", "GCE_TIMER";
|
|
};
|
|
|
|
ap_ccif2@1023c000 {
|
|
compatible = "mediatek,ap_ccif2";
|
|
reg = <0 0x1023c000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif4@1024d000 {
|
|
compatible = "mediatek,md_ccif4";
|
|
reg = <0 0x1024d000 0 0x1000>;
|
|
};
|
|
|
|
md_ccif4@1024e000 {
|
|
compatible = "mediatek,md_ccif4";
|
|
reg = <0 0x1024e000 0 0x1000>;
|
|
};
|
|
|
|
sspm: sspm@10400000 {
|
|
compatible = "mediatek,mt6779-sspm";
|
|
reg = <0 0x10400000 0 0x28000>,
|
|
<0 0x10440000 0 0x10000>,
|
|
<0 0x10450000 0 0x100>,
|
|
<0 0x10451000 0 0x8>,
|
|
<0 0x10460000 0 0x100>,
|
|
<0 0x10461000 0 0x8>,
|
|
<0 0x10470000 0 0x100>,
|
|
<0 0x10471000 0 0x8>,
|
|
<0 0x10480000 0 0x100>,
|
|
<0 0x10481000 0 0x8>,
|
|
<0 0x10490000 0 0x100>,
|
|
<0 0x10491000 0 0x8>;
|
|
|
|
reg-names = "sspm_base",
|
|
"cfgreg",
|
|
"mbox0_base",
|
|
"mbox0_ctrl",
|
|
"mbox1_base",
|
|
"mbox1_ctrl",
|
|
"mbox2_base",
|
|
"mbox2_ctrl",
|
|
"mbox3_base",
|
|
"mbox3_ctrl",
|
|
"mbox4_base",
|
|
"mbox4_ctrl";
|
|
|
|
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "ipc",
|
|
"mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4";
|
|
|
|
clocks = <&infracfg_ao CLK_INFRA_SSPM_26M_SELF>,
|
|
<&infracfg_ao CLK_INFRA_SSPM_32K_SELF>,
|
|
<&infracfg_ao CLK_INFRA_SSPM_BUS_HCLK>;
|
|
|
|
clock-names = "sspm_26m", "sspm_32k", "sspm_bus_hclk";
|
|
};
|
|
|
|
scp: scp@10500000 {
|
|
compatible = "mediatek,scp";
|
|
status = "okay";
|
|
reg = <0 0x10500000 0 0x80000>,
|
|
<0 0x105c0000 0 0x3000>,
|
|
<0 0x105c4000 0 0x1000>,
|
|
<0 0x105d4000 0 0x6000>;
|
|
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
|
|
core_1 = "enable";
|
|
scp_sramSize = <0x00080000>;
|
|
scp_mpuRegionId = <6>;
|
|
scp_feature_tbl = <0 47>, /* vow */
|
|
<1 356>, /* dsp */
|
|
<2 62>, /* sensor */
|
|
<3 47>, /* mp3 */
|
|
<4 26>, /* flp */
|
|
<5 0>, /* rtos */
|
|
<6 200>, /* speaker */
|
|
<7 0>, /* vcore */
|
|
<8 100>, /* barge in */
|
|
<9 10>; /* vow dump */
|
|
|
|
scp_mem_key = "mediatek,reserve-memory-scp_share";
|
|
scp_mem_tbl = <1 0x100000>, /* sensor */
|
|
<3 0x001000>, /* flp */
|
|
<4 0x200000>; /* logger */
|
|
};
|
|
|
|
scp_dvfs {
|
|
compatible = "mediatek,scp_dvfs";
|
|
clocks = <&topckgen CLK_TOP_SCP>,
|
|
<&clk26m>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D2_D8>,
|
|
<&topckgen CLK_TOP_MAINPLL_D2_D4>,
|
|
<&topckgen CLK_TOP_MAINPLL_D3>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3>,
|
|
<&topckgen CLK_TOP_AD_OSC2_CK>,
|
|
<&topckgen CLK_TOP_OSC2_D2>,
|
|
<&topckgen CLK_TOP_OSC2_D3>;
|
|
|
|
clock-names = "clk_mux",
|
|
"clk_pll_0",
|
|
"clk_pll_1",
|
|
"clk_pll_2",
|
|
"clk_pll_3",
|
|
"clk_pll_4",
|
|
"clk_pll_5",
|
|
"clk_pll_6",
|
|
"clk_pll_7";
|
|
|
|
dvfsrc-opp-num = <3>;
|
|
dvfs-opp =
|
|
/* vcore vsram uv rc spm freq mux */
|
|
< 575000 825000 0xff 0x0 0x0 110 1>,
|
|
< 600000 875000 0xff 0x0 0x0 130 1>,
|
|
< 625000 875000 2 0x0 0x1 165 2>,
|
|
< 700000 875000 1 0x1 0x12 330 2>,
|
|
< 800000 875000 0 0x2 0x28 416 4>;
|
|
|
|
sshub-vcore-supply = <&mt_pmic_vcore_sshub_buck_reg>;
|
|
sshub-vsram-supply =
|
|
<&mt_pmic_vsram_others_sshub_ldo_reg>;
|
|
|
|
pmic = <&main_pmic>;
|
|
pmic-feature = "pmic-vow-lp", "pmic-pmrc";
|
|
/*
|
|
* feature on off setting.
|
|
* 1: turns on, 0: turns off.
|
|
*/
|
|
pmic-feature-cfg = <1 0>;
|
|
pmic-vow-lp-reg = <0x1520 0x1 11 1>,
|
|
<0x1514 0x1 11 1>,
|
|
<0x151a 0x1 11 1>,
|
|
<0x1f14 0x1 11 1>,
|
|
<0x1f1a 0x1 11 1>;
|
|
pmic-vow-lp-cfg = <0 0>, <1 0>, <1 0>, <1 0>, <1 0>;
|
|
pmic-pmrc-reg = <0x1ac 0x1 2 1>;
|
|
pmic-pmrc-cfg = <1 0>;
|
|
|
|
gpio = <&pio 1>;
|
|
gpio-feature = "gpio-mode";
|
|
gpio-feature-cfg = <1>;
|
|
gpio-mode-reg = <0x410 0x7 24 1>;
|
|
};
|
|
|
|
adsp: adsp@10600000 {
|
|
compatible = "mediatek,audio_dsp";
|
|
reg = <0 0x10600000 0 0x10000>, /*ctrl reg*/
|
|
<0 0x10630000 0 0x9000>, /* ITCM */
|
|
<0 0x10610000 0 0x8000>, /* DTCM */
|
|
<0 0x10001000 0 0x1000>, /* infracfg_ao */
|
|
<0 0x10003000 0 0x1000>; /* pericfg */
|
|
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao INFRACFG_AO_FADSP_CG>,
|
|
<&topckgen TOP_MUX_ADSP>,
|
|
<&clk26m>,
|
|
<&topckgen TOP_MMPLL_D4>,
|
|
<&topckgen TOP_ADSPPLL_D4>,
|
|
<&topckgen TOP_ADSPPLL_D6>;
|
|
clock-names = "clk_adsp_infra",
|
|
"clk_top_adsp_sel",
|
|
"clk_adsp_clk26m",
|
|
"clk_top_mmpll_d4",
|
|
"clk_top_adsppll_d4",
|
|
"clk_top_adsppll_d6";
|
|
sysram = /bits/ 64 <0x55c00000 0x700000>;
|
|
nvmem-cells = <&efuse_segment>;
|
|
nvmem-cell-names = "efuse_segment_cell";
|
|
};
|
|
|
|
auxadc: auxadc@11001000 {
|
|
compatible = "mediatek,mt6779-auxadc",
|
|
"mediatek,mt6765-auxadc";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AUXADC>;
|
|
clock-names = "main";
|
|
#io-channel-cells = <1>;
|
|
/* Auxadc efuse calibration */
|
|
/* 1. Auxadc cali on/off bit shift */
|
|
mediatek,cali-en-bit = <20>;
|
|
/* 2. Auxadc cali ge bits shift */
|
|
mediatek,cali-ge-bit = <10>;
|
|
/* 3. Auxadc cali oe bits shift */
|
|
mediatek,cali-oe-bit = <0>;
|
|
/* 4. Auxadc cali efuse reg offset */
|
|
mediatek,cali-efuse-reg-offset = <0x1c4>;
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
apdma: dma-controller@11000880 {
|
|
compatible = "mediatek, mt6779-uart-dma",
|
|
"mediatek,mt6577-uart-dma";
|
|
reg = <0 0x11000880 0 0x80>,
|
|
<0 0x11000900 0 0x80>,
|
|
<0 0x11000980 0 0x80>,
|
|
<0 0x11000A00 0 0x80>;
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_LOW>;
|
|
dma-requests = <4>;
|
|
clocks = <&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "apdma";
|
|
dma-bits = <34>;
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@11002000 {
|
|
compatible = "mediatek,mt6779-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>, <&infracfg_ao CLK_INFRA_UART0>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 0
|
|
&apdma 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
uart1: serial@11003000 {
|
|
compatible = "mediatek,mt6779-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&uart_clk>, <&infracfg_ao CLK_INFRA_UART1>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 2
|
|
&apdma 3>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
i2c_common: i2c_common {
|
|
compatible = "mediatek,i2c_common";
|
|
dma_support = /bits/ 8 <3>;
|
|
idvfs = /bits/ 8 <1>;
|
|
set_dt_div = /bits/ 8 <1>;
|
|
check_max_freq = /bits/ 8 <1>;
|
|
ver = /bits/ 8 <2>;
|
|
set_ltiming = /bits/ 8 <1>;
|
|
ext_time_config = /bits/ 16 <0x1801>;
|
|
cnt_constraint = /bits/ 8 <1>;
|
|
};
|
|
|
|
i2c0: i2c0@11007000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <0>;
|
|
reg = <0 0x11007000 0 0x1000>,
|
|
<0 0x11000080 0 0x80>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <51>;
|
|
sda-gpio-id = <52>;
|
|
gpio_start = <0x11e20000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x80>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c1: i2c1@11008000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <1>;
|
|
reg = <0 0x11008000 0 0x1000>,
|
|
<0 0x11000100 0 0x80>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <61>;
|
|
sda-gpio-id = <62>;
|
|
gpio_start = <0x11e20000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x80>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c2: i2c2@11009000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <2>;
|
|
reg = <0 0x11009000 0 0x1000>,
|
|
<0 0x11000180 0 0x180>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <112>;
|
|
sda-gpio-id = <113>;
|
|
gpio_start = <0x11d10000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
ch_offset_ccu = <0x200>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c3: i2c3@1100f000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <3>;
|
|
reg = <0 0x1100f000 0 0x1000>,
|
|
<0 0x11000300 0 0x80>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <55>;
|
|
sda-gpio-id = <56>;
|
|
gpio_start = <0x11e20000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x80>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c4: i2c4@11011000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <4>;
|
|
reg = <0 0x11011000 0 0x1000>,
|
|
<0 0x11000380 0 0x180>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <110>;
|
|
sda-gpio-id = <111>;
|
|
gpio_start = <0x11d10000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0xa0>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
ch_offset_ccu = <0x200>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c5: i2c5@11016000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <5>;
|
|
reg = <0 0x11016000 0 0x1000>,
|
|
<0 0x11000500 0 0x80>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <28>;
|
|
sda-gpio-id = <29>;
|
|
gpio_start = <0x11f20000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x70>;
|
|
rsel_cfg = <0xb0>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c6: i2c6@11005000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <6>;
|
|
reg = <0 0x11005000 0 0x1000>,
|
|
<0 0x11000580 0 0x100>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <45>;
|
|
sda-gpio-id = <46>;
|
|
gpio_start = <0x11e20000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x30>;
|
|
pu_cfg = <0x80>;
|
|
rsel_cfg = <0xd0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
mediatek,hs_only;
|
|
};
|
|
i2c7: i2c7@1101a000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <7>;
|
|
reg = <0 0x1101a000 0 0x1000>,
|
|
<0 0x11000680 0 0x100>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <198>;
|
|
sda-gpio-id = <199>;
|
|
gpio_start = <0x11e70000>;
|
|
mem_len = <0x1000>;
|
|
eh_cfg = <0x10>;
|
|
pu_cfg = <0x40>;
|
|
rsel_cfg = <0x60>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
mediatek,hs_only;
|
|
};
|
|
i2c8: i2c8@1101b000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <8>;
|
|
reg = <0 0x1101b000 0 0x1000>,
|
|
<0 0x11000780 0 0x80>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
i2c9: i2c9@11015000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <9>;
|
|
reg = <0 0x11015000 0 0x1000>,
|
|
<0 0x11000800 0 0x80>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_I2C0>,
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
spi0: spi0@1100a000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI0>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
therm_ctrl@1100b000 {
|
|
compatible = "mediatek,therm_ctrl";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_THERM>;
|
|
clock-names = "therm-main";
|
|
/* TOPRGU access */
|
|
regmap = <&toprgu>;
|
|
therm_ctrl,toprgu_en_offset = <0x30>;
|
|
therm_ctrl,toprgu_en_bit = <18>;
|
|
therm_ctrl,toprgu_en_key = <0x33000000>;
|
|
therm_ctrl,toprgu_irq_offset = <0x34>;
|
|
therm_ctrl,toprgu_irq_bit = <18>;
|
|
therm_ctrl,toprgu_irq_key = <0x44000000>;
|
|
/* efuse access */
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
therm_ctrl,efuse_num = <6>;
|
|
therm_ctrl,efuse_offset =
|
|
<0x194 0x190 0x198 0x1bc 0x1c0 0x1c8>;
|
|
};
|
|
tboard_thermistor1: thermal-sensor1 {
|
|
compatible = "mediatek,mtboard-thermistor1";
|
|
io-channels = <&auxadc 0>;
|
|
io-channel-names = "thermistor-ch0";
|
|
interconnects = <&auxadc 0>;
|
|
};
|
|
|
|
tboard_thermistor2: thermal-sensor2 {
|
|
compatible = "mediatek,mtboard-thermistor2";
|
|
io-channels = <&auxadc 1>;
|
|
io-channel-names = "thermistor-ch1";
|
|
interconnects = <&auxadc 1>;
|
|
};
|
|
drcc: drcc {
|
|
compatible = "mediatek,drcc";
|
|
state = <255>;
|
|
drcc0_Vref = <255>;
|
|
drcc1_Vref = <255>;
|
|
drcc2_Vref = <255>;
|
|
drcc3_Vref = <255>;
|
|
drcc4_Vref = <255>;
|
|
drcc5_Vref = <255>;
|
|
drcc6_Vref = <255>;
|
|
drcc7_Vref = <255>;
|
|
drcc0_Hwgatepct = <255>;
|
|
drcc1_Hwgatepct = <255>;
|
|
drcc2_Hwgatepct = <255>;
|
|
drcc3_Hwgatepct = <255>;
|
|
drcc4_Hwgatepct = <255>;
|
|
drcc5_Hwgatepct = <255>;
|
|
drcc6_Hwgatepct = <255>;
|
|
drcc7_Hwgatepct = <255>;
|
|
drcc0_Code = <255>;
|
|
drcc1_Code = <255>;
|
|
drcc2_Code = <255>;
|
|
drcc3_Code = <255>;
|
|
drcc4_Code = <255>;
|
|
drcc5_Code = <255>;
|
|
drcc6_Code = <255>;
|
|
drcc7_Code = <255>;
|
|
};
|
|
btif@1100c000 {
|
|
compatible = "mediatek,btif";
|
|
/*btif base*/
|
|
reg = <0 0x1100c000 0 0x1000>,
|
|
/*btif tx dma base*/
|
|
<0 0x11000b80 0 0x80>,
|
|
/*btif rx dma base*/
|
|
<0 0x11000c00 0 0x80>;
|
|
/*btif irq, IRQS_Sync ID, btif_irq_b*/
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>,
|
|
/*btif tx dma irq*/
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>,
|
|
/*btif rx dma irq*/
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_INFRA_BTIF>,
|
|
/*btif clock*/
|
|
<&infracfg_ao CLK_INFRA_AP_DMA>;
|
|
/*ap dma clock*/
|
|
clock-names = "btifc","apdmac";
|
|
};
|
|
|
|
disp_pwm0@1100e000 {
|
|
compatible = "mediatek,mt6779-disp_pwm0";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
regulator_vibrator {
|
|
compatible = "regulator-vibrator";
|
|
min-volt = <2300000>;
|
|
max-volt = <3200000>;
|
|
min-limit = <15>;
|
|
max-limit = <15000>;
|
|
vib-supply = <&mt_pmic_vibr_ldo_reg>;
|
|
};
|
|
|
|
spi1: spi1@11010000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI1>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi2: spi2@11012000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI2>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi3: spi3@11013000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI3>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi4: spi4@11018000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11018000 0 0x1000>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI4>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi5: spi5@11019000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11019000 0 0x1000>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI5>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi6: spi6@1101d000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x1101d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI6>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi7: spi7@1101e000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x1101e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>,
|
|
<&topckgen CLK_TOP_SPI>,
|
|
<&infracfg_ao CLK_INFRA_SPI7>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
mmc0: mmc@11230000 {
|
|
compatible = "mediatek,mt6779-mmc";
|
|
reg = <0 0x11230000 0 0x10000>,
|
|
<0 0x11f50000 0 0x10000>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MSDC50_0>,
|
|
<&infracfg_ao CLK_INFRA_MSDC0>,
|
|
<&infracfg_ao CLK_INFRA_MSDC0_SCK>,
|
|
<&infracfg_ao CLK_INFRA_AES_UFSFDE>;
|
|
clock-names = "source", "hclk", "source_cg",
|
|
"crypto_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
mmc1: mmc@11240000 {
|
|
compatible = "mediatek,mt6779-mmc";
|
|
reg = <0 0x11240000 0 0x1000>,
|
|
<0 0x11e10000 0 0x1000>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_MSDC30_1>,
|
|
<&infracfg_ao CLK_INFRA_MSDC1>,
|
|
<&infracfg_ao CLK_INFRA_MSDC1_SCK>;
|
|
clock-names = "source", "hclk", "source_cg";
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshci@11270000 {
|
|
compatible = "mediatek,mt8183-ufshci";
|
|
reg = <0 0x11270000 0 0x2300>;
|
|
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>;
|
|
phys = <&ufsphy>;
|
|
|
|
clocks = <&infracfg_ao CLK_INFRA_UFS>,
|
|
<&infracfg_ao CLK_INFRA_UFS_TICK>,
|
|
<&infracfg_ao CLK_INFRA_UFS_AXI>,
|
|
<&infracfg_ao CLK_INFRA_UNIPRO_TICK>,
|
|
<&infracfg_ao CLK_INFRA_UNIPRO_MBIST>,
|
|
<&topckgen CLK_TOP_FAES_UFSFDE>,
|
|
<&infracfg_ao CLK_INFRA_AES_UFSFDE>,
|
|
<&infracfg_ao CLK_INFRA_AES_BCLK>;
|
|
clock-names = "ufs", "ufs_tick", "ufs_axi",
|
|
"unipro_tick", "unipro_mbist",
|
|
"aes_top", "aes_infra", "aes_bclk";
|
|
freq-table-hz = <0 0>, <0 0>, <0 0>,
|
|
<0 0>, <0 0>, <0 0>,
|
|
<0 0>, <0 0>;
|
|
|
|
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
|
|
vccq2-supply = <&mt_pmic_vufs_ldo_reg>;
|
|
|
|
resets = <&infracfg_rst 0>, <&infracfg_rst 1>,
|
|
<&infracfg_rst 2>;
|
|
reset-names = "hci_rst", "unipro_rst", "crypto_rst";
|
|
|
|
/* Reference clock control mode */
|
|
/* SW mode: 0, Half-HW mode: 1, HW mode: 2 */
|
|
mediatek,refclk_ctrl = <1>;
|
|
};
|
|
|
|
mipi_tx0@11e50000 {
|
|
compatible = "mediatek,mt6779-mipi_tx0";
|
|
reg = <0 0x11e50000 0 0x1000>;
|
|
};
|
|
|
|
ufsphy: phy@11fa0000 {
|
|
compatible = "mediatek,mt8183-ufsphy";
|
|
reg = <0 0x11fa0000 0 0xc000>;
|
|
#phy-cells = <0>;
|
|
|
|
clocks = <&infracfg_ao CLK_INFRA_UNIPRO_SCK>,
|
|
<&infracfg_ao CLK_INFRA_UFS_MP_SAP_BCLK>;
|
|
clock-names = "unipro", "mp";
|
|
};
|
|
|
|
mfg_lorne: mfg_lorne@13000000 {
|
|
clock-frequency = <100000000>;
|
|
compatible = "mediatek,lorne";
|
|
interrupt-names = "RGX";
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_LOW>;
|
|
reg = <0 0x13000000 0 0x80000>;
|
|
ged-supply = <&ged>;
|
|
};
|
|
|
|
gpufreq: gpufreq {
|
|
compatible = "mediatek,mt6779-gpufreq";
|
|
clocks =
|
|
<&topckgen TOP_MUX_MFG>,
|
|
<&topckgen TOP_MFGPLL_CK>,
|
|
<&topckgen TOP_UNIVPLL_D3>,
|
|
<&scpsys SCP_SYS_MFG0>,
|
|
<&scpsys SCP_SYS_MFG1>,
|
|
<&scpsys SCP_SYS_MFG2>,
|
|
<&scpsys SCP_SYS_MFG3>;
|
|
clock-names =
|
|
"clk_mux",
|
|
"clk_main_parent",
|
|
"clk_sub_parent",
|
|
"mtcmos_mfg_async",
|
|
"mtcmos_mfg",
|
|
"mtcmos_mfg_core0",
|
|
"mtcmos_mfg_core1";
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
};
|
|
|
|
ged: ged {
|
|
compatible = "mediatek,ged";
|
|
gpufreq-supply = <&gpufreq>;
|
|
};
|
|
|
|
mfgcfg: clock-controller@13fbf000 {
|
|
compatible = "mediatek,mt6779-mfgcfg", "syscon";
|
|
reg = <0 0x13fbf000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
emichn: emichn@10235000 {
|
|
compatible = "mediatek,mt6779-emichn",
|
|
"mediatek,common-emichn";
|
|
reg = <0 0x10235000 0 0x1000>,
|
|
<0 0x10245000 0 0x1000>;
|
|
};
|
|
|
|
emicen: emicen@10219000 {
|
|
compatible = "mediatek,mt6779-emicen",
|
|
"mediatek,common-emicen";
|
|
reg = <0 0x10219000 0 0x1000>;
|
|
mediatek,emi-reg = <&emichn>;
|
|
};
|
|
|
|
emiisu {
|
|
compatible = "mediatek,mt6779-emiisu",
|
|
"mediatek,common-emiisu";
|
|
ctrl_intf = <1>;
|
|
};
|
|
|
|
emimpu@10226000 {
|
|
compatible = "mediatek,mt6779-emimpu",
|
|
"mediatek,common-emimpu";
|
|
reg = <0 0x10226000 0 0x1000>;
|
|
mediatek,emi-reg = <&emicen>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
|
|
region_cnt = <32>;
|
|
domain_cnt = <16>;
|
|
addr_align = <16>;
|
|
ap_region = <31>;
|
|
ap_apc = <0 5 5 5 0 0 6 5>,
|
|
<0 0 5 0 0 0 5 5>;
|
|
dump = <0x1f0 0x1f8 0x1fc>;
|
|
clear = <0x160 0xffffffff 16>,
|
|
<0x200 0x00000003 16>,
|
|
<0x1f0 0x80000000 1>;
|
|
clear_md = <0x1fc 0x80000000 1>;
|
|
ctrl_intf = <1>;
|
|
slverr = <0>;
|
|
};
|
|
|
|
sys_timer@10017000 {
|
|
compatible = "mediatek,sys_timer",
|
|
"mediatek,mt6765-timer",
|
|
"mediatek,mt6779-timer";
|
|
reg = <0 0x10017000 0 0x1000>;
|
|
reg-names = "sys_timer_base";
|
|
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks =<&clk13m>;
|
|
};
|
|
|
|
sleep: sleep@10006000 {
|
|
compatible = "mediatek,sleep", "syscon";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dramc@10230000 {
|
|
compatible = "mediatek,dramc";
|
|
reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
|
|
<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
|
|
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
|
|
<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
|
|
<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
|
|
<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
|
|
<0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
|
|
<0 0x10246000 0 0x1000>; /* DDRPHY NAO CHB */
|
|
};
|
|
|
|
|
|
mmdvfs_pmqos {
|
|
compatible = "mediatek,mmdvfs_pmqos";
|
|
larb_groups = <0 1 2 3 5 8 9 10>;
|
|
larb0 = <7 7 7 7 7 7 7 8 7>;
|
|
larb1 = <7 7 7 7 7 7 7 7 7 8 7 8 7 7>;
|
|
larb2 = <3 7 4 7 7 7 7 7 7 7 4 7>;
|
|
larb3 = <7 8 8 8 7 7 7 7 7 7 8 8 8 8 8 7
|
|
7 7 7>;
|
|
larb5 = <7 7 7 7 7 7 8 8 8 8 7 7 7 8 8 7
|
|
7 6 6 8 7 7 7 7 7 7>;
|
|
larb8 = <7 7 8 8 7 7 8 8 6 7>;
|
|
larb9 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8
|
|
8 8 8 8 8 7 8 8>;
|
|
larb10 = <8 8 7 7 8 7 7 7 8 8 7 7 8 7 7 7
|
|
8 8 8 8 8 8 8 8 8 8 8 8 8 8 8>;
|
|
cam_larb = <9 10 14>; /* include SMI common CCU */
|
|
max_ostd_larb = <0 1>;
|
|
max_ostd = <40>;
|
|
comm_freq = "disp_freq";
|
|
mm_step0 = <606 1 0 10>;
|
|
mm_step1 = <450 1 0 14>;
|
|
mm_step2 = <315 1 0 17>;
|
|
cam_step0 = <560 1 1 11>;
|
|
cam_step0_P95 = <560 1 1 11>;
|
|
cam_step1 = <416 1 1 15>;
|
|
cam_step2 = <315 1 1 17>;
|
|
ccu_step0 = <560 1 7 11>;
|
|
ccu_step0_P95 = <560 1 7 11>;
|
|
ccu_step1 = <416 1 7 15>;
|
|
ccu_step2 = <315 1 7 17>;
|
|
img_step0 = <606 1 2 10>;
|
|
img_step1 = <416 1 2 15>;
|
|
img_step2 = <315 1 2 17>;
|
|
img_step_limit_0 = <546 1 2 12>;
|
|
ipe_step0 = <546 1 3 12>;
|
|
ipe_step1 = <416 1 3 15>;
|
|
ipe_step2 = <315 1 3 17>;
|
|
dpe_step0 = <546 1 6 12>;
|
|
dpe_step1 = <450 1 6 14>;
|
|
dpe_step2 = <364 1 6 16>;
|
|
venc_step0 = <630 1 4 8>;
|
|
venc_step1 = <450 1 4 14>;
|
|
venc_step2 = <364 1 4 16>;
|
|
vdec_step0 = <624 1 5 9>;
|
|
vdec_step1 = <416 1 5 15>;
|
|
vdec_step2 = <312 1 5 18>;
|
|
/* fmeter_mux_ids: Mapping to mux sequence in clocks */
|
|
fmeter_mux_ids = <2 8 5 6 50 51 7 9>;
|
|
vopp_steps = <0 1 2>;
|
|
disp_freq = "mm_step0", "mm_step1", "mm_step2";
|
|
mdp_freq = "mm_step0", "mm_step1", "mm_step2";
|
|
cam_freq = "cam_step0","cam_step1","cam_step2";
|
|
ccu_freq = "ccu_step0","ccu_step1","ccu_step2";
|
|
img_freq = "img_step0","img_step1","img_step2";
|
|
vdec_freq = "vdec_step0","vdec_step1","vdec_step2";
|
|
venc_freq = "venc_step0","venc_step1","venc_step2";
|
|
ipe_freq = "ipe_step0","ipe_step1","ipe_step2";
|
|
dpe_freq = "dpe_step0","dpe_step1","dpe_step2";
|
|
img_freq_limit_size = <3>;
|
|
img_freq_limit_0 = "img_step_limit_0",
|
|
"img_step1","img_step2";
|
|
img_freq_limit_1 = "img_step1","img_step1","img_step2";
|
|
img_freq_limit_2 = "img_step2","img_step1","img_step2";
|
|
clocks = <&topckgen TOP_MUX_MM>, /* 0 */
|
|
<&topckgen TOP_MUX_CAM>, /* 1 */
|
|
<&topckgen TOP_MUX_IMG>, /* 2 */
|
|
<&topckgen TOP_MUX_IPE>, /* 3 */
|
|
<&topckgen TOP_MUX_VENC>, /* 4 */
|
|
<&topckgen TOP_MUX_VDEC>, /* 5 */
|
|
<&topckgen TOP_MUX_DPE>, /* 6 */
|
|
<&topckgen TOP_MUX_CCU>, /* 7 */
|
|
<&topckgen TOP_MMPLL_D5>, /* 8 */
|
|
<&topckgen TOP_UNIVPLL_D2>, /* 9 */
|
|
<&topckgen TOP_TVDPLL_MAINPLL_D2_CK>, /* 10 */
|
|
<&topckgen TOP_ADSPPLL_D5>, /* 11 */
|
|
<&topckgen TOP_MAINPLL_D2>, /* 12 */
|
|
<&topckgen TOP_MMPLL_D6>, /* 13 */
|
|
<&topckgen TOP_MMPLL_D7>, /* 14 */
|
|
<&topckgen TOP_UNIVPLL_D3>, /* 15 */
|
|
<&topckgen TOP_MAINPLL_D3>, /* 16 */
|
|
<&topckgen TOP_MMPLL_D5_D2>, /* 17 */
|
|
<&topckgen TOP_UNIVPLL_D2_D2>; /* 18 */
|
|
clock-names = "mmdvfs_clk_mm_mux", /* 0 */
|
|
"mmdvfs_clk_cam_mux", /* 1 */
|
|
"mmdvfs_clk_img_mux", /* 2 */
|
|
"mmdvfs_clk_ipe_mux", /* 3 */
|
|
"mmdvfs_clk_venc_mux", /* 4 */
|
|
"mmdvfs_clk_vdec_mux", /* 5 */
|
|
"mmdvfs_clk_dpe_mux", /* 6 */
|
|
"mmdvfs_clk_ccu_mux", /* 7 */
|
|
"mmdvfs_clk_MMPLL_D5", /* 8 */
|
|
"mmdvfs_clk_UNIVPLL_D2", /* 9 */
|
|
"mmdvfs_clk_TVDPLL_MAINPLL_D2_CK", /* 10 */
|
|
"mmdvfs_clk_ADSPPLL_D5", /* 11 */
|
|
"mmdvfs_clk_MAINPLL_D2", /* 12 */
|
|
"mmdvfs_clk_MMPLL_D6", /* 13 */
|
|
"mmdvfs_clk_MMPLL_D7", /* 14 */
|
|
"mmdvfs_clk_UNIVPLL_D3", /* 15 */
|
|
"mmdvfs_clk_MAINPLL_D3", /* 16 */
|
|
"mmdvfs_clk_MMPLL_D5_D2", /* 17 */
|
|
"mmdvfs_clk_UNIVPLL_D2_D2"; /* 18 */
|
|
};
|
|
|
|
mmsys: clock-controller@14000000 {
|
|
compatible = "mediatek,mt6779-mmsys", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_LOW>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
|
|
<&mmsys CLK_MM_MDP_DL_RX_CK>,
|
|
<&mmsys CLK_MM_IPU_DL_TXCK>,
|
|
<&mmsys CLK_MM_IPU_DL_RX_CK>;
|
|
clock-names = "CAM_MDP_TX",
|
|
"CAM_MDP_RX",
|
|
"CAM_MDP2_TX",
|
|
"CAM_MDP2_RX";
|
|
};
|
|
|
|
mdp_rdma0: mdp_rdma0@14001000 {
|
|
compatible = "mediatek,mt6779-mdp_rdma0";
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_RDMA0>;
|
|
clock-names = "MDP_RDMA0";
|
|
};
|
|
|
|
mdp_rdma1: mdp_rdma1@14002000 {
|
|
compatible = "mediatek,mt6779-mdp_rdma1";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_RDMA1>;
|
|
clock-names = "MDP_RDMA1";
|
|
};
|
|
|
|
mdp_rsz0: mdp_rsz0@14003000 {
|
|
compatible = "mediatek,mt6779-mdp_rsz0";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
|
|
clock-names = "MDP_RSZ0";
|
|
};
|
|
|
|
mdp_rsz1: mdp_rsz1@14004000 {
|
|
compatible = "mediatek,mt6779-mdp_rsz1";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
|
|
clock-names = "MDP_RSZ1";
|
|
};
|
|
|
|
mdp_wrot0: mdp_wrot0@14005000 {
|
|
compatible = "mediatek,mt6779-mdp_wrot0";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_WROT0>;
|
|
clock-names = "MDP_WROT0";
|
|
};
|
|
|
|
mdp_tdshp: mdp_tdshp@14007000 {
|
|
compatible = "mediatek,mt6779-mdp_tdshp";
|
|
reg = <0 0x14007000 0 0x1000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_MDP_TDSHP>;
|
|
clock-names = "MDP_TDSHP";
|
|
};
|
|
|
|
disp_ovl0@14008000 {
|
|
compatible = "mediatek,mt6779-disp_ovl0";
|
|
reg = <0 0x14008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_ovl0_2l@14009000 {
|
|
compatible = "mediatek,mt6779-disp_ovl0_2l";
|
|
reg = <0 0x14009000 0 0x1000>;
|
|
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_ovl1_2l@1400a000 {
|
|
compatible = "mediatek,mt6779-disp_ovl1_2l";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_rdma0@1400b000 {
|
|
compatible = "mediatek,mt6779-disp_rdma0";
|
|
reg = <0 0x1400b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_rdma1@1400c000 {
|
|
compatible = "mediatek,mt6779-disp_rdma1";
|
|
reg = <0 0x1400c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_wdma0@1400d000 {
|
|
compatible = "mediatek,mt6779-disp_wdma0";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_color0: disp_color0@1400e000 {
|
|
compatible = "mediatek,mt6779-disp_color0";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys CLK_MM_DISP_COLOR0>;
|
|
clock-names = "MDP_COLOR";
|
|
};
|
|
|
|
disp_ccorr0@1400f000 {
|
|
compatible = "mediatek,mt6779-disp_ccorr0";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_aal0@14010000 {
|
|
compatible = "mediatek,mt6779-disp_aal0";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_gamma0@14011000 {
|
|
compatible = "mediatek,mt6779-disp_gamma0";
|
|
reg = <0 0x14011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_dither0@14012000 {
|
|
compatible = "mediatek,mt6779-disp_dither0";
|
|
reg = <0 0x14012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dsi_split@14013000 {
|
|
compatible = "mediatek,mt6779-dsi_split";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
};
|
|
|
|
dsi0@14014000 {
|
|
compatible = "mediatek,mt6779-dsi0";
|
|
reg = <0 0x14014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dpi0@14015000 {
|
|
compatible = "mediatek,mt6779-dpi0";
|
|
reg = <0 0x14015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mm_mutex: mm_mutex@14016000 {
|
|
compatible = "mediatek,mt6779-mm_mutex";
|
|
reg = <0 0x14016000 0 0x1000>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
smi_common: smi_common@14019000 {
|
|
compatible = "mediatek,mt6779-smi-common",
|
|
"mediatek,smi_common", "syscon";
|
|
reg = <0 0x14019000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys MMSYS_GALS_COMM0>,
|
|
<&mmsys MMSYS_GALS_COMM1>,
|
|
<&mmsys MMSYS_SMI_COMMON>;
|
|
clock-names = "mtcmos-dis",
|
|
"gals-comm0", "gals-comm1", "mm-common";
|
|
mediatek,smi-id = <12>;
|
|
mediatek,smi-cnt = <13>;
|
|
mmsys_config = <&mmsys>;
|
|
};
|
|
|
|
smi_larb0: smi_larb0@14017000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb0", "mediatek,smi_larb";
|
|
reg = <0 0x14017000 0 0x1000>;
|
|
mediatek,larb-id = <0>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "mtcmos-dis";
|
|
mediatek,smi-id = <0>;
|
|
};
|
|
|
|
smi_larb1: smi_larb1@14018000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb1", "mediatek,smi_larb";
|
|
reg = <0 0x14018000 0 0x1000>;
|
|
mediatek,larb-id = <1>;
|
|
clocks = <&scpsys SCP_SYS_DIS>;
|
|
clock-names = "mtcmos-dis";
|
|
mediatek,smi-id = <1>;
|
|
};
|
|
|
|
disp_rsz0@1401a000 {
|
|
compatible = "mediatek,mt6779-disp_rsz0";
|
|
reg = <0 0x1401a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mdp_aal: mdp_aal0@1401b000 {
|
|
compatible = "mediatek,mt6779-mdp_aal0";
|
|
reg = <0 0x1401b000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_AAL>;
|
|
clock-names = "MDP_AAL";
|
|
};
|
|
|
|
mdp_hdr: mdp_hdr0@1401c000 {
|
|
compatible = "mediatek,mt6779-mdp_hdr0";
|
|
reg = <0 0x1401c000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_HDR>;
|
|
clock-names = "MDP_HDR";
|
|
};
|
|
|
|
mdp_wrot1: mdp_wrot1@14020000 {
|
|
compatible = "mediatek,mt6779-mdp_wrot1";
|
|
reg = <0 0x14020000 0 0x1000>;
|
|
clocks = <&mmsys CLK_MM_MDP_WROT1>;
|
|
clock-names = "MDP_WROT1";
|
|
};
|
|
|
|
disp_postmask0@14021000 {
|
|
compatible = "mediatek,mt6779-disp_postmask0";
|
|
reg = <0 0x14021000 0 0x1000>;
|
|
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
imgsys: clock-controller@15020000 {
|
|
compatible = "mediatek,mt6779-imgsys", "syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imgsys_config: imgsys_config@15020000 {
|
|
compatible = "mediatek,imgsys","syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
clocks = <&imgsys IMG_LARB5>,
|
|
<&imgsys IMG_DIP>;
|
|
clock-names = "DIP_CG_IMG_LARB5",
|
|
"DIP_CG_IMG_DIP";
|
|
};
|
|
|
|
dip: dip@15021000 {
|
|
compatible = "mediatek,dip";
|
|
reg = <0 0x15021000 0 0xc000>;
|
|
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
smi_larb5: smi_larb5@1502e000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb5", "mediatek,smi_larb";
|
|
reg = <0 0x1502e000 0 0x1000>;
|
|
mediatek,larb-id = <5>;
|
|
clocks = <&scpsys SCP_SYS_ISP>, <&imgsys IMG_LARB5>;
|
|
clock-names = "mtcmos-isp", "img-larb5";
|
|
mediatek,smi-id = <5>;
|
|
};
|
|
|
|
smi_larb6: smi_larb6@1502f000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb6", "mediatek,smi_larb";
|
|
reg = <0 0x1502f000 0 0x1000>;
|
|
mediatek,larb-id = <6>;
|
|
clocks = <&scpsys SCP_SYS_ISP>, <&imgsys IMG_LARB6>;
|
|
clock-names = "mtcmos-isp", "img-larb6";
|
|
mediatek,smi-id = <6>;
|
|
};
|
|
|
|
mfb@15010000 {
|
|
compatible = "mediatek,mfb";
|
|
reg = <0 0x15010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys IMG_MFB>;
|
|
clock-names = "MFB_CLK_IMG_MFB";
|
|
};
|
|
|
|
wpe_a@15011000 {
|
|
compatible = "mediatek,wpe_a";
|
|
reg = <0 0x15011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
clocks = <&imgsys IMG_LARB5>, <&imgsys IMG_WPE_A>;
|
|
clock-names = "WPE_CLK_IMG_LARB5", "WPE_CLK_IMG_WPE_A";
|
|
};
|
|
|
|
vcu: vcu@16000000 {
|
|
compatible = "mediatek-vcu";
|
|
mediatek,vcuid = <0>;
|
|
mediatek,vcuname = "vcu";
|
|
reg = <0 0x16000000 0 0x40000>,/* VDEC_BASE */
|
|
<0 0x17020000 0 0x10000>,/* VENC_BASE */
|
|
<0 0x19002000 0 0x1000>;/* VENC_LT */
|
|
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>;
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
mediatek,dec_gce_th_num = <1>;
|
|
mediatek,enc_gce_th_num = <1>;
|
|
mboxes = <&gce_mbox 16 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 17 0 CMDQ_THR_PRIO_1>;
|
|
|
|
gce-event-names = "vdec_pic_start",
|
|
"vdec_decode_done",
|
|
"vdec_pause",
|
|
"vdec_dec_error",
|
|
"vdec_mc_busy_overflow_timeout",
|
|
"vdec_all_dram_req_done",
|
|
"vdec_ini_fetch_rdy",
|
|
"vdec_process_flag",
|
|
"vdec_search_start_code_done",
|
|
"vdec_ref_reorder_done",
|
|
"vdec_wp_tble_done",
|
|
"vdec_count_sram_clr_done",
|
|
"venc_eof",
|
|
"venc_cmdq_pause_done",
|
|
"venc_mb_done",
|
|
"venc_128B_cnt_done";
|
|
|
|
gce-events = <&gce_mbox CMDQ_EVENT_VDEC_EVENT_0>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_1>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_2>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_3>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_4>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_5>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_6>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_7>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_8>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_9>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_10>,
|
|
<&gce_mbox CMDQ_EVENT_VDEC_EVENT_11>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_EOF>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_MB_DONE>,
|
|
<&gce_mbox CMDQ_EVENT_VENC_128BYTE_CNT_DONE>;
|
|
};
|
|
|
|
vcodec_dec: vcodec_dec@16000000 {
|
|
compatible = "mediatek,mt6779-vcodec-dec";
|
|
reg = <0 0x16000000 0 0x1000>,/* VDEC_SYS */
|
|
<0 0x16020000 0 0x400>,/* VDEC_VLD */
|
|
<0 0x16025000 0 0x1000>;/* VDEC_MISC */
|
|
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,vcu = <&vcu>;
|
|
iommus = <&iommu0 M4U_PORT_HW_VDEC_MC_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_PP_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_VLD_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_AVC_MV_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_PRED_RD_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_PRED_WR_EXT>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_PPWRAP_EXT>;
|
|
mediatek,larb = <&smi_larb2>;
|
|
clocks =
|
|
<&vdecsys CLK_VDEC_VDEC>;
|
|
clock-names =
|
|
"MT_CG_VDEC";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vdecsys: clock-controller@16000000 {
|
|
compatible = "mediatek,mt6779-vdecsys", "syscon";
|
|
reg = <0 0x16000000 0 0x1000>, /* VDEC_SYS */
|
|
<0 0x16025000 0 0x1000>; /* VDEC_MISC */
|
|
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_LOW>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smi_larb2: smi_larb2@16010000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb2", "mediatek,smi_larb";
|
|
reg = <0 0x16010000 0 0x1000>;
|
|
mediatek,larb-id = <2>;
|
|
clocks = <&scpsys SCP_SYS_VDE>, <&vdecsys VDEC_VDEC>;
|
|
clock-names = "mtcmos-vde", "vdec-vdec";
|
|
mediatek,smi-id = <2>;
|
|
};
|
|
|
|
vencsys: clock-controller@17000000 {
|
|
compatible = "mediatek,mt6779-vencsys", "syscon";
|
|
reg = <0 0x17000000 0 0x1000>,
|
|
<0 0x17020000 0 0x1000>;
|
|
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_LOW>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
vcodec_enc: vcodec_enc@17000000 {
|
|
compatible = "mediatek,mt6779-vcodec-enc", "syscon";
|
|
reg = <0 0x17000000 0 0x1000>,
|
|
<0 0x17020000 0 0x1000>;
|
|
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,vcu = <&vcu>;
|
|
iommus = <&iommu0 M4U_PORT_VENC_RCPU>,
|
|
<&iommu0 M4U_PORT_VENC_REC>,
|
|
<&iommu0 M4U_PORT_VENC_BSDMA>,
|
|
<&iommu0 M4U_PORT_VENC_SV_COMV>,
|
|
<&iommu0 M4U_PORT_VENC_RD_COMV>,
|
|
<&iommu0 M4U_PORT_VENC_NBM_RDMA>,
|
|
<&iommu0 M4U_PORT_VENC_NBM_RDMA_LITE>,
|
|
<&iommu0 M4U_PORT_VENC_NBM_WDMA>,
|
|
<&iommu0 M4U_PORT_VENC_NBM_WDMA_LITE>,
|
|
<&iommu0 M4U_PORT_VENC_CUR_LUMA>,
|
|
<&iommu0 M4U_PORT_VENC_CUR_CHROMA>,
|
|
<&iommu0 M4U_PORT_VENC_REF_LUMA>,
|
|
<&iommu0 M4U_PORT_VENC_REF_CHROMA>;
|
|
mediatek,larb = <&smi_larb3>;
|
|
clocks =
|
|
<&vencsys CLK_VENC_GCON_VENC>;
|
|
clock-names =
|
|
"MT_CG_VENC";
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smi_larb3: smi_larb3@17010000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb3", "mediatek,smi_larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
mediatek,larb-id = <3>;
|
|
clocks = <&scpsys SCP_SYS_VEN>,
|
|
<&vencsys CLK_VENC_GCON_LARB>;
|
|
clock-names = "mtcmos-ven", "venc-larb";
|
|
cell-index = <3>;
|
|
mediatek,smi-id = <3>;
|
|
};
|
|
|
|
smi_larb4: smi_larb4@17011000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb4", "mediatek,smi_larb";
|
|
reg = <0 0x17011000 0 0x1000>;
|
|
mediatek,larb-id = <4>;
|
|
clocks = <&scpsys SCP_SYS_VEN>;
|
|
clock-names = "mtcmos-ven";
|
|
mediatek,smi-id = <4>;
|
|
};
|
|
|
|
venc_jpg@17030000 {
|
|
compatible = "mediatek,venc_jpg";
|
|
reg = <0 0x17030000 0 0x10000>;
|
|
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&vencsys CLK_VENC_GCON_JPGENC>;
|
|
clock-names = "MT_CG_VENC_JPGENC";
|
|
};
|
|
|
|
wifi: wifi@18000000 {
|
|
compatible = "mediatek,wifi";
|
|
reg = <0 0x18000000 0 0x100000>;
|
|
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_LOW>;
|
|
memory-region = <&wifi_mem>;
|
|
};
|
|
|
|
consys: consys@18002000 {
|
|
compatible = "mediatek,mt6779-consys";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
/*CONN_MCU_CONFIG_BASE */
|
|
reg = <0 0x18002000 0 0x3000>,
|
|
/*TOP_RGU_BASE */
|
|
<0 0x10007000 0 0x0100>,
|
|
/*INFRACFG_AO_BASE */
|
|
<0 0x10001000 0 0x1000>,
|
|
/*SPM_BASE */
|
|
<0 0x10006000 0 0x1000>,
|
|
/*CONN_HIF_ON_BASE */
|
|
<0 0x18007000 0 0x1000>,
|
|
/*CONN_TOP_MISC_OFF_BASE */
|
|
<0 0x180b1000 0 0x1000>,
|
|
/*CONN_MCU_CFG_ON_BASE */
|
|
<0 0x180a3000 0 0x1000>,
|
|
/*CONN_MCU_CIRQ_BASE */
|
|
<0 0x180a5000 0 0x800>,
|
|
/*CONN_TOP_MISC_ON_BASE */
|
|
<0 0x180c1000 0 0x1000>,
|
|
/*CONN_HIF_PDMA_BASE, dummy */
|
|
<0 0x00000000 0 0x0>,
|
|
/* INFRASYS_COMMON AP2MD_PCCIF4_BASE */
|
|
<0 0x1024C000 0 0x40>,
|
|
/*INFRA_AO_PERICFG_BASE */
|
|
<0 0x10003000 0 0x1000>;
|
|
/*BGF_EINT conn2ap_btif_wakeup_out_b*/
|
|
interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_LOW>,
|
|
/*WDT_EINT conn_wdt_irq_b*/
|
|
<GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>,
|
|
/*conn2ap_sw_irq_b*/
|
|
<GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&scpsys SCP_SYS_CONN>,
|
|
<&infracfg_ao INFRACFG_AO_CCIF4_AP_CG>;
|
|
clock-names = "conn", "ccif";
|
|
pmic = <&main_pmic>;
|
|
memory-region = <&consys_mem>;
|
|
};
|
|
|
|
camsys1: camsys@1a000000 {
|
|
compatible = "mediatek,camsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x10000>;
|
|
#clock-cells = <1>;
|
|
#if 1
|
|
/* Camera CCF */
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_CAM>,
|
|
<&camsys CAMSYS_CAM_CGPDN>,
|
|
<&camsys CAMSYS_CAMTG_CGPDN>,
|
|
<&camsys CAMSYS_CAMSV0_CGPDN>,
|
|
<&camsys CAMSYS_CAMSV1_CGPDN>,
|
|
<&camsys CAMSYS_CAMSV2_CGPDN>,
|
|
<&camsys CAMSYS_CAMSV3_CGPDN>;
|
|
clock-names = "ISP_SCP_SYS_DIS",
|
|
"ISP_SCP_SYS_CAM",
|
|
"CAMSYS_CAM_CGPDN",
|
|
"CAMSYS_CAMTG_CGPDN",
|
|
"CAMSYS_CAMSV0_CGPDN",
|
|
"CAMSYS_CAMSV1_CGPDN",
|
|
"CAMSYS_CAMSV2_CGPDN",
|
|
"CAMSYS_CAMSV3_CGPDN";
|
|
#endif
|
|
};
|
|
|
|
cam1@1a010000 {
|
|
compatible = "mediatek,cam1";
|
|
reg = <0 0x1a010000 0 0x8000>;
|
|
interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam2@1a020000 {
|
|
compatible = "mediatek,cam2";
|
|
reg = <0 0x1a020000 0 0x8000>;
|
|
interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam3@1a030000 {
|
|
compatible = "mediatek,cam3";
|
|
reg = <0 0x1a030000 0 0x8000>;
|
|
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam1_inner@1a018000 {
|
|
compatible = "mediatek,cam1_inner";
|
|
reg = <0 0x1a018000 0 0x8000>;
|
|
};
|
|
|
|
cam2_inner@1a028000 {
|
|
compatible = "mediatek,cam2_inner";
|
|
reg = <0 0x1a028000 0 0x8000>;
|
|
};
|
|
|
|
cam3_inner@1a038000 {
|
|
compatible = "mediatek,cam3_inner";
|
|
reg = <0 0x1a038000 0 0x8000>;
|
|
};
|
|
|
|
camsv1@1a051000 {
|
|
compatible = "mediatek,camsv1";
|
|
reg = <0 0x1a051000 0 0x1000>;
|
|
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv2@1a052000 {
|
|
compatible = "mediatek,camsv2";
|
|
reg = <0 0x1a052000 0 0x1000>;
|
|
interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv3@1a053000 {
|
|
compatible = "mediatek,camsv3";
|
|
reg = <0 0x1a053000 0 0x1000>;
|
|
interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv4@1a054000 {
|
|
compatible = "mediatek,camsv4";
|
|
reg = <0 0x1a054000 0 0x1000>;
|
|
interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv5@1a055000 {
|
|
compatible = "mediatek,camsv5";
|
|
reg = <0 0x1a055000 0 0x1000>;
|
|
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv6@1a056000 {
|
|
compatible = "mediatek,camsv6";
|
|
reg = <0 0x1a056000 0 0x1000>;
|
|
interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv7@1a057000 {
|
|
compatible = "mediatek,camsv7";
|
|
reg = <0 0x1a057000 0 0x1000>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv8@1a058000 {
|
|
compatible = "mediatek,camsv8";
|
|
reg = <0 0x1a058000 0 0x1000>;
|
|
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
apu_conn: clock-controller@19000000 {
|
|
compatible = "mediatek,mt6779-apu_conn", "syscon";
|
|
reg = <0 0x19000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apu_vcore: clock-controller@19020000 {
|
|
compatible = "mediatek,mt6779-apu_vcore", "syscon";
|
|
reg = <0 0x19020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apu0: clock-controller@19180000 {
|
|
compatible = "mediatek,mt6779-apu0", "syscon";
|
|
reg = <0 0x19180000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apu1: clock-controller@19280000 {
|
|
compatible = "mediatek,mt6779-apu1", "syscon";
|
|
reg = <0 0x19280000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apu_mdla: clock-controller@19380000 {
|
|
compatible = "mediatek,mt6779-apu_mdla", "syscon";
|
|
reg = <0 0x19380000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mtk_mdla: mdla@19390000 {
|
|
compatible = "mtk,mdla";
|
|
reg = <0 0x19380000 0 0x1000>, /* mdla config */
|
|
<0 0x19390000 0 0x1000>, /* mdla command */
|
|
<0 0x19391000 0 0x1000>, /* mdla bui */
|
|
<0 0x1d000000 0 0x100000>, /* GSM */
|
|
<0 0x19000000 0 0x40000>, /* APU CONN */
|
|
<0 0x10001000 0 0x1000>; /* Infracfg_ao */
|
|
interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
nvmem-cells = <&apu_segment>;
|
|
nvmem-cell-names = "efuse_segment";
|
|
|
|
clocks = <&topckgen TOP_MUX_DSP>,
|
|
<&topckgen TOP_MUX_DSP1>,
|
|
<&topckgen TOP_MUX_DSP2>,
|
|
<&topckgen TOP_MUX_DSP3>,
|
|
<&topckgen TOP_MUX_IPU_IF>,
|
|
<&apu0 APU0_JTAG_CG>,
|
|
<&apu0 APU0_AXI_M_CG>,
|
|
<&apu0 APU0_APU_CG>,
|
|
<&apu1 APU1_JTAG_CG>,
|
|
<&apu1 APU1_AXI_M_CG>,
|
|
<&apu1 APU1_APU_CG>,
|
|
<&apu_mdla APU_MDLA_APB_CG>,
|
|
<&apu_mdla APU_MDLA_CG_B0>,
|
|
<&apu_mdla APU_MDLA_CG_B1>,
|
|
<&apu_mdla APU_MDLA_CG_B2>,
|
|
<&apu_mdla APU_MDLA_CG_B3>,
|
|
<&apu_mdla APU_MDLA_CG_B4>,
|
|
<&apu_mdla APU_MDLA_CG_B5>,
|
|
<&apu_mdla APU_MDLA_CG_B6>,
|
|
<&apu_mdla APU_MDLA_CG_B7>,
|
|
<&apu_mdla APU_MDLA_CG_B8>,
|
|
<&apu_mdla APU_MDLA_CG_B9>,
|
|
<&apu_mdla APU_MDLA_CG_B10>,
|
|
<&apu_mdla APU_MDLA_CG_B11>,
|
|
<&apu_mdla APU_MDLA_CG_B12>,
|
|
<&apu_conn APU_CONN_APU_CG>,
|
|
<&apu_conn APU_CONN_AHB_CG>,
|
|
<&apu_conn APU_CONN_AXI_CG>,
|
|
<&apu_conn APU_CONN_ISP_CG>,
|
|
<&apu_conn APU_CONN_CAM_ADL_CG>,
|
|
<&apu_conn APU_CONN_IMG_ADL_CG>,
|
|
<&apu_conn APU_CONN_EMI_26M_CG>,
|
|
<&apu_conn APU_CONN_VPU_UDI_CG>,
|
|
<&apu_vcore APU_VCORE_AHB_CG>,
|
|
<&apu_vcore APU_VCORE_AXI_CG>,
|
|
<&apu_vcore APU_VCORE_ADL_CG>,
|
|
<&apu_vcore APU_VCORE_QOS_CG>,
|
|
<&clk26m>,
|
|
<&topckgen TOP_UNIVPLL_D3_D8>,
|
|
<&topckgen TOP_UNIVPLL_D3_D4>,
|
|
<&topckgen TOP_MAINPLL_D2_D4>,
|
|
<&topckgen TOP_UNIVPLL_D3_D2>,
|
|
<&topckgen TOP_MAINPLL_D2_D2>,
|
|
<&topckgen TOP_UNIVPLL_D2_D2>,
|
|
<&topckgen TOP_MAINPLL_D3>,
|
|
<&topckgen TOP_UNIVPLL_D3>,
|
|
<&topckgen TOP_MMPLL_D7>,
|
|
<&topckgen TOP_MMPLL_D6>,
|
|
<&topckgen TOP_ADSPPLL_D5>,
|
|
<&topckgen TOP_TVDPLL_CK>,
|
|
<&topckgen TOP_TVDPLL_MAINPLL_D2_CK>,
|
|
<&topckgen TOP_UNIVPLL_D2>,
|
|
<&topckgen TOP_ADSPPLL_D4>,
|
|
<&topckgen TOP_MAINPLL_D2>,
|
|
<&topckgen TOP_MMPLL_D4>,
|
|
<&mmsys MMSYS_GALS_IPU2MM>,
|
|
<&mmsys MMSYS_GALS_IPU12MM>,
|
|
<&mmsys MMSYS_GALS_COMM1>,
|
|
<&mmsys MMSYS_GALS_COMM0>,
|
|
<&mmsys MMSYS_SMI_COMMON>,
|
|
<&mmsys MMSYS_IPU_DL_TXCK>,
|
|
<&mmsys MMSYS_IPU_DL_RX_CK>,
|
|
<&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_VPU_VCORE_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_VCORE_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CONN_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CONN_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE0_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE0_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE1_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE1_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE2_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE2_SHUTDOWN>;
|
|
|
|
clock-names = "clk_top_dsp_sel",
|
|
"clk_top_dsp1_sel",
|
|
"clk_top_dsp2_sel",
|
|
"clk_top_dsp3_sel",
|
|
"clk_top_ipu_if_sel",
|
|
"clk_apu_core0_jtag_cg",
|
|
"clk_apu_core0_axi_m_cg",
|
|
"clk_apu_core0_apu_cg",
|
|
"clk_apu_core1_jtag_cg",
|
|
"clk_apu_core1_axi_m_cg",
|
|
"clk_apu_core1_apu_cg",
|
|
"clk_apu_mdla_apb_cg",
|
|
"clk_apu_mdla_cg_b0",
|
|
"clk_apu_mdla_cg_b1",
|
|
"clk_apu_mdla_cg_b2",
|
|
"clk_apu_mdla_cg_b3",
|
|
"clk_apu_mdla_cg_b4",
|
|
"clk_apu_mdla_cg_b5",
|
|
"clk_apu_mdla_cg_b6",
|
|
"clk_apu_mdla_cg_b7",
|
|
"clk_apu_mdla_cg_b8",
|
|
"clk_apu_mdla_cg_b9",
|
|
"clk_apu_mdla_cg_b10",
|
|
"clk_apu_mdla_cg_b11",
|
|
"clk_apu_mdla_cg_b12",
|
|
"clk_apu_conn_apu_cg",
|
|
"clk_apu_conn_ahb_cg",
|
|
"clk_apu_conn_axi_cg",
|
|
"clk_apu_conn_isp_cg",
|
|
"clk_apu_conn_cam_adl_cg",
|
|
"clk_apu_conn_img_adl_cg",
|
|
"clk_apu_conn_emi_26m_cg",
|
|
"clk_apu_conn_vpu_udi_cg",
|
|
"clk_apu_vcore_ahb_cg",
|
|
"clk_apu_vcore_axi_cg",
|
|
"clk_apu_vcore_adl_cg",
|
|
"clk_apu_vcore_qos_cg",
|
|
"clk_top_clk26m",
|
|
"clk_top_univpll_d3_d8",
|
|
"clk_top_univpll_d3_d4",
|
|
"clk_top_mainpll_d2_d4",
|
|
"clk_top_univpll_d3_d2",
|
|
"clk_top_mainpll_d2_d2",
|
|
"clk_top_univpll_d2_d2",
|
|
"clk_top_mainpll_d3",
|
|
"clk_top_univpll_d3",
|
|
"clk_top_mmpll_d7",
|
|
"clk_top_mmpll_d6",
|
|
"clk_top_adsppll_d5",
|
|
"clk_top_tvdpll_ck",
|
|
"clk_top_tvdpll_mainpll_d2_ck",
|
|
"clk_top_univpll_d2",
|
|
"clk_top_adsppll_d4",
|
|
"clk_top_mainpll_d2",
|
|
"clk_top_mmpll_d4",
|
|
"clk_mmsys_gals_ipu2mm",
|
|
"clk_mmsys_gals_ipu12mm",
|
|
"clk_mmsys_gals_comm1",
|
|
"clk_mmsys_gals_comm0",
|
|
"clk_mmsys_smi_common",
|
|
"clk_mmsys_ipu_dl_txck",
|
|
"clk_mmsys_ipu_dl_rx_ck",
|
|
"mtcmos_dis",
|
|
"mtcmos_vpu_vcore_dormant",
|
|
"mtcmos_vpu_vcore_shutdown",
|
|
"mtcmos_vpu_conn_dormant",
|
|
"mtcmos_vpu_conn_shutdown",
|
|
"mtcmos_vpu_core0_dormant",
|
|
"mtcmos_vpu_core0_shutdown",
|
|
"mtcmos_vpu_core1_dormant",
|
|
"mtcmos_vpu_core1_shutdown",
|
|
"mtcmos_vpu_core2_dormant",
|
|
"mtcmos_vpu_core2_shutdown";
|
|
};
|
|
|
|
ccu@1a081000 {
|
|
compatible = "mediatek,ccu";
|
|
reg = <0 0x1a081000 0 0x1000>;
|
|
interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
clocks = <&camsys CAMSYS_CCU_CGPDN>,
|
|
<&mmsys MMSYS_GALS_CCU2MM>,
|
|
<&topckgen TOP_MUX_CCU>,
|
|
<&scpsys SCP_SYS_CAM>;
|
|
clock-names = "CCU_CLK_CAM_CCU",
|
|
"CCU_CLK_MMSYS_CCU",
|
|
"CCU_CLK_TOP_MUX",
|
|
"CAM_PWR";
|
|
};
|
|
|
|
camsys: clock-controller@1a000000 {
|
|
compatible = "mediatek,mt6779-camsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x10000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smi_larb9: smi_larb9@1a001000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb9", "mediatek,smi_larb";
|
|
reg = <0 0x1a001000 0 0x1000>;
|
|
mediatek,larb-id = <9>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CAMSYS_LARB9_CGPDN>;
|
|
clock-names = "mtcmos-cam", "cam-larb9";
|
|
mediatek,smi-id = <9>;
|
|
};
|
|
|
|
smi_larb10: smi_larb10@1a002000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb10", "mediatek,smi_larb";
|
|
reg = <0 0x1a002000 0 0x1000>;
|
|
mediatek,larb-id = <10>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CAMSYS_LARB10_CGPDN>;
|
|
clock-names = "mtcmos-cam", "cam-larb10";
|
|
mediatek,smi-id = <10>;
|
|
};
|
|
|
|
smi_larb11: smi_larb11@1a003000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb11", "mediatek,smi_larb";
|
|
reg = <0 0x1a003000 0 0x1000>;
|
|
mediatek,smi = <&smi_common>;
|
|
mediatek,larb-id = <11>;
|
|
clocks = <&scpsys SCP_SYS_CAM>,
|
|
<&camsys CAMSYS_LARB11_CGPDN>;
|
|
clock-names = "mtcmos-cam", "cam-larb11";
|
|
mediatek,smi-id = <11>;
|
|
};
|
|
|
|
kd_camera_hw1:kd_camera_hw1@1a004000 {
|
|
compatible = "mediatek,imgsensor";
|
|
};
|
|
|
|
camera_af_hw_node: camera_af_hw_node {
|
|
compatible = "mediatek,camera_af_lens";
|
|
};
|
|
|
|
flashlight_core: flashlight_core {
|
|
compatible = "mediatek,flashlight_core";
|
|
};
|
|
|
|
flashlights_mt6360: flashlights_mt6360 {
|
|
compatible = "mediatek,flashlights_mt6360";
|
|
decouple = <1>;
|
|
channel@1 {
|
|
type = <0>;
|
|
ct = <0>;
|
|
part = <0>;
|
|
};
|
|
channel@2 {
|
|
type = <0>;
|
|
ct = <1>;
|
|
part = <0>;
|
|
};
|
|
};
|
|
|
|
seninf_top@1a004000 {
|
|
compatible = "mediatek,seninf_top";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_CAM>,
|
|
<&camsys CLK_CAM_SENINF>,
|
|
<&topckgen CLK_TOP_SENINF>,
|
|
<&topckgen CLK_TOP_SENINF1>,
|
|
<&topckgen CLK_TOP_SENINF2>,
|
|
<&topckgen CLK_TOP_CAMTG>,
|
|
<&topckgen CLK_TOP_CAMTG2>,
|
|
<&topckgen CLK_TOP_CAMTG3>,
|
|
<&topckgen CLK_TOP_CAMTG4>,
|
|
<&topckgen CLK_TOP_CAMTG5>,
|
|
<&clk26m>,
|
|
<&topckgen CLK_TOP_UNIVP_192M_D8>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3_D8>,
|
|
<&topckgen CLK_TOP_UNIVP_192M_D4>,
|
|
<&topckgen CLK_TOP_F26M_CK_D2>,
|
|
<&topckgen CLK_TOP_UNIVP_192M_D16>,
|
|
<&topckgen CLK_TOP_UNIVP_192M_D32>;
|
|
clock-names = "SCP_SYS_DIS",
|
|
"SCP_SYS_CAM",
|
|
"CAMSYS_SENINF_CGPDN",
|
|
"TOP_MUX_SENINF",
|
|
"TOP_MUX_SENINF1",
|
|
"TOP_MUX_SENINF2",
|
|
"TOP_MUX_CAMTG",
|
|
"TOP_MUX_CAMTG2",
|
|
"TOP_MUX_CAMTG3",
|
|
"TOP_MUX_CAMTG4",
|
|
"TOP_MUX_CAMTG5",
|
|
"TOP_CLK26M",
|
|
"TOP_UNIVP_192M_D8",
|
|
"TOP_UNIVPLL_D3_D8",
|
|
"TOP_UNIVP_192M_D4",
|
|
"TOP_F26M_CK_D2",
|
|
"TOP_UNIVP_192M_D16",
|
|
"TOP_UNIVP_192M_D32";
|
|
};
|
|
|
|
seninf1@1a004000 {
|
|
compatible = "mediatek,seninf1";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
};
|
|
|
|
seninf2@1a005000 {
|
|
compatible = "mediatek,seninf2";
|
|
reg = <0 0x1a005000 0 0x1000>;
|
|
};
|
|
|
|
seninf3@1a006000 {
|
|
compatible = "mediatek,seninf3";
|
|
reg = <0 0x1a006000 0 0x1000>;
|
|
};
|
|
|
|
seninf4@1a007000 {
|
|
compatible = "mediatek,seninf4";
|
|
reg = <0 0x1a007000 0 0x1000>;
|
|
};
|
|
|
|
seninf5@1a008000 {
|
|
compatible = "mediatek,seninf5";
|
|
reg = <0 0x1a008000 0 0x1000>;
|
|
};
|
|
|
|
ipesys: clock-controller@1b000000 {
|
|
compatible = "mediatek,mt6779-ipesys", "syscon";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
ipesyscq@1b000000 {
|
|
compatible = "mediatek,ipesyscq";
|
|
reg = <0 0x1b000000 0 0x1000>;
|
|
};
|
|
|
|
fdvt@1b001000 {
|
|
compatible = "mediatek,fdvt";
|
|
reg = <0 0x1b001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&ipesys IPE_FD>;
|
|
clock-names = "FD_CLK_IPE_FD";
|
|
};
|
|
|
|
rsc@1b003000 {
|
|
compatible = "mediatek,rsc";
|
|
reg = <0 0x1b003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&ipesys CLK_IPE_RSC>;
|
|
clock-names = "RSC_CLK_IPE_RSC";
|
|
};
|
|
|
|
smi_larb8: smi_larb8@1b00f000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb8", "mediatek,smi_larb";
|
|
reg = <0 0x1b00f000 0 0x1000>;
|
|
mediatek,larb-id = <8>;
|
|
clocks = <&scpsys SCP_SYS_IPE>,
|
|
<&ipesys IPE_LARB8>;
|
|
clock-names = "mtcmos-ipe", "ipe-larb8";
|
|
mediatek,smi-id = <8>;
|
|
};
|
|
|
|
dvs@1b100000 {
|
|
compatible = "mediatek,dvs";
|
|
reg = <0 0x1b100000 0 0x1000>;
|
|
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen TOP_MUX_DPE>,
|
|
<&ipesys IPE_DPE>;
|
|
clock-names = "DPE_TOP_MUX",
|
|
"DPE_CLK_IPE_DPE";
|
|
};
|
|
|
|
dvp@1b100800 {
|
|
compatible = "mediatek,dvp";
|
|
reg = <0 0x1b100000 0 0x1000>;
|
|
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen TOP_MUX_DPE>,
|
|
<&ipesys IPE_DPE>;
|
|
clock-names = "DPE_TOP_MUX",
|
|
"DPE_CLK_IPE_DPE";
|
|
};
|
|
|
|
smi_larb7: smi_larb7@1b10f000 {
|
|
compatible = "mediatek,mt6779-smi-larb",
|
|
"mediatek,smi_larb7", "mediatek,smi_larb";
|
|
reg = <0 0x1b10f000 0 0x1000>;
|
|
mediatek,larb-id = <7>;
|
|
clocks = <&scpsys SCP_SYS_IPE>, <&topckgen TOP_MUX_DPE>,
|
|
<&ipesys IPE_LARB7>;
|
|
clock-names = "mtcmos-ipe", "top-dpe", "ipe-larb7";
|
|
mediatek,smi-id = <7>;
|
|
};
|
|
|
|
hwrng: hwrng {
|
|
compatible = "mediatek,mt67xx-rng";
|
|
};
|
|
|
|
mobicore {
|
|
compatible = "trustonic,mobicore";
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
tee_sanity {
|
|
compatible = "mediatek,tee_sanity";
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
ssusb: usb0@11201000 {
|
|
compatible = "mediatek,mtu3";
|
|
reg = <0 0x11201000 0 0x2e00>,
|
|
<0 0x11203e00 0 0x0100>;
|
|
reg-names = "mac", "ippc";
|
|
vusb33-supply = <&mt_pmic_vusb_ldo_reg>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
|
phy-cells = <1>;
|
|
phys = <&u2port0 PHY_TYPE_USB2>,
|
|
<&u3port0 PHY_TYPE_USB3>;
|
|
clocks = <&infracfg_ao CLK_INFRA_USB>,
|
|
<&infracfg_ao CLK_INFRA_SSUSB_XHCI>;
|
|
clock-names = "sys_ck","ref_ck";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
dr_mode = "otg";
|
|
maximum-speed = "high-speed";
|
|
mediatek,force-vbus;
|
|
mediatek,clk-mgr;
|
|
mediatek,spm-mgr;
|
|
mediatek,usb3-drd;
|
|
mediatek,noise-still-tr;
|
|
usb-role-switch;
|
|
mediatek,syscon-wakeup = <&pericfg 0x420 101>;
|
|
wakeup-source;
|
|
status = "okay";
|
|
|
|
usb_host: xhci0@11200000 {
|
|
compatible = "mediatek,mtk-xhci";
|
|
reg = <0 0x11200000 0 0x1000>;
|
|
reg-names = "mac";
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "sys_ck";
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
efuse: efuse@11c10000 {
|
|
compatible = "mediatek,devinfo";
|
|
reg = <0 0x11c10000 0 0x10000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
efuse_segment: segment@78 {
|
|
reg = <0x78 0x4>;
|
|
};
|
|
|
|
apu_efuse_data: apu_efuse1 {
|
|
reg = <0x0c 0x4>;
|
|
};
|
|
|
|
apu_segment: apu_efuse2 {
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
apu_ptpod: apu_efuse3 {
|
|
reg = <0xfc 0x4>;
|
|
};
|
|
};
|
|
|
|
u3phy: usb-phy0@11e40000 {
|
|
compatible = "mediatek,generic-tphy-v2";
|
|
clocks = <&clk26m>;
|
|
clock-names = "u3phya_ref";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "okay";
|
|
|
|
u2port0: usb2-phy0@11e40000 {
|
|
reg = <0 0x11e40000 0 0x700>;
|
|
#phy-cells = <1>;
|
|
mediatek,eye-vrt = <4>; /* 0~7 */
|
|
mediatek,eye-term = <4>; /* 0~7 */
|
|
mediatek,eye-rev6 = <0>; /* 0~3 */
|
|
mediatek,eye-disc = <4>; /* 0~8 */
|
|
mediatek,host-eye-vrt = <4>; /* 0~7 */
|
|
mediatek,host-eye-term = <4>; /* 0~7 */
|
|
mediatek,host-eye-rev6 = <0>; /* 0~3 */
|
|
mediatek,host-eye-disc = <4>; /* 0~8 */
|
|
status = "okay";
|
|
};
|
|
|
|
u3port0: usb3-phy0@11e40700 {
|
|
reg = <0 0x11e40700 0 0x900>;
|
|
#phy-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
|
|
boot_dramboost {
|
|
compatible = "mediatek,dvfsrc-qosboost";
|
|
required-opps = <&dvfsrc_freq_opp0>;
|
|
};
|
|
|
|
audclk: audclk@11210000 {
|
|
compatible = "mediatek,mt6779-audio", "syscon";
|
|
reg = <0 0x11210000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
afe: mt6779-afe-pcm@11210000 {
|
|
compatible = "mediatek,mt6779-sound";
|
|
reg = <0 0x11210000 0 0x1000>;
|
|
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
|
|
topckgen = <&topckgen>;
|
|
clocks = <&audclk CLK_AUD_AFE>,
|
|
<&audclk CLK_AUD_DAC>,
|
|
<&audclk CLK_AUD_DAC_PREDIS>,
|
|
<&audclk CLK_AUD_ADC>,
|
|
<&audclk CLK_AUD_PDN_ADDA6_ADC>,
|
|
<&audclk CLK_AUD_22M>,
|
|
<&audclk CLK_AUD_24M>,
|
|
<&audclk CLK_AUD_APLL_TUNER>,
|
|
<&audclk CLK_AUD_APLL2_TUNER>,
|
|
<&audclk CLK_AUD_TDM>,
|
|
<&audclk CLK_AUD_TML>,
|
|
<&audclk CLK_AUD_NLE>,
|
|
<&audclk CLK_AUD_DAC_HIRES>,
|
|
<&audclk CLK_AUD_ADC_HIRES>,
|
|
<&audclk CLK_AUD_ADC_HIRES_TML>,
|
|
<&audclk CLK_AUD_ADDA6_ADC_HIRES>,
|
|
<&audclk CLK_AUD_3RD_DAC>,
|
|
<&audclk CLK_AUD_3RD_DAC_PREDIS>,
|
|
<&audclk CLK_AUD_3RD_DAC_TML>,
|
|
<&audclk CLK_AUD_3RD_DAC_HIRES>,
|
|
<&scpsys SCP_SYS_AUDIO>,
|
|
<&infracfg_ao CLK_INFRA_AUD>,
|
|
<&infracfg_ao CLK_INFRA_AUD_26M_BCLK_CK>,
|
|
<&topckgen CLK_TOP_AUD>,
|
|
<&topckgen CLK_TOP_AUD_INTBUS>,
|
|
<&topckgen CLK_TOP_MAINPLL_D2_D4>,
|
|
<&topckgen CLK_TOP_AUD_1>,
|
|
<&topckgen CLK_TOP_APLL1_CK>,
|
|
<&topckgen CLK_TOP_AUD_2>,
|
|
<&topckgen CLK_TOP_APLL2_CK>,
|
|
<&topckgen CLK_TOP_AUD_ENG1>,
|
|
<&topckgen CLK_TOP_APLL1_D8>,
|
|
<&topckgen CLK_TOP_AUD_ENG2>,
|
|
<&topckgen CLK_TOP_APLL2_D8>,
|
|
<&topckgen CLK_TOP_I2S0_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S1_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S2_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S3_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S4_M_SEL>,
|
|
<&topckgen CLK_TOP_I2S5_M_SEL>,
|
|
<&topckgen CLK_TOP_APLL12_DIV0>,
|
|
<&topckgen CLK_TOP_APLL12_DIV1>,
|
|
<&topckgen CLK_TOP_APLL12_DIV2>,
|
|
<&topckgen CLK_TOP_APLL12_DIV3>,
|
|
<&topckgen CLK_TOP_APLL12_DIV4>,
|
|
<&topckgen CLK_TOP_APLL12_DIVB>,
|
|
<&topckgen CLK_TOP_APLL12_DIV5>,
|
|
<&topckgen CLK_TOP_AUD_H>,
|
|
<&clk26m>;
|
|
clock-names = "aud_afe_clk",
|
|
"aud_dac_clk",
|
|
"aud_dac_predis_clk",
|
|
"aud_adc_clk",
|
|
"aud_adda6_adc_clk",
|
|
"aud_apll22m_clk",
|
|
"aud_apll24m_clk",
|
|
"aud_apll1_tuner_clk",
|
|
"aud_apll2_tuner_clk",
|
|
"aud_tdm_clk",
|
|
"aud_tml_clk",
|
|
"aud_nle",
|
|
"aud_dac_hires_clk",
|
|
"aud_adc_hires_clk",
|
|
"aud_adc_hires_tml",
|
|
"aud_adda6_adc_hires_clk",
|
|
"aud_3rd_dac_clk",
|
|
"aud_3rd_dac_predis_clk",
|
|
"aud_3rd_dac_tml",
|
|
"aud_3rd_dac_hires_clk",
|
|
"scp_sys_audio",
|
|
"aud_infra_clk",
|
|
"mtkaif_26m_clk",
|
|
"top_mux_audio",
|
|
"top_mux_audio_int",
|
|
"top_mainpll_d2_d4",
|
|
"top_mux_aud_1",
|
|
"top_apll1_ck",
|
|
"top_mux_aud_2",
|
|
"top_apll2_ck",
|
|
"top_mux_aud_eng1",
|
|
"top_apll1_d8",
|
|
"top_mux_aud_eng2",
|
|
"top_apll2_d8",
|
|
"top_i2s0_m_sel",
|
|
"top_i2s1_m_sel",
|
|
"top_i2s2_m_sel",
|
|
"top_i2s3_m_sel",
|
|
"top_i2s4_m_sel",
|
|
"top_i2s5_m_sel",
|
|
"top_apll12_div0",
|
|
"top_apll12_div1",
|
|
"top_apll12_div2",
|
|
"top_apll12_div3",
|
|
"top_apll12_div4",
|
|
"top_apll12_divb",
|
|
"top_apll12_div5",
|
|
"top_mux_audio_h",
|
|
"top_clk26m_clk";
|
|
};
|
|
|
|
mt6660: mt6660@34 {
|
|
compatible = "mediatek,mt6660";
|
|
};
|
|
|
|
sound: sound {
|
|
compatible = "mediatek,mt6779-mt6359-sound";
|
|
mediatek,audio-codec = <&mt6359_snd>;
|
|
mediatek,platform = <&afe>;
|
|
mediatek,snd_audio_dsp = <&snd_audio_dsp>;
|
|
mtk_spk_i2s_out = <3>;
|
|
mtk_spk_i2s_in = <0>;
|
|
/* mtk_spk_i2s_mck = <3>; */
|
|
mediatek,speaker-codec {
|
|
sound-dai = <&speaker_amp>;
|
|
};
|
|
};
|
|
|
|
/* feature : $enable $dl_mem $ul_mem $ref_mem */
|
|
snd_audio_dsp: snd_audio_dsp {
|
|
compatible = "mediatek,snd_audio_dsp";
|
|
mtk_dsp_voip = <0x1 0x1 0xffffffff 0xffffffff>;
|
|
mtk_dsp_primary = <0x0 0x0 0xffffffff 0xffffffff>;
|
|
mtk_dsp_offload = <0x0 0x6 0xffffffff 0xffffffff>;
|
|
mtk_dsp_deep = <0x0 0x3 0xffffffff 0xffffffff>;
|
|
mtk_dsp_playback = <0x1 0x4 0xf 0x13>;
|
|
mtk_dsp_capture1 = <0x1 0xffffffff 0xc 0x12>;
|
|
mtk_dsp_a2dp = <0x0 0xffffffff 0xffffffff 0xffffffff>;
|
|
mtk_dsp_dataprovider = <0x1 0xffffffff 0xf 0xffffffff>;
|
|
mtk_dsp_call_final = <0x5 0x4 0xf 0x13>;
|
|
mtk_dsp_ktv = <0x1 0x8 0x11 0xffffffff>;
|
|
mtk_dsp_capture_raw = <0x1 0xffffffff 0xffffffff 0xffffffff>;
|
|
swdsp_smartpa_process_enable = <0x5>;
|
|
};
|
|
|
|
audio_sram@11211000 {
|
|
compatible = "mediatek,audio_sram";
|
|
reg = <0 0x11211000 0 0x18000>;
|
|
prefer_mode = <1>;
|
|
mode_size = <0x12000 0x18000>;
|
|
block_size = <0x1000>;
|
|
};
|
|
|
|
smart_pa: smart_pa {
|
|
};
|
|
|
|
mtk-btcvsd-snd@18050000 {
|
|
compatible = "mediatek,mtk-btcvsd-snd";
|
|
reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
|
|
<0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
|
|
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
/*INFRA MISC, conn_bt_cvsd_mask*/
|
|
/*cvsd_mcu_read, write, packet_indicator*/
|
|
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
|
|
disable_write_silence = <0>;
|
|
};
|
|
|
|
atf_logger {
|
|
compatible = "mediatek,atf_logger";
|
|
};
|
|
|
|
/* Microtrust SW IRQ number 91(123) ~ 95(127) 331(363) */
|
|
utos {
|
|
compatible = "microtrust,utos";
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 92 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
utos_tester {
|
|
compatible = "microtrust,tester-v1";
|
|
};
|
|
|
|
amms_control {
|
|
compatible = "mediatek,amms";
|
|
interrupts = <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
mrdump_ext_rst: mrdump_ext_rst {
|
|
compatible = "mediatek, mrdump_ext_rst-eint";
|
|
mode = "IRQ";
|
|
status = "okay";
|
|
};
|
|
|
|
swtp:swtp {
|
|
compatible = "mediatek, swtp-eint";
|
|
};
|
|
|
|
swtp_1:swtp_1 {
|
|
compatible = "mediatek, swtp_1-eint";
|
|
};
|
|
|
|
mddriver:mddriver {
|
|
compatible = "mediatek,mddriver", "mediatek,mddriver-mt6779";
|
|
mediatek,mdhif_type = <6>; /* bit0~3: CLDMA|CCIF|DPMAIF */
|
|
mediatek,md_id = <0>;
|
|
mediatek,ap_plat_info = <6779>;
|
|
mediatek,md_generation = <6295>;
|
|
mediatek,offset_apon_md1 = <0x1C24>;
|
|
mediatek,cldma_capability = <6>;
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_FALLING>, /*MDWDT*/
|
|
<GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>, /*CCIF0 174/206*/
|
|
<GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; /*CCIF0 175/207*/
|
|
clocks = <&scpsys SCP_SYS_MD1>,
|
|
<&infracfg_ao CLK_INFRA_DPMAIF_CK>,
|
|
<&infracfg_ao CLK_INFRA_CCIF_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF1_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF1_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF2_AP>,
|
|
<&infracfg_ao CLK_INFRA_CCIF2_MD>,
|
|
<&infracfg_ao CLK_INFRA_CCIF4_MD>;
|
|
clock-names = "scp-sys-md1-main",
|
|
"infra-dpmaif-clk",
|
|
"infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif2-ap",
|
|
"infra-ccif2-md",
|
|
"infra-ccif4-md";
|
|
vmodem-supply = <&mt_pmic_vmodem_buck_reg>;
|
|
vsram-supply = <&mt_pmic_vsram_md_ldo_reg>;
|
|
/* power-domains = <&scpsys MT6779_POWER_DOMAIN_MD>; */
|
|
ccci-infracfg = <&infracfg_ao>;
|
|
};
|
|
|
|
md_auxadc:md_auxadc {
|
|
compatible = "mediatek,md_auxadc";
|
|
io-channels = <&auxadc 2>;
|
|
io-channel-names = "md-channel",
|
|
"md-battery";
|
|
};
|
|
|
|
md_ccci_rtc:md_ccci_rtc {
|
|
compatible = "mediatek,md_ccci_rtc";
|
|
nvmem-cells = <&ext_32k>;
|
|
nvmem-cell-names = "external-32k";
|
|
};
|
|
|
|
ccci_md_clk:ccci_md_clk {
|
|
compatible = "mediatek,ccci_md_clk";
|
|
clocks = <&infracfg_ao CLK_INFRA_AES_BCLK>,
|
|
<&infracfg_ao CLK_INFRA_MODEM_TEMP_SHARE>;
|
|
clock-names = "infra-aes-bclk-md",
|
|
"infra-temp-share-md";
|
|
};
|
|
|
|
gpio_usage_mapping:gpio {
|
|
compatible = "mediatek,gpio_usage_mapping";
|
|
};
|
|
|
|
md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
|
|
};
|
|
|
|
md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
|
|
};
|
|
|
|
dram_ctrl {
|
|
compatible = "mediatek,dram-qosctrl";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>;
|
|
};
|
|
|
|
mtkfb: mtkfb {
|
|
compatible = "mediatek,mtkfb";
|
|
|
|
iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
|
|
<&iommu0 M4U_PORT_DISP_OVL0_HDR>,
|
|
<&iommu0 M4U_PORT_DISP_OVL0_2L_HDR>,
|
|
<&iommu0 M4U_PORT_DISP_OVL0>,
|
|
<&iommu0 M4U_PORT_DISP_OVL0_2L>,
|
|
<&iommu0 M4U_PORT_DISP_PVRIC0>,
|
|
<&iommu0 M4U_PORT_DISP_RDMA0>,
|
|
<&iommu0 M4U_PORT_DISP_WDMA0>,
|
|
<&iommu0 M4U_PORT_DISP_FAKE0>;
|
|
};
|
|
|
|
dispsys {
|
|
compatible = "mediatek,dispsys";
|
|
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys CLK_MM_SMI_COMMON>,
|
|
<&mmsys CLK_MM_SMI_LARB0>,
|
|
<&mmsys CLK_MM_SMI_LARB1>,
|
|
<&mmsys CLK_MM_GALS_COMM0>,
|
|
<&mmsys CLK_MM_GALS_COMM1>,
|
|
<&mmsys CLK_MM_DISP_OVL0>,
|
|
<&mmsys CLK_MM_DISP_OVL0_2L>,
|
|
<&mmsys CLK_MM_DISP_OVL1_2L>,
|
|
<&mmsys CLK_MM_DISP_RDMA0>,
|
|
<&mmsys CLK_MM_DISP_RDMA1>,
|
|
<&mmsys CLK_MM_DISP_WDMA0>,
|
|
<&mmsys CLK_MM_DISP_COLOR0>,
|
|
<&mmsys CLK_MM_DISP_CCORR0>,
|
|
<&mmsys CLK_MM_DISP_AAL0>,
|
|
<&mmsys CLK_MM_DISP_GAMMA0>,
|
|
<&mmsys CLK_MM_DISP_DITHER0>,
|
|
<&mmsys CLK_MM_DSI0_MM_CK>,
|
|
<&mmsys CLK_MM_DSI0_IF_CK>,
|
|
<&mmsys CLK_MM_DPI_MM_CK>,
|
|
<&mmsys CLK_MM_DPI_IF_CK>,
|
|
<&mmsys CLK_MM_26M>,
|
|
<&mmsys CLK_MM_DISP_RSZ>,
|
|
<&topckgen CLK_TOP_MM>,
|
|
<&topckgen CLK_TOP_DISP_PWM>,
|
|
<&infracfg_ao CLK_INFRA_DISP_PWM>,
|
|
<&clk26m>,
|
|
<&mmsys CLK_MM_DISP_POSTMASK0>,
|
|
<&mmsys CLK_MM_DISP_OVL_FBDC>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3_D2>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3_D4>,
|
|
<&topckgen CLK_TOP_OSC_D2>,
|
|
<&topckgen CLK_TOP_OSC_D4>,
|
|
<&topckgen CLK_TOP_OSC_D16>,
|
|
<&topckgen CLK_TOP_DPI0>,
|
|
<&topckgen CLK_TOP_TVDPLL_D2>,
|
|
<&topckgen CLK_TOP_TVDPLL_D4>,
|
|
<&topckgen CLK_TOP_TVDPLL_D8>,
|
|
<&topckgen CLK_TOP_TVDPLL_D16>,
|
|
<&topckgen CLK_TOP_TVDPLL_CK>,
|
|
<&apmixed CLK_APMIXED_MIPID0_26M>;
|
|
|
|
clock-names = "CLK_MM_MTCMOS",
|
|
"CLK_SMI_COMMON",
|
|
"CLK_SMI_LARB0",
|
|
"CLK_SMI_LARB1",
|
|
"CLK_GALS_COMM0",
|
|
"CLK_GALS_COMM1",
|
|
"CLK_DISP_OVL0",
|
|
"CLK_DISP_OVL0_2L",
|
|
"CLK_DISP_OVL1_2L",
|
|
"CLK_DISP_RDMA0",
|
|
"CLK_DISP_RDMA1",
|
|
"CLK_DISP_WDMA0",
|
|
"CLK_DISP_COLOR0",
|
|
"CLK_DISP_CCORR0",
|
|
"CLK_DISP_AAL0",
|
|
"CLK_DISP_GAMMA0",
|
|
"CLK_DISP_DITHER0",
|
|
"CLK_DSI0_MM_CK",
|
|
"CLK_DSI0_IF_CK",
|
|
"CLK_DPI_MM_CK",
|
|
"CLK_DPI_IF_CK",
|
|
"CLK_MM_26M",
|
|
"CLK_DISP_RSZ",
|
|
"CLK_MUX_MM",
|
|
"CLK_MUX_DISP_PWM",
|
|
"CLK_DISP_PWM",
|
|
"CLK_26M",
|
|
"CLK_DISP_POSTMASK",
|
|
"CLK_DISP_OVL_FBDC",
|
|
"CLK_UNIVPLL_D3_D2",
|
|
"CLK_UNIVPLL_D3_D4",
|
|
"CLK_OSC_D2",
|
|
"CLK_OSC_D4",
|
|
"CLK_OSC_D16",
|
|
"CLK_MUX_DPI0",
|
|
"CLK_TVDPLL_D2",
|
|
"CLK_TVDPLL_D4",
|
|
"CLK_TVDPLL_D8",
|
|
"CLK_TVDPLL_D16",
|
|
"CLK_TVDPLL_CK",
|
|
"CLK_MIPID0_26M";
|
|
};
|
|
|
|
dsi_te: dsi_te {
|
|
compatible = "mediatek, dsi_te-eint";
|
|
};
|
|
|
|
mtk_edmc: edmc@19050000 {
|
|
compatible = "mtk,edmc";
|
|
reg = <0 0x19050000 0 0x1000>;
|
|
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
ipu_conn@19000000 {
|
|
compatible = "mediatek,ipu_conn";
|
|
reg = <0 0x19000000 0 0x1000>;
|
|
};
|
|
|
|
ipu_vcore@19020000 {
|
|
compatible = "mediatek,ipu_vcore";
|
|
reg = <0 0x19020000 0 0x1000>;
|
|
};
|
|
|
|
vpu_core0@0x19100000 {
|
|
compatible = "mediatek,vpu_core0";
|
|
reg = <0 0x19100000 0 0x94000>;
|
|
interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
nvmem-cells = <&apu_efuse_data &apu_segment>;
|
|
nvmem-cell-names = "efuse_data","efuse_segment";
|
|
|
|
clocks = <&topckgen TOP_MUX_DSP>,
|
|
<&topckgen TOP_MUX_DSP1>,
|
|
<&topckgen TOP_MUX_DSP2>,
|
|
<&topckgen TOP_MUX_DSP3>,
|
|
<&topckgen TOP_MUX_IPU_IF>,
|
|
<&apu0 APU0_JTAG_CG>,
|
|
<&apu0 APU0_AXI_M_CG>,
|
|
<&apu0 APU0_APU_CG>,
|
|
<&apu1 APU1_JTAG_CG>,
|
|
<&apu1 APU1_AXI_M_CG>,
|
|
<&apu1 APU1_APU_CG>,
|
|
<&apu_mdla APU_MDLA_APB_CG>,
|
|
<&apu_mdla APU_MDLA_CG_B0>,
|
|
<&apu_mdla APU_MDLA_CG_B1>,
|
|
<&apu_mdla APU_MDLA_CG_B2>,
|
|
<&apu_mdla APU_MDLA_CG_B3>,
|
|
<&apu_mdla APU_MDLA_CG_B4>,
|
|
<&apu_mdla APU_MDLA_CG_B5>,
|
|
<&apu_mdla APU_MDLA_CG_B6>,
|
|
<&apu_mdla APU_MDLA_CG_B7>,
|
|
<&apu_mdla APU_MDLA_CG_B8>,
|
|
<&apu_mdla APU_MDLA_CG_B9>,
|
|
<&apu_mdla APU_MDLA_CG_B10>,
|
|
<&apu_mdla APU_MDLA_CG_B11>,
|
|
<&apu_mdla APU_MDLA_CG_B12>,
|
|
<&apu_conn APU_CONN_APU_CG>,
|
|
<&apu_conn APU_CONN_AHB_CG>,
|
|
<&apu_conn APU_CONN_AXI_CG>,
|
|
<&apu_conn APU_CONN_ISP_CG>,
|
|
<&apu_conn APU_CONN_CAM_ADL_CG>,
|
|
<&apu_conn APU_CONN_IMG_ADL_CG>,
|
|
<&apu_conn APU_CONN_EMI_26M_CG>,
|
|
<&apu_conn APU_CONN_VPU_UDI_CG>,
|
|
<&apu_vcore APU_VCORE_AHB_CG>,
|
|
<&apu_vcore APU_VCORE_AXI_CG>,
|
|
<&apu_vcore APU_VCORE_ADL_CG>,
|
|
<&apu_vcore APU_VCORE_QOS_CG>,
|
|
<&clk26m>,
|
|
<&topckgen TOP_UNIVPLL_D3_D8>,
|
|
<&topckgen TOP_UNIVPLL_D3_D4>,
|
|
<&topckgen TOP_MAINPLL_D2_D4>,
|
|
<&topckgen TOP_UNIVPLL_D3_D2>,
|
|
<&topckgen TOP_MAINPLL_D2_D2>,
|
|
<&topckgen TOP_UNIVPLL_D2_D2>,
|
|
<&topckgen TOP_MAINPLL_D3>,
|
|
<&topckgen TOP_UNIVPLL_D3>,
|
|
<&topckgen TOP_MMPLL_D7>,
|
|
<&topckgen TOP_MMPLL_D6>,
|
|
<&topckgen TOP_ADSPPLL_D5>,
|
|
<&topckgen TOP_TVDPLL_CK>,
|
|
<&topckgen TOP_TVDPLL_MAINPLL_D2_CK>,
|
|
<&topckgen TOP_UNIVPLL_D2>,
|
|
<&topckgen TOP_ADSPPLL_D4>,
|
|
<&topckgen TOP_MAINPLL_D2>,
|
|
<&topckgen TOP_MMPLL_D4>,
|
|
<&mmsys MMSYS_GALS_IPU2MM>,
|
|
<&mmsys MMSYS_GALS_IPU12MM>,
|
|
<&mmsys MMSYS_GALS_COMM1>,
|
|
<&mmsys MMSYS_GALS_COMM0>,
|
|
<&mmsys MMSYS_SMI_COMMON>,
|
|
<&mmsys MMSYS_IPU_DL_TXCK>,
|
|
<&mmsys MMSYS_IPU_DL_RX_CK>,
|
|
<&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_VPU_VCORE_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_VCORE_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CONN_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CONN_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE0_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE0_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE1_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE1_SHUTDOWN>,
|
|
<&scpsys SCP_SYS_VPU_CORE2_DORMANT>,
|
|
<&scpsys SCP_SYS_VPU_CORE2_SHUTDOWN>;
|
|
|
|
clock-names = "clk_top_dsp_sel",
|
|
"clk_top_dsp1_sel",
|
|
"clk_top_dsp2_sel",
|
|
"clk_top_dsp3_sel",
|
|
"clk_top_ipu_if_sel",
|
|
"clk_apu_core0_jtag_cg",
|
|
"clk_apu_core0_axi_m_cg",
|
|
"clk_apu_core0_apu_cg",
|
|
"clk_apu_core1_jtag_cg",
|
|
"clk_apu_core1_axi_m_cg",
|
|
"clk_apu_core1_apu_cg",
|
|
"clk_apu_mdla_apb_cg",
|
|
"clk_apu_mdla_cg_b0",
|
|
"clk_apu_mdla_cg_b1",
|
|
"clk_apu_mdla_cg_b2",
|
|
"clk_apu_mdla_cg_b3",
|
|
"clk_apu_mdla_cg_b4",
|
|
"clk_apu_mdla_cg_b5",
|
|
"clk_apu_mdla_cg_b6",
|
|
"clk_apu_mdla_cg_b7",
|
|
"clk_apu_mdla_cg_b8",
|
|
"clk_apu_mdla_cg_b9",
|
|
"clk_apu_mdla_cg_b10",
|
|
"clk_apu_mdla_cg_b11",
|
|
"clk_apu_mdla_cg_b12",
|
|
"clk_apu_conn_apu_cg",
|
|
"clk_apu_conn_ahb_cg",
|
|
"clk_apu_conn_axi_cg",
|
|
"clk_apu_conn_isp_cg",
|
|
"clk_apu_conn_cam_adl_cg",
|
|
"clk_apu_conn_img_adl_cg",
|
|
"clk_apu_conn_emi_26m_cg",
|
|
"clk_apu_conn_vpu_udi_cg",
|
|
"clk_apu_vcore_ahb_cg",
|
|
"clk_apu_vcore_axi_cg",
|
|
"clk_apu_vcore_adl_cg",
|
|
"clk_apu_vcore_qos_cg",
|
|
"clk_top_clk26m",
|
|
"clk_top_univpll_d3_d8",
|
|
"clk_top_univpll_d3_d4",
|
|
"clk_top_mainpll_d2_d4",
|
|
"clk_top_univpll_d3_d2",
|
|
"clk_top_mainpll_d2_d2",
|
|
"clk_top_univpll_d2_d2",
|
|
"clk_top_mainpll_d3",
|
|
"clk_top_univpll_d3",
|
|
"clk_top_mmpll_d7",
|
|
"clk_top_mmpll_d6",
|
|
"clk_top_adsppll_d5",
|
|
"clk_top_tvdpll_ck",
|
|
"clk_top_tvdpll_mainpll_d2_ck",
|
|
"clk_top_univpll_d2",
|
|
"clk_top_adsppll_d4",
|
|
"clk_top_mainpll_d2",
|
|
"clk_top_mmpll_d4",
|
|
"clk_mmsys_gals_ipu2mm",
|
|
"clk_mmsys_gals_ipu12mm",
|
|
"clk_mmsys_gals_comm1",
|
|
"clk_mmsys_gals_comm0",
|
|
"clk_mmsys_smi_common",
|
|
"clk_mmsys_ipu_dl_txck",
|
|
"clk_mmsys_ipu_dl_rx_ck",
|
|
"mtcmos_dis",
|
|
"mtcmos_vpu_vcore_dormant",
|
|
"mtcmos_vpu_vcore_shutdown",
|
|
"mtcmos_vpu_conn_dormant",
|
|
"mtcmos_vpu_conn_shutdown",
|
|
"mtcmos_vpu_core0_dormant",
|
|
"mtcmos_vpu_core0_shutdown",
|
|
"mtcmos_vpu_core1_dormant",
|
|
"mtcmos_vpu_core1_shutdown",
|
|
"mtcmos_vpu_core2_dormant",
|
|
"mtcmos_vpu_core2_shutdown";
|
|
};
|
|
|
|
vpu_core1@0x19200000 {
|
|
compatible = "mediatek,vpu_core1";
|
|
reg = <0 0x19200000 0 0x94000>;
|
|
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
apu_dvfs@19180000 {
|
|
compatible = "mediatek,apu_dvfs";
|
|
reg = <0 0x19180000 0 0x1000>;
|
|
|
|
nvmem-cells = <&apu_ptpod>;
|
|
nvmem-cell-names = "efuse_ptpod";
|
|
};
|
|
|
|
odm: odm {
|
|
compatible = "simple-bus";
|
|
/* reserved for overlay by odm */
|
|
};
|
|
|
|
memory_ssmr_features: memory-ssmr-features {
|
|
compatible = "mediatek,memory-ssmr-features";
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
|
|
defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || \
|
|
defined(CONFIG_MICROTRUST_TEE_SUPPORT)
|
|
svp-region-based-size = <0 0x10000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_CAM_SECURITY_SUPPORT
|
|
2d_fr-size = <0 0x8000000>;
|
|
#endif
|
|
#if defined(CONFIG_TRUSTONIC_TRUSTED_UI) || \
|
|
defined(CONFIG_BLOWFISH_TUI_SUPPORT)
|
|
tui-size = <0 0x4000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT
|
|
wfd-size = <0 0x5000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_PROT_MEM_SUPPORT
|
|
prot-region-based-size = <0 0x8000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_HAPP_MEM_SUPPORT
|
|
ta-elf-size = <0 0x1000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_HAPP_MEM_SUPPORT
|
|
ta-stack-heap-size = <0 0x6000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_SDSP_SHARED_MEM_SUPPORT
|
|
sdsp-tee-sharedmem-size = <0 0x1000000>;
|
|
#endif
|
|
#ifdef CONFIG_MTK_SDSP_MEM_SUPPORT
|
|
sdsp-firmware-size = <0 0x1000000>;
|
|
#endif
|
|
};
|
|
|
|
touch: touch {
|
|
compatible = "goodix,touch";
|
|
};
|
|
|
|
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
|
|
compatible = "mediatek,pmic_clock_buffer";
|
|
mediatek,clkbuf-quantity = <7>;
|
|
mediatek,clkbuf-config = <2 1 1 2 0 0 1>;
|
|
mediatek,clkbuf-output-impedance = <6 4 6 4 0 0 6>;
|
|
mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>;
|
|
mediatek,bblpm-support = "enable";
|
|
|
|
pwrap-dcxo-en = <0x190 0 0x190 1 0x190 0>;
|
|
pwrap-dcxo-cfg = <0x194 0x1A4>;
|
|
spm-pwr-status = <0x160 0 0x160 1>;
|
|
|
|
pwrap = <&pwrap>;
|
|
sleep = <&sleep>;
|
|
};
|
|
|
|
nfc:nfc {
|
|
compatible = "mediatek,nfc-gpio-v2";
|
|
gpio-rst = <36>;
|
|
gpio-rst-std = <&pio 36 0x0>;
|
|
gpio-irq = <35>;
|
|
gpio-irq-std = <&pio 35 0x0>;
|
|
};
|
|
|
|
irq_nfc: irq_nfc {
|
|
compatible = "mediatek,irq_nfc-eint";
|
|
};
|
|
|
|
mtee_svp: mtee_svp {
|
|
compatible = "medaitek,svp";
|
|
};
|
|
/* svp end */
|
|
|
|
bat_gm30: battery {
|
|
compatible = "mediatek,bat_gm30";
|
|
};
|
|
|
|
mtk_m4u_debug {
|
|
compatible = "mediatek,mt6779-m4u-debug";
|
|
};
|
|
|
|
secure_m4u {
|
|
compatible = "mediatek,secure_m4u";
|
|
mediatek,mm_m4u = <&iommu0>;
|
|
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>, /* sec mm m4u */
|
|
<GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; /* sec vpu m4u */
|
|
iommus = <&iommu0 M4U_PORT_DISP_POSTMASK0>,
|
|
<&iommu0 M4U_PORT_DISP_OVL0_2L_HDR>,
|
|
<&iommu0 M4U_PORT_HW_VDEC_MC_EXT>,
|
|
<&iommu0 M4U_PORT_VENC_RCPU>,
|
|
<&iommu0 M4U_PORT_IMGI_D1>,
|
|
<&iommu0 M4U_PORT_DVS_RDMA>,
|
|
<&iommu0 M4U_PORT_FDVT_RDA>,
|
|
<&iommu0 M4U_PORT_CAM_IMGO_R1_C>,
|
|
<&iommu0 M4U_PORT_CAM_IMGO_R1_A>;
|
|
};
|
|
|
|
ssmr {
|
|
compatible = "mediatek,trusted_mem";
|
|
memory-region = <&ssmr_cma_mem>;
|
|
};
|
|
|
|
rt-pd-manager {
|
|
compatible = "mediatek,rt-pd-manager";
|
|
};
|
|
|
|
subpmic_pmu_eint: mt6360_pmu_eint {
|
|
};
|
|
|
|
tcpc_pd: tcpc_pd {
|
|
};
|
|
|
|
msdc1_ins: msdc1_ins {
|
|
};
|
|
|
|
goodix_fp: fingerprint {
|
|
compatible = "mediatek,goodix-fp";
|
|
};
|
|
|
|
lk_charger: lk_charger {
|
|
compatible = "mediatek,lk_charger";
|
|
enable_anime;
|
|
enable_pe_plus;
|
|
enable_pd20_reset;
|
|
power_path_support;
|
|
max_charger_voltage = <6500000>;
|
|
fast_charge_voltage = <3000000>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
non_std_ac_charger_current = <500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
ta_ac_charger_current = <3000000>;
|
|
pd_charger_current = <500000>;
|
|
|
|
/* battery temperature protection */
|
|
temp_t4_threshold = <50>;
|
|
temp_t3_threshold = <45>;
|
|
temp_t1_threshold = <0>;
|
|
};
|
|
|
|
pe: pe {
|
|
compatible = "mediatek,charger,pe";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
ta_12v_support;
|
|
ta_9v_support;
|
|
|
|
pe_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
ta_ac_12v_input_current = <3200000>;
|
|
ta_ac_9v_input_current = <3200000>;
|
|
ta_ac_7v_input_current = <3200000>;
|
|
pe_charger_current = <3000000>;
|
|
|
|
};
|
|
|
|
pe2: pe2 {
|
|
compatible = "mediatek,charger,pe2";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
/* PE 2.0 */
|
|
pe20_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* cable measurement impedance */
|
|
cable_imp_threshold = <699>;
|
|
vbat_cable_imp_threshold = <3900000>; /* uV */
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
pdc: pdc {
|
|
compatible = "mediatek,charger,pd";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min_charger_voltage = <4600000>;
|
|
pd_vbus_low_bound = <5000000>;
|
|
pd_vbus_upper_bound = <5000000>;
|
|
vsys_watt = <5000000>;
|
|
ibus_err = <14>;
|
|
|
|
pd_stop_battery_soc = <80>;
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
/* dual charger */
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
pe4: pe4 {
|
|
compatible = "mediatek,charger,pe4";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min_charger_voltage = <4600000>;
|
|
pe40_stop_battery_soc = <80>;
|
|
|
|
high_temp_to_leave_pe40 = <46>;
|
|
high_temp_to_enter_pe40 = <39>;
|
|
low_temp_to_leave_pe40 = <10>;
|
|
low_temp_to_enter_pe40 = <16>;
|
|
ibus_err = <14>;
|
|
|
|
/* PE 4.0 cable impedance (mohm) */
|
|
pe40_r_cable_1a_lower = <500>;
|
|
pe40_r_cable_2a_lower = <351>;
|
|
pe40_r_cable_3a_lower = <240>;
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
charger: charger {
|
|
compatible = "mediatek,charger";
|
|
gauge = <&mtk_gauge>;
|
|
charger = <&mt6360_chg>;
|
|
bootmode = <&chosen>;
|
|
pmic = <&main_pmic>;
|
|
|
|
algorithm_name = "Basic";
|
|
charger_configuration= <0>;
|
|
|
|
/* common */
|
|
battery_cv = <4350000>;
|
|
max_charger_voltage = <6500000>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* sw jeita */
|
|
/* enable_sw_jeita; */
|
|
jeita_temp_above_t4_cv = <4240000>;
|
|
jeita_temp_t3_to_t4_cv = <4240000>;
|
|
jeita_temp_t2_to_t3_cv = <4340000>;
|
|
jeita_temp_t1_to_t2_cv = <4240000>;
|
|
jeita_temp_t0_to_t1_cv = <4040000>;
|
|
jeita_temp_below_t0_cv = <4040000>;
|
|
temp_t4_thres = <50>;
|
|
temp_t4_thres_minus_x_degree = <47>;
|
|
temp_t3_thres = <45>;
|
|
temp_t3_thres_minus_x_degree = <39>;
|
|
temp_t2_thres = <10>;
|
|
temp_t2_thres_plus_x_degree = <16>;
|
|
temp_t1_thres = <0>;
|
|
temp_t1_thres_plus_x_degree = <6>;
|
|
temp_t0_thres = <0>;
|
|
temp_t0_thres_plus_x_degree = <0>;
|
|
temp_neg_10_thres = <0>;
|
|
|
|
/* battery temperature protection */
|
|
enable_min_charge_temp;
|
|
min_charge_temp = <0>;
|
|
min_charge_temp_plus_x_degree = <6>;
|
|
max_charge_temp = <50>;
|
|
max_charge_temp_minus_x_degree = <47>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2050000>;
|
|
ac_charger_input_current = <3200000>;
|
|
charging_host_charger_current = <1500000>;
|
|
|
|
/* dynamic mivr */
|
|
enable_dynamic_mivr;
|
|
min_charger_voltage_1 = <4400000>;
|
|
min_charger_voltage_2 = <4200000>;
|
|
max_dmivr_charger_current = <1800000>;
|
|
};
|
|
|
|
pd_adapter: pd_adapter {
|
|
compatible = "mediatek,pd_adapter";
|
|
adapter_name = "pd_adapter";
|
|
};
|
|
|
|
iommu_test {
|
|
compatible = "mediatek,ktf-iommu-test";
|
|
iommus = <&iommu0 M4U_PORT_DISP_RDMA0>;
|
|
};
|
|
|
|
extcon_usb: extcon_usb {
|
|
compatible = "mediatek,extcon-usb";
|
|
charger = <&mt6360_chg>;
|
|
vbus-supply = <&otg_vbus>;
|
|
vbus-voltage = <5000000>;
|
|
vbus-current = <1800000>;
|
|
dev-conn = <&ssusb>;
|
|
mediatek,bypss-typec-sink = <1>;
|
|
};
|
|
};
|
|
|
|
&i2c6 {
|
|
speaker_amp: speaker_amp@34 {
|
|
compatible = "mediatek,speaker_amp";
|
|
#sound-dai-cells = <0>;
|
|
reg = <0x34>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
&kd_camera_hw1 {
|
|
vcamio-supply = <&mt_pmic_vcamio_ldo_reg>;
|
|
vcamio_sub-supply = <&mt_pmic_vcamio_ldo_reg>;
|
|
vcamio_main2-supply = <&mt_pmic_vcamio_ldo_reg>;
|
|
vcamaf-supply = <&mt_pmic_vcamio_ldo_reg>;
|
|
vcamaf_main2-supply = <&mt_pmic_vcamio_ldo_reg>;
|
|
status = "okay";
|
|
};
|
|
|
|
#include "mediatek/mt6360_pd.dtsi"
|
|
#include "mediatek/mt6360.dtsi"
|
|
#include "mediatek/mt6359.dtsi"
|
|
#include "mediatek/bat_setting/mt6779_battery_prop.dtsi"
|
|
#include "mediatek/cust_mt6779_msdc.dtsi"
|
|
#include "mediatek/cust_mt6779_camera.dtsi"
|
|
#include "mediatek/trusty.dtsi"
|