225 lines
6.6 KiB
C
225 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_LAYERING_RULE_BASE__
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#define __MTK_LAYERING_RULE_BASE__
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#if 0
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#include "disp_session.h"
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#include "disp_lcm.h"
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#include "disp_drv_log.h"
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#include "primary_display.h"
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#include "disp_drv_platform.h"
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#include "display_recorder.h"
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#endif
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#include <drm/drmP.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_gem.h>
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#include <drm/mediatek_drm.h>
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#include <drm/drm_modes.h>
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/* move to Platform dependent part? */
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#define TOTAL_OVL_LAYER_NUM (4 + 3 + 2 + 3)
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#define PRIMARY_SESSION_INPUT_LAYER_COUNT (12) /* phy(4+2) + ext(3+3) */
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#define EXTERNAL_SESSION_INPUT_LAYER_COUNT \
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(2 /*2+3*/) /* 2 is enough, no need ext layer */
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/* ***************************************** */
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#define PRIMARY_OVL_LAYER_NUM PRIMARY_SESSION_INPUT_LAYER_COUNT
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#define SECONDARY_OVL_LAYER_NUM EXTERNAL_SESSION_INPUT_LAYER_COUNT
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/* #define HRT_DEBUG_LEVEL1 */
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/* #define HRT_DEBUG_LEVEL2 */
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/* #define HRT_UT_DEBUG */
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#define PATH_FMT_RSZ_SHIFT 9
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#define PATH_FMT_PIPE_SHIFT 7
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#define PATH_FMT_DISP_SHIFT 5
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#define PATH_FMT_ID_SHIFT 0
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#define HRT_UINT_BOUND_BPP 4
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#define HRT_UINT_WEIGHT 100
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/* bpp x uint weight = 2 x 100 */
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#define HRT_AEE_WEIGHT 200
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#define HRT_ROUND_CORNER_WEIGHT 200
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#define HRT_GET_FIRST_SET_BIT(n) (((n) - ((n) & ((n) - 1))))
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enum HRT_DISP_TYPE {
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HRT_PRIMARY = 0,
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HRT_SECONDARY,
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HRT_THIRD,
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HRT_TYPE_NUM,
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};
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enum HRT_DEBUG_LAYER_DATA {
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HRT_LAYER_DATA_ID = 0,
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HRT_LAYER_DATA_SRC_FMT,
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HRT_LAYER_DATA_DST_OFFSET_X,
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HRT_LAYER_DATA_DST_OFFSET_Y,
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HRT_LAYER_DATA_DST_WIDTH,
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/*5*/
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HRT_LAYER_DATA_DST_HEIGHT,
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HRT_LAYER_DATA_SRC_WIDTH,
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HRT_LAYER_DATA_SRC_HEIGHT,
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HRT_LAYER_DATA_SRC_OFFSET_X,
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HRT_LAYER_DATA_SRC_OFFSET_Y,
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HRT_LAYER_DATA_COMPRESS,
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HRT_LAYER_DATA_CAPS,
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HRT_LAYER_DATA_NUM,
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};
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enum HRT_TYPE {
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HRT_TYPE_LARB0 = 0,
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HRT_TYPE_LARB1,
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HRT_TYPE_EMI,
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HRT_TYPE_UNKNOWN,
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};
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enum HRT_SYS_STATE {
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DISP_HRT_MJC_ON = 0,
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DISP_HRT_FORCE_DUAL_OFF,
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DISP_HRT_MULTI_TUI_ON,
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};
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enum DISP_HW_MAPPING_TB_TYPE {
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DISP_HW_EMI_BOUND_TB,
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DISP_HW_LARB_BOUND_TB,
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DISP_HW_OVL_TB,
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DISP_HW_LARB_TB,
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DISP_HW_LAYER_TB,
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};
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enum LYE_HELPER_OPT {
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LYE_OPT_DUAL_PIPE,
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LYE_OPT_EXT_LAYER,
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LYE_OPT_RPO,
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LYE_OPT_CLEAR_LAYER,
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LYE_OPT_NUM
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};
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enum ADJUST_LAYOUT_PURPOSE {
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ADJUST_LAYOUT_EXT_GROUPING,
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ADJUST_LAYOUT_OVERLAP_CAL,
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};
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enum LYE_TYPE {
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LYE_NORMAL,
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LYE_EXT0,
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LYE_EXT1,
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LYE_EXT2,
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};
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struct hrt_sort_entry {
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struct hrt_sort_entry *head, *tail;
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struct drm_mtk_layer_config *layer_info;
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int key;
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int overlap_w;
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};
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struct layering_rule_info_t {
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int bound_tb_idx;
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int addon_scn[HRT_TYPE_NUM];
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int dal_enable;
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int primary_fps;
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int hrt_sys_state;
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int wrot_sram;
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unsigned int hrt_idx;
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};
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enum SCN_FACTOR {
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SCN_NEED_VP_PQ = 0x00000001,
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SCN_NEED_GAME_PQ = 0x00000002,
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SCN_TRIPLE_DISP = 0x00000004,
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};
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struct layering_rule_ops {
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void (*scenario_decision)(unsigned int scn_decision_flag,
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unsigned int scale_num);
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int *(*get_bound_table)(enum DISP_HW_MAPPING_TB_TYPE tb_type);
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uint16_t (*get_mapping_table)(struct drm_device *dev, int disp_idx,
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enum DISP_HW_MAPPING_TB_TYPE tb_type,
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int param);
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/* should be removed */
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int (*get_hrt_bound)(int is_larb, int hrt_level);
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void (*copy_hrt_bound_table)(struct drm_mtk_layering_info *disp_info,
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int is_larb, int *hrt_table, struct drm_device *dev);
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bool (*rollback_to_gpu_by_hw_limitation)(
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struct drm_device *dev,
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struct drm_mtk_layering_info *disp_info);
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bool (*rollback_all_to_GPU_for_idle)(struct drm_device *dev);
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/* for fbdc */
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void (*fbdc_pre_calculate)(struct drm_mtk_layering_info *disp_info);
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void (*fbdc_adjust_layout)(struct drm_mtk_layering_info *disp_info,
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enum ADJUST_LAYOUT_PURPOSE p);
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void (*fbdc_restore_layout)(struct drm_mtk_layering_info *dst_info,
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enum ADJUST_LAYOUT_PURPOSE p);
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void (*fbdc_rule)(struct drm_mtk_layering_info *disp_info);
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};
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#define HRT_GET_DVFS_LEVEL(hrt_num) (hrt_num & 0xF)
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#define HRT_SET_DVFS_LEVEL(hrt_num, value) \
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(hrt_num = ((hrt_num & ~(0xF)) | (value & 0xF)))
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#define HRT_GET_SCALE_SCENARIO(hrt_num) ((hrt_num & 0xF0) >> 4)
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#define HRT_SET_SCALE_SCENARIO(hrt_num, value) \
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(hrt_num = ((hrt_num & ~(0xF0)) | ((value & 0xF) << 4)))
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#define HRT_GET_AEE_FLAG(hrt_num) ((hrt_num & 0x100) >> 8)
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#define HRT_SET_AEE_FLAG(hrt_num, value) \
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(hrt_num = ((hrt_num & ~(0x100)) | ((value & 0x1) << 8)))
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#define HRT_GET_WROT_SRAM_FLAG(hrt_num) ((hrt_num & 0x600) >> 9)
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#define HRT_SET_WROT_SRAM_FLAG(hrt_num, value) \
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(hrt_num = ((hrt_num & ~(0x600)) | ((value & 0x3) << 9)))
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#define HRT_GET_NO_COMPRESS_FLAG(hrt_num) ((hrt_num & 0x7800) >> 11)
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#define HRT_SET_NO_COMPRESS_FLAG(hrt_num, value) \
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(hrt_num = ((hrt_num & ~(0x7800)) | ((value & 0xf) << 11)))
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#define HRT_GET_PATH_ID(hrt_path) (hrt_path & 0x1F)
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// int layering_rule_start(struct drm_mtk_layering_info *disp_info, int
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// debug_mode);
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extern int hdmi_get_dev_info(int is_sf, void *info);
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// int gen_hrt_pattern(void);
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// int set_hrt_state(enum HRT_SYS_STATE sys_state, int en);
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void mtk_register_layering_rule_ops(struct layering_rule_ops *ops,
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struct layering_rule_info_t *info);
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int mtk_get_phy_layer_limit(uint16_t layer_map_tb);
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// int get_phy_ovl_layer_cnt(struct drm_mtk_layering_info *disp_info, int
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// disp_idx);
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// bool is_decouple_path(struct drm_mtk_layering_info *disp_info);
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int mtk_rollback_resize_layer_to_GPU_range(
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struct drm_mtk_layering_info *disp_info, int disp_idx, int start_idx,
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int end_idx);
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int mtk_rollback_all_resize_layer_to_GPU(
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struct drm_mtk_layering_info *disp_info, int disp_idx);
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bool mtk_is_yuv(uint32_t format);
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// bool is_argb_fmt(uint32_t format);
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bool mtk_is_gles_layer(struct drm_mtk_layering_info *disp_info, int disp_idx,
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int layer_idx);
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bool mtk_has_layer_cap(struct drm_mtk_layer_config *layer_info,
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enum MTK_LAYERING_CAPS l_caps);
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void mtk_set_layering_opt(enum LYE_HELPER_OPT opt, int value);
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void mtk_rollback_layer_to_GPU(struct drm_mtk_layering_info *disp_info,
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int disp_idx, int i);
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/* rollback and set NO_FBDC flag */
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void mtk_rollback_compress_layer_to_GPU(struct drm_mtk_layering_info *disp_info,
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int disp_idx, int i);
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bool mtk_is_layer_id_valid(struct drm_mtk_layering_info *disp_info,
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int disp_idx, int i);
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int mtk_layering_rule_ioctl(struct drm_device *drm, void *data,
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struct drm_file *file_priv);
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#if IS_ENABLED(CONFIG_COMPAT)
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int mtk_layering_rule_ioctl_compat(struct file *file, unsigned int cmd,
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unsigned long arg);
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#endif
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bool is_triple_disp(struct drm_mtk_layering_info *disp_info);
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#endif
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