375 lines
18 KiB
C
375 lines
18 KiB
C
/*************************************************************************/ /*!
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@File rgx_mips.h
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@Title
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Platform RGX
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@Description RGX MIPS definitions, kernel/user space
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(RGX_MIPS_H)
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#define RGX_MIPS_H
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/*
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* Utility defines for memory management
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*/
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#define RGXMIPSFW_LOG2_PAGE_SIZE_4K (12)
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#define RGXMIPSFW_PAGE_SIZE_4K (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE_4K)
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#define RGXMIPSFW_PAGE_MASK_4K (RGXMIPSFW_PAGE_SIZE_4K - 1)
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#define RGXMIPSFW_LOG2_PAGE_SIZE_64K (16)
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#define RGXMIPSFW_PAGE_SIZE_64K (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE_64K)
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#define RGXMIPSFW_PAGE_MASK_64K (RGXMIPSFW_PAGE_SIZE_64K - 1)
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#define RGXMIPSFW_LOG2_PAGE_SIZE_256K (18)
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#define RGXMIPSFW_PAGE_SIZE_256K (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE_256K)
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#define RGXMIPSFW_PAGE_MASK_256K (RGXMIPSFW_PAGE_SIZE_256K - 1)
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#define RGXMIPSFW_LOG2_PAGE_SIZE_1MB (20)
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#define RGXMIPSFW_PAGE_SIZE_1MB (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE_1MB)
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#define RGXMIPSFW_PAGE_MASK_1MB (RGXMIPSFW_PAGE_SIZE_1MB - 1)
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#define RGXMIPSFW_LOG2_PAGE_SIZE_4MB (22)
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#define RGXMIPSFW_PAGE_SIZE_4MB (0x1 << RGXMIPSFW_LOG2_PAGE_SIZE_4MB)
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#define RGXMIPSFW_PAGE_MASK_4MB (RGXMIPSFW_PAGE_SIZE_4MB - 1)
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#define RGXMIPSFW_LOG2_PTE_ENTRY_SIZE (2)
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/* log2 page table sizes dependent on FW heap size and page size (for each OS) */
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#define RGXMIPSFW_LOG2_PAGETABLE_SIZE_4K (RGX_FIRMWARE_HEAP_SHIFT - RGXMIPSFW_LOG2_PAGE_SIZE_4K + RGXMIPSFW_LOG2_PTE_ENTRY_SIZE)
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#define RGXMIPSFW_LOG2_PAGETABLE_SIZE_64K (RGX_FIRMWARE_HEAP_SHIFT - RGXMIPSFW_LOG2_PAGE_SIZE_64K + RGXMIPSFW_LOG2_PTE_ENTRY_SIZE)
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/* Maximum number of page table pages (both Host and MIPS pages) */
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#define RGXMIPSFW_MAX_NUM_PAGETABLE_PAGES (4)
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/* Total number of TLB entries */
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#define RGXMIPSFW_NUMBER_OF_TLB_ENTRIES (16)
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/* "Uncached" caching policy */
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#define RGXMIPSFW_UNCACHED_CACHE_POLICY (0X00000002)
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/* "Write-back write-allocate" caching policy */
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#define RGXMIPSFW_WRITEBACK_CACHE_POLICY (0X00000003)
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/* "Write-through no write-allocate" caching policy */
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#define RGXMIPSFW_WRITETHROUGH_CACHE_POLICY (0X00000001)
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/* Cached policy used by MIPS in case of physical bus on 32 bit */
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#define RGXMIPSFW_CACHED_POLICY (RGXMIPSFW_WRITEBACK_CACHE_POLICY)
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/* Cached policy used by MIPS in case of physical bus on more than 32 bit */
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#define RGXMIPSFW_CACHED_POLICY_ABOVE_32BIT (RGXMIPSFW_WRITETHROUGH_CACHE_POLICY)
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/* Total number of Remap entries */
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#define RGXMIPSFW_NUMBER_OF_REMAP_ENTRIES (2 * RGXMIPSFW_NUMBER_OF_TLB_ENTRIES)
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/*
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* MIPS EntryLo/PTE format
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*/
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#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_SHIFT (31U)
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#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_CLRMSK (0X7FFFFFFF)
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#define RGXMIPSFW_ENTRYLO_READ_INHIBIT_EN (0X80000000)
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#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_SHIFT (30U)
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#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_CLRMSK (0XBFFFFFFF)
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#define RGXMIPSFW_ENTRYLO_EXEC_INHIBIT_EN (0X40000000)
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/* Page Frame Number */
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#define RGXMIPSFW_ENTRYLO_PFN_SHIFT (6)
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#define RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT (12)
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/* Mask used for the MIPS Page Table in case of physical bus on 32 bit */
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#define RGXMIPSFW_ENTRYLO_PFN_MASK (0x03FFFFC0)
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#define RGXMIPSFW_ENTRYLO_PFN_SIZE (20)
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/* Mask used for the MIPS Page Table in case of physical bus on more than 32 bit */
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#define RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT (0x3FFFFFC0)
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#define RGXMIPSFW_ENTRYLO_PFN_SIZE_ABOVE_32BIT (24)
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#define RGXMIPSFW_ADDR_TO_ENTRYLO_PFN_RSHIFT (RGXMIPSFW_ENTRYLO_PFN_ALIGNSHIFT - \
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RGXMIPSFW_ENTRYLO_PFN_SHIFT)
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#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT (3U)
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#define RGXMIPSFW_ENTRYLO_CACHE_POLICY_CLRMSK (0XFFFFFFC7)
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#define RGXMIPSFW_ENTRYLO_DIRTY_SHIFT (2U)
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#define RGXMIPSFW_ENTRYLO_DIRTY_CLRMSK (0XFFFFFFFB)
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#define RGXMIPSFW_ENTRYLO_DIRTY_EN (0X00000004)
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#define RGXMIPSFW_ENTRYLO_VALID_SHIFT (1U)
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#define RGXMIPSFW_ENTRYLO_VALID_CLRMSK (0XFFFFFFFD)
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#define RGXMIPSFW_ENTRYLO_VALID_EN (0X00000002)
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#define RGXMIPSFW_ENTRYLO_GLOBAL_SHIFT (0U)
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#define RGXMIPSFW_ENTRYLO_GLOBAL_CLRMSK (0XFFFFFFFE)
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#define RGXMIPSFW_ENTRYLO_GLOBAL_EN (0X00000001)
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#define RGXMIPSFW_ENTRYLO_DVG (RGXMIPSFW_ENTRYLO_DIRTY_EN | \
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RGXMIPSFW_ENTRYLO_VALID_EN | \
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RGXMIPSFW_ENTRYLO_GLOBAL_EN)
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#define RGXMIPSFW_ENTRYLO_UNCACHED (RGXMIPSFW_UNCACHED_CACHE_POLICY << \
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RGXMIPSFW_ENTRYLO_CACHE_POLICY_SHIFT)
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#define RGXMIPSFW_ENTRYLO_DVG_UNCACHED (RGXMIPSFW_ENTRYLO_DVG | RGXMIPSFW_ENTRYLO_UNCACHED)
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/* Remap Range Config Addr Out */
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/* These defines refer to the upper half of the Remap Range Config register */
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#define RGXMIPSFW_REMAP_RANGE_ADDR_OUT_MASK (0x0FFFFFF0)
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#define RGXMIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT (4) /* wrt upper half of the register */
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#define RGXMIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT (12)
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#define RGXMIPSFW_ADDR_TO_RR_ADDR_OUT_RSHIFT (RGXMIPSFW_REMAP_RANGE_ADDR_OUT_ALIGNSHIFT - \
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RGXMIPSFW_REMAP_RANGE_ADDR_OUT_SHIFT)
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#if defined(SECURE_FW_CODE_OSID) && (SECURE_FW_CODE_OSID + 1 > 2)
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#define MIPS_FW_CODE_OSID (SECURE_FW_CODE_OSID)
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#elif defined(SECURE_FW_CODE_OSID)
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#define MIPS_FW_CODE_OSID (1U)
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#endif
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/*
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* Pages to trampoline problematic physical addresses:
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* - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN : 0x1FC0_0000
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* - RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN : 0x1FC0_1000
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* - RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN : 0x1FC0_2000
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* - (benign trampoline) : 0x1FC0_3000
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* that would otherwise be erroneously remapped by the MIPS wrapper
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* (see "Firmware virtual layout and remap configuration" section below)
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*/
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#define RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES (2)
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#define RGXMIPSFW_TRAMPOLINE_NUMPAGES (1 << RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES)
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#define RGXMIPSFW_TRAMPOLINE_SIZE (RGXMIPSFW_TRAMPOLINE_NUMPAGES << RGXMIPSFW_LOG2_PAGE_SIZE_4K)
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#define RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE (RGXMIPSFW_TRAMPOLINE_LOG2_NUMPAGES + RGXMIPSFW_LOG2_PAGE_SIZE_4K)
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#define RGXMIPSFW_TRAMPOLINE_TARGET_PHYS_ADDR (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define RGXMIPSFW_TRAMPOLINE_OFFSET(a) (a - RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN)
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#define RGXMIPSFW_SENSITIVE_ADDR(a) (RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN == (~((1<<RGXMIPSFW_TRAMPOLINE_LOG2_SEGMENT_SIZE)-1) & a))
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/*
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* Firmware virtual layout and remap configuration
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*/
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/*
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* For each remap region we define:
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* - the virtual base used by the Firmware to access code/data through that region
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* - the microAptivAP physical address correspondent to the virtual base address,
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* used as input address and remapped to the actual physical address
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* - log2 of size of the region remapped by the MIPS wrapper, i.e. number of bits from
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* the bottom of the base input address that survive onto the output address
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* (this defines both the alignment and the maximum size of the remapped region)
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* - one or more code/data segments within the remapped region
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*/
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/* Boot remap setup */
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#define RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE (0xBFC00000)
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#define RGXMIPSFW_BOOT_REMAP_PHYS_ADDR_IN (0x1FC00000)
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#define RGXMIPSFW_BOOT_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_BOOT_NMI_CODE_VIRTUAL_BASE (RGXMIPSFW_BOOT_REMAP_VIRTUAL_BASE)
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/* Data remap setup */
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#define RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE (0xBFC01000)
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#define RGXMIPSFW_DATA_CACHED_REMAP_VIRTUAL_BASE (0x9FC01000)
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#define RGXMIPSFW_DATA_REMAP_PHYS_ADDR_IN (0x1FC01000)
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#define RGXMIPSFW_DATA_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_BOOT_NMI_DATA_VIRTUAL_BASE (RGXMIPSFW_DATA_REMAP_VIRTUAL_BASE)
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/* Code remap setup */
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#define RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE (0x9FC02000)
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#define RGXMIPSFW_CODE_REMAP_PHYS_ADDR_IN (0x1FC02000)
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#define RGXMIPSFW_CODE_REMAP_LOG2_SEGMENT_SIZE (12)
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#define RGXMIPSFW_EXCEPTIONS_VIRTUAL_BASE (RGXMIPSFW_CODE_REMAP_VIRTUAL_BASE)
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/* Permanent mappings setup */
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#define RGXMIPSFW_PT_VIRTUAL_BASE (0xCF000000)
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#define RGXMIPSFW_REGISTERS_VIRTUAL_BASE (0xCF800000)
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#define RGXMIPSFW_STACK_VIRTUAL_BASE (0xCF600000)
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/*
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* Bootloader configuration data
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*/
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/* Bootloader configuration offset (where RGXMIPSFW_BOOT_DATA lives)
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* within the bootloader/NMI data page */
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#define RGXMIPSFW_BOOTLDR_CONF_OFFSET (0x0)
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/*
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* NMI shared data
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*/
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/* Base address of the shared data within the bootloader/NMI data page */
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#define RGXMIPSFW_NMI_SHARED_DATA_BASE (0x100)
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/* Size used by Debug dump data */
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#define RGXMIPSFW_NMI_SHARED_SIZE (0x2B0)
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/* Offsets in the NMI shared area in 32-bit words */
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#define RGXMIPSFW_NMI_SYNC_FLAG_OFFSET (0x0)
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#define RGXMIPSFW_NMI_STATE_OFFSET (0x1)
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#define RGXMIPSFW_NMI_ERROR_STATE_SET (0x1)
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/*
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* MIPS boot stage
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*/
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#define RGXMIPSFW_BOOT_STAGE_OFFSET (0x400)
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/*
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* MIPS private data in the bootloader data page.
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* Memory below this offset is used by the FW only, no interface data allowed.
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*/
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#define RGXMIPSFW_PRIVATE_DATA_OFFSET (0x800)
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/* The things that follow are excluded when compiling assembly sources */
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#if !defined(RGXMIPSFW_ASSEMBLY_CODE)
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#include "img_types.h"
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#include "km/rgxdefs_km.h"
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typedef struct
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{
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IMG_UINT64 ui64StackPhyAddr;
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IMG_UINT64 ui64RegBase;
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IMG_UINT64 aui64PTPhyAddr[RGXMIPSFW_MAX_NUM_PAGETABLE_PAGES];
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IMG_UINT32 ui32PTLog2PageSize;
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IMG_UINT32 ui32PTNumPages;
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IMG_UINT32 ui32Reserved1;
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IMG_UINT32 ui32Reserved2;
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} RGXMIPSFW_BOOT_DATA;
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#define RGXMIPSFW_GET_OFFSET_IN_DWORDS(offset) (offset / sizeof(IMG_UINT32))
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#define RGXMIPSFW_GET_OFFSET_IN_QWORDS(offset) (offset / sizeof(IMG_UINT64))
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/* Used for compatibility checks */
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#define RGXMIPSFW_ARCHTYPE_VER_CLRMSK (0xFFFFE3FFU)
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#define RGXMIPSFW_ARCHTYPE_VER_SHIFT (10U)
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#define RGXMIPSFW_CORE_ID_VALUE (0x001U)
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#define RGXFW_PROCESSOR_MIPS "MIPS"
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/* microAptivAP cache line size */
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#define RGXMIPSFW_MICROAPTIVEAP_CACHELINE_SIZE (16U)
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/* The SOCIF transactions are identified with the top 16 bits of the physical address emitted by the MIPS */
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#define RGXMIPSFW_WRAPPER_CONFIG_REGBANK_ADDR_ALIGN (16U)
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/* Values to put in the MIPS selectors for performance counters */
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#define RGXMIPSFW_PERF_COUNT_CTRL_ICACHE_ACCESSES_C0 (9U) /* Icache accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_ICACHE_MISSES_C1 (9U) /* Icache misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_DCACHE_ACCESSES_C0 (10U) /* Dcache accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_DCACHE_MISSES_C1 (11U) /* Dcache misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_ITLB_INSTR_ACCESSES_C0 (5U) /* ITLB instruction accesses in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_JTLB_INSTR_MISSES_C1 (7U) /* JTLB instruction accesses misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_INSTR_COMPLETED_C0 (1U) /* Instructions completed in COUNTER0 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_JTLB_DATA_MISSES_C1 (8U) /* JTLB data misses in COUNTER1 */
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#define RGXMIPSFW_PERF_COUNT_CTRL_EVENT_SHIFT (5U) /* Shift for the Event field in the MIPS perf ctrl registers */
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/* Additional flags for performance counters. See MIPS manual for further reference */
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_USER_MODE (8U)
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_KERNEL_MODE (2U)
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#define RGXMIPSFW_PERF_COUNT_CTRL_COUNT_EXL (1U)
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#define RGXMIPSFW_C0_NBHWIRQ 8
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/* Macros to decode C0_Cause register */
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#define RGXMIPSFW_C0_CAUSE_EXCCODE(CAUSE) (((CAUSE) & 0x7c) >> 2)
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#define RGXMIPSFW_C0_CAUSE_EXCCODE_FWERROR 9
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/* Use only when Coprocessor Unusable exception */
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#define RGXMIPSFW_C0_CAUSE_UNUSABLE_UNIT(CAUSE) (((CAUSE) >> 28) & 0x3)
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#define RGXMIPSFW_C0_CAUSE_PENDING_HWIRQ(CAUSE) (((CAUSE) & 0x3fc00) >> 10)
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#define RGXMIPSFW_C0_CAUSE_FDCIPENDING (1 << 21)
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#define RGXMIPSFW_C0_CAUSE_IV (1 << 23)
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#define RGXMIPSFW_C0_CAUSE_IC (1 << 25)
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#define RGXMIPSFW_C0_CAUSE_PCIPENDING (1 << 26)
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#define RGXMIPSFW_C0_CAUSE_TIPENDING (1 << 30)
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#define RGXMIPSFW_C0_CAUSE_BRANCH_DELAY (1 << 31)
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/* Macros to decode C0_Debug register */
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#define RGXMIPSFW_C0_DEBUG_EXCCODE(DEBUG) (((DEBUG) >> 10) & 0x1f)
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#define RGXMIPSFW_C0_DEBUG_DSS (1 << 0)
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#define RGXMIPSFW_C0_DEBUG_DBP (1 << 1)
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#define RGXMIPSFW_C0_DEBUG_DDBL (1 << 2)
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#define RGXMIPSFW_C0_DEBUG_DDBS (1 << 3)
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#define RGXMIPSFW_C0_DEBUG_DIB (1 << 4)
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#define RGXMIPSFW_C0_DEBUG_DINT (1 << 5)
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#define RGXMIPSFW_C0_DEBUG_DIBIMPR (1 << 6)
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#define RGXMIPSFW_C0_DEBUG_DDBLIMPR (1 << 18)
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#define RGXMIPSFW_C0_DEBUG_DDBSIMPR (1 << 19)
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#define RGXMIPSFW_C0_DEBUG_IEXI (1 << 20)
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#define RGXMIPSFW_C0_DEBUG_DBUSEP (1 << 21)
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#define RGXMIPSFW_C0_DEBUG_CACHEEP (1 << 22)
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#define RGXMIPSFW_C0_DEBUG_MCHECKP (1 << 23)
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#define RGXMIPSFW_C0_DEBUG_IBUSEP (1 << 24)
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#define RGXMIPSFW_C0_DEBUG_DM (1 << 30)
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#define RGXMIPSFW_C0_DEBUG_DBD (1 << 31)
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/* Macros to decode TLB entries */
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#define RGXMIPSFW_TLB_GET_MASK(PAGE_MASK) (((PAGE_MASK) >> 13) & 0XFFFFU)
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#define RGXMIPSFW_TLB_GET_PAGE_SIZE(PAGE_MASK) ((((PAGE_MASK) | 0x1FFF) + 1) >> 11) /* page size in KB */
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#define RGXMIPSFW_TLB_GET_PAGE_MASK(PAGE_SIZE) ((((PAGE_SIZE) << 11) - 1) & ~0x7FF) /* page size in KB */
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#define RGXMIPSFW_TLB_GET_VPN2(ENTRY_HI) ((ENTRY_HI) >> 13)
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#define RGXMIPSFW_TLB_GET_COHERENCY(ENTRY_LO) (((ENTRY_LO) >> 3) & 0x7U)
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#define RGXMIPSFW_TLB_GET_PFN(ENTRY_LO) (((ENTRY_LO) >> 6) & 0XFFFFFU)
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/* GET_PA uses a non-standard PFN mask for 36 bit addresses */
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#define RGXMIPSFW_TLB_GET_PA(ENTRY_LO) (((IMG_UINT64)(ENTRY_LO) & RGXMIPSFW_ENTRYLO_PFN_MASK_ABOVE_32BIT) << 6)
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#define RGXMIPSFW_TLB_GET_INHIBIT(ENTRY_LO) (((ENTRY_LO) >> 30) & 0x3U)
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#define RGXMIPSFW_TLB_GET_DGV(ENTRY_LO) ((ENTRY_LO) & 0x7U)
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#define RGXMIPSFW_TLB_GLOBAL (1U)
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#define RGXMIPSFW_TLB_VALID (1U << 1)
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#define RGXMIPSFW_TLB_DIRTY (1U << 2)
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#define RGXMIPSFW_TLB_XI (1U << 30)
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#define RGXMIPSFW_TLB_RI (1U << 31)
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typedef struct {
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IMG_UINT32 ui32TLBPageMask;
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IMG_UINT32 ui32TLBHi;
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IMG_UINT32 ui32TLBLo0;
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IMG_UINT32 ui32TLBLo1;
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} RGX_MIPS_TLB_ENTRY;
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typedef struct {
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IMG_UINT32 ui32RemapAddrIn; /* always 4k aligned */
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IMG_UINT32 ui32RemapAddrOut; /* always 4k aligned */
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IMG_UINT32 ui32RemapRegionSize;
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} RGX_MIPS_REMAP_ENTRY;
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typedef struct {
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IMG_UINT32 ui32ErrorState; /* This must come first in the structure */
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IMG_UINT32 ui32ErrorEPC;
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IMG_UINT32 ui32StatusRegister;
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IMG_UINT32 ui32CauseRegister;
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IMG_UINT32 ui32BadRegister;
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IMG_UINT32 ui32EPC;
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IMG_UINT32 ui32SP;
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IMG_UINT32 ui32Debug;
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IMG_UINT32 ui32DEPC;
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IMG_UINT32 ui32BadInstr;
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IMG_UINT32 ui32UnmappedAddress;
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RGX_MIPS_TLB_ENTRY asTLB[RGXMIPSFW_NUMBER_OF_TLB_ENTRIES];
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RGX_MIPS_REMAP_ENTRY asRemap[RGXMIPSFW_NUMBER_OF_REMAP_ENTRIES];
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} RGX_MIPS_STATE;
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#endif /* RGXMIPSFW_ASSEMBLY_CODE */
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#endif /* RGX_MIPS_H */
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