251 lines
9.1 KiB
C
251 lines
9.1 KiB
C
/*************************************************************************/ /*!
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@File rgx_riscv.h
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@Title
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Platform RGX
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@Description RGX RISCV definitions, kernel/user space
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(RGX_RISCV_H)
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#define RGX_RISCV_H
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#include "km/rgxdefs_km.h"
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/* Utility defines to convert regions to virtual addresses and remaps */
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#define RGXRISCVFW_GET_REGION_BASE(r) IMG_UINT32_C((r) << 28)
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#define RGXRISCVFW_GET_REGION(a) IMG_UINT32_C((a) >> 28)
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#define RGXRISCVFW_MAX_REGION_SIZE IMG_UINT32_C(1 << 28)
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#define RGXRISCVFW_GET_REMAP(r) (RGX_CR_FWCORE_ADDR_REMAP_CONFIG0 + ((r) * 8U))
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/* RISCV remap output is aligned to 4K */
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#define RGXRISCVFW_REMAP_CONFIG_DEVVADDR_ALIGN (0x1000U)
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/*
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* FW bootloader defines
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*/
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#define RGXRISCVFW_BOOTLDR_CODE_REGION IMG_UINT32_C(0xC)
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#define RGXRISCVFW_BOOTLDR_DATA_REGION IMG_UINT32_C(0x5)
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#define RGXRISCVFW_BOOTLDR_CODE_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_BOOTLDR_CODE_REGION))
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#define RGXRISCVFW_BOOTLDR_DATA_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_BOOTLDR_DATA_REGION))
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#define RGXRISCVFW_BOOTLDR_CODE_REMAP (RGXRISCVFW_GET_REMAP(RGXRISCVFW_BOOTLDR_CODE_REGION))
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#define RGXRISCVFW_BOOTLDR_DATA_REMAP (RGXRISCVFW_GET_REMAP(RGXRISCVFW_BOOTLDR_DATA_REGION))
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/* Bootloader data offset in dwords from the beginning of the FW data allocation */
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#define RGXRISCVFW_BOOTLDR_CONF_OFFSET (0x0)
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/*
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* FW coremem region defines
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*/
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#define RGXRISCVFW_COREMEM_REGION IMG_UINT32_C(0x8)
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#define RGXRISCVFW_COREMEM_MAX_SIZE IMG_UINT32_C(0x10000000) /* 256 MB */
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#define RGXRISCVFW_COREMEM_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_COREMEM_REGION))
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#define RGXRISCVFW_COREMEM_END (RGXRISCVFW_COREMEM_BASE + RGXRISCVFW_COREMEM_MAX_SIZE - 1)
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/*
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* Host-FW shared data defines
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*/
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#define RGXRISCVFW_SHARED_CACHED_DATA_REGION (0x6U)
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#define RGXRISCVFW_SHARED_UNCACHED_DATA_REGION (0xDU)
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#define RGXRISCVFW_SHARED_CACHED_DATA_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_SHARED_CACHED_DATA_REGION))
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#define RGXRISCVFW_SHARED_UNCACHED_DATA_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_SHARED_UNCACHED_DATA_REGION))
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#define RGXRISCVFW_SHARED_CACHED_DATA_REMAP (RGXRISCVFW_GET_REMAP(RGXRISCVFW_SHARED_CACHED_DATA_REGION))
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#define RGXRISCVFW_SHARED_UNCACHED_DATA_REMAP (RGXRISCVFW_GET_REMAP(RGXRISCVFW_SHARED_UNCACHED_DATA_REGION))
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/*
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* GPU SOCIF access defines
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*/
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#define RGXRISCVFW_SOCIF_REGION (0x2U)
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#define RGXRISCVFW_SOCIF_BASE (RGXRISCVFW_GET_REGION_BASE(RGXRISCVFW_SOCIF_REGION))
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/* The things that follow are excluded when compiling assembly sources */
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#if !defined(RGXRISCVFW_ASSEMBLY_CODE)
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#include "img_types.h"
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#define RGXFW_PROCESSOR_RISCV "RISCV"
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#define RGXRISCVFW_CORE_ID_VALUE (0x00450B02U)
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#define RGXRISCVFW_MISA_ADDR (0x301U)
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#define RGXRISCVFW_MISA_VALUE (0x40001104U)
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#define RGXRISCVFW_MSCRATCH_ADDR (0x340U)
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typedef struct
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{
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IMG_UINT64 ui64CorememCodeDevVAddr;
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IMG_UINT64 ui64CorememDataDevVAddr;
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IMG_UINT32 ui32CorememCodeFWAddr;
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IMG_UINT32 ui32CorememDataFWAddr;
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IMG_UINT32 ui32CorememCodeSize;
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IMG_UINT32 ui32CorememDataSize;
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IMG_UINT32 ui32Flags;
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IMG_UINT32 ui32Reserved;
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} RGXRISCVFW_BOOT_DATA;
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/*
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* List of registers to be printed in debug dump.
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* First column: register names (general purpose or control/status registers)
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* Second column: register number to be used in abstract access register command
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* (see RISC-V debug spec v0.13)
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*/
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#define RGXRISCVFW_DEBUG_DUMP_REGISTERS \
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X(pc, 0x7b1) /* dpc */ \
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X(ra, 0x1001) \
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X(sp, 0x1002) \
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X(mepc, 0x341) \
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X(mcause, 0x342) \
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X(mdseac, 0xfc0) \
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X(mstatus, 0x300) \
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X(mie, 0x304) \
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X(mip, 0x344) \
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X(mscratch, 0x340) \
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X(mbvnc0, 0xffe) \
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X(mbvnc1, 0xfff) \
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X(micect, 0x7f0) \
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X(mdcect, 0x7f3) \
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X(mdcrfct, 0x7f4) \
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typedef struct
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{
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#define X(name, address) \
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IMG_UINT32 name;
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RGXRISCVFW_DEBUG_DUMP_REGISTERS
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#undef X
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} RGXRISCVFW_STATE;
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#define RGXRISCVFW_MCAUSE_INTERRUPT (1U << 31)
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#define RGXRISCVFW_MCAUSE_TABLE \
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X(0x00000000, IMG_FALSE, "NMI pin assertion") /* Also reset value */ \
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X(0x00000001, IMG_TRUE, "Instruction access fault") \
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X(0x00000002, IMG_TRUE, "Illegal instruction") \
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X(0x00000003, IMG_TRUE, "Breakpoint") \
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X(0x00000004, IMG_TRUE, "Load address misaligned") \
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X(0x00000005, IMG_TRUE, "Load access fault") \
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X(0x00000006, IMG_TRUE, "Store/AMO address misaligned") \
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X(0x00000007, IMG_TRUE, "Store/AMO access fault") \
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X(0x0000000B, IMG_TRUE, "Environment call from M-mode (FW assert)") \
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X(0x80000007, IMG_FALSE, "Machine timer interrupt") \
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X(0x8000000B, IMG_FALSE, "Machine external interrupt") \
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X(0x8000001E, IMG_FALSE, "Machine correctable error local interrupt") \
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X(0xF0000000, IMG_TRUE, "Machine D-bus store error NMI") \
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X(0xF0000001, IMG_TRUE, "Machine D-bus non-blocking load error NMI") \
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X(0xF0000002, IMG_TRUE, "dCache unrecoverable NMI")
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/* Debug module HW defines */
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#define RGXRISCVFW_DMI_COMMAND_ACCESS_REGISTER (0U)
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#define RGXRISCVFW_DMI_COMMAND_ACCESS_MEMORY (2U)
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#define RGXRISCVFW_DMI_COMMAND_AAxSIZE_32BIT (2U << 20)
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#define RGXRISCVFW_DMI_COMMAND_WRITE (1U << 16)
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#define RGXRISCVFW_DMI_COMMAND_READ (0U << 16)
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#define RGXRISCVFW_DMI_SBCS_SBACCESS_32BIT (2U)
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/* Abstract command error codes (descriptions from RISC-V debug spec v0.13) */
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typedef enum
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{
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/* No error. */
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RISCV_ABSTRACT_CMD_NO_ERROR = 0,
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/*
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* An abstract command was executing while command, abstractcs, or abstractauto
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* was written, or when one of the data or progbuf registers was read or
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* written. This status is only written if cmderr contains 0.
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*/
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RISCV_ABSTRACT_CMD_BUSY = 1,
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/*
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* The requested command is not supported, regardless of whether
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* the hart is running or not.
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*/
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RISCV_ABSTRACT_CMD_NOT_SUPPORTED = 2,
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/*
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* An exception occurred while executing the command
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* (e.g. while executing the Program Buffer).
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*/
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RISCV_ABSTRACT_CMD_EXCEPTION = 3,
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/*
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* The abstract command couldn't execute because the hart wasn't in the required
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* state (running/halted), or unavailable.
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*/
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RISCV_ABSTRACT_CMD_HALT_RESUME = 4,
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/*
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* The abstract command failed due to a bus error
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* (e.g. alignment, access size, or timeout).
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*/
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RISCV_ABSTRACT_CMD_BUS_ERROR = 5,
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/* The command failed for another reason. */
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RISCV_ABSTRACT_CMD_OTHER_ERROR = 7
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} RGXRISCVFW_ABSTRACT_CMD_ERR;
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/* System Bus error codes (descriptions from RISC-V debug spec v0.13) */
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typedef enum
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{
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/* There was no bus error. */
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RISCV_SYSBUS_NO_ERROR = 0,
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/* There was a timeout. */
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RISCV_SYSBUS_TIMEOUT = 1,
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/* A bad address was accessed. */
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RISCV_SYSBUS_BAD_ADDRESS = 2,
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/* There was an alignment error. */
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RISCV_SYSBUS_BAD_ALIGNMENT = 3,
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/* An access of unsupported size was requested. */
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RISCV_SYSBUS_UNSUPPORTED_SIZE = 4,
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/* Other. */
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RISCV_SYSBUS_OTHER_ERROR = 7
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} RGXRISCVFW_SYSBUS_ERR;
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#endif /* RGXRISCVFW_ASSEMBLY_CODE */
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#endif /* RGX_RISCV_H */
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