399 lines
11 KiB
C
399 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/errno.h>
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#include <linux/wait.h>
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#include "mtk_vcodec_intr.h"
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#include "mtk_vcodec_util.h"
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int mtk_vcodec_wait_for_done_ctx(struct mtk_vcodec_ctx *ctx,
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int core_id, int command, unsigned int timeout_ms)
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{
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int status = 0;
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#ifndef FPGA_INTERRUPT_API_DISABLE
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wait_queue_head_t *waitqueue;
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long timeout_jiff, ret;
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if (core_id >= MTK_VDEC_HW_NUM ||
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core_id < 0) {
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mtk_v4l2_err("ctx %d, invalid core_id=%d", ctx->id, core_id);
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return -1;
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}
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waitqueue = (wait_queue_head_t *)&ctx->queue[core_id];
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timeout_jiff = msecs_to_jiffies(timeout_ms);
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ret = wait_event_interruptible_timeout(*waitqueue,
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ctx->int_cond[core_id],
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timeout_jiff);
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if (!ret) {
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status = -1; /* timeout */
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mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, core_id %d timeout time=%ums out %d %d!",
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ctx->id, ctx->type, core_id, command, timeout_ms,
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ctx->int_cond[core_id], ctx->int_type);
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} else if (-ERESTARTSYS == ret) {
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mtk_v4l2_err("[%d] cmd=%d, ctx->type=%d, core_id %d timeout interrupted by a signal %d %d",
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ctx->id, ctx->type, core_id,
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command, ctx->int_cond[core_id],
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ctx->int_type);
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status = -2;
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}
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ctx->int_cond[core_id] = 0;
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ctx->int_type = 0;
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#endif
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return status;
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}
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EXPORT_SYMBOL(mtk_vcodec_wait_for_done_ctx);
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/* Wake up context wait_queue */
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void wake_up_dec_ctx(struct mtk_vcodec_ctx *ctx, int core_id)
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{
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ctx->int_cond[core_id] = 1;
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wake_up_interruptible(&ctx->queue[core_id]);
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}
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irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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u32 cg_status = 0;
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unsigned int dec_done_status = 0;
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void __iomem *vdec_misc_addr = dev->dec_reg_base[VDEC_MISC] +
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MTK_VDEC_IRQ_CFG_REG;
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ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE);
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if (ctx == NULL)
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return IRQ_HANDLED;
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if (ctx->dec_params.svp_mode) {
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mtk_v4l2_debug(4, "svp_mode %d don't handle",
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ctx->dec_params.svp_mode);
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return IRQ_HANDLED;
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}
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/* check if HW active or not */
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cg_status = readl(dev->dec_reg_base[VDEC_SYS]);
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if ((cg_status & MTK_VDEC_HW_ACTIVE) != 0) {
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mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)",
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cg_status);
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return IRQ_HANDLED;
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}
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dec_done_status = readl(vdec_misc_addr);
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ctx->irq_status = dec_done_status;
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if ((dec_done_status & MTK_VDEC_IRQ_STATUS_DEC_SUCCESS) !=
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MTK_VDEC_IRQ_STATUS_DEC_SUCCESS)
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return IRQ_HANDLED;
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/* clear interrupt */
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writel((readl(vdec_misc_addr) | MTK_VDEC_IRQ_CFG),
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dev->dec_reg_base[VDEC_MISC] + MTK_VDEC_IRQ_CFG_REG);
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writel((readl(vdec_misc_addr) & ~MTK_VDEC_IRQ_CLR),
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dev->dec_reg_base[VDEC_MISC] + MTK_VDEC_IRQ_CFG_REG);
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wake_up_dec_ctx(ctx, MTK_VDEC_CORE);
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mtk_v4l2_debug(4,
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"%s :wake up ctx %d, dec_done_status=%x",
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__func__, ctx->id, dec_done_status);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(mtk_vcodec_dec_irq_handler);
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irqreturn_t mtk_vcodec_lat_dec_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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u32 cg_status = 0;
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unsigned int dec_done_status = 0;
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void __iomem *vdec_misc_addr = dev->dec_reg_base[VDEC_LAT_MISC] +
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MTK_VDEC_IRQ_CFG_REG;
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ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_LAT);
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if (ctx == NULL)
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return IRQ_HANDLED;
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/* check if HW active or not */
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cg_status = readl(dev->dec_reg_base[VDEC_BASE]);
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if ((cg_status & MTK_VDEC_HW_ACTIVE) != 0) {
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mtk_v4l2_err("DEC LAT ISR, VDEC active is not 0x0 (0x%08x)",
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cg_status);
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return IRQ_HANDLED;
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}
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dec_done_status = readl(vdec_misc_addr);
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ctx->irq_status = dec_done_status;
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if ((dec_done_status & MTK_VDEC_IRQ_STATUS_DEC_SUCCESS) !=
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MTK_VDEC_IRQ_STATUS_DEC_SUCCESS)
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return IRQ_HANDLED;
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/* clear interrupt */
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writel((readl(vdec_misc_addr) | MTK_VDEC_IRQ_CFG),
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dev->dec_reg_base[VDEC_LAT_MISC] + MTK_VDEC_IRQ_CFG_REG);
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writel((readl(vdec_misc_addr) & ~MTK_VDEC_IRQ_CLR),
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dev->dec_reg_base[VDEC_LAT_MISC] + MTK_VDEC_IRQ_CFG_REG);
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wake_up_dec_ctx(ctx, MTK_VDEC_LAT);
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mtk_v4l2_debug(4,
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"%s :wake up ctx %d, dec_done_status=%x",
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__func__, ctx->id, dec_done_status);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(mtk_vcodec_lat_dec_irq_handler);
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void clean_irq_status(unsigned int irq_status, void __iomem *addr)
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{
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if (irq_status & MTK_VENC_IRQ_STATUS_PAUSE)
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writel(MTK_VENC_IRQ_STATUS_PAUSE, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_SWITCH)
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writel(MTK_VENC_IRQ_STATUS_SWITCH, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_DRAM)
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writel(MTK_VENC_IRQ_STATUS_DRAM, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_SPS)
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writel(MTK_VENC_IRQ_STATUS_SPS, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_PPS)
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writel(MTK_VENC_IRQ_STATUS_PPS, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_FRM)
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writel(MTK_VENC_IRQ_STATUS_FRM, addr);
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if (irq_status & MTK_VENC_IRQ_STATUS_VPS)
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writel(MTK_VENC_IRQ_STATUS_VPS, addr);
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}
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/* Wake up context wait_queue */
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void wake_up_enc_ctx(struct mtk_vcodec_ctx *ctx, unsigned int reason)
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{
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ctx->int_cond[0] = 1;
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ctx->int_type = reason;
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wake_up_interruptible(&ctx->queue[0]);
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}
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irqreturn_t mtk_vcodec_enc_irq_handler(int irq, void *priv)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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struct mtk_vcodec_dev *dev = priv;
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struct mtk_vcodec_ctx *ctx;
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unsigned long flags;
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void __iomem *addr;
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spin_lock_irqsave(&dev->irqlock, flags);
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ctx = dev->curr_enc_ctx[0];
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spin_unlock_irqrestore(&dev->irqlock, flags);
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if (ctx == NULL)
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return IRQ_HANDLED;
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mtk_v4l2_debug(1, "id=%d", ctx->id);
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addr = dev->enc_reg_base[VENC_SYS] + MTK_VENC_IRQ_ACK_OFFSET;
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ctx->irq_status = readl(dev->enc_reg_base[VENC_SYS] +
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(MTK_VENC_IRQ_STATUS_OFFSET));
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clean_irq_status(ctx->irq_status, addr);
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wake_up_enc_ctx(ctx, MTK_INST_IRQ_RECEIVED);
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#endif
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return IRQ_HANDLED;
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}
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EXPORT_SYMBOL(mtk_vcodec_enc_irq_handler);
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int mtk_vcodec_dec_irq_setup(struct platform_device *pdev,
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struct mtk_vcodec_dev *dev)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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int i = 0;
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int ret = 0;
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for (i = 0; i < MTK_VDEC_HW_NUM; i++) {
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dev->dec_irq[i] = platform_get_irq(pdev, i);
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if (i == MTK_VDEC_CORE)
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ret = devm_request_irq(&pdev->dev, dev->dec_irq[i],
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mtk_vcodec_dec_irq_handler,
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IRQF_NO_THREAD | IRQF_SHARED | IRQF_PROBE_SHARED, pdev->name, dev);
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else if (i == MTK_VDEC_LAT)
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ret = devm_request_irq(&pdev->dev, dev->dec_irq[i],
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mtk_vcodec_lat_dec_irq_handler, 0,
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pdev->name, dev);
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if (ret) {
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mtk_v4l2_debug(1, "Failed to install dev->dec_irq[%d] %d (%d)",
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i, dev->dec_irq[i],
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ret);
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}
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disable_irq(dev->dec_irq[i]);
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL(mtk_vcodec_dec_irq_setup);
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int mtk_vcodec_enc_irq_setup(struct platform_device *pdev,
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struct mtk_vcodec_dev *dev)
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{
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#ifndef FPGA_INTERRUPT_API_DISABLE
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int ret = 0;
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dev->enc_irq = platform_get_irq(pdev, 0);
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ret = devm_request_irq(&pdev->dev, dev->enc_irq,
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mtk_vcodec_enc_irq_handler,
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0, pdev->name, dev);
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if (ret) {
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mtk_v4l2_debug(1, "Failed to install dev->enc_irq %d (%d)",
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dev->enc_irq,
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ret);
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return -1;
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}
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disable_irq(dev->enc_irq);
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#endif
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return 0;
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}
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EXPORT_SYMBOL(mtk_vcodec_enc_irq_setup);
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void mtk_vcodec_gce_timeout_dump(void *ctx)
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{
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struct mtk_vcodec_ctx *curr_ctx = ctx;
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if (IS_ERR_OR_NULL(curr_ctx)) {
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mtk_v4l2_err("invalid arguments, curr_ctx: %p", curr_ctx);
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return;
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}
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if (curr_ctx->type == MTK_INST_ENCODER)
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mtk_vcodec_enc_timeout_dump(ctx);
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else if (curr_ctx->type == MTK_INST_DECODER)
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mtk_vcodec_dec_timeout_dump(ctx);
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}
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EXPORT_SYMBOL(mtk_vcodec_gce_timeout_dump);
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void mtk_vcodec_enc_timeout_dump(void *ctx)
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{
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unsigned long value;
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int i = 0, j = 0;
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struct mtk_vcodec_ctx *curr_ctx = ctx;
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struct mtk_vcodec_dev *dev = curr_ctx->dev;
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#define REG1_COUNT 15
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#define REG2_COUNT 20
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unsigned int Reg_1[REG1_COUNT] = {
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0x0, 0x14, 0xEC, 0x1C0, 0x1168, 0x11C0,
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0x11C4, 0xF4, 0x5C, 0x60, 0x130,
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0x24, 0x114C, 0x1164, 0x0140};
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unsigned int Reg_2[REG2_COUNT] = {
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0xEC, 0x200, 0x204, 0x208,
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0x20C, 0x218, 0x21C, 0x228,
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0x22C, 0x230, 0xF4, 0x1168,
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0x11C0, 0x11C4, 0x1030, 0x240,
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0x248, 0x250, 0x130, 0x0140};
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mtk_v4l2_debug(0, "is_codec_suspending: %d",
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dev->is_codec_suspending);
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for (j = 0; j < MTK_VENC_HW_NUM; j++) {
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for (i = 0; i < REG1_COUNT; i++) {
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value = readl(dev->enc_reg_base[j] + Reg_1[i]);
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mtk_v4l2_debug(0, "[%d] 0x%x = 0x%lx",
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j, Reg_1[i], value);
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}
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}
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for (j = 0; j < MTK_VENC_HW_NUM; j++) {
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for (i = 0x0; i <= 0x220; i = i+4) {
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value = readl(dev->enc_reg_base[j] + i);
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mtk_v4l2_debug(0, "[line: %d] Core[%d] 0x%x = 0x%lx",__LINE__,
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j, i, value);
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}
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for (i = 0x1140; i <= 0x12B0; i = i+4) {
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value = readl(dev->enc_reg_base[j] + i);
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mtk_v4l2_debug(0, "[line: %d] Core[%d] 0x%x = 0x%lx",__LINE__,
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j, i, value);
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}
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}
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writel(1, dev->enc_reg_base[0] + 0xEC);
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writel(1, dev->enc_reg_base[1] + 0xEC);
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writel(0, dev->enc_reg_base[0] + 0xF4);
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writel(0, dev->enc_reg_base[1] + 0xF4);
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for (j = 0; j < MTK_VENC_HW_NUM; j++) {
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for (i = 0; i < REG2_COUNT; i++) {
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value = readl(dev->enc_reg_base[j] + Reg_2[i]);
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mtk_v4l2_debug(0, "[%d] 0x%x = 0x%lx",
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j, Reg_2[i], value);
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}
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}
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}
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void mtk_vcodec_dec_timeout_dump(void *ctx)
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{
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unsigned long value;
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int i = 0;
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struct mtk_vcodec_ctx *curr_ctx = ctx;
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struct mtk_vcodec_dev *dev = NULL;
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#define LAT_REG_COUNT 26
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#define CORE_MISC_REG_COUNT 30
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#define CORE_VLD_REG_COUNT 5
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unsigned int lat_reg[LAT_REG_COUNT] = {
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0x5120, 0x512C, 0x5090, // BITCNT, POS, picture start
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0x50E0, 0x50E4, 0x50E8,
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0x1120, 0x1124, 0x1128, 0x112C, 0x196C, // input, cycle
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0x108, 0x110, 0x114, 0x118, 0x11C, // SMI
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0x120, 0x124, 0x128, 0x12C, 0x130, 0x134, 0x138, 0x13C,
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0x854, 0x878}; // crc, wptr
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unsigned int core_misc_reg[CORE_MISC_REG_COUNT] = {
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0x3120, 0x312C, 0x3090, // BITCNT, POS, picture start
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0x30E0, 0x30E4, 0x30E8, // error
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0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C, 0x20, 0x24,
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0xC8, 0xCC, 0x178, // power
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0x108, 0x110, 0x114, 0x118, 0x11C, // SMI
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0x120, 0x124, 0x128, 0x12C, 0x130, 0x134, 0x138, 0x13C};
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unsigned int core_vld_reg[CORE_VLD_REG_COUNT] = {
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0x120, 0x124, 0x128, 0x12C, 0x96C}; // input, cycle
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if (ctx == NULL) {
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mtk_v4l2_debug(0, "can't dump vdec for NULL ctx");
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return;
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}
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dev = curr_ctx->dev;
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mtk_v4l2_debug(0, "ctx: %p, is_codec_suspending: %d",
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ctx, dev->is_codec_suspending);
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for (i = 0; i < LAT_REG_COUNT; i++) {
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value = readl(dev->dec_reg_base[VDEC_LAT_MISC] + lat_reg[i]);
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mtk_v4l2_debug(0, "[LAT][MISC] 0x%x(%d) = 0x%lx",
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lat_reg[i], ((lat_reg[i]&0x0FFF)%0x800)/4, value);
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}
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for (i = 0; i < CORE_MISC_REG_COUNT; i++) {
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value = readl(dev->dec_reg_base[VDEC_MISC] + core_misc_reg[i]);
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mtk_v4l2_debug(0, "[CORE][MISC] 0x%x(%d) = 0x%lx",
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core_misc_reg[i], (core_misc_reg[i] & 0x0FFF)/4, value);
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}
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for (i = 0; i < CORE_VLD_REG_COUNT; i++) {
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value = readl(dev->dec_reg_base[VDEC_VLD] + core_vld_reg[i]);
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mtk_v4l2_debug(0, "[CORE][VLD] 0x%x(%d) = 0x%lx",
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core_vld_reg[i], (core_vld_reg[i] % 0x800)/4, value);
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}
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}
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