134 lines
3.1 KiB
C
134 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#include <linux/clk.h>
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#include "adsp_clk.h"
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#include "adsp_platform.h"
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static uint32_t adsp_clock_count;
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DEFINE_SPINLOCK(adsp_clock_spinlock);
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struct adsp_clock_attr {
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const char *name;
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struct clk *clock;
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};
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static struct adsp_clock_attr adsp_clks[ADSP_CLK_NUM] = {
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[CLK_ADSP_INFRA] = {"clk_adsp_infra", NULL},
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[CLK_ADSP_INFRA_26M] = {"clk_adsp_infra_26m", NULL},
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[CLK_ADSP_INFRA_32K] = {"clk_adsp_infra_32k", NULL},
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[CLK_TOP_ADSP_SEL] = {"clk_top_adsp_sel", NULL},
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[CLK_TOP_CLK26M] = {"clk_adsp_clk26m", NULL},
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[CLK_TOP_ADSPPLL] = {"clk_top_adsppll_ck", NULL},
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};
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int adsp_set_top_mux(enum adsp_clk clk)
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{
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int ret = 0;
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pr_debug("%s(%x)\n", __func__, clk);
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if (clk >= ADSP_CLK_NUM || clk < 0)
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return -EINVAL;
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ret = clk_set_parent(adsp_clks[CLK_TOP_ADSP_SEL].clock,
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adsp_clks[clk].clock);
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if (IS_ERR(&ret))
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pr_err("%s() clk_set_parent(clk_top_adsp_sel-%x) fail %d\n",
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__func__, clk, ret);
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return ret;
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}
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void adsp_set_clock_freq(enum adsp_clk clk)
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{
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switch (clk) {
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case CLK_TOP_CLK26M:
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case CLK_TOP_ADSPPLL:
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adsp_set_top_mux(clk);
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break;
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default:
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break;
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}
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}
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/* clock init */
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int adsp_clk_device_probe(struct platform_device *pdev)
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{
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int ret = 0;
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size_t i;
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struct device *dev = &pdev->dev;
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for (i = 0; i < ARRAY_SIZE(adsp_clks); i++) {
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adsp_clks[i].clock = devm_clk_get(dev, adsp_clks[i].name);
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if (IS_ERR(adsp_clks[i].clock)) {
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ret = PTR_ERR(adsp_clks[i].clock);
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pr_err("%s devm_clk_get %s fail %d\n", __func__,
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adsp_clks[i].name, ret);
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}
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}
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return ret;
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}
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/* clock deinit */
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void adsp_clk_device_remove(void *dev)
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{
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pr_info("%s\n", __func__);
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}
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int adsp_enable_clock(void)
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{
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int ret = 0;
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unsigned long spin_flags;
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pr_info("%s()\n", __func__);
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spin_lock_irqsave(&adsp_clock_spinlock, spin_flags);
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if (++adsp_clock_count == 1)
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/* unable to access adsp sram before set way_en to 1 */
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adsp_way_en_ctrl(1);
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spin_unlock_irqrestore(&adsp_clock_spinlock, spin_flags);
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ret = clk_prepare_enable(adsp_clks[CLK_ADSP_INFRA_26M].clock);
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if (IS_ERR(&ret)) {
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pr_err("%s(), clk_prepare_enable %s fail, ret %d\n",
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__func__, adsp_clks[CLK_ADSP_INFRA_26M].name, ret);
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return -EINVAL;
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}
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ret = clk_prepare_enable(adsp_clks[CLK_ADSP_INFRA_32K].clock);
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if (IS_ERR(&ret)) {
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pr_err("%s(), clk_prepare_enable %s fail, ret %d\n",
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__func__, adsp_clks[CLK_ADSP_INFRA_32K].name, ret);
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return -EINVAL;
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}
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ret = clk_prepare_enable(adsp_clks[CLK_ADSP_INFRA].clock);
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if (IS_ERR(&ret)) {
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pr_err("%s(), clk_prepare_enable %s fail, ret %d\n",
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__func__, adsp_clks[CLK_ADSP_INFRA].name, ret);
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adsp_clock_count--;
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return -EINVAL;
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}
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return 0;
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}
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void adsp_disable_clock(void)
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{
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unsigned long spin_flags;
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pr_info("%s()\n", __func__);
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clk_disable_unprepare(adsp_clks[CLK_ADSP_INFRA].clock);
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clk_disable_unprepare(adsp_clks[CLK_ADSP_INFRA_32K].clock);
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clk_disable_unprepare(adsp_clks[CLK_ADSP_INFRA_26M].clock);
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spin_lock_irqsave(&adsp_clock_spinlock, spin_flags);
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if (--adsp_clock_count == 0)
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/* unable to access adsp sram before set way_en to 1 */
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adsp_way_en_ctrl(0);
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spin_unlock_irqrestore(&adsp_clock_spinlock, spin_flags);
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}
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