123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __APUSYS_MIDWARE_PLATFORM_H__
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#define __APUSYS_MIDWARE_PLATFORM_H__
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extern struct dentry *mdw_dbg_root;
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#define APUSYS_VLM_START 0x1D800000 // tcm tmp
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#define APUSYS_VLM_SIZE 0x100000
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#define APUSYS_REG_SIZE (0x100000)
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#define APUSYS_BASE (0x19000000)
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#define INFRA_BASE (0x10000000)
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#define INFRA_SIZE (0x10000)
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#define NA (-1)
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char *reg_all_mem;
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bool apusys_dump_force;
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static void *apu_top;
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static void *apu_to_infra_top;
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struct dbg_mux_sel_info {
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int offset;
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int start_bit;
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int end_bit;
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};
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struct dbg_mux_sel_info info_table[] = {
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{0x29010, 1, 1 }, //vcore_dbg_sel
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{0x29010, 4, 2 }, //vcore_dbg_sel0
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{0x29010, 7, 5 }, //vcore_dbg_sel1
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{0x20138, 2, 0 }, //conn_dbg0_sel
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{0x20138, 11, 9 }, //conn_dbg3_sel
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{0x20138, 20, 18}, //conn_dbg6_sel
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{0x01098, 15, 8 }, //edma_up_dbg_bus_sel
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{0x30a10, 10, 10}, //vpu0_apu_gals_m_ctl_sel
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{0x31a10, 10, 10}, //vpu1_apu_gals_m_ctl_sel
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};
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#define DBG_MUX_SEL_COUNT (sizeof(info_table)/sizeof(struct dbg_mux_sel_info))
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struct dbg_mux_sel_value {
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char name[128];
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int status_reg_offset;
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int dbg_sel[DBG_MUX_SEL_COUNT];
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};
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struct dbg_mux_sel_value value_table[] = {
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{"VCORE2EMI_S0_GALS_TX", 0x2901C,
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{ 0, 3, NA, NA, NA, NA, NA, NA, NA} },
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{"VCORE2EMI_S1_GALS_TX", 0x2901C,
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{ 0, 4, NA, NA, NA, NA, NA, NA, NA} },
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{"APUSYS2ACP_VCORE_GALS_TX", 0x2901C,
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{ 0, 5, NA, NA, NA, NA, NA, NA, NA} },
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{"XPU2APUSYS_VCORE_GALS_RX", 0x2901C,
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{ 0, 6, NA, NA, NA, NA, NA, NA, NA} },
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{"MNOC_MISC_1/0_DBG_BUS", 0x2901C,
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{ 0, 7, NA, 4, NA, 2, NA, NA, NA} },
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{"MNOC_MISC_3/2_DBG_BUS", 0x2901C,
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{ 0, 7, NA, 4, NA, 3, NA, NA, NA} },
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{"MNOC_MISC_4_DBG_BUS", 0x2901C,
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{ 0, 7, NA, 4, NA, 4, NA, NA, NA} },
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{"APU_UP_SYS_DBG_BUS", 0x2901C,
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{ 0, 7, NA, 4, NA, 5, 1, NA, NA} },
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{"APU_EDMA_0_DBG_BUS_0", 0x2901C,
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{ 0, 7, NA, 4, NA, 5, 2, NA, NA} },
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{"APU_EDMA_0_DBG_BUS_1", 0x2901C,
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{ 0, 7, NA, 4, NA, 5, 3, NA, NA} },
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{"CONN2VCORE_EMI_S0_GALS_RX", 0x2901C,
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{ 1, NA, 3, NA, NA, NA, NA, NA, NA} },
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{"CONN2VCORE_EMI_S1_GALS_RX", 0x2901C,
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{ 1, NA, 4, NA, NA, NA, NA, NA, NA} },
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{"APUSYS2ACP_VCORE_GALS_RX", 0x2901C,
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{ 1, NA, 5, NA, NA, NA, NA, NA, NA} },
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{"XPU2APUSYS_VCORE_GALS_TX", 0x2901C,
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{ 1, NA, 6, NA, NA, NA, NA, NA, NA} },
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};
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#define TOTAL_DBG_MUX_COUNT \
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(sizeof(value_table)/sizeof(struct dbg_mux_sel_value))
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struct reg_dump_info {
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char name[128];
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u32 base;
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u32 size;
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};
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struct reg_dump_info range_table[] = {
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{"md32_sysCtrl", 0x19001000, 0x800 },
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{"md32_sysCtrl_PMU", 0x19001800, 0x800 },
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{"md32_wdt", 0x19002000, 0x1000},
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{"apu_iommu0_r0", 0x19010000, 0x1000},
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{"apu_iommu0_r1", 0x19011000, 0x1000},
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{"apu_iommu0_r2", 0x19012000, 0x1000},
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{"apu_iommu0_r3", 0x19013000, 0x1000},
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{"apu_iommu0_r4", 0x19014000, 0x1000},
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{"apu_xpu_rsi_config", 0x1901C000, 0x1000},
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{"apu_acp_ssc_config", 0x1901F000, 0x1000},
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{"apu_conn_config", 0x19020000, 0x1000},
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{"apu_sema_stimer", 0x19022000, 0x1000},
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{"emi_config", 0x19023000, 0x1000},
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{"apb_dapc_wrapper", 0x19064000, 0x1000},
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{"infra_bcrm", 0x19065000, 0x1000},
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{"apb_debug_ctl", 0x19066000, 0x1000},
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{"noc_dapc_wrapper", 0x1906C000, 0x1000},
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{"apu_noc_bcrm", 0x1906D000, 0x1000},
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{"apu_noc_config_0", 0x1906E000, 0x2000},
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{"apu_noc_config_1", 0x19070000, 0x2000},
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{"apu_noc_config_2", 0x19072000, 0x2000},
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{"apu_noc_config_3", 0x19074000, 0x2000},
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{"apu_noc_config_4", 0x19076000, 0x2000},
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{"apu_rpc(CPC)", 0x190F0000, 0x1000},
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{"apu_rpc(DVFS)", 0x190F1000, 0x1000},
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{"apu_ao_ctrl", 0x190F2000, 0x1000},
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{"apb_dapc_ap_wrapper", 0x190F8000, 0x4000},
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{"noc_dapc_ap_wrapper", 0x190FC000, 0x4000},
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};
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#define SEGMENT_COUNT (sizeof(range_table)/sizeof(struct reg_dump_info))
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#endif
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