122 lines
3.6 KiB
C
122 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __APUSYS_MIDWARE_PLATFORM_H__
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#define __APUSYS_MIDWARE_PLATFORM_H__
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extern struct dentry *mdw_dbg_root;
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#define APUSYS_VLM_START 0x1D800000 // tcm tmp
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#define APUSYS_VLM_SIZE 0x100000
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#define APUSYS_REG_SIZE (0x100000)
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#define APUSYS_BASE (0x19000000)
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#define INFRA_BASE (0x10000000)
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#define INFRA_SIZE (0x10000)
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#define NA (-1)
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char *reg_all_mem;
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bool apusys_dump_force;
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static void *apu_top;
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static void *apu_to_infra_top;
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struct dbg_mux_sel_info {
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int offset;
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int start_bit;
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int end_bit;
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};
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struct dbg_mux_sel_info info_table[] = {
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{0x29010, 1, 1 }, //vcore_dbg_sel
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{0x29010, 4, 2 }, //vcore_dbg_sel0
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{0x29010, 7, 5 }, //vcore_dbg_sel1
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{0x20138, 2, 0 }, //conn_dbg0_sel
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{0x20138, 11, 9 }, //conn_dbg3_sel
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{0x20138, 14, 12}, //conn_dbg4_sel
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{0x20138, 17, 15}, //conn_dbg5_sel
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{0x20138, 20, 18}, //conn_dbg6_sel
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{0x20138, 23, 21}, //conn_dbg7_sel
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};
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#define DBG_MUX_SEL_COUNT (sizeof(info_table)/sizeof(struct dbg_mux_sel_info))
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struct dbg_mux_sel_value {
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char name[128];
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int status_reg_offset;
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int dbg_sel[DBG_MUX_SEL_COUNT];
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};
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struct dbg_mux_sel_value value_table[] = {
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{"VCORE2EMI_N0_GALS_TX", 0x2901C,
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{ 0, 1, NA, NA, NA, NA, NA, NA, NA} },
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{"VCORE2EMI_N1_GALS_TX", 0x2901C,
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{ 0, 2, NA, NA, NA, NA, NA, NA, NA} },
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{"DLA02CONN_M0_GALS_RX", 0x2901C,
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{ 0, 6, NA, 2, NA, 1, NA, NA, NA} },
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{"DLA02CONN_M1_GALS_RX", 0x2901C,
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{ 0, 6, NA, 2, NA, 2, NA, NA, NA} },
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{"MMU0_N0_GALS_TX", 0x2901C,
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{ 0, 6, NA, 3, NA, NA, 1, NA, NA} },
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{"MMU0_N1_GALS_TX", 0x2901C,
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{ 0, 6, NA, 3, NA, NA, 2, NA, NA} },
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{"EDMMA_NOC_0_RX", 0x2901C,
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{ 0, 6, NA, 4, NA, NA, NA, 1, NA} },
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{"MNOC_MISC_0_DBG_BUS", 0x2901C,
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{ 0, 6, NA, 5, NA, NA, NA, NA, 1} },
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{"APU_UP_SYS_DBG_BUS", 0x2901C,
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{ 0, 6, NA, 5, NA, NA, NA, NA, 4} },
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{"APUSYS_AO_DBG_PCU", 0x2901C,
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{ 1, NA, 7, NA, NA, NA, NA, NA, NA} },
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{"APUSYS_AO_DBG_RPC", 0x2901C,
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{ 1, NA, 7, NA, NA, NA, NA, NA, NA} },
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};
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#define TOTAL_DBG_MUX_COUNT \
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(sizeof(value_table)/sizeof(struct dbg_mux_sel_value))
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struct reg_dump_info {
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char name[128];
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u32 base;
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u32 size;
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};
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struct reg_dump_info range_table[] = {
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{"apusys_ao-0", 0x190f0000, 0x1000},
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{"apusys_ao-1", 0x190f1000, 0x1000},
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{"apusys_ao-2", 0x190f2000, 0x1000},
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{"apusys_ao-3", 0x190f3000, 0x1000},
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{"apusys_ao-4", 0x190f4000, 0x800},
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{"apusys_ao-5", 0x190f4800, 0x800},
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{"apusys_ao-6", 0x19029000, 0x1000},
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{"apusys_ao-8", 0x190f8000, 0x400},
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{"apusys_ao-9", 0x190fc000, 0x400},
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{"md32_apb_s-0", 0x19001000, 0x800},
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{"md32_apb_s-1", 0x19002000, 0x1000},
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{"noc_axi", 0x1d000000, 0x0},
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{"apu_con2_config", 0x19020000, 0x1000},
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{"apu_con1_config", 0x19024000, 0x1000},
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{"apu_sema_stimer", 0x19022000, 0x1000},
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{"apu_emi_config", 0x19023000, 0x1000},
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{"apu_edma0", 0x19025000, 0x1000},
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{"apu_dapc", 0x19064000, 0x1000},
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{"infra_bcrm", 0x19065000, 0x1000},
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{"infra_ao_bcrm", 0x19067000, 0x1000},
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{"noc_dapc", 0x1906c000, 0x1000},
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{"apu_noc_bcrm", 0x1906d000, 0x1000},
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{"apu_noc_config_0", 0x1906e000, 0x2000},
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{"vpu_core0_config-0", 0x19030000, 0x800},
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{"vpu_core0_config-1", 0x19030800, 0x800},
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{"vpu_core1_config-0", 0x19031000, 0x800},
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{"vpu_core1_config-1", 0x19031800, 0x800},
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{"mdla0_apb-0", 0x19034000, 0x1000},
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{"mdla0_apb-1", 0x19035000, 0x800},
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{"mdla0_apb-2", 0x19035800, 0x800},
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{"mdla0_apb-3", 0x19036000, 0x2000},
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{"apu_iommu0_r0", 0x19010000, 0x1000},
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{"apu_n0_ssc_config", 0x1901e000, 0x1000},
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};
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#define SEGMENT_COUNT (sizeof(range_table)/sizeof(struct reg_dump_info))
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#endif
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