209 lines
5.7 KiB
C
209 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __APUSYS_MNOC_HW_H__
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#define __APUSYS_MNOC_HW_H__
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/*
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* BIT Operation
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*/
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#undef BIT
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#define BIT(_bit_) (unsigned int)(1 << (_bit_))
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#define BITS(_bits_, _val_) ((((unsigned int) -1 >> (31 - ((1) ? _bits_))) \
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& ~((1U << ((0) ? _bits_)) - 1)) & ((_val_)<<((0) ? _bits_)))
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#define BITMASK(_bits_) (((unsigned int) -1 >> (31 - ((1) ? _bits_))) \
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& ~((1U << ((0) ? _bits_)) - 1))
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#define GET_BITS_VAL(_bits_, _val_) (((_val_) & \
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(BITMASK(_bits_))) >> ((0) ? _bits_))
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/**
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* Read/Write a field of a register.
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* @addr: Address of the register
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* @range: The field bit range in the form of MSB:LSB
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* @val: The value to be written to the field
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*/
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//#define mnoc_read(addr) ioread32((void*) (uintptr_t) addr)
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#define mnoc_read(addr) __raw_readl((void __iomem *) (uintptr_t) (addr))
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#define mnoc_write(addr, val) \
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__raw_writel(val, (void __iomem *) (uintptr_t) addr)
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#define mnoc_read_field(addr, range) GET_BITS_VAL(range, mnoc_read(addr))
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#define mnoc_write_field(addr, range, val) mnoc_write(addr, (mnoc_read(addr) \
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& ~(BITMASK(range))) | BITS(range, val))
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#define mnoc_set_bit(addr, set) mnoc_write(addr, (mnoc_read(addr) | (set)))
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#define mnoc_clr_bit(addr, clr) mnoc_write(addr, (mnoc_read(addr) & ~(clr)))
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enum apu_qos_mni {
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MNI_VPU0,
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MNI_VPU1,
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MNI_VPU2,
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MNI_MDLA0_0,
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MNI_MDLA0_1,
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MNI_MDLA1_0,
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MNI_MDLA1_1,
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MNI_EDMA0,
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MNI_EDMA1,
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MNI_MD32,
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NR_APU_QOS_MNI
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};
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enum apu_qos_engine {
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APU_QOS_ENGINE_VPU0,
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APU_QOS_ENGINE_VPU1,
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APU_QOS_ENGINE_VPU2,
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APU_QOS_ENGINE_MDLA0,
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APU_QOS_ENGINE_MDLA1,
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APU_QOS_ENGINE_EDMA0,
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APU_QOS_ENGINE_EDMA1,
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APU_QOS_ENGINE_MD32,
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NR_APU_QOS_ENGINE
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};
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enum mni_int_sta {
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MNOC_INT_MNI_QOS_IRQ_FLAG,
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MNOC_INT_ADDR_DEC_ERR_FLAG,
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MNOC_INT_MST_PARITY_ERR_FLAG,
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MNOC_INT_MST_MISRO_ERR_FLAG,
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MNOC_INT_MST_CRDT_ERR_FLAG,
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NR_MNI_INT_STA
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};
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enum sni_int_sta {
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MNOC_INT_SLV_PARITY_ERR_FLA,
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MNOC_INT_SLV_MISRO_ERR_FLAG,
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MNOC_INT_SLV_CRDT_ERR_FLAG,
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NR_SNI_INT_STA
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};
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enum rt_int_sta {
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MNOC_INT_REQRT_MISRO_ERR_FLAG,
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MNOC_INT_RSPRT_MISRO_ERR_FLAG,
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MNOC_INT_REQRT_TO_ERR_FLAG,
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MNOC_INT_RSPRT_TO_ERR_FLAG,
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MNOC_INT_REQRT_CBUF_ERR_FLAG,
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MNOC_INT_RSPRT_CBUF_ERR_FLAG,
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MNOC_INT_REQRT_CRDT_ERR_FLAG,
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MNOC_INT_RSPRT_CRDT_ERR_FLAG,
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NR_RT_INT_STA
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};
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#define NR_APU_ENGINE_VPU (3)
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#define NR_APU_ENGINE_MDLA (2)
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#define NR_APU_ENGINE_EDMA (2)
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#define NR_MNOC_RT (5)
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#define NR_GROUP (1)
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#define NR_MNOC_MNI (16)
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#define NR_MNOC_SNI (16)
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#define NR_MNOC_PMU_CNTR (16)
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/* 0x1906E000 */
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#define APU_NOC_TOP_BASEADDR mnoc_base
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/* 0x19001000 */
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#define MNOC_INT_BASEADDR mnoc_int_base
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/* 0x19020000 */
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#define MNOC_APU_CONN_BASEADDR mnoc_apu_conn_base
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/* 0x10001000 */
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#define MNOC_SLP_PROT_BASEADDR1 mnoc_slp_prot_base1
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/* 0x10215000 */
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#define MNOC_SLP_PROT_BASEADDR2 mnoc_slp_prot_base2
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/* MNoC register definition */
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#define APUSYS_INT_EN (MNOC_INT_BASEADDR + 0x80)
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#define APUSYS_INT_STA (MNOC_INT_BASEADDR + 0x34)
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#define MNOC_INT_MAP (0x3)
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#define APU_TCM_HASH_TRUNCATE_CTRL0 (MNOC_APU_CONN_BASEADDR + 0x7C)
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/* #define APU_NOC_TOP_BASEADDR (0x1906E000) */
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#define APU_NOC_TOP_ADDR (0x1906E000)
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#define APU_NOC_TOP_RANGE (0x2000)
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#define APU_NOC_PMU_ADDR (0x1906E200)
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#define APU_NOC_PMU_RANGE (0x48C)
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#define MNI_QOS_CTRL_BASE (APU_NOC_TOP_BASEADDR + 0x1000)
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#define MNI_QOS_INFO_BASE (APU_NOC_TOP_BASEADDR + 0x1800)
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#define MNI_QOS_REG(base, reg_num, mni_offset) \
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(base + reg_num*16*4 + mni_offset*4)
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#define REQ_RT_PMU_BASE (APU_NOC_TOP_BASEADDR + 0x500)
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#define RSP_RT_PMU_BASE (APU_NOC_TOP_BASEADDR + 0x600)
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#define MNOC_RT_PMU_REG(base, reg_num, rt_num) (base + reg_num*5*4 + rt_num*4)
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#define MISC_CTRL (0x0)
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#define SLV_QOS_CTRL1 (0x14)
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#define MNI_QOS_IRQ_FLAG (0x18)
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#define ADDR_DEC_ERR_FLAG (0x30)
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#define MST_PARITY_ERR_FLAG (0x38)
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#define SLV_PARITY_ERR_FLA (0x3C)
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#define MST_MISRO_ERR_FLAG (0x40)
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#define SLV_MISRO_ERR_FLAG (0x44)
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#define REQRT_MISRO_ERR_FLAG (0x48)
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#define RSPRT_MISRO_ERR_FLAG (0x4C)
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#define REQRT_TO_ERR_FLAG (0x50)
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#define RSPRT_TO_ERR_FLAG (0x54)
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#define REQRT_CBUF_ERR_FLAG (0x188)
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#define RSPRT_CBUF_ERR_FLAG (0x18C)
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#define MST_CRDT_ERR_FLAG (0x190)
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#define SLV_CRDT_ERR_FLAG (0x194)
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#define REQRT_CRDT_ERR_FLAG (0x198)
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#define RSPRT_CRDT_ERR_FLAG (0x19C)
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#define MNOC_REG(offset) (APU_NOC_TOP_BASEADDR + offset)
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#define PMU_COUNTER0_OUT (APU_NOC_TOP_BASEADDR + 0x240)
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#define QG_LT_THL_PRE_ULTRA (0x1FFF)
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#define QG_LT_THH_PRE_ULTRA (0x1FFF)
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/* to deal with dual IOMMU tfrp addr hash aware problem */
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#define NR_IOMMU (2)
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#define APU_TFRP_ALIGN (0x1000)
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#define INFRA_AO_BASE (0x10001000)
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#define INFRA_AO_REG_SIZE (0x2000)
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#define EMI_HASH_RULE_OFFSET (0x1050)
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#define F_VAL(val, msb, lsb) (((val)&((1<<(msb-lsb+1))-1))<<lsb)
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#define F_MSK(msb, lsb) F_VAL(0xffffffff, msb, lsb)
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/* F_RP_PA_REG_BIT32 = 0x7 */
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#define F_RP_PA_REG_BIT32 F_MSK(2, 0)
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struct int_sta_info {
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uint32_t reg_val;
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uint64_t timestamp;
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};
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struct mnoc_int_dump {
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uint32_t count;
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struct int_sta_info apusys_int_sta;
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struct int_sta_info mni_int_sta[NR_MNI_INT_STA];
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struct int_sta_info sni_int_sta[NR_SNI_INT_STA];
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struct int_sta_info rt_int_sta[NR_RT_INT_STA];
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struct int_sta_info sw_irq_sta;
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};
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int mnoc_check_int_status(void);
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int apusys_dev_to_core_id(int dev_type, int dev_core);
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void mnoc_get_pmu_counter(unsigned int *buf);
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void mnoc_tcm_hash_set(unsigned int sel, unsigned int en0, unsigned int en1);
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void mnoc_hw_reinit(void);
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void mnoc_clear_pmu_counter(unsigned int grp);
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bool mnoc_pmu_reg_in_range(unsigned int addr);
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void mnoc_int_endis(bool endis);
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void infra2apu_sram_en(void);
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void infra2apu_sram_dis(void);
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void apu2infra_bus_protect_en(void);
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void apu2infra_bus_protect_dis(void);
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void print_int_sta(struct seq_file *m);
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void mnoc_hw_init(void);
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void mnoc_hw_exit(void);
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int mnoc_alloc_iommu_tfrp(void);
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#endif
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