236 lines
5.8 KiB
C
236 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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*/
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#ifndef __VPU_CFG_H__
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#define __VPU_CFG_H__
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#include <linux/types.h>
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struct vpu_device;
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static inline
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void vpu_emi_mpu_set(unsigned long start, unsigned int size)
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{
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}
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bool vpu_is_disabled(struct vpu_device *vd);
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/* 20180703, 00:00: vpu log mechanism */
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#define HOST_VERSION (0x18070300)
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/* iommu */
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#if (defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) && \
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(CONFIG_MTK_IOMMU_PGTABLE_EXT > 32))
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#define VPU_IOVA_BANK (0x300000000ULL)
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#else
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#define VPU_IOVA_BANK (0x0ULL)
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#endif
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#define VPU_IOVA_START (0x7DA00000)
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#define VPU_IOVA_END (0x82600000)
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/* Firmware Binary */
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#define VPU_MAX_NUM_CODE_SEGMENTS (50)
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#define VPU_MAX_NUM_ALGOS (50)
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#define VPU_SIZE_BINARY_CODE (0x02A10000)
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#define VPU_NUMS_IMAGE_HEADER (3)
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#define VPU_OFFSET_ALGO_AREA (0x00C00000)
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#define VPU_OFFSET_MAIN_PROGRAM_IMEM (VPU_SIZE_BINARY_CODE - 0xC0000)
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#define VPU_OFFSET_IMAGE_HEADERS (VPU_SIZE_BINARY_CODE - 0x30000)
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/* Command */
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#define VPU_CMD_SIZE (0x2000)
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/* Time Constrains */
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#define VPU_CMD_TIMEOUT (9000)
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#define VPU_PWR_OFF_LATENCY (3000)
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#define WAIT_CMD_LATENCY_US (2000)
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#define WAIT_CMD_RETRY (5)
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#define WAIT_XOS_LATENCY_US (500)
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#define WAIT_XOS_RETRY (10)
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/* Remote Proc */
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#define VPU_REMOTE_PROC (0)
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/* Image Layout */
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#define VPU_IMG_LEGACY (0)
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#define VPU_IMG_PRELOAD (1)
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/* efuse register related define */
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#define EFUSE_VPU_OFFSET 5
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#define EFUSE_VPU_MASK 0x7
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#define EFUSE_VPU_SHIFT 16
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#define EFUSE_SEG_OFFSET 30
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/* mpu protect region definition */
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#define MPU_PROCT_REGION 21
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#define MPU_PROCT_D0_AP 0
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#define MPU_PROCT_D5_APUSYS 5
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/* VPU XOS */
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#define VPU_XOS (1) /* XOS: 1, non-XOS: 0 */
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#define XOS_TIMEOUT_US (1000000)
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#if VPU_XOS
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#define VPU_MAX_PRIORITY (3)
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#else
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#define VPU_MAX_PRIORITY (1)
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#endif
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/* Work Buffer */
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#define VPU_LOG_OFFSET (0)
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#define VPU_LOG_HEADER_SIZE (0x10)
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/* Dump: Sizes */
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#define VPU_DMP_RESET_SZ 0x400U
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#define VPU_DMP_MAIN_SZ 0x40000U // 256 KB
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#define VPU_DMP_KERNEL_SZ 0x20000U // 128 KB
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#define VPU_DMP_PRELOAD_SZ 0x20000U // 128 KB
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#define VPU_DMP_IRAM_SZ 0x10000U // 64 KB
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#define VPU_DMP_WORK_SZ 0x2000U // 8 KB
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#define VPU_DMP_REG_SZ 0x1000U // 4 KB
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#define VPU_DMP_IMEM_SZ 0x30000U // 192 KB
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#define VPU_DMP_DMEM_SZ 0x40000U // 256 KB
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/* Dump: Registers */
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#define VPU_DMP_REG_CNT_INFO 32
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#define VPU_DMP_REG_CNT_DBG 8
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#define VPU_DMP_REG_CNT_MBOX 32
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/* Dump: Information String Size */
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#define VPU_DMP_INFO_SZ 128
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/* Tags: Count of Tags */
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#define VPU_TAGS_CNT (3000)
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/* Register Defines */
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#define MBOX_INBOX_0 0x000
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#define MBOX_INBOX_1 0x004
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#define MBOX_INBOX_2 0x008
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#define MBOX_INBOX_3 0x00C
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#define MBOX_INBOX_4 0x010
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#define MBOX_INBOX_5 0x014
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#define MBOX_INBOX_6 0x018
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#define MBOX_INBOX_7 0x01C
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#define MBOX_INBOX_8 0x020
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#define MBOX_INBOX_9 0x024
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#define MBOX_INBOX_10 0x028
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#define MBOX_INBOX_11 0x02C
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#define MBOX_INBOX_12 0x030
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#define MBOX_INBOX_13 0x034
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#define MBOX_INBOX_14 0x038
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#define MBOX_INBOX_15 0x03C
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#define MBOX_INBOX_16 0x040
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#define MBOX_INBOX_17 0x044
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#define MBOX_INBOX_18 0x048
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#define MBOX_INBOX_19 0x04C
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#define MBOX_INBOX_20 0x050
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#define MBOX_INBOX_21 0x054
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#define MBOX_INBOX_22 0x058
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#define MBOX_INBOX_23 0x05C
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#define MBOX_INBOX_24 0x060
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#define MBOX_INBOX_25 0x064
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#define MBOX_INBOX_26 0x068
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#define MBOX_INBOX_27 0x06C
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#define MBOX_INBOX_28 0x070
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#define MBOX_INBOX_29 0x074
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#define MBOX_INBOX_30 0x078
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#define MBOX_INBOX_31 0x07C
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#define MBOX_DUMMY_0 0x080
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#define MBOX_DUMMY_1 0x084
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#define MBOX_DUMMY_2 0x088
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#define MBOX_DUMMY_3 0x08C
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#define MBOX_DUMMY_4 0x090
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#define MBOX_DUMMY_5 0x094
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#define MBOX_DUMMY_6 0x098
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#define MBOX_DUMMY_7 0x09C
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#define MBOX_INBOX_IRQ 0x0A0
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#define MBOX_INBOX_MASK 0x0A4
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#define MBOX_INBOX_PRI_MASK 0x0A8
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#define CG_CON 0x100
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#define CG_CLR 0x108
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#define SW_RST 0x10C
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#define DONE_ST 0x90C
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#define CTRL 0x910
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#define XTENSA_INT 0x200
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#define CTL_XTENSA_INT 0x204
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#define DEFAULT0 0x93C
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#define DEFAULT1 0x940
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#define DEFAULT2 0x944
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#define XTENSA_INFO00 0x250
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#define XTENSA_INFO01 0x254
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#define XTENSA_INFO02 0x258
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#define XTENSA_INFO03 0x25C
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#define XTENSA_INFO04 0x260
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#define XTENSA_INFO05 0x264
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#define XTENSA_INFO06 0x268
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#define XTENSA_INFO07 0x26C
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#define XTENSA_INFO08 0x270
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#define XTENSA_INFO09 0x274
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#define XTENSA_INFO10 0x278
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#define XTENSA_INFO11 0x27C
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#define XTENSA_INFO12 0x280
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#define XTENSA_INFO13 0x284
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#define XTENSA_INFO14 0x288
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#define XTENSA_INFO15 0x28C
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#define XTENSA_INFO16 0x290
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#define XTENSA_INFO17 0x294
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#define XTENSA_INFO18 0x298
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#define XTENSA_INFO19 0x29C
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#define XTENSA_INFO20 0x2A0
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#define XTENSA_INFO21 0x2A4
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#define XTENSA_INFO22 0x2A8
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#define XTENSA_INFO23 0x2AC
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#define XTENSA_INFO24 0x2B0
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#define XTENSA_INFO25 0x2B4
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#define XTENSA_INFO26 0x2B8
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#define XTENSA_INFO27 0x2BC
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#define XTENSA_INFO28 0x2C0
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#define XTENSA_INFO29 0x2C4
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#define XTENSA_INFO30 0x2C8
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#define XTENSA_INFO31 0x2CC
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#define DEBUG_INFO00 0x2D0
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#define DEBUG_INFO01 0x2D4
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#define DEBUG_INFO02 0x2D8
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#define DEBUG_INFO03 0x2DC
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#define DEBUG_INFO04 0x2E0
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#define DEBUG_INFO05 0x2E4
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#define DEBUG_INFO06 0x2E8
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#define DEBUG_INFO07 0x2EC
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#define XTENSA_ALTRESETVEC 0x2F8
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/* Register Config: CTRL */
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#define P_DEBUG_ENABLE (1 << 31)
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#define STATE_VECTOR_SELECT (1 << 19)
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#define PBCLK_ENABLE (1 << 26)
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#define PRID (0x1FFFE)
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#define PIF_GATED (1 << 17)
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/* Register Config: SW_RST */
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#define APU_D_RST (1 << 8)
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#define APU_B_RST (1 << 4)
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#define OCDHALTONRESET (1 << 12)
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/* Register Config: DEFAULT0 */
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#define ARUSER (0x2 << 23)
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#define AWUSER (0x2 << 18)
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#define QOS_SWAP (1 << 28)
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/* Register Config: DEFAULT1 */
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#define ARUSER_IDMA (0x2 << 0)
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#define AWUSER_IDMA (0x2 << 5)
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/* Register Config: DEFAULT2 */
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#define DBG_EN (0xf)
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/* Register Config: CG_CLR */
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#define JTAG_CG_CLR (0x2)
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/* Register Mask: DONE_ST */
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#define PWAITMODE (1 << 7)
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#endif
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