407 lines
12 KiB
C
407 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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//
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// Copyright (c) 2015 MediaTek Inc.
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#ifndef _MT_FDVT_H
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#define _MT_FDVT_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/*
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* enforce kernel log enable
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*/
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define MAX_FDVT_FRAME_REQUEST 32
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#define MAX_FDVT_REQUEST_RING_SIZE 32
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/*
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*
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*/
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#define FDVT_DEV_MAJOR_NUMBER 258
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#define FDVT_MAGIC 'N'
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#define FDVT_REG_RANGE (0x1000)
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#ifdef CONFIG_MACH_MT6781
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#define FDVT_BASE_HW 0x1C001000
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#else
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#define FDVT_BASE_HW 0x1B001000
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#endif
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#define MAX_FACE_NUM 1024
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/*This macro is for setting irq status represnted
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* by a local variable,FDVTInfo.IrqInfo.status[FDVT_IRQ_TYPE_INT_FDVT_ST]
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*/
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#define FDVT_INT_ST (1<<0)
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struct FDVT_REG_STRUCT {
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unsigned int module;
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unsigned int addr; /* register's addr */
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unsigned int val; /* register's value */
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};
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#define FDVT_REG_STRUCT struct FDVT_REG_STRUCT
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struct FDVT_REG_IO_STRUCT {
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FDVT_REG_STRUCT *pData; /* pointer to FDVT_REG_STRUCT */
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unsigned int count; /* count */
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};
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#define FDVT_REG_IO_STRUCT struct FDVT_REG_IO_STRUCT
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/*
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* interrupt clear type
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*/
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enum FDVT_IRQ_CLEAR_ENUM {
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FDVT_IRQ_CLEAR_NONE, /* non-clear wait, clear after wait */
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FDVT_IRQ_CLEAR_WAIT, /* clear wait, clear before and after wait */
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/* wait the signal and clear it, avoid the hw executime is too s hort. */
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FDVT_IRQ_WAIT_CLEAR,
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FDVT_IRQ_CLEAR_STATUS, /* clear specific status only */
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FDVT_IRQ_CLEAR_ALL /* clear all status */
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};
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#define FDVT_IRQ_CLEAR_ENUM enum FDVT_IRQ_CLEAR_ENUM
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/*
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* module's interrupt , each module should have its own isr.
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* note:
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* mapping to isr table,ISR_TABLE when using no device tree
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*/
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enum FDVT_IRQ_TYPE_ENUM {
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FDVT_IRQ_TYPE_INT_FDVT_ST, /* FDVT */
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FDVT_IRQ_TYPE_AMOUNT
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};
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#define FDVT_IRQ_TYPE_ENUM enum FDVT_IRQ_TYPE_ENUM
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struct FDVT_WAIT_IRQ_STRUCT {
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FDVT_IRQ_CLEAR_ENUM clear;
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FDVT_IRQ_TYPE_ENUM type;
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unsigned int status; /*IRQ status */
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unsigned int timeout;
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int user_key; /* user key for doing interrupt operation */
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int process_id; /* user process_id (will filled in kernel) */
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unsigned int dump_reg; /* check dump register or not */
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bool isSecure;
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};
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#define FDVT_WAIT_IRQ_STRUCT struct FDVT_WAIT_IRQ_STRUCT
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struct FDVT_CLEAR_IRQ_STRUCT {
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FDVT_IRQ_TYPE_ENUM type;
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int user_key; /* user key for doing interrupt operation */
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unsigned int status; /* Input */
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};
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#define FDVT_CLEAR_IRQ_STRUCT struct FDVT_CLEAR_IRQ_STRUCT
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struct FDVT_ROI {
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unsigned int x1;
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unsigned int y1;
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unsigned int x2;
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unsigned int y2;
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};
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struct FDVT_PADDING {
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unsigned int left;
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unsigned int right;
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unsigned int down;
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unsigned int up;
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};
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enum FDVTFORMAT {
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FMT_NA = 0,
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FMT_YUV_2P = 1,
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FMT_YVU_2P = 2,
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FMT_YUYV = 3, //1plane
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FMT_YVYU = 4, //1plane
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FMT_UYVY = 5, //1plane
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FMT_VYUY = 6, //1plane
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FMT_MONO = 7 //AIE2.0
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};
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#define FDVTFORMAT enum FDVTFORMAT
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struct FDVT_MetaDataToGCE {
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unsigned int ImgSrcY_Handler;
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unsigned int ImgSrcUV_Handler;
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unsigned int YUVConfig_Handler;
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unsigned int YUVOutBuf_Handler;
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unsigned int RSConfig_Handler;
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unsigned int RSOutBuf_Handler;
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unsigned int FDConfig_Handler;
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unsigned int FDOutBuf_Handler;
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unsigned int FD_POSE_Config_Handler;
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unsigned int FDResultBuf_MVA;
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unsigned int ImgSrc_Y_Size;
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unsigned int ImgSrc_UV_Size;
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unsigned int YUVConfigSize;
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unsigned int YUVOutBufSize;
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unsigned int RSConfigSize;
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unsigned int RSOutBufSize;
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unsigned int FDConfigSize;
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unsigned int FD_POSE_ConfigSize;
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unsigned int FDOutBufSize;
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unsigned int FDResultBufSize;
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unsigned int FDMode;
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unsigned int srcImgFmt;
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unsigned int srcImgWidth;
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unsigned int srcImgHeight;
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unsigned int maxWidth;
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unsigned int maxHeight;
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unsigned int rotateDegree;
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unsigned short featureTH;
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unsigned short SecMemType;
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unsigned int enROI;
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struct FDVT_ROI src_roi;
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unsigned int enPadding;
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struct FDVT_PADDING src_padding;
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unsigned int SRC_IMG_STRIDE;
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unsigned int pyramid_width;
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unsigned int pyramid_height;
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bool isReleased;
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};
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#define FDVT_MetaDataToGCE struct FDVT_MetaDataToGCE
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struct FDRESULT {
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unsigned short anchor_x0[MAX_FACE_NUM];
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unsigned short anchor_x1[MAX_FACE_NUM];
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unsigned short anchor_y0[MAX_FACE_NUM];
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unsigned short anchor_y1[MAX_FACE_NUM];
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unsigned short landmark_x0[MAX_FACE_NUM];
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unsigned short landmark_x1[MAX_FACE_NUM];
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unsigned short landmark_x2[MAX_FACE_NUM];
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unsigned short landmark_x3[MAX_FACE_NUM];
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unsigned short landmark_x4[MAX_FACE_NUM];
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unsigned short landmark_x5[MAX_FACE_NUM];
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unsigned short landmark_x6[MAX_FACE_NUM];
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unsigned short landmark_y0[MAX_FACE_NUM];
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unsigned short landmark_y1[MAX_FACE_NUM];
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unsigned short landmark_y2[MAX_FACE_NUM];
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unsigned short landmark_y3[MAX_FACE_NUM];
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unsigned short landmark_y4[MAX_FACE_NUM];
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unsigned short landmark_y5[MAX_FACE_NUM];
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unsigned short landmark_y6[MAX_FACE_NUM];
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signed short anchor_score[MAX_FACE_NUM];
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signed short landmark_score0[MAX_FACE_NUM];
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signed short landmark_score1[MAX_FACE_NUM];
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signed short landmark_score2[MAX_FACE_NUM];
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signed short landmark_score3[MAX_FACE_NUM];
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signed short landmark_score4[MAX_FACE_NUM];
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signed short landmark_score5[MAX_FACE_NUM];
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signed short landmark_score6[MAX_FACE_NUM];
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signed short rip_landmark_score0[MAX_FACE_NUM];
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signed short rip_landmark_score1[MAX_FACE_NUM];
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signed short rip_landmark_score2[MAX_FACE_NUM];
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signed short rip_landmark_score3[MAX_FACE_NUM];
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signed short rip_landmark_score4[MAX_FACE_NUM];
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signed short rip_landmark_score5[MAX_FACE_NUM];
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signed short rip_landmark_score6[MAX_FACE_NUM];
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signed short rop_landmark_score0[MAX_FACE_NUM];
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signed short rop_landmark_score1[MAX_FACE_NUM];
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signed short rop_landmark_score2[MAX_FACE_NUM];
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unsigned short face_result_index[MAX_FACE_NUM];
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unsigned short anchor_index[MAX_FACE_NUM];
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unsigned int fd_partial_result;
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};
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struct FD_RESULT {
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struct FDRESULT PYRAMID0_RESULT;
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struct FDRESULT PYRAMID1_RESULT;
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struct FDRESULT PYRAMID2_RESULT;
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unsigned short FD_TOTAL_NUM;
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unsigned long *FD_raw_result_0_va; // AIE2.0 for bit-true test only
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unsigned long *FD_raw_result_1_va; // AIE2.0 for bit-true test only
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unsigned long *FD_raw_result_2_va; // AIE2.0 for bit-true test only
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unsigned long *FD_raw_result_run2_0_va; // AIE2.0 for bit-true test only
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unsigned long *FD_raw_result_run2_1_va; // AIE2.0 for bit-true test only
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unsigned long *FD_raw_result_run2_2_va; // AIE2.0 for bit-true test only
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};
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struct RACERESULT {
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signed short RESULT[4][64]; // RESULT[Channel][Feature]
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};
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struct GENDERRESULT {
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signed short RESULT[2][64]; // RESULT[Channel][Feature]
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};
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struct RIPRESULT {
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signed short RESULT[7][64]; // RESULT[Channel][Feature]
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};
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struct ROPRESULT {
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signed short RESULT[3][64]; // RESULT[Channel][Feature]
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};
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struct MERGED_RACERESULT { // AIE2.0
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signed short RESULT[4]; // RESULT[Feature]
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};
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struct MERGED_GENDERRESULT { // AIE2.0
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signed short RESULT[2]; // RESULT[Feature]
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};
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struct MERGED_AGERESULT { // AIE2.0
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signed short RESULT[2]; // RESULT[Feature]
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};
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struct MERGED_IS_INDIANRESULT { // AIE2.0
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signed short RESULT[2]; // RESULT[Feature]
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};
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struct MERGED_RIPRESULT { // AIE2.0
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signed short RESULT[7]; // RESULT[Feature]
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};
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struct MERGED_ROPRESULT { // AIE2.0
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signed short RESULT[3]; // RESULT[Feature]
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};
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struct ATTRIBUTE_RESULT {
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struct GENDERRESULT GENDER_RESULT;
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struct RACERESULT RACE_RESULT;
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struct MERGED_AGERESULT MERGED_AGE_RESULT;
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struct MERGED_GENDERRESULT MERGED_GENDER_RESULT;
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struct MERGED_IS_INDIANRESULT MERGED_IS_INDIAN_RESULT;
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struct MERGED_RACERESULT MERGED_RACE_RESULT;
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unsigned long *ATTR_raw_result_0_va; // AIE2.0 for bit-true test only
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unsigned long *ATTR_raw_result_1_va; // AIE2.0 for bit-true test only
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unsigned long *ATTR_raw_result_2_va; // AIE2.0 for bit-true test only
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unsigned long *ATTR_raw_result_3_va; // AIE2.0 for bit-true test only
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};
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struct POSE_RESULT {
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struct RIPRESULT RIP_RESULT;
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struct ROPRESULT ROP_RESULT;
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struct MERGED_RIPRESULT MERGED_RIP_RESULT;
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struct MERGED_ROPRESULT MERGED_ROP_RESULT;
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};
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struct fdvt_config {
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/*fdvt_reg_t REG_STRUCT;*/
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unsigned int FDVT_RSCON_BASE_ADR;
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unsigned int FDVT_YUV2RGB;
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unsigned int FDVT_YUV2RGBCON_BASE_ADR;
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unsigned int FDVT_FD_CON_BASE_ADR;
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unsigned int FDVT_FD_POSE_CON_BASE_ADR;
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unsigned int FDVT_YUV_SRC_WD_HT;
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unsigned int FD_MODE;
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unsigned int RESULT;
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unsigned int RESULT1;
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unsigned int FDVT_IS_SECURE;
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unsigned int FDVT_RSCON_BUFSIZE;
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unsigned int FDVT_YUV2RGBCON_BUFSIZE;
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unsigned int FDVT_FD_CON_BUFSIZE;
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unsigned int FDVT_FD_POSE_CON_BUFSIZE;
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unsigned int FDVT_LOOPS_OF_FDMODE;
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unsigned int FDVT_NUMBERS_OF_PYRAMID;
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struct FD_RESULT *FDOUTPUT;
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struct ATTRIBUTE_RESULT *ATTRIBUTEOUTPUT;
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struct POSE_RESULT *POSEOUTPUT;
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FDVT_MetaDataToGCE FDVT_METADATA_TO_GCE;
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unsigned int *FDVT_IMG_Y_VA;
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unsigned int *FDVT_IMG_UV_VA;
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unsigned int FDVT_IMG_Y_FD;
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unsigned int FDVT_IMG_UV_FD;
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unsigned int FDVT_IMG_Y_OFFSET;
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unsigned int FDVT_IMG_UV_OFFSET;
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unsigned int SRC_IMG_STRIDE;
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struct FDVT_ROI src_roi;
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FDVTFORMAT SRC_IMG_FMT;
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unsigned int enROI;
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unsigned int IS_LEGACY;
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};
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#define FDVT_Config struct fdvt_config
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/*
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*
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*/
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enum FDVT_CMD_ENUM {
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FDVT_CMD_RESET, /* Reset */
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FDVT_CMD_DUMP_REG, /* Dump FDVT Register */
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FDVT_CMD_DUMP_ISR_LOG, /* Dump FDVT ISR log */
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FDVT_CMD_READ_REG, /* Read register from driver */
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FDVT_CMD_WRITE_REG, /* Write register to driver */
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FDVT_CMD_WAIT_IRQ, /* Wait IRQ */
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FDVT_CMD_CLEAR_IRQ, /* Clear IRQ */
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FDVT_CMD_ENQUE_NUM, /* FDVT Enque Number */
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FDVT_CMD_ENQUE, /* FDVT Enque */
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FDVT_CMD_ENQUE_REQ, /* FDVT Enque Request */
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FDVT_CMD_DEQUE_NUM, /* FDVT Deque Number */
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FDVT_CMD_DEQUE, /* FDVT Deque */
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FDVT_CMD_DEQUE_REQ, /* FDVT Deque Request */
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FDVT_CMD_TOTAL,
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};
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/* */
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struct FDVT_Request {
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unsigned int m_ReqNum;
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FDVT_Config *m_pFdvtConfig;
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};
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#define FDVT_Request struct FDVT_Request
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#ifdef CONFIG_COMPAT
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struct compat_FDVT_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int count; /* count */
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};
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#define compat_FDVT_REG_IO_STRUCT struct compat_FDVT_REG_IO_STRUCT
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struct compat_FDVT_Request {
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unsigned int m_ReqNum;
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compat_uptr_t m_pFdvtConfig;
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};
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#define compat_FDVT_Request struct compat_FDVT_Request
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#endif
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#define FDVT_RESET _IO(FDVT_MAGIC, FDVT_CMD_RESET)
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#define FDVT_DUMP_REG _IO(FDVT_MAGIC, FDVT_CMD_DUMP_REG)
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#define FDVT_DUMP_ISR_LOG _IO(FDVT_MAGIC, FDVT_CMD_DUMP_ISR_LOG)
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#define FDVT_READ_REGISTER \
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_IOWR(FDVT_MAGIC, FDVT_CMD_READ_REG, FDVT_REG_IO_STRUCT)
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#define FDVT_WRITE_REGISTER \
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_IOWR(FDVT_MAGIC, FDVT_CMD_WRITE_REG, FDVT_REG_IO_STRUCT)
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#define FDVT_WAIT_IRQ \
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_IOW(FDVT_MAGIC, FDVT_CMD_WAIT_IRQ, FDVT_WAIT_IRQ_STRUCT)
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#define FDVT_CLEAR_IRQ \
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_IOW(FDVT_MAGIC, FDVT_CMD_CLEAR_IRQ, FDVT_CLEAR_IRQ_STRUCT)
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#define FDVT_ENQNUE_NUM _IOW(FDVT_MAGIC, FDVT_CMD_ENQUE_NUM, int)
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#define FDVT_ENQUE _IOWR(FDVT_MAGIC, FDVT_CMD_ENQUE, FDVT_Config)
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#define FDVT_ENQUE_REQ _IOWR(FDVT_MAGIC, FDVT_CMD_ENQUE_REQ, FDVT_Request)
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#define FDVT_DEQUE_NUM _IOR(FDVT_MAGIC, FDVT_CMD_DEQUE_NUM, int)
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#define FDVT_DEQUE _IOWR(FDVT_MAGIC, FDVT_CMD_DEQUE, FDVT_Config)
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#define FDVT_DEQUE_REQ _IOWR(FDVT_MAGIC, FDVT_CMD_DEQUE_REQ, FDVT_Request)
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#ifdef CONFIG_COMPAT
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#define COMPAT_FDVT_WRITE_REGISTER \
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_IOWR(FDVT_MAGIC, FDVT_CMD_WRITE_REG, compat_FDVT_REG_IO_STRUCT)
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#define COMPAT_FDVT_READ_REGISTER \
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_IOWR(FDVT_MAGIC, FDVT_CMD_READ_REG, compat_FDVT_REG_IO_STRUCT)
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#define COMPAT_FDVT_ENQUE_REQ \
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_IOWR(FDVT_MAGIC, FDVT_CMD_ENQUE_REQ, compat_FDVT_Request)
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#define COMPAT_FDVT_DEQUE_REQ \
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_IOWR(FDVT_MAGIC, FDVT_CMD_DEQUE_REQ, compat_FDVT_Request)
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#endif
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extern int m4u_gz_sec_init(int);
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/* */
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#endif
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