246 lines
6.8 KiB
C
246 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MT_OWE_H
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#define _MT_OWE_H
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#include <linux/ioctl.h>
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#ifdef CONFIG_COMPAT
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/* 64 bit */
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#include <linux/fs.h>
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#include <linux/compat.h>
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#endif
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/* enforce kernel log enable */
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#define KERNEL_LOG /* enable debug log flag if defined */
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#define _SUPPORT_MAX_OWE_FRAME_REQUEST_ 6
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#define _SUPPORT_MAX_OWE_REQUEST_RING_SIZE_ 4
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#define SIG_ERESTARTSYS 512 /* ERESTARTSYS */
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/******************************************************************************
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*
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******************************************************************************/
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#define OWE_DEV_MAJOR_NUMBER 251
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#define OWE_MAGIC 'o'
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#define OWE_REG_RANGE (0x1000)
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#define OWE_BASE_HW 0x1502C000
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#define OWE_OCC_INT_ST (1<<1)
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#define OWE_WMFE_INT_ST (1<<2)
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#define WMFE_CTRL_SIZE 5
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struct OWE_REG_STRUCT {
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unsigned int module;
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unsigned int Addr; /* register's addr */
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unsigned int Val; /* register's value */
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};
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struct OWE_REG_IO_STRUCT {
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struct OWE_REG_STRUCT *pData; /* pointer to OWE_REG_STRUCT */
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unsigned int Count; /* count */
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};
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/* interrupt clear type */
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enum OWE_IRQ_CLEAR_ENUM {
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OWE_IRQ_CLEAR_NONE, /*non-clear wait, clear after wait */
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OWE_IRQ_CLEAR_WAIT, /*clear wait, clear before and after wait */
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OWE_IRQ_WAIT_CLEAR, /*wait the signal and clear it, avoid the hw
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*executime is too short.
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*/
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OWE_IRQ_CLEAR_STATUS, /*clear specific status only */
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OWE_IRQ_CLEAR_ALL /*clear all status */
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};
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/* module's interrupt , each module should have its own isr. */
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/* note: */
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/* mapping to isr table,ISR_TABLE when using no device tree */
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enum OWE_IRQ_TYPE_ENUM {
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OWE_IRQ_TYPE_INT_OWE_ST, /*OWE*/
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OWE_IRQ_TYPE_AMOUNT
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};
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struct OWE_WAIT_IRQ_STRUCT {
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enum OWE_IRQ_CLEAR_ENUM Clear;
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enum OWE_IRQ_TYPE_ENUM Type;
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unsigned int Status; /* IRQ Status */
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unsigned int Timeout;
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int UserKey; /* user key for interrupt operation */
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int ProcessID; /* user ProcessID (filled in kernel) */
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unsigned int bDumpReg; /* check dump register or not*/
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};
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struct OWE_CLEAR_IRQ_STRUCT {
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enum OWE_IRQ_TYPE_ENUM Type;
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int UserKey; /* user key for doing interrupt operation */
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unsigned int Status; /* Input */
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};
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enum OCC_DMA {
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OCC_DMA_REF_VEC = 0x0,
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OCC_DMA_REF_PXL = 0x1,
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OCC_DMA_MAJ_VEC = 0x2,
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OCC_DMA_MAJ_PXL = 0x3,
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OCC_DMA_WDMA = 0x4,
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OCC_DMA_NUM,
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};
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enum WMFE_DMA {
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WMFE_DMA_IMGI = 0x0,
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WMFE_DMA_DPI = 0x1,
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WMFE_DMA_TBLI = 0x2,
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WMFE_DMA_MASKI = 0x3,
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WMFE_DMA_DPO = 0x4,
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WMFE_DMA_NUM,
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};
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struct OWE_OCCConfig {
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unsigned int DPE_OCC_CTRL_0; /* 0030, 0x1502C030 */
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unsigned int DPE_OCC_CTRL_1; /* 0034, 0x1502C034 */
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unsigned int DPE_OCC_CTRL_2; /* 0038, 0x1502C038 */
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unsigned int DPE_OCC_CTRL_3; /* 003C, 0x1502C03C */
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unsigned int DPE_OCC_REF_VEC_BASE; /* 0040, 0x1502C040 */
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unsigned int DPE_OCC_REF_VEC_STRIDE; /* 0044, 0x1502C044 */
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unsigned int DPE_OCC_REF_PXL_BASE; /* 0048, 0x1502C048 */
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unsigned int DPE_OCC_REF_PXL_STRIDE; /* 004C, 0x1502C04C */
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unsigned int DPE_OCC_MAJ_VEC_BASE; /* 0050, 0x1502C050 */
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unsigned int DPE_OCC_MAJ_VEC_STRIDE; /* 0054, 0x1502C054 */
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unsigned int DPE_OCC_MAJ_PXL_BASE; /* 0058, 0x1502C058 */
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unsigned int DPE_OCC_MAJ_PXL_STRIDE; /* 005C, 0x1502C05C */
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unsigned int DPE_OCC_WDMA_BASE; /* 0060, 0x1502C060 */
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unsigned int DPE_OCC_WDMA_STRIDE; /* 0064, 0x1502C064 */
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unsigned int DPE_OCC_PQ_0; /* 0068, 0x1502C068 */
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unsigned int DPE_OCC_PQ_1; /* 006C, 0x1502C06C */
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unsigned int DPE_OCC_SPARE; /* 0070, 0x1502C070 */
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unsigned int DPE_OCC_DFT; /* 0074, 0x1502C074 */
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unsigned int eng_secured;
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unsigned int dma_sec_size[OCC_DMA_NUM];
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};
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struct OWE_WMFECtrl {
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unsigned int WMFE_CTRL;
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unsigned int WMFE_SIZE;
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unsigned int WMFE_IMGI_BASE_ADDR;
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unsigned int WMFE_IMGI_STRIDE;
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unsigned int WMFE_DPI_BASE_ADDR;
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unsigned int WMFE_DPI_STRIDE;
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unsigned int WMFE_TBLI_BASE_ADDR;
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unsigned int WMFE_TBLI_STRIDE;
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unsigned int WMFE_MASKI_BASE_ADDR;
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unsigned int WMFE_MASKI_STRIDE;
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unsigned int WMFE_DPO_BASE_ADDR;
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unsigned int WMFE_DPO_STRIDE;
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unsigned int eng_secured;
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unsigned int dma_sec_size[WMFE_DMA_NUM];
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};
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struct OWE_WMFEConfig {
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unsigned int WmfeCtrlSize;
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struct OWE_WMFECtrl WmfeCtrl[WMFE_CTRL_SIZE];
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};
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/******************************************************************************
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*
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******************************************************************************/
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enum OWE_CMD_ENUM {
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OWE_CMD_RESET, /* Reset */
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OWE_CMD_DUMP_REG, /* Dump OWE Register */
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OWE_CMD_DUMP_ISR_LOG, /* Dump OWE ISR log */
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OWE_CMD_READ_REG, /* Read register from driver */
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OWE_CMD_WRITE_REG, /* Write register to driver */
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OWE_CMD_WAIT_IRQ, /* Wait IRQ */
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OWE_CMD_CLEAR_IRQ, /* Clear IRQ */
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OWE_CMD_OCC_ENQUE_REQ, /* OCC Enque Request */
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OWE_CMD_OCC_DEQUE_REQ, /* OCC Deque Request */
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OWE_CMD_WMFE_ENQUE_REQ, /* WMFE Enque Request */
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OWE_CMD_WMFE_DEQUE_REQ, /* WMFE Deque Request */
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OWE_CMD_TOTAL,
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};
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struct OWE_OCCRequest {
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unsigned int m_ReqNum;
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struct OWE_OCCConfig *m_pOweConfig;
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};
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struct OWE_WMFERequest {
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unsigned int m_ReqNum;
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struct OWE_WMFEConfig *m_pWmfeConfig;
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};
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#ifdef CONFIG_COMPAT
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struct compat_OWE_REG_IO_STRUCT {
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compat_uptr_t pData;
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unsigned int Count; /* count */
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};
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struct compat_OWE_OCCRequest {
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unsigned int m_ReqNum;
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compat_uptr_t m_pOweConfig;
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};
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struct compat_OWE_WMFERequest {
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unsigned int m_ReqNum;
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compat_uptr_t m_pWmfeConfig;
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};
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#endif
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#define OWE_RESET _IO(OWE_MAGIC, OWE_CMD_RESET)
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#define OWE_DUMP_REG _IO(OWE_MAGIC, OWE_CMD_DUMP_REG)
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#define OWE_DUMP_ISR_LOG _IO(OWE_MAGIC, OWE_CMD_DUMP_ISR_LOG)
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#define OWE_READ_REGISTER \
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_IOWR(OWE_MAGIC, OWE_CMD_READ_REG, struct OWE_REG_IO_STRUCT)
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#define OWE_WRITE_REGISTER \
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_IOWR(OWE_MAGIC, OWE_CMD_WRITE_REG, struct OWE_REG_IO_STRUCT)
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#define OWE_WAIT_IRQ \
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_IOW(OWE_MAGIC, OWE_CMD_WAIT_IRQ, struct OWE_WAIT_IRQ_STRUCT)
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#define OWE_CLEAR_IRQ \
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_IOW(OWE_MAGIC, OWE_CMD_CLEAR_IRQ, struct OWE_CLEAR_IRQ_STRUCT)
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#define OWE_OCC_ENQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_OCC_ENQUE_REQ, struct OWE_OCCRequest)
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#define OWE_OCC_DEQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_OCC_DEQUE_REQ, struct OWE_OCCRequest)
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#define OWE_WMFE_ENQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_WMFE_ENQUE_REQ, struct OWE_WMFERequest)
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#define OWE_WMFE_DEQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_WMFE_DEQUE_REQ, struct OWE_WMFERequest)
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#ifdef CONFIG_COMPAT
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#define COMPAT_OWE_WRITE_REGISTER \
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_IOWR(OWE_MAGIC, OWE_CMD_WRITE_REG, struct compat_OWE_REG_IO_STRUCT)
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#define COMPAT_OWE_READ_REGISTER \
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_IOWR(OWE_MAGIC, OWE_CMD_READ_REG, struct compat_OWE_REG_IO_STRUCT)
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#define COMPAT_OWE_OCC_ENQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_OCC_ENQUE_REQ, struct compat_OWE_OCCRequest)
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#define COMPAT_OWE_OCC_DEQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_OCC_DEQUE_REQ, struct compat_OWE_OCCRequest)
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#define COMPAT_OWE_WMFE_ENQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_WMFE_ENQUE_REQ, struct compat_OWE_WMFERequest)
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#define COMPAT_OWE_WMFE_DEQUE_REQ \
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_IOWR(OWE_MAGIC, OWE_CMD_WMFE_DEQUE_REQ, struct compat_OWE_WMFERequest)
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#endif
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#endif
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