661 lines
24 KiB
C
661 lines
24 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 MediaTek Inc.
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*/
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#ifndef CMDQ_EVENT_COMMON
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#define CMDQ_EVENT_COMMON
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/* Define CMDQ events
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*
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* For hardware event must define in device tree.
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* For SW event assign event ID here directly.
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*
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* Note: event name must sync to cmdq_events table in cmdq_event_common.c
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*/
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enum cmdq_event {
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/* MDP start frame */
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CMDQ_EVENT_MDP_RDMA0_SOF, /* 0 */
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CMDQ_EVENT_MDP_RDMA1_SOF, /* 1 */
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CMDQ_EVENT_MDP_RSZ0_SOF, /* 2 */
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CMDQ_EVENT_MDP_RSZ1_SOF, /* 3 */
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CMDQ_EVENT_MDP_RSZ2_SOF, /* 4 */
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CMDQ_EVENT_MDP_TDSHP_SOF, /* 5 */
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CMDQ_EVENT_MDP_TDSHP0_SOF, /* 6 */
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CMDQ_EVENT_MDP_TDSHP1_SOF, /* 7 */
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CMDQ_EVENT_MDP_WDMA_SOF, /* 8 */
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CMDQ_EVENT_MDP_WROT_SOF, /* 9 */
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CMDQ_EVENT_MDP_WROT0_SOF, /* 10 */
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CMDQ_EVENT_MDP_WROT1_SOF, /* 11 */
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CMDQ_EVENT_MDP_COLOR_SOF, /* 12 */
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CMDQ_EVENT_MDP_MVW_SOF, /* 13 */
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CMDQ_EVENT_MDP_CROP_SOF, /* 14 */
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CMDQ_EVENT_MDP_AAL_SOF, /* 15 */
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/* Display start frame */
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CMDQ_EVENT_DISP_OVL0_SOF, /* 16 */
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CMDQ_EVENT_DISP_OVL1_SOF, /* 17 */
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CMDQ_EVENT_DISP_2L_OVL0_SOF, /* 18 */
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CMDQ_EVENT_DISP_2L_OVL1_SOF, /* 19 */
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CMDQ_EVENT_DISP_RDMA0_SOF, /* 20 */
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CMDQ_EVENT_DISP_RDMA1_SOF, /* 21 */
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CMDQ_EVENT_DISP_RDMA2_SOF, /* 22 */
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CMDQ_EVENT_DISP_WDMA0_SOF, /* 23 */
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CMDQ_EVENT_DISP_WDMA1_SOF, /* 24 */
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CMDQ_EVENT_DISP_COLOR_SOF, /* 25 */
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CMDQ_EVENT_DISP_COLOR0_SOF, /* 26 */
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CMDQ_EVENT_DISP_COLOR1_SOF, /* 27 */
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CMDQ_EVENT_DISP_CCORR_SOF, /* 28 */
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CMDQ_EVENT_DISP_CCORR0_SOF, /* 29 */
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CMDQ_EVENT_DISP_CCORR1_SOF, /* 30 */
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CMDQ_EVENT_DISP_AAL_SOF, /* 31 */
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CMDQ_EVENT_DISP_AAL0_SOF, /* 32 */
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CMDQ_EVENT_DISP_AAL1_SOF, /* 33 */
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CMDQ_EVENT_DISP_GAMMA_SOF, /* 34 */
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CMDQ_EVENT_DISP_GAMMA0_SOF, /* 35 */
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CMDQ_EVENT_DISP_GAMMA1_SOF, /* 36 */
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CMDQ_EVENT_DISP_DITHER_SOF, /* 37 */
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CMDQ_EVENT_DISP_DITHER0_SOF, /* 38 */
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CMDQ_EVENT_DISP_DITHER1_SOF, /* 39 */
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CMDQ_EVENT_DISP_UFOE_SOF, /* 40 */
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CMDQ_EVENT_DISP_PWM0_SOF, /* 41 */
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CMDQ_EVENT_DISP_PWM1_SOF, /* 42 */
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CMDQ_EVENT_DISP_OD_SOF, /* 43 */
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CMDQ_EVENT_DISP_DSC_SOF, /* 44 */
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CMDQ_EVENT_UFOD_RAMA0_L0_SOF, /* 45 */
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CMDQ_EVENT_UFOD_RAMA0_L1_SOF, /* 46 */
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CMDQ_EVENT_UFOD_RAMA0_L2_SOF, /* 47 */
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CMDQ_EVENT_UFOD_RAMA0_L3_SOF, /* 48 */
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CMDQ_EVENT_UFOD_RAMA1_L0_SOF, /* 49 */
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CMDQ_EVENT_UFOD_RAMA1_L1_SOF, /* 50 */
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CMDQ_EVENT_UFOD_RAMA1_L2_SOF, /* 51 */
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CMDQ_EVENT_UFOD_RAMA1_L3_SOF, /* 52 */
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/* MDP frame done */
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CMDQ_EVENT_MDP_RDMA0_EOF, /* 53 */
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CMDQ_EVENT_MDP_RDMA1_EOF, /* 54 */
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CMDQ_EVENT_MDP_RSZ0_EOF, /* 55 */
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CMDQ_EVENT_MDP_RSZ1_EOF, /* 56 */
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CMDQ_EVENT_MDP_RSZ2_EOF, /* 57 */
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CMDQ_EVENT_MDP_TDSHP_EOF, /* 58 */
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CMDQ_EVENT_MDP_TDSHP0_EOF, /* 59 */
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CMDQ_EVENT_MDP_TDSHP1_EOF, /* 60 */
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CMDQ_EVENT_MDP_WDMA_EOF, /* 61 */
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CMDQ_EVENT_MDP_WROT_WRITE_EOF, /* 62 */
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CMDQ_EVENT_MDP_WROT_READ_EOF, /* 63 */
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CMDQ_EVENT_MDP_WROT0_WRITE_EOF, /* 64 */
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CMDQ_EVENT_MDP_WROT0_READ_EOF, /* 65 */
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CMDQ_EVENT_MDP_WROT1_WRITE_EOF, /* 66 */
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CMDQ_EVENT_MDP_WROT1_READ_EOF, /* 67 */
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CMDQ_EVENT_MDP_WROT0_W_EOF, /* 68 */
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CMDQ_EVENT_MDP_WROT0_R_EOF, /* 69 */
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CMDQ_EVENT_MDP_WROT1_W_EOF, /* 70 */
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CMDQ_EVENT_MDP_WROT1_R_EOF, /* 71 */
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CMDQ_EVENT_MDP_COLOR_EOF, /* 72 */
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CMDQ_EVENT_MDP_CROP_EOF, /* 73 */
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/* Display frame done */
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CMDQ_EVENT_DISP_OVL0_EOF, /* 74 */
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CMDQ_EVENT_DISP_OVL1_EOF, /* 75 */
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CMDQ_EVENT_DISP_2L_OVL0_EOF, /* 76 */
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CMDQ_EVENT_DISP_2L_OVL1_EOF, /* 77 */
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CMDQ_EVENT_DISP_RDMA0_EOF, /* 78 */
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CMDQ_EVENT_DISP_RDMA1_EOF, /* 79 */
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CMDQ_EVENT_DISP_RDMA2_EOF, /* 80 */
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CMDQ_EVENT_DISP_WDMA0_EOF, /* 81 */
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CMDQ_EVENT_DISP_WDMA1_EOF, /* 82 */
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CMDQ_EVENT_DISP_COLOR_EOF, /* 83 */
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CMDQ_EVENT_DISP_COLOR0_EOF, /* 84 */
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CMDQ_EVENT_DISP_COLOR1_EOF, /* 85 */
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CMDQ_EVENT_DISP_CCORR_EOF, /* 86 */
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CMDQ_EVENT_DISP_CCORR0_EOF, /* 87 */
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CMDQ_EVENT_DISP_CCORR1_EOF, /* 88 */
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CMDQ_EVENT_DISP_AAL_EOF, /* 89 */
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CMDQ_EVENT_DISP_AAL0_EOF, /* 90 */
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CMDQ_EVENT_DISP_AAL1_EOF, /* 91 */
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CMDQ_EVENT_DISP_GAMMA_EOF, /* 92 */
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CMDQ_EVENT_DISP_GAMMA0_EOF, /* 93 */
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CMDQ_EVENT_DISP_GAMMA1_EOF, /* 94 */
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CMDQ_EVENT_DISP_DITHER_EOF, /* 95 */
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CMDQ_EVENT_DISP_DITHER0_EOF, /* 96 */
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CMDQ_EVENT_DISP_DITHER1_EOF, /* 97 */
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CMDQ_EVENT_DISP_UFOE_EOF, /* 98 */
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CMDQ_EVENT_DISP_OD_EOF, /* 99 */
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CMDQ_EVENT_DISP_OD_RDMA_EOF, /* 100 */
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CMDQ_EVENT_DISP_OD_WDMA_EOF, /* 101 */
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CMDQ_EVENT_DISP_DSC_EOF, /* 102 */
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CMDQ_EVENT_DISP_DSI0_EOF, /* 103 */
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CMDQ_EVENT_DISP_DSI1_EOF, /* 104 */
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CMDQ_EVENT_DISP_DPI0_EOF, /* 105 */
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CMDQ_EVENT_UFOD_RAMA0_L0_EOF, /* 106 */
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CMDQ_EVENT_UFOD_RAMA0_L1_EOF, /* 107 */
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CMDQ_EVENT_UFOD_RAMA0_L2_EOF, /* 108 */
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CMDQ_EVENT_UFOD_RAMA0_L3_EOF, /* 109 */
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CMDQ_EVENT_UFOD_RAMA1_L0_EOF, /* 110 */
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CMDQ_EVENT_UFOD_RAMA1_L1_EOF, /* 111 */
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CMDQ_EVENT_UFOD_RAMA1_L2_EOF, /* 112 */
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CMDQ_EVENT_UFOD_RAMA1_L3_EOF, /* 113 */
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CMDQ_EVENT_DISP_POSTMASK0_SOF, /* 114 */
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CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE, /* 115 */
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CMDQ_EVENT_DISP_POSTMASK0_FRAME_RST_DONE_PULSE, /* 116 */
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/* Mutex frame done */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX0_STREAM_EOF, /* 117 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX1_STREAM_EOF, /* 118 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX2_STREAM_EOF, /* 119 */
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/* DISPSYS */
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CMDQ_EVENT_MUTEX3_STREAM_EOF, /* 120 */
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/* DISPSYS, please refer to disp_hal.h */
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CMDQ_EVENT_MUTEX4_STREAM_EOF, /* 121 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX5_STREAM_EOF, /* 122 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX6_STREAM_EOF, /* 123 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX7_STREAM_EOF, /* 124 */
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/* DpFramework */
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CMDQ_EVENT_MUTEX8_STREAM_EOF, /* 125 */
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/* DpFramework via CMDQ_IOCTL_LOCK_MUTEX */
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CMDQ_EVENT_MUTEX9_STREAM_EOF, /* 126 */
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CMDQ_EVENT_MUTEX10_STREAM_EOF, /* 127 */
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CMDQ_EVENT_MUTEX11_STREAM_EOF, /* 128 */
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CMDQ_EVENT_MUTEX12_STREAM_EOF, /* 129 */
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CMDQ_EVENT_MUTEX13_STREAM_EOF, /* 130 */
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CMDQ_EVENT_MUTEX14_STREAM_EOF, /* 131 */
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CMDQ_EVENT_MUTEX15_STREAM_EOF, /* 132 */
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/* Display underrun */
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CMDQ_EVENT_DISP_RDMA0_UNDERRUN, /* 133 */
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CMDQ_EVENT_DISP_RDMA1_UNDERRUN, /* 134 */
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CMDQ_EVENT_DISP_RDMA2_UNDERRUN, /* 135 */
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CMDQ_EVENT_DISP_RDMA3_UNDERRUN, /* 136 */
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/* Display TE */
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CMDQ_EVENT_DSI_TE, /* 137 */
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CMDQ_EVENT_DSI0_TE, /* 138 */
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CMDQ_EVENT_DSI1_TE, /* 139 */
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CMDQ_EVENT_MDP_DSI0_TE_SOF, /* 140 */
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CMDQ_EVENT_MDP_DSI1_TE_SOF, /* 141 */
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CMDQ_EVENT_DISP_DSI0_SOF, /* 142 */
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CMDQ_EVENT_DISP_DSI1_SOF, /* 143 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK0, /* 144 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK1, /* 145 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK2, /* 146 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK3, /* 147 */
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CMDQ_EVENT_DSI0_TO_GCE_MMCK4, /* 148 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK0, /* 149 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK1, /* 150 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK2, /* 151 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK3, /* 152 */
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CMDQ_EVENT_DSI1_TO_GCE_MMCK4, /* 153 */
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CMDQ_EVENT_DSI0_IRQ_EVENT, /* 154 */
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CMDQ_EVENT_DSI0_DONE_EVENT, /* 155 */
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CMDQ_EVENT_DSI1_IRQ_EVENT, /* 156 */
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CMDQ_EVENT_DSI1_DONE_EVENT, /* 157 */
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/* Reset Event */
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CMDQ_EVENT_DISP_WDMA0_RST_DONE, /* 158 */
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CMDQ_EVENT_DISP_WDMA1_RST_DONE, /* 159 */
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CMDQ_EVENT_MDP_WROT0_RST_DONE, /* 160 */
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CMDQ_EVENT_MDP_WROT1_RST_DONE, /* 161 */
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CMDQ_EVENT_MDP_WDMA_RST_DONE, /* 162 */
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CMDQ_EVENT_MDP_RDMA0_RST_DONE, /* 163 */
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CMDQ_EVENT_MDP_RDMA1_RST_DONE, /* 164 */
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/* Display Mutex */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD0, /* 165 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD1, /* 166 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD2, /* 167 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD3, /* 168 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD4, /* 169 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD5, /* 170 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD6, /* 171 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD7, /* 172 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD8, /* 173 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD9, /* 174 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD10, /* 175 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD11, /* 176 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD12, /* 177 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD13, /* 178 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD14, /* 179 */
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CMDQ_EVENT_DISP_MUTEX_ALL_MODULE_UPD15, /* 180 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE0, /* 181 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE1, /* 182 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE2, /* 183 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE3, /* 184 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE4, /* 185 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE5, /* 186 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE6, /* 187 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE7, /* 188 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE8, /* 189 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE9, /* 190 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE10, /* 191 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE11, /* 192 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE12, /* 193 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE13, /* 194 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE14, /* 195 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE15, /* 196 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE16, /* 197 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE17, /* 198 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE18, /* 199 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE19, /* 200 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE20, /* 201 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE21, /* 202 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE22, /* 203 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE23, /* 204 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE24, /* 205 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE25, /* 206 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE26, /* 207 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE27, /* 208 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE28, /* 209 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE29, /* 210 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE30, /* 211 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE31, /* 212 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE32, /* 213 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE33, /* 214 */
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CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE34, /* 215 */
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/* ISP frame done */
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CMDQ_EVENT_ISP_PASS2_2_EOF, /* 216 */
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CMDQ_EVENT_ISP_PASS2_1_EOF, /* 217 */
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CMDQ_EVENT_ISP_PASS2_0_EOF, /* 218 */
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CMDQ_EVENT_ISP_PASS1_1_EOF, /* 219 */
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CMDQ_EVENT_ISP_PASS1_0_EOF, /* 220 */
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/* ISP (IMGSYS) frame done */
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CMDQ_EVENT_DIP_CQ_THREAD0_EOF, /* 221 */
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CMDQ_EVENT_DIP_CQ_THREAD1_EOF, /* 222 */
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CMDQ_EVENT_DIP_CQ_THREAD2_EOF, /* 223 */
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CMDQ_EVENT_DIP_CQ_THREAD3_EOF, /* 224 */
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CMDQ_EVENT_DIP_CQ_THREAD4_EOF, /* 225 */
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CMDQ_EVENT_DIP_CQ_THREAD5_EOF, /* 226 */
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CMDQ_EVENT_DIP_CQ_THREAD6_EOF, /* 227 */
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CMDQ_EVENT_DIP_CQ_THREAD7_EOF, /* 228 */
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CMDQ_EVENT_DIP_CQ_THREAD8_EOF, /* 229 */
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CMDQ_EVENT_DIP_CQ_THREAD9_EOF, /* 230 */
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CMDQ_EVENT_DIP_CQ_THREAD10_EOF, /* 231 */
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CMDQ_EVENT_DIP_CQ_THREAD11_EOF, /* 232 */
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CMDQ_EVENT_DIP_CQ_THREAD12_EOF, /* 233 */
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CMDQ_EVENT_DIP_CQ_THREAD13_EOF, /* 234 */
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CMDQ_EVENT_DIP_CQ_THREAD14_EOF, /* 235 */
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CMDQ_EVENT_DIP_CQ_THREAD15_EOF, /* 236 */
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CMDQ_EVENT_DIP_CQ_THREAD16_EOF, /* 237 */
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CMDQ_EVENT_DIP_CQ_THREAD17_EOF, /* 238 */
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CMDQ_EVENT_DIP_CQ_THREAD18_EOF, /* 239 */
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CMDQ_EVENT_DPE_EOF, /* 240 */
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CMDQ_EVENT_DVE_EOF, /* 241 */
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CMDQ_EVENT_WMF_EOF, /* 242 */
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CMDQ_EVENT_GEPF_EOF, /* 243 */
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CMDQ_EVENT_GEPF_TEMP_EOF, /* 244 */
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CMDQ_EVENT_GEPF_BYPASS_EOF, /* 245 */
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CMDQ_EVENT_RSC_EOF, /* 246 */
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CMDQ_EVENT_DIP_DMA_ERR_EVENT, /* 247 */
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/* ISP (IMGSYS) engine events */
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CMDQ_EVENT_ISP_SENINF_CAM1_2_3_FULL, /* 248 */
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CMDQ_EVENT_ISP_SENINF_CAM0_FULL, /* 249 */
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/* VENC frame done */
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CMDQ_EVENT_VENC_EOF, /* 250 */
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CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE, /* 251 */
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/* JPEG frame done */
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CMDQ_EVENT_JPEG_ENC_EOF, /* 252 */
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CMDQ_EVENT_JPEG_ENC_PASS2_EOF, /* 253 */
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CMDQ_EVENT_JPEG_ENC_PASS1_EOF, /* 254 */
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CMDQ_EVENT_JPEG_DEC_EOF, /* 255 */
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/* VENC engine events */
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CMDQ_EVENT_VENC_MB_DONE, /* 256 */
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CMDQ_EVENT_VENC_128BYTE_CNT_DONE, /* 257 */
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/* ISP (CAMSYS) frame done */
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CMDQ_EVENT_ISP_FRAME_DONE_A, /* 258 */
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CMDQ_EVENT_ISP_FRAME_DONE_B, /* 259 */
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CMDQ_EVENT_ISP_FRAME_DONE_C, /* 260 */
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CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE, /* 261 */
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CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE, /* 262 */
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CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE, /* 263 */
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CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE, /* 264 */
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CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE, /* 265 */
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CMDQ_EVENT_ISP_TSF_DONE, /* 266 */
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CMDQ_EVENT_ISP_RELAY_SOF, /* 267 */
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CMDQ_EVENT_IPU_RELAY_SOF, /* 268 */
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/* ISP (CAMSYS) engine events */
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CMDQ_EVENT_SENINF_0_FIFO_FULL, /* 269 */
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CMDQ_EVENT_SENINF_1_FIFO_FULL, /* 270 */
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CMDQ_EVENT_SENINF_2_FIFO_FULL, /* 271 */
|
|
CMDQ_EVENT_SENINF_3_FIFO_FULL, /* 272 */
|
|
CMDQ_EVENT_SENINF_4_FIFO_FULL, /* 273 */
|
|
CMDQ_EVENT_SENINF_5_FIFO_FULL, /* 274 */
|
|
CMDQ_EVENT_SENINF_6_FIFO_FULL, /* 275 */
|
|
CMDQ_EVENT_SENINF_7_FIFO_FULL, /* 276 */
|
|
|
|
CMDQ_EVENT_TG_OVRUN_A_INT_DLY, /* 277 */
|
|
CMDQ_EVENT_TG_OVRUN_B_INT_DLY, /* 278 */
|
|
CMDQ_EVENT_TG_OVRUN_C_INT, /* 279 */
|
|
CMDQ_EVENT_TG_GRABERR_A_INT_DLY, /* 280 */
|
|
CMDQ_EVENT_TG_GRABERR_B_INT_DLY, /* 281 */
|
|
CMDQ_EVENT_TG_GRABERR_C_INT, /* 282 */
|
|
|
|
CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY, /* 283 */
|
|
CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY, /* 284 */
|
|
CMDQ_EVENT_CQ_VR_SNAP_C_INT, /* 285 */
|
|
|
|
/* 6799 New Event */
|
|
CMDQ_EVENT_DISP_DSC1_SOF, /* 286 */
|
|
CMDQ_EVENT_DISP_DSC2_SOF, /* 287 */
|
|
CMDQ_EVENT_DISP_RSZ0_SOF, /* 288 */
|
|
CMDQ_EVENT_DISP_RSZ1_SOF, /* 289 */
|
|
CMDQ_EVENT_DISP_DSC0_EOF, /* 290 */
|
|
CMDQ_EVENT_DISP_DSC1_EOF, /* 291 */
|
|
CMDQ_EVENT_DISP_RSZ0_EOF, /* 292 */
|
|
CMDQ_EVENT_DISP_RSZ1_EOF, /* 293 */
|
|
CMDQ_EVENT_DISP_OVL0_RST_DONE, /* 294 */
|
|
CMDQ_EVENT_DISP_OVL1_RST_DONE, /* 295 */
|
|
CMDQ_EVENT_DISP_OVL0_2L_RST_DONE, /* 296 */
|
|
CMDQ_EVENT_DISP_OVL1_2L_RST_DONE, /* 297 */
|
|
CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE35, /* 298 */
|
|
CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE36, /* 299 */
|
|
CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE37, /* 300 */
|
|
CMDQ_EVENT_DISP_MUTEX_REG_UPD_FOR_MODULE38, /* 301 */
|
|
CMDQ_EVENT_WPE_A_EOF, /* 302 */
|
|
CMDQ_EVENT_EAF_EOF, /* 303 */
|
|
CMDQ_EVENT_VENC_BSDMA_FULL, /* 304 */
|
|
CMDQ_EVENT_IPU0_EOF, /* 305 */
|
|
CMDQ_EVENT_IPU1_EOF, /* 306 */
|
|
CMDQ_EVENT_IPU2_EOF, /* 307 */
|
|
CMDQ_EVENT_IPU3_EOF, /* 308 */
|
|
|
|
/* 6759 New Event */
|
|
CMDQ_EVENT_DISP_SPLIT_SOF, /* 309 */
|
|
CMDQ_EVENT_DISP_SPLIT_FRAME_DONE, /* 310 */
|
|
CMDQ_EVENT_AMD_FRAME_DONE, /* 311 */
|
|
|
|
CMDQ_EVENT_DISP_DPI0_SOF, /* 312 */
|
|
CMDQ_EVENT_DSI0_TE_INFRA, /* 313 */
|
|
|
|
/* 6739 New Event*/
|
|
CMDQ_EVENT_DISP_DBI0_SOF, /* 314 */
|
|
CMDQ_EVENT_DISP_DBI0_EOF, /* 315 */
|
|
|
|
/* 6775 New Event*/
|
|
CMDQ_EVENT_MDP_CCORR_SOF, /* 316 */
|
|
CMDQ_EVENT_MDP_CCORR_FRAME_DONE, /* 317 */
|
|
CMDQ_EVENT_MDP_AAL_FRAME_DONE, /* 318 */
|
|
CMDQ_EVENT_WPE_B_FRAME_DONE, /* 319 */
|
|
CMDQ_EVENT_MFB_DONE, /* 320 */
|
|
CMDQ_EVENT_OCC_DONE, /* 321 */
|
|
CMDQ_EVENT_IPU_DONE_1_1, /* 322 */
|
|
CMDQ_EVENT_IPU_DONE_1_2, /* 323 */
|
|
CMDQ_EVENT_IPU_DONE_1_0, /* 324 */
|
|
CMDQ_EVENT_IPU_DONE_1_3, /* 325 */
|
|
CMDQ_EVENT_IPU_DONE_2_0, /* 326 */
|
|
CMDQ_EVENT_IPU_DONE_2_1, /* 327 */
|
|
CMDQ_EVENT_IPU_DONE_2_3, /* 328 */
|
|
CMDQ_EVENT_IPU_DONE_2_2, /* 329 */
|
|
|
|
/* 6765 New Event */
|
|
CMDQ_EVENT_MDP_CCORR0_SOF, /* 330 */
|
|
CMDQ_EVENT_MDP_CCORR0_FRAME_DONE, /* 331 */
|
|
CMDQ_EVENT_IMG_DL_RELAY_SOF, /* 332 */
|
|
|
|
CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY, /* 333 */
|
|
CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY, /* 334 */
|
|
CMDQ_EVENT_DMA_R1_ERROR_C_INT, /* 335 */
|
|
|
|
CMDQ_EVENT_APU_GCE_CORE0_EVENT_0, /* 336 */
|
|
CMDQ_EVENT_APU_GCE_CORE0_EVENT_1, /* 337 */
|
|
CMDQ_EVENT_APU_GCE_CORE0_EVENT_2, /* 338 */
|
|
CMDQ_EVENT_APU_GCE_CORE0_EVENT_3, /* 339 */
|
|
CMDQ_EVENT_APU_GCE_CORE1_EVENT_0, /* 340 */
|
|
CMDQ_EVENT_APU_GCE_CORE1_EVENT_1, /* 341 */
|
|
CMDQ_EVENT_APU_GCE_CORE1_EVENT_2, /* 342 */
|
|
CMDQ_EVENT_APU_GCE_CORE1_EVENT_3, /* 343 */
|
|
|
|
CMDQ_EVENT_VDEC_EVENT_0, /* 344 */
|
|
CMDQ_EVENT_VDEC_EVENT_1, /* 345 */
|
|
CMDQ_EVENT_VDEC_EVENT_2, /* 346 */
|
|
CMDQ_EVENT_VDEC_EVENT_3, /* 347 */
|
|
CMDQ_EVENT_VDEC_EVENT_4, /* 348 */
|
|
CMDQ_EVENT_VDEC_EVENT_5, /* 349 */
|
|
CMDQ_EVENT_VDEC_EVENT_6, /* 350 */
|
|
CMDQ_EVENT_VDEC_EVENT_7, /* 351 */
|
|
CMDQ_EVENT_VDEC_EVENT_8, /* 352 */
|
|
CMDQ_EVENT_VDEC_EVENT_9, /* 353 */
|
|
CMDQ_EVENT_VDEC_EVENT_10, /* 354 */
|
|
CMDQ_EVENT_VDEC_EVENT_11, /* 355 */
|
|
CMDQ_EVENT_VDEC_EVENT_12, /* 356 */
|
|
CMDQ_EVENT_VDEC_EVENT_13, /* 357 */
|
|
CMDQ_EVENT_VDEC_EVENT_14, /* 358 */
|
|
CMDQ_EVENT_VDEC_EVENT_15, /* 359 */
|
|
|
|
CMDQ_EVENT_FDVT_DONE, /* 360 */
|
|
CMDQ_EVENT_FE_DONE, /* 361 */
|
|
CMDQ_EVENT_DVS_DONE_ASYNC_SHOT, /* 362 */
|
|
CMDQ_EVENT_DVP_DONE_ASYNC_SHOT, /* 363 */
|
|
|
|
CMDQ_EVENT_VENC_FRAME_DONE, /* 364 */
|
|
CMDQ_EVENT_VENC_PAUSE_DONE, /* 365 */
|
|
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_0, /* 366 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_1, /* 367 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_2, /* 368 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_3, /* 369 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_4, /* 370 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_5, /* 371 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_6, /* 372 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_7, /* 373 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_8, /* 374 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_9, /* 375 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_10, /* 376 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_11, /* 377 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_12, /* 378 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_13, /* 379 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_14, /* 380 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_15, /* 381 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_16, /* 382 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_17, /* 383 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_18, /* 384 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_19, /* 385 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_20, /* 386 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_21, /* 387 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_22, /* 388 */
|
|
CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_23, /* 389 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_0, /* 390 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_1, /* 391 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_2, /* 392 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_3, /* 393 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_4, /* 394 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_5, /* 395 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_6, /* 396 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_7, /* 397 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_8, /* 398 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_9, /* 399 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_10, /* 400 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_11, /* 401 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_12, /* 402 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_13, /* 403 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_14, /* 404 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_15, /* 405 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_16, /* 406 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_17, /* 407 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_18, /* 408 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_19, /* 409 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_20, /* 410 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_21, /* 411 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_22, /* 412 */
|
|
CMDQ_EVENT_IMG2_EVENT_TX_FRAME_DONE_23, /* 413 */
|
|
CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_0, /* 414 */
|
|
CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_1, /* 415 */
|
|
CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_2, /* 416 */
|
|
CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_3, /* 417 */
|
|
CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_4, /* 418 */
|
|
|
|
/* Keep this at the end of HW events */
|
|
CMDQ_MAX_HW_EVENT_COUNT = 512,
|
|
|
|
/* token 512 to 639 may set secure */
|
|
|
|
/* SW Sync Tokens (Pre-defined) */
|
|
/* Config thread notify trigger thread */
|
|
CMDQ_SYNC_TOKEN_CONFIG_DIRTY = 640,
|
|
/* Trigger thread notify config thread */
|
|
CMDQ_SYNC_TOKEN_STREAM_EOF, /* 641 */
|
|
/* Block Trigger thread until the ESD check finishes. */
|
|
CMDQ_SYNC_TOKEN_ESD_EOF, /* 642 */
|
|
/* check CABC setup finish */
|
|
CMDQ_SYNC_TOKEN_CABC_EOF, /* 643 */
|
|
/* Block Trigger thread until the path freeze finishes */
|
|
CMDQ_SYNC_TOKEN_FREEZE_EOF, /* 644 */
|
|
/* Pass-2 notifies VENC frame is ready to be encoded */
|
|
CMDQ_SYNC_TOKEN_VENC_INPUT_READY, /* 645 */
|
|
/* VENC notifies Pass-2 encode done so next frame may start */
|
|
CMDQ_SYNC_TOKEN_VENC_EOF, /* 646 */
|
|
|
|
/* Notify normal CMDQ there are some secure task done */
|
|
CMDQ_SYNC_SECURE_THR_EOF, /* 647 */
|
|
/* Lock WSM resource */
|
|
CMDQ_SYNC_SECURE_WSM_LOCK, /* 648 */
|
|
|
|
/* SW Sync Tokens (User-defined) */
|
|
CMDQ_SYNC_TOKEN_USER_0, /* 649 */
|
|
CMDQ_SYNC_TOKEN_USER_1, /* 650 */
|
|
CMDQ_SYNC_TOKEN_POLL_MONITOR, /* 651 */
|
|
|
|
/* SW Sync Tokens (Pre-defined) */
|
|
/* Config thread notify trigger thread for external display */
|
|
CMDQ_SYNC_TOKEN_EXT_CONFIG_DIRTY, /* 652 */
|
|
/* Trigger thread notify config thread */
|
|
CMDQ_SYNC_TOKEN_EXT_STREAM_EOF, /* 653 */
|
|
/* Check CABC setup finish */
|
|
CMDQ_SYNC_TOKEN_EXT_CABC_EOF, /* 654 */
|
|
|
|
/* Secure video path notify SW token */
|
|
CMDQ_SYNC_DISP_OVL0_2NONSEC_END, /* 655 */
|
|
CMDQ_SYNC_DISP_OVL1_2NONSEC_END, /* 656 */
|
|
CMDQ_SYNC_DISP_2LOVL0_2NONSEC_END, /* 657 */
|
|
CMDQ_SYNC_DISP_2LOVL1_2NONSEC_END, /* 658 */
|
|
CMDQ_SYNC_DISP_RDMA0_2NONSEC_END, /* 659 */
|
|
CMDQ_SYNC_DISP_RDMA1_2NONSEC_END, /* 660 */
|
|
CMDQ_SYNC_DISP_WDMA0_2NONSEC_END, /* 661 */
|
|
CMDQ_SYNC_DISP_WDMA1_2NONSEC_END, /* 662 */
|
|
CMDQ_SYNC_DISP_EXT_STREAM_EOF, /* 663 */
|
|
|
|
/* Event for CMDQ to block executing command when append command
|
|
* Plz sync CMDQ_SYNC_TOKEN_APPEND_THR(id) in cmdq_core source file.
|
|
*/
|
|
CMDQ_SYNC_TOKEN_APPEND_THR0 = 670,
|
|
CMDQ_SYNC_TOKEN_APPEND_THR1, /* 671 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR2, /* 672 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR3, /* 673 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR4, /* 674 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR5, /* 675 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR6, /* 676 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR7, /* 677 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR8, /* 678 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR9, /* 679 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR10, /* 680 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR11, /* 681 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR12, /* 682 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR13, /* 683 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR14, /* 684 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR15, /* 685 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR16, /* 686 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR17, /* 687 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR18, /* 688 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR19, /* 689 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR20, /* 690 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR21, /* 691 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR22, /* 692 */
|
|
CMDQ_SYNC_TOKEN_APPEND_THR23, /* 693 */
|
|
|
|
/* secure world notify normal world task done */
|
|
CMDQ_SYNC_TOKEN_SEC_DONE, /* 694 */
|
|
|
|
/* token after 700 sync user space header */
|
|
|
|
/* GPR access tokens (for HW register backup)
|
|
* There are 15 32-bit GPR, 3 GPR form a set
|
|
* (64-bit for address, 32-bit for value)
|
|
*/
|
|
CMDQ_SYNC_TOKEN_GPR_SET_0 = 700,
|
|
CMDQ_SYNC_TOKEN_GPR_SET_1, /* 701 */
|
|
CMDQ_SYNC_TOKEN_GPR_SET_2, /* 702 */
|
|
CMDQ_SYNC_TOKEN_GPR_SET_3, /* 703 */
|
|
CMDQ_SYNC_TOKEN_GPR_SET_4, /* 704 */
|
|
|
|
/* Resource lock event to control resource in GCE thread */
|
|
CMDQ_SYNC_RESOURCE_WROT0 = 710,
|
|
CMDQ_SYNC_RESOURCE_WROT1 = 711,
|
|
|
|
/**
|
|
* Event for CMDQ delay implement
|
|
* Plz sync CMDQ_SYNC_TOKEN_DELAY_THR(id) in cmdq_core source file.
|
|
*/
|
|
CMDQ_SYNC_TOKEN_TIMER = 720,
|
|
CMDQ_SYNC_TOKEN_DELAY_SET0 = 721,
|
|
CMDQ_SYNC_TOKEN_DELAY_SET1 = 722,
|
|
CMDQ_SYNC_TOKEN_DELAY_SET2 = 723,
|
|
|
|
/* GCE reserved hw event */
|
|
CMDQ_OUT_EVENT = 898,
|
|
|
|
/* GCE HW TPR Event*/
|
|
CMDQ_EVENT_TIMER_00 = 962,
|
|
CMDQ_EVENT_TIMER_01 = 963,
|
|
CMDQ_EVENT_TIMER_02 = 964,
|
|
CMDQ_EVENT_TIMER_03 = 965,
|
|
CMDQ_EVENT_TIMER_04 = 966,
|
|
/* 5: 1us */
|
|
CMDQ_EVENT_TIMER_05 = 967,
|
|
CMDQ_EVENT_TIMER_06 = 968,
|
|
CMDQ_EVENT_TIMER_07 = 969,
|
|
/* 8: 10us */
|
|
CMDQ_EVENT_TIMER_08 = 970,
|
|
CMDQ_EVENT_TIMER_09 = 971,
|
|
CMDQ_EVENT_TIMER_10 = 972,
|
|
/* 11: 100us */
|
|
CMDQ_EVENT_TIMER_11 = 973,
|
|
CMDQ_EVENT_TIMER_12 = 974,
|
|
CMDQ_EVENT_TIMER_13 = 975,
|
|
CMDQ_EVENT_TIMER_14 = 976,
|
|
/* 15: 1ms */
|
|
CMDQ_EVENT_TIMER_15 = 977,
|
|
CMDQ_EVENT_TIMER_16 = 978,
|
|
CMDQ_EVENT_TIMER_17 = 979,
|
|
/* 18: 10ms */
|
|
CMDQ_EVENT_TIMER_18 = 980,
|
|
CMDQ_EVENT_TIMER_19 = 981,
|
|
CMDQ_EVENT_TIMER_20 = 982,
|
|
/* 21: 100ms */
|
|
CMDQ_EVENT_TIMER_21 = 983,
|
|
CMDQ_EVENT_TIMER_22 = 984,
|
|
CMDQ_EVENT_TIMER_23 = 985,
|
|
CMDQ_EVENT_TIMER_24 = 986,
|
|
CMDQ_EVENT_TIMER_25 = 987,
|
|
CMDQ_EVENT_TIMER_26 = 988,
|
|
CMDQ_EVENT_TIMER_27 = 989,
|
|
CMDQ_EVENT_TIMER_28 = 990,
|
|
CMDQ_EVENT_TIMER_29 = 991,
|
|
CMDQ_EVENT_TIMER_30 = 992,
|
|
CMDQ_EVENT_TIMER_31 = 993,
|
|
|
|
/* GPR timer token, 994 to 994+23 */
|
|
CMDQ_EVENT_TIMER_GPR = 994,
|
|
|
|
/* event id is 9 bit */
|
|
CMDQ_SYNC_TOKEN_MAX = 0x3FF,
|
|
CMDQ_SYNC_TOKEN_INVALID = -1,
|
|
};
|
|
|
|
#endif
|