unplugged-kernel/drivers/misc/mediatek/cmdq/v3/mt6885/cmdq_engine.h

182 lines
5.4 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 MediaTek Inc.
*/
#ifndef __CMDQ_ENGINE_H__
#define __CMDQ_ENGINE_H__
enum CMDQ_ENG_ENUM {
/* ISP */
CMDQ_ENG_WPEI = 0,
CMDQ_ENG_WPEO, /* 1 */
CMDQ_ENG_WPEI2, /* 2 */
CMDQ_ENG_WPEO2, /* 3 */
CMDQ_ENG_ISP_IMGI, /* 4 */
CMDQ_ENG_ISP_IMGO, /* 5 */
CMDQ_ENG_ISP_IMG2O, /* 6 */
/* MDP */
CMDQ_ENG_MDP_CAMIN, /* 7 */
CMDQ_ENG_MDP_CAMIN2, /* 8 */
CMDQ_ENG_MDP_RDMA0, /* 9 */
CMDQ_ENG_MDP_RDMA1, /* 10 */
CMDQ_ENG_MDP_FG0, /* 11 */
CMDQ_ENG_MDP_FG1, /* 12 */
CMDQ_ENG_MDP_PQ0_SOUT, /* 13 */
CMDQ_ENG_MDP_PQ1_SOUT, /* 14 */
CMDQ_ENG_MDP_HDR0, /* 15 */
CMDQ_ENG_MDP_HDR1, /* 16 */
CMDQ_ENG_MDP_COLOR0, /* 17 */
CMDQ_ENG_MDP_COLOR1, /* 18 */
CMDQ_ENG_MDP_AAL0, /* 19 */
CMDQ_ENG_MDP_AAL1, /* 20 */
CMDQ_ENG_MDP_RSZ0, /* 21 */
CMDQ_ENG_MDP_RSZ1, /* 22 */
CMDQ_ENG_MDP_TDSHP0, /* 23 */
CMDQ_ENG_MDP_TDSHP1, /* 24 */
CMDQ_ENG_MDP_TCC0, /* 25 */
CMDQ_ENG_MDP_TCC1, /* 26 */
CMDQ_ENG_MDP_WROT0, /* 27 */
CMDQ_ENG_MDP_WROT1, /* 28 */
/* JPEG & VENC */
CMDQ_ENG_JPEG_ENC, /* 29 */
CMDQ_ENG_VIDEO_ENC, /* 30 */
CMDQ_ENG_JPEG_DEC, /* 31 */
CMDQ_ENG_JPEG_REMDC, /* 32 */
/* DPE */
CMDQ_ENG_DPE, /* 33 */
CMDQ_ENG_RSC, /* 34 */
CMDQ_ENG_GEPF, /* 35 */
CMDQ_ENG_EAF, /* 36 */
CMDQ_ENG_OWE, /* 37 */
CMDQ_ENG_MFB, /* 38 */
CMDQ_ENG_FDVT, /* 39 */
/* temp: CMDQ internal usage */
CMDQ_ENG_CMDQ, /* 40 */
CMDQ_ENG_DISP_MUTEX, /* 41 */
CMDQ_ENG_MMSYS_CONFIG, /* 42 */
CMDQ_ENG_MDP_RSZ2, /* 43 */
CMDQ_ENG_INORDER, /* 44 */
CMDQ_ENG_ISP_VIPI, /* 45 */
CMDQ_ENG_ISP_LCEI, /* 46 */
CMDQ_ENG_ISP_IMG3O, /* 47 */
CMDQ_ENG_ISP_SMXIO, /* 48 */
/* Dummy Engine */
CMDQ_ENG_DISP_AAL = 63,
CMDQ_ENG_DISP_COLOR0 = 63,
CMDQ_ENG_DISP_RDMA0 = 63,
CMDQ_ENG_DISP_RDMA1 = 63,
CMDQ_ENG_DISP_WDMA0 = 63,
CMDQ_ENG_DISP_WDMA1 = 63,
CMDQ_ENG_DISP_OVL0 = 63,
CMDQ_ENG_DISP_OVL1 = 63,
CMDQ_ENG_DISP_GAMMA = 63,
CMDQ_ENG_DISP_DSI0 = 63,
CMDQ_ENG_DISP_COLOR1 = 63,
CMDQ_ENG_DISP_2L_OVL1 = 63,
CMDQ_ENG_MDP_WDMA = 63,
CMDQ_ENG_MDP_MOUT0 = 63,
CMDQ_ENG_MDP_MOUT1 = 63,
CMDQ_ENG_DISP_MERGE = 63,
CMDQ_ENG_DISP_RDMA2 = 63,
CMDQ_ENG_DISP_SPLIT0 = 63,
CMDQ_ENG_DISP_SPLIT1 = 63,
CMDQ_ENG_DISP_DSI1_VDO = 63,
CMDQ_ENG_DISP_DSI1_CMD = 63,
CMDQ_ENG_DISP_DSI1 = 63,
CMDQ_ENG_DISP_UFOE = 63,
CMDQ_ENG_DISP_OVL2 = 63,
CMDQ_ENG_DISP_DSI0_VDO = 63,
CMDQ_ENG_DISP_DSI0_CMD = 63,
CMDQ_ENG_DISP_DPI = 63,
CMDQ_ENG_DISP_2L_OVL0 = 63,
CMDQ_ENG_DISP_2L_OVL2 = 63,
CMDQ_MAX_ENGINE_COUNT /* ALWAYS keep at the end */
};
#define CMDQ_ENG_ISP_GROUP_BITS ((1LL << CMDQ_ENG_ISP_IMGI) | \
(1LL << CMDQ_ENG_ISP_IMGO) | \
(1LL << CMDQ_ENG_ISP_IMG2O))
#define CMDQ_ENG_MDP_GROUP_BITS ((1LL << CMDQ_ENG_MDP_CAMIN) | \
(1LL << CMDQ_ENG_MDP_CAMIN2) | \
(1LL << CMDQ_ENG_MDP_RDMA0) | \
(1LL << CMDQ_ENG_MDP_RDMA1) | \
(1LL << CMDQ_ENG_MDP_RSZ0) | \
(1LL << CMDQ_ENG_MDP_RSZ1) | \
(1LL << CMDQ_ENG_MDP_RSZ2) | \
(1LL << CMDQ_ENG_MDP_TDSHP0) | \
(1LL << CMDQ_ENG_MDP_TDSHP1) | \
(1LL << CMDQ_ENG_MDP_COLOR0) | \
(1LL << CMDQ_ENG_MDP_COLOR1) | \
(1LL << CMDQ_ENG_MDP_WROT0) | \
(1LL << CMDQ_ENG_MDP_WROT1) | \
(1LL << CMDQ_ENG_MDP_AAL0) | \
(1LL << CMDQ_ENG_MDP_AAL1) | \
(1LL << CMDQ_ENG_MDP_TCC0) | \
(1LL << CMDQ_ENG_MDP_TCC1) | \
(1LL << CMDQ_ENG_MDP_FG0) | \
(1LL << CMDQ_ENG_MDP_FG1) | \
(1LL << CMDQ_ENG_MDP_HDR0) | \
(1LL << CMDQ_ENG_MDP_HDR1))
#define CMDQ_ENG_DISP_GROUP_BITS ((1LL << CMDQ_ENG_DISP_AAL) | \
(1LL << CMDQ_ENG_DISP_COLOR0) | \
(1LL << CMDQ_ENG_DISP_COLOR1) | \
(1LL << CMDQ_ENG_DISP_RDMA0) | \
(1LL << CMDQ_ENG_DISP_RDMA1) | \
(1LL << CMDQ_ENG_DISP_WDMA0) | \
(1LL << CMDQ_ENG_DISP_WDMA1) | \
(1LL << CMDQ_ENG_DISP_OVL0) | \
(1LL << CMDQ_ENG_DISP_OVL1) | \
(1LL << CMDQ_ENG_DISP_GAMMA) | \
(1LL << CMDQ_ENG_DISP_DSI0))
#define CMDQ_ENG_VENC_GROUP_BITS (0)
#define CMDQ_ENG_JPEG_GROUP_BITS ((1LL << CMDQ_ENG_JPEG_DEC))
#define CMDQ_ENG_DPE_GROUP_BITS (1LL << CMDQ_ENG_DPE)
#define CMDQ_ENG_RSC_GROUP_BITS (1LL << CMDQ_ENG_RSC)
#define CMDQ_ENG_GEPF_GROUP_BITS (1LL << CMDQ_ENG_GEPF)
#define CMDQ_ENG_EAF_GROUP_BITS (1LL << CMDQ_ENG_EAF)
#define CMDQ_ENG_FDVT_GROUP_BITS (1LL << CMDQ_ENG_FDVT)
#define CMDQ_ENG_ISP_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_ISP_GROUP_BITS))
#define CMDQ_ENG_MDP_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_MDP_GROUP_BITS))
#define CMDQ_ENG_DISP_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_DISP_GROUP_BITS))
#define CMDQ_ENG_JPEG_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_JPEG_GROUP_BITS))
#define CMDQ_ENG_VENC_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_VENC_GROUP_BITS))
#define CMDQ_ENG_DPE_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_DPE_GROUP_BITS))
#define CMDQ_ENG_RSC_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_RSC_GROUP_BITS))
#define CMDQ_ENG_GEPF_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_GEPF_GROUP_BITS))
#define CMDQ_ENG_EAF_GROUP_FLAG(flag) ((flag) & (CMDQ_ENG_EAF_GROUP_BITS))
#define CMDQ_FOREACH_GROUP(ACTION_struct)\
ACTION_struct(CMDQ_GROUP_ISP, ISP) \
ACTION_struct(CMDQ_GROUP_MDP, MDP) \
ACTION_struct(CMDQ_GROUP_DISP, DISP) \
ACTION_struct(CMDQ_GROUP_JPEG, JPEG) \
ACTION_struct(CMDQ_GROUP_VENC, VENC) \
ACTION_struct(CMDQ_GROUP_DPE, DPE) \
ACTION_struct(CMDQ_GROUP_RSC, RSC) \
ACTION_struct(CMDQ_GROUP_GEPF, GEPF) \
ACTION_struct(CMDQ_GROUP_EAF, EAF)
#define MDP_GENERATE_ENUM(_enum, _string) _enum,
enum CMDQ_GROUP_ENUM {
CMDQ_FOREACH_GROUP(MDP_GENERATE_ENUM)
CMDQ_MAX_GROUP_COUNT, /* ALWAYS keep at the end */
};
#endif /* __CMDQ_ENGINE_H__ */