136 lines
5.1 KiB
C
136 lines
5.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT6761_DCM_AUTOGEN_H__
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#define __MT6761_DCM_AUTOGEN_H__
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#include <mtk_dcm.h>
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#if defined(__KERNEL__) && defined(CONFIG_OF)
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extern unsigned long dcm_infracfg_ao_base;
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extern unsigned long dcm_mcucfg_base;
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extern unsigned long dcm_mcucfg_phys_base;
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extern unsigned long dcm_dramc0_ao_base;
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extern unsigned long dcm_dramc1_ao_base;
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extern unsigned long dcm_ddrphy0_ao_base;
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extern unsigned long dcm_ddrphy1_ao_base;
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extern unsigned long dcm_chn0_emi_base;
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extern unsigned long dcm_chn1_emi_base;
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/* extern unsigned long dcm_emi_base; */
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#define INFRACFG_AO_BASE (dcm_infracfg_ao_base)
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#define MCUCFG_BASE (dcm_mcucfg_base)
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#define MP0_CPUCFG_BASE (MCUCFG_BASE)
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#define MCU_MISCCFG_BASE (MCUCFG_BASE + 0x400)
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#define DRAMC_CH0_TOP0_BASE (dcm_ddrphy0_ao_base)
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#define DRAMC_CH0_TOP1_BASE (dcm_dramc0_ao_base)
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#define DRAMC_CH1_TOP0_BASE (dcm_ddrphy1_ao_base)
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#define DRAMC_CH1_TOP1_BASE (dcm_dramc1_ao_base)
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#define CHN0_EMI_BASE (dcm_chn0_emi_base)
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#define CHN1_EMI_BASE (dcm_chn1_emi_base)
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/* #define EMI_BASE (dcm_emi_base) */
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#else /* !(defined(__KERNEL__) && defined(CONFIG_OF)) */
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#undef INFRACFG_AO_BASE
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#undef MCUCFG_BASE
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#undef MP0_CPUCFG_BASE
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#undef MCU_MISCCFG_BASE
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#undef DRAMC_CH0_TOP0_BASE
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#undef DRAMC_CH0_TOP1_BASE
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#undef CHN0_EMI_BASE
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#undef DRAMC_CH1_TOP0_BASE
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#undef DRAMC_CH1_TOP1_BASE
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#undef CHN1_EMI_BASE
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/* Base */
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#define INFRACFG_AO_BASE 0x10001000
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#define MCUCFG_BASE 0x10200000
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#define MP0_CPUCFG_BASE 0x10200000
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#define MCU_MISCCFG_BASE 0x10200400
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#define DRAMC_CH0_TOP0_BASE 0x10228000
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#define DRAMC_CH0_TOP1_BASE 0x1022a000
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#define CHN0_EMI_BASE 0x1022d000
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#define DRAMC_CH1_TOP0_BASE 0x10230000
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#define DRAMC_CH1_TOP1_BASE 0x10232000
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#define CHN1_EMI_BASE 0x10235000
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#endif /* #if defined(__KERNEL__) && defined(CONFIG_OF) */
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/* Register Definition */
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#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70)
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#define PERI_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x74)
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#define MEM_DCM_CTRL (INFRACFG_AO_BASE + 0x78)
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#define DFS_MEM_DCM_CTRL (INFRACFG_AO_BASE + 0x7c)
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#define P2P_RX_CLK_ON (INFRACFG_AO_BASE + 0xa0)
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#define MP0_CPUCFG_MP0_RGU_DCM_CONFIG (MP0_CPUCFG_BASE + 0x88)
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#define L2C_SRAM_CTRL (MCU_MISCCFG_BASE + 0x248)
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#define CCI_CLK_CTRL (MCU_MISCCFG_BASE + 0x260)
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#define BUS_FABRIC_DCM_CTRL (MCU_MISCCFG_BASE + 0x268)
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#define MCU_MISC_DCM_CTRL (MCU_MISCCFG_BASE + 0x26c)
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#define CCI_ADB400_DCM_CONFIG (MCU_MISCCFG_BASE + 0x340)
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#define SYNC_DCM_CONFIG (MCU_MISCCFG_BASE + 0x344)
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#define MP_GIC_RGU_SYNC_DCM (MCU_MISCCFG_BASE + 0x358)
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#define BUS_PLL_DIVIDER_CFG (MCU_MISCCFG_BASE + 0x3c0)
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#define DRAMC_CH0_TOP0_MISC_CG_CTRL0 (DRAMC_CH0_TOP0_BASE + 0x284)
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#define DRAMC_CH0_TOP0_MISC_CG_CTRL2 (DRAMC_CH0_TOP0_BASE + 0x28c)
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#define DRAMC_CH0_TOP0_MISC_CTRL3 (DRAMC_CH0_TOP0_BASE + 0x2a8)
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#define DRAMC_CH0_TOP1_DRAMC_PD_CTRL (DRAMC_CH0_TOP1_BASE + 0x38)
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#define DRAMC_CH0_TOP1_CLKAR (DRAMC_CH0_TOP1_BASE + 0x3c)
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#define CHN0_EMI_CHN_EMI_CONB (CHN0_EMI_BASE + 0x8)
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#define DRAMC_CH1_TOP0_MISC_CG_CTRL0 (DRAMC_CH1_TOP0_BASE + 0x284)
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#define DRAMC_CH1_TOP0_MISC_CG_CTRL2 (DRAMC_CH1_TOP0_BASE + 0x28c)
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#define DRAMC_CH1_TOP0_MISC_CTRL3 (DRAMC_CH1_TOP0_BASE + 0x2a8)
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#define DRAMC_CH1_TOP1_DRAMC_PD_CTRL (DRAMC_CH1_TOP1_BASE + 0x38)
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#define DRAMC_CH1_TOP1_CLKAR (DRAMC_CH1_TOP1_BASE + 0x3c)
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#define CHN1_EMI_CHN_EMI_CONB (CHN1_EMI_BASE + 0x8)
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/* INFRACFG_AO */
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bool dcm_infracfg_ao_dcm_infrabus_group_is_on(void);
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void dcm_infracfg_ao_dcm_infrabus_group(int on);
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bool dcm_infracfg_ao_dcm_mem_group_is_on(void);
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void dcm_infracfg_ao_dcm_mem_group(int on);
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bool dcm_infracfg_ao_dcm_peribus_group_is_on(void);
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void dcm_infracfg_ao_dcm_peribus_group(int on);
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bool dcm_infracfg_ao_dcm_ssusb_group_is_on(void);
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void dcm_infracfg_ao_dcm_ssusb_group(int on);
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/* MP0_CPUCFG */
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bool dcm_mp0_cpucfg_mp0_rgu_dcm_is_on(void);
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void dcm_mp0_cpucfg_mp0_rgu_dcm(int on);
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/* MCU_MISCCFG */
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bool dcm_mcu_misccfg_adb400_dcm_is_on(void);
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void dcm_mcu_misccfg_adb400_dcm(int on);
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bool dcm_mcu_misccfg_bus_arm_pll_divider_dcm_is_on(void);
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void dcm_mcu_misccfg_bus_arm_pll_divider_dcm(int on);
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bool dcm_mcu_misccfg_bus_clock_dcm_is_on(void);
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void dcm_mcu_misccfg_bus_clock_dcm(int on);
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bool dcm_mcu_misccfg_bus_fabric_dcm_is_on(void);
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void dcm_mcu_misccfg_bus_fabric_dcm(int on);
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bool dcm_mcu_misccfg_gic_sync_dcm_is_on(void);
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void dcm_mcu_misccfg_gic_sync_dcm(int on);
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bool dcm_mcu_misccfg_l2_shared_dcm_is_on(void);
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void dcm_mcu_misccfg_l2_shared_dcm(int on);
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bool dcm_mcu_misccfg_mcu_misc_dcm_is_on(void);
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void dcm_mcu_misccfg_mcu_misc_dcm(int on);
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/* DRAMC_CH0_TOP0 */
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bool dcm_dramc_ch0_top0_ddrphy_is_on(void);
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void dcm_dramc_ch0_top0_ddrphy(int on);
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/* DRAMC_CH0_TOP1 */
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bool dcm_dramc_ch0_top1_dcm_dramc_group_is_on(void);
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void dcm_dramc_ch0_top1_dcm_dramc_group(int on);
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/* CHN0_EMI */
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bool dcm_chn0_emi_dcm_emi_group_is_on(void);
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void dcm_chn0_emi_dcm_emi_group(int on);
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/* DRAMC_CH1_TOP0 */
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bool dcm_dramc_ch1_top0_ddrphy_is_on(void);
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void dcm_dramc_ch1_top0_ddrphy(int on);
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/* DRAMC_CH1_TOP1 */
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bool dcm_dramc_ch1_top1_dcm_dramc_group_is_on(void);
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void dcm_dramc_ch1_top1_dcm_dramc_group(int on);
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/* CHN1_EMI */
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bool dcm_chn1_emi_dcm_emi_group_is_on(void);
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void dcm_chn1_emi_dcm_emi_group(int on);
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#endif /* __MT6761_DCM_AUTOGEN_H__ */
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