109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT6761_DCM_INTERNAL_H__
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#define __MT6761_DCM_INTERNAL_H__
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#include <mtk_dcm_common.h>
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#include "mt6761_dcm_autogen.h"
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/* #define DCM_DEFAULT_ALL_OFF */
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/* #define DCM_BRINGUP */
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/* Note: ENABLE_DCM_IN_LK is used in kernel if DCM is enabled in LK */
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#define ENABLE_DCM_IN_LK
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#ifdef ENABLE_DCM_IN_LK
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#define INIT_DCM_TYPE_BY_K 0
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#endif
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/* #define CTRL_BIGCORE_DCM_IN_KERNEL */
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/* #define reg_read(addr) __raw_readl(IOMEM(addr)) */
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#define reg_read(addr) readl((void *)addr)
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/*#define reg_write(addr, val) mt_reg_sync_writel((val), ((void *)addr))*/
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#define reg_write(addr, val) \
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do { writel(val, (void *)addr); wmb(); } while (0) /* sync write */
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#if defined(CONFIG_ARM_PSCI) || defined(CONFIG_MTK_PSCI)
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#define MCUSYS_SMC_WRITE(addr, val) mcusys_smc_write_phy(addr##_PHYS, val)
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#ifndef mcsi_reg_read
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#define mcsi_reg_read(offset) \
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mt_secure_call(MTK_SIP_KERENL_MCSI_NS_ACCESS, 0, offset, 0)
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#endif
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#ifndef mcsi_reg_write
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#define mcsi_reg_write(val, offset) \
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mt_secure_call(MTK_SIP_KERENL_MCSI_NS_ACCESS, 1, offset, val)
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#endif
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#define MCSI_SMC_WRITE(addr, val) mcsi_reg_write(val, (addr##_PHYS & 0xFFFF))
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#define MCSI_SMC_READ(addr) mcsi_reg_read(addr##_PHYS & 0xFFFF)
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#else
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#define MCUSYS_SMC_WRITE(addr, val) mcusys_smc_write(addr, val)
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#define MCSI_SMC_WRITE(addr, val) reg_write(addr, val)
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#define MCSI_SMC_READ(addr) reg_read(addr)
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#endif
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#define REG_DUMP(addr) \
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dcm_pr_info("%-30s(0x%08lx): 0x%08x\n", #addr, addr, reg_read(addr))
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#define SECURE_REG_DUMP(addr) \
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dcm_pr_info("%-30s(0x%08lx): 0x%08x\n", \
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#addr, addr, mcsi_reg_read(addr##_PHYS & 0xFFFF))
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/* Sync DCM related RG bit definitions. */
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/* TODO: Why not autogen? */
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#define SYNC_DCM_CLK_MIN_FREQ 52
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#define SYNC_DCM_MAX_DIV_VAL 127
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#define MCUCFG_SYNC_DCM_CCI_REG SYNC_DCM_CONFIG
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#define MCUCFG_SYNC_DCM_CCI (1)
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#define MCUCFG_SYNC_DCM_CCI_TOGMASK (0x1 << MCUCFG_SYNC_DCM_CCI)
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#define MCUCFG_SYNC_DCM_TOGMASK (MCUCFG_SYNC_DCM_CCI_TOGMASK)
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#define MCUCFG_SYNC_DCM_TOG1 MCUCFG_SYNC_DCM_TOGMASK
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#define MCUCFG_SYNC_DCM_CCI_TOG1 MCUCFG_SYNC_DCM_CCI_TOGMASK
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#define MCUCFG_SYNC_DCM_CCI_TOG0 (0x0 << MCUCFG_SYNC_DCM_CCI)
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#define MCUCFG_SYNC_DCM_TOG0 (MCUCFG_SYNC_DCM_CCI_TOG0)
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#define MCUCFG_SYNC_DCM_SEL_CCI (2)
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#define MCUCFG_SYNC_DCM_SEL_CCI_MASK (0x7F << MCUCFG_SYNC_DCM_SEL_CCI)
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#define MCUCFG_SYNC_DCM_SEL_MASK (MCUCFG_SYNC_DCM_SEL_CCI_MASK)
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int dcm_armcore(int mode);
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int dcm_infra(int on);
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int dcm_peri(int on);
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int dcm_mcusys(int on);
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int dcm_dramc_ao(int on);
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int dcm_emi(int on);
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int dcm_ddrphy(int on);
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int dcm_stall(int on);
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int dcm_big_core(int on);
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int dcm_gic_sync(int on);
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int dcm_last_core(int on);
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int dcm_rgu(int on);
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int dcm_topckg(int on);
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int dcm_lpdma(int on);
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int dcm_mcsi(int on);
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int mt_dcm_dts_map(void);
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void dcm_set_hotplug_nb(void);
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short dcm_get_cpu_cluster_stat(void);
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/* unit of frequency is MHz */
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int sync_dcm_set_cpu_freq(unsigned int cci,
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unsigned int mp0,
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unsigned int mp1,
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unsigned int mp2);
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int sync_dcm_set_cpu_div(unsigned int cci,
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unsigned int mp0,
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unsigned int mp1,
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unsigned int mp2);
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/* remove for new arch extern struct DCM dcm_array[NR_DCM_TYPE]; */
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void dcm_array_register(void);
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extern void *mt_dramc_chn_base_get(int channel);
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extern void *mt_ddrphy_chn_base_get(int channel);
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extern void __iomem *mt_cen_emi_base_get(void);
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extern void __iomem *mt_chn_emi_base_get(int chn);
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#endif /* #ifndef __MT6761_DCM_INTERNAL_H__ */
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