255 lines
9.1 KiB
C
255 lines
9.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MTK_DCM_AUTOGEN_H__
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#define __MTK_DCM_AUTOGEN_H__
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#include <mtk_dcm.h>
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#if defined(__KERNEL__) && defined(CONFIG_OF)
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/* TODO: Fix all base addresses. */
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extern unsigned long dcm_infracfg_ao_base;
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extern unsigned long dcm_pwrap_base;
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extern unsigned long dcm_mcucfg_base;
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extern unsigned long dcm_cpccfg_rg_base;
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extern unsigned long dcm_infracfg_ao_mem_base;
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extern unsigned long dcm_dramc_ch0_top0_ao_base;
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extern unsigned long dcm_dramc_ch1_top0_ao_base;
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extern unsigned long dcm_dramc_ch0_top5_ao_base;
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extern unsigned long dcm_dramc_ch1_top5_ao_base;
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extern unsigned long dcm_ch0_emi_base;
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extern unsigned long dcm_emi_base;
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/* not used actually in MT6779 */
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extern unsigned long dcm_mm_iommu_base;
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extern unsigned long dcm_vpu_iommu_base;
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extern unsigned long dcm_sspm_base;
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extern unsigned long dcm_audio_base;
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extern unsigned long dcm_msdc1_base;
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#ifndef USE_DRAM_API_INSTEAD
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extern unsigned long dcm_ddrphy1_ao_base;
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#endif /* #ifndef USE_DRAM_API_INSTEAD */
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#define INFRACFG_AO_BASE (dcm_infracfg_ao_base)
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#define PWRAP_BASE (dcm_pwrap_base)
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#define MP_CPUSYS_TOP_BASE (dcm_mcucfg_base)
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#define CPCCFG_REG_BASE (dcm_cpccfg_rg_base)
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#define INFRACFG_AO_MEM_BASE (dcm_infracfg_ao_mem_base)
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/* dram staff */
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/* dramc */
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#define DRAMC_CH0_TOP0_BASE (dcm_dramc_ch0_top0_ao_base)
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#define DRAMC_CH0_TOP5_BASE (dcm_dramc_ch0_top5_ao_base)
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/* ddrphy */
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#define DRAMC_CH1_TOP0_BASE (dcm_dramc_ch1_top0_ao_base)
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#define DRAMC_CH1_TOP5_BASE (dcm_dramc_ch1_top5_ao_base)
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/* emi */
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#define CHN0_EMI_BASE (dcm_ch0_emi_base)
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#define EMI_BASE (dcm_emi_base)
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/* not used actually in MT6779 */
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#define MM_IOMMU_BASE (dcm_mm_iommu_base)
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#define VPU_IOMMU_BASE (dcm_vpu_iommu_base)
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#define SSPM_BASE (dcm_sspm_base)
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#define AUDIO_BASE (dcm_audio_base)
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#define MSDC1_BASE (dcm_msdc1_base)
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#else /* !(defined(__KERNEL__) && defined(CONFIG_OF)) */
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/* Here below used in CTP and lk for references. */
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#undef INFRACFG_AO_BASE
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#undef INFRACFG_AO_MEM_BASE
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#undef PWRAP_BASE
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#undef EMI_BASE
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#undef MM_IOMMU_BASE /* not used */
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#undef DRAMC_CH0_TOP0_BASE
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#undef CHN0_EMI_BASE
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#undef DRAMC_CH0_TOP5_BASE
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#undef DRAMC_CH1_TOP0_BASE
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#undef DRAMC_CH1_TOP5_BASE
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#undef VPU_IOMMU_BASE /* not used */
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#undef SSPM_BASE /* not used */
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#undef AUDIO_BASE /* not used */
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#undef MSDC1_BASE /* not used */
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#undef MP_CPUSYS_TOP_BASE
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#undef CPCCFG_REG_BASE
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/* Base */
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#define INFRACFG_AO_BASE 0x10001000
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#define INFRACFG_AO_MEM_BASE 0x10002000
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#define PWRAP_BASE 0x1000d000
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#define EMI_BASE 0x10219000
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#define MM_IOMMU_BASE 0x10220000
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#define DRAMC_CH0_TOP0_BASE 0x10230000
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#define CHN0_EMI_BASE 0x10235000
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#define DRAMC_CH0_TOP5_BASE 0x10238000
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#define DRAMC_CH1_TOP0_BASE 0x10240000
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#define DRAMC_CH1_TOP5_BASE 0x10248000
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#define VPU_IOMMU_BASE 0x1024f000
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#define SSPM_BASE 0x10400000
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#define AUDIO_BASE 0x11210000
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#define MSDC1_BASE 0x11240000
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#define MP_CPUSYS_TOP_BASE 0xc538000
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#define CPCCFG_REG_BASE 0xc53a800
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#endif /* #if defined(__KERNEL__) && defined(CONFIG_OF) */
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/* Register Definition */
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#define CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
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#define CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
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#define CPU_PLLDIV_CFG2 (MP_CPUSYS_TOP_BASE + 0x22a8)
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#define BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
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#define MCSI_CFG2 (MP_CPUSYS_TOP_BASE + 0x2418)
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#define MCSI_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
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#define MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
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#define MP_ADB_DCM_CFG2 (MP_CPUSYS_TOP_BASE + 0x2508)
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#define MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
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#define MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
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#define MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
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#define EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
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#define SLOW_CK_CFG (CPCCFG_REG_BASE + 0x120)
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#define MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
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#define MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
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#define INFRA_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x70)
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#define PERI_BUS_DCM_CTRL (INFRACFG_AO_BASE + 0x74)
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#define MEM_DCM_CTRL (INFRACFG_AO_BASE + 0x78)
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#define P2P_RX_CLK_ON (INFRACFG_AO_BASE + 0xa0)
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#define INFRA_AXIMEM_IDLE_BIT_EN_0 (INFRACFG_AO_BASE + 0xa30)
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#define INFRA_EMI_DCM_CFG0 (INFRACFG_AO_MEM_BASE + 0x28)
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#define INFRA_EMI_DCM_CFG1 (INFRACFG_AO_MEM_BASE + 0x2c)
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#define INFRA_EMI_DCM_CFG3 (INFRACFG_AO_MEM_BASE + 0x34)
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#define TOP_CK_ANCHOR_CFG (INFRACFG_AO_MEM_BASE + 0x38)
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#define PMIC_WRAP_DCM_EN (PWRAP_BASE + 0x1ec)
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#define EMI_CONM (EMI_BASE + 0x60)
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#define EMI_CONN (EMI_BASE + 0x68)
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#define EMI_THRO_CTRL0 (EMI_BASE + 0x830)
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#define MM_MMU_DCM_DIS (MM_IOMMU_BASE + 0x50)
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#define DRAMC_CH0_TOP0_DRAMC_PD_CTRL (DRAMC_CH0_TOP0_BASE + 0x38)
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#define DRAMC_CH0_TOP0_CLKAR (DRAMC_CH0_TOP0_BASE + 0x3c)
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#define CHN0_EMI_CHN_EMI_CONB (CHN0_EMI_BASE + 0x8)
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#define DRAMC_CH0_TOP5_MISC_CG_CTRL0 (DRAMC_CH0_TOP5_BASE + 0x284)
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#define DRAMC_CH0_TOP5_MISC_CG_CTRL2 (DRAMC_CH0_TOP5_BASE + 0x28c)
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#define DRAMC_CH0_TOP5_MISC_CTRL2 (DRAMC_CH0_TOP5_BASE + 0x2a4)
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#define DRAMC_CH1_TOP0_DRAMC_PD_CTRL (DRAMC_CH1_TOP0_BASE + 0x38)
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#define DRAMC_CH1_TOP0_CLKAR (DRAMC_CH1_TOP0_BASE + 0x3c)
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#define DRAMC_CH1_TOP5_MISC_CG_CTRL0 (DRAMC_CH1_TOP5_BASE + 0x284)
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#define DRAMC_CH1_TOP5_MISC_CG_CTRL2 (DRAMC_CH1_TOP5_BASE + 0x28c)
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#define DRAMC_CH1_TOP5_MISC_CTRL2 (DRAMC_CH1_TOP5_BASE + 0x2a4)
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#define VPU_MMU_DCM_DIS (VPU_IOMMU_BASE + 0x50)
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#define SSPM_MCLK_DIV (SSPM_BASE + 0x43004)
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#define SSPM_DCM_CTRL (SSPM_BASE + 0x43008)
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#define AUDIO_TOP_CON0 (AUDIO_BASE + 0x0)
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#define MSDC1_PATCH_BIT1 (MSDC1_BASE + 0xb4)
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/* INFRACFG_AO */
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bool dcm_infracfg_ao_infra_bus_dcm_is_on(void);
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void dcm_infracfg_ao_infra_bus_dcm(int on);
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bool dcm_infracfg_ao_infra_rx_p2p_dcm_is_on(void);
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void dcm_infracfg_ao_infra_rx_p2p_dcm(int on);
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bool dcm_infracfg_ao_peri_bus_dcm_is_on(void);
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void dcm_infracfg_ao_peri_bus_dcm(int on);
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bool dcm_infracfg_ao_peri_module_dcm_is_on(void);
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void dcm_infracfg_ao_peri_module_dcm(int on);
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/* INFRACFG_AO_MEM */
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bool dcm_infracfg_ao_mem_dcm_emi_group_is_on(void);
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void dcm_infracfg_ao_mem_dcm_emi_group(int on);
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/* PWRAP */
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bool dcm_pwrap_pmic_wrap_is_on(void);
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void dcm_pwrap_pmic_wrap(int on);
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/* EMI */
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bool dcm_emi_emi_dcm_is_on(void);
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void dcm_emi_emi_dcm(int on);
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/* MM_IOMMU */
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bool dcm_mm_iommu_mm_mmu_dcm_cfg_is_on(void);
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void dcm_mm_iommu_mm_mmu_dcm_cfg(int on);
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/* DRAMC_CH0_TOP0 */
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bool dcm_dramc_ch0_top0_ddrphy_is_on(void);
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void dcm_dramc_ch0_top0_ddrphy(int on);
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/* CHN0_EMI */
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bool dcm_chn0_emi_chn_emi_dcm_is_on(void);
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void dcm_chn0_emi_chn_emi_dcm(int on);
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/* DRAMC_CH0_TOP5 */
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bool dcm_dramc_ch0_top5_ddrphy_is_on(void);
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void dcm_dramc_ch0_top5_ddrphy(int on);
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/* DRAMC_CH1_TOP0 */
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bool dcm_dramc_ch1_top0_ddrphy_is_on(void);
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void dcm_dramc_ch1_top0_ddrphy(int on);
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/* DRAMC_CH1_TOP5 */
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bool dcm_dramc_ch1_top5_ddrphy_is_on(void);
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void dcm_dramc_ch1_top5_ddrphy(int on);
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/* VPU_IOMMU */
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bool dcm_vpu_iommu_vpu_mmu_dcm_cfg_is_on(void);
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void dcm_vpu_iommu_vpu_mmu_dcm_cfg(int on);
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/* SSPM */
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bool dcm_sspm_sspm_dcm_is_on(void);
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void dcm_sspm_sspm_dcm(int on);
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/* AUDIO */
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bool dcm_audio_aud_mas_ahb_ck_dcm_is_on(void);
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void dcm_audio_aud_mas_ahb_ck_dcm(int on);
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/* MSDC1 */
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bool dcm_msdc1_dcmen_dcm_is_on(void);
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void dcm_msdc1_dcmen_dcm(int on);
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bool dcm_msdc1_hgdmacken_dcm_is_on(void);
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void dcm_msdc1_hgdmacken_dcm(int on);
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bool dcm_msdc1_macmdcken_dcm_is_on(void);
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void dcm_msdc1_macmdcken_dcm(int on);
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bool dcm_msdc1_mpsccken_dcm_is_on(void);
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void dcm_msdc1_mpsccken_dcm(int on);
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bool dcm_msdc1_mrctlcken_dcm_is_on(void);
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void dcm_msdc1_mrctlcken_dcm(int on);
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bool dcm_msdc1_msdcken_dcm_is_on(void);
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void dcm_msdc1_msdcken_dcm(int on);
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bool dcm_msdc1_mshbfcken_dcm_is_on(void);
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void dcm_msdc1_mshbfcken_dcm(int on);
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bool dcm_msdc1_mspccken_dcm_is_on(void);
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void dcm_msdc1_mspccken_dcm(int on);
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bool dcm_msdc1_mvoldtcken_dcm_is_on(void);
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void dcm_msdc1_mvoldtcken_dcm(int on);
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bool dcm_msdc1_mwctlcken_dcm_is_on(void);
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void dcm_msdc1_mwctlcken_dcm(int on);
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/* MP_CPUSYS_TOP */
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bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
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void dcm_mp_cpusys_top_adb_dcm(int on);
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bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
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void dcm_mp_cpusys_top_apb_dcm(int on);
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bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
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void dcm_mp_cpusys_top_bus_pll_div_dcm(int on);
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bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_core_stall_dcm(int on);
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bool dcm_mp_cpusys_top_cpubiu_dbg_cg_is_on(void);
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void dcm_mp_cpusys_top_cpubiu_dbg_cg(int on);
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bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpubiu_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(int on);
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bool dcm_mp_cpusys_top_cpu_pll_div_2_dcm_is_on(void);
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void dcm_mp_cpusys_top_cpu_pll_div_2_dcm(int on);
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bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
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void dcm_mp_cpusys_top_fcm_stall_dcm(int on);
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bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
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void dcm_mp_cpusys_top_last_cor_idle_dcm(int on);
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bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
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void dcm_mp_cpusys_top_misc_dcm(int on);
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bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
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void dcm_mp_cpusys_top_mp0_qdcm(int on);
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/* CPCCFG_REG */
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bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
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void dcm_cpccfg_reg_emi_wfifo(int on);
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bool dcm_cpccfg_reg_mp_stall_dcm_is_on(void);
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void dcm_cpccfg_reg_mp_stall_dcm(int on);
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#endif /* __MTK_DCM_AUTOGEN_H__ */
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