1005 lines
27 KiB
C
1005 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/io.h>
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#include <mt6761_dcm_internal.h>
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#include <mt6761_dcm_autogen.h>
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#include <mtk_dcm.h>
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/* Below from DCM autogen. */
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#define INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 3) | \
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(0x1 << 4) | \
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(0x1f << 5) | \
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(0x1 << 20) | \
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(0x1 << 21) | \
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(0x1 << 22) | \
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(0x1 << 23) | \
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(0x1 << 30))
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#define INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x0 << 2) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x10 << 5) | \
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(0x1 << 20) | \
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(0x1 << 21) | \
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(0x1 << 22) | \
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(0x1 << 23) | \
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(0x1 << 30))
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#define INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 2) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x10 << 5) | \
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(0x0 << 20) | \
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(0x1 << 21) | \
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(0x1 << 22) | \
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(0x0 << 23) | \
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(0x0 << 30))
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static void infracfg_ao_infra_dcm_rg_sfsel_set(unsigned int val)
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{
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~(0x1f << 10)) |
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(val & 0x1f) << 10);
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}
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bool dcm_infracfg_ao_dcm_infrabus_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(INFRA_BUS_DCM_CTRL) &
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INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_dcm_infrabus_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_dcm_infrabus_group'" */
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infracfg_ao_infra_dcm_rg_sfsel_set(0x1);
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_dcm_infrabus_group'" */
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infracfg_ao_infra_dcm_rg_sfsel_set(0x1);
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reg_write(INFRA_BUS_DCM_CTRL,
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(reg_read(INFRA_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_INFRABUS_GROUP_REG0_OFF);
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}
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}
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#define INFRACFG_AO_DCM_MEM_GROUP_REG0_MASK ((0x1 << 0) | \
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(0x1 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x7f << 9) | \
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(0x1f << 16) | \
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(0x1f << 21) | \
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(0x1 << 26) | \
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(0x1 << 27) | \
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(0x1 << 28) | \
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(0x1 << 29) | \
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(0x1 << 31))
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#define INFRACFG_AO_DCM_MEM_GROUP_REG1_MASK ((0x1 << 0) | \
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(0x1 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x1f << 16) | \
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(0x1f << 21) | \
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(0x1 << 26))
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#define INFRACFG_AO_DCM_MEM_GROUP_REG0_ON ((0x0 << 0) | \
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(0x0 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x0 << 9) | \
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(0x0 << 16) | \
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(0x1f << 21) | \
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(0x0 << 26) | \
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(0x1 << 27) | \
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(0x0 << 28) | \
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(0x0 << 29) | \
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(0x0 << 31))
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#define INFRACFG_AO_DCM_MEM_GROUP_REG1_ON ((0x0 << 0) | \
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(0x0 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x0 << 16) | \
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(0x1f << 21) | \
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(0x0 << 26))
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#define INFRACFG_AO_DCM_MEM_GROUP_REG0_OFF ((0x0 << 0) | \
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(0x0 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x0 << 9) | \
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(0x0 << 16) | \
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(0x1f << 21) | \
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(0x0 << 26) | \
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(0x1 << 27) | \
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(0x0 << 28) | \
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(0x0 << 29) | \
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(0x0 << 31))
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#define INFRACFG_AO_DCM_MEM_GROUP_REG1_OFF ((0x0 << 0) | \
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(0x0 << 6) | \
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(0x1 << 7) | \
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(0x1 << 8) | \
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(0x0 << 16) | \
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(0x1f << 21) | \
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(0x0 << 26))
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bool dcm_infracfg_ao_dcm_mem_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(MEM_DCM_CTRL) &
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INFRACFG_AO_DCM_MEM_GROUP_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_MEM_GROUP_REG0_ON);
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ret &= ((reg_read(DFS_MEM_DCM_CTRL) &
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INFRACFG_AO_DCM_MEM_GROUP_REG1_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_MEM_GROUP_REG1_ON);
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return ret;
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}
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void dcm_infracfg_ao_dcm_mem_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_dcm_mem_group'" */
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reg_write(MEM_DCM_CTRL,
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(reg_read(MEM_DCM_CTRL) &
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~INFRACFG_AO_DCM_MEM_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_MEM_GROUP_REG0_ON);
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reg_write(DFS_MEM_DCM_CTRL,
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(reg_read(DFS_MEM_DCM_CTRL) &
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~INFRACFG_AO_DCM_MEM_GROUP_REG1_MASK) |
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INFRACFG_AO_DCM_MEM_GROUP_REG1_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_dcm_mem_group'" */
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reg_write(MEM_DCM_CTRL,
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(reg_read(MEM_DCM_CTRL) &
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~INFRACFG_AO_DCM_MEM_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_MEM_GROUP_REG0_OFF);
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reg_write(DFS_MEM_DCM_CTRL,
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(reg_read(DFS_MEM_DCM_CTRL) &
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~INFRACFG_AO_DCM_MEM_GROUP_REG1_MASK) |
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INFRACFG_AO_DCM_MEM_GROUP_REG1_OFF);
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}
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}
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 3) | \
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(0x1 << 4) | \
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(0x1f << 5) | \
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(0x1f << 15) | \
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(0x1 << 20) | \
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(0x1 << 21) | \
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(0x1 << 22) | \
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(0x1f << 23) | \
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(0x1 << 28) | \
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(0x1 << 29))
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_MASK ((0xf << 0))
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x1f << 5) | \
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(0x1f << 15) | \
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(0x1 << 20) | \
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(0x1 << 21) | \
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(0x1 << 22) | \
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(0x0 << 23) | \
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(0x1 << 28) | \
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(0x1 << 29))
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_ON ((0x0 << 0))
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 3) | \
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(0x0 << 4) | \
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(0x1f << 5) | \
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(0x0 << 15) | \
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(0x0 << 20) | \
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(0x0 << 21) | \
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(0x0 << 22) | \
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(0x0 << 23) | \
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(0x0 << 28) | \
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(0x0 << 29))
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#define INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_OFF ((0xf << 0))
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static void infracfg_ao_peri_dcm_rg_sfsel_set(unsigned int val)
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{
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~(0x1f << 10)) |
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(val & 0x1f) << 10);
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}
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bool dcm_infracfg_ao_dcm_peribus_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_ON);
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ret &= ((reg_read(P2P_RX_CLK_ON) &
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_ON);
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return ret;
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}
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void dcm_infracfg_ao_dcm_peribus_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_dcm_peribus_group'" */
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infracfg_ao_peri_dcm_rg_sfsel_set(0x0);
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_ON);
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reg_write(P2P_RX_CLK_ON,
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(reg_read(P2P_RX_CLK_ON) &
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~INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_MASK) |
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_dcm_peribus_group'" */
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infracfg_ao_peri_dcm_rg_sfsel_set(0x0);
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG0_OFF);
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reg_write(P2P_RX_CLK_ON,
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(reg_read(P2P_RX_CLK_ON) &
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~INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_MASK) |
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INFRACFG_AO_DCM_PERIBUS_GROUP_REG1_OFF);
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}
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}
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#define INFRACFG_AO_DCM_SSUSB_GROUP_REG0_MASK ((0x1 << 31))
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#define INFRACFG_AO_DCM_SSUSB_GROUP_REG0_ON ((0x1 << 31))
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#define INFRACFG_AO_DCM_SSUSB_GROUP_REG0_OFF ((0x0 << 31))
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bool dcm_infracfg_ao_dcm_ssusb_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(PERI_BUS_DCM_CTRL) &
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INFRACFG_AO_DCM_SSUSB_GROUP_REG0_MASK) ==
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(unsigned int) INFRACFG_AO_DCM_SSUSB_GROUP_REG0_ON);
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return ret;
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}
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void dcm_infracfg_ao_dcm_ssusb_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'infracfg_ao_dcm_ssusb_group'" */
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_SSUSB_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_SSUSB_GROUP_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'infracfg_ao_dcm_ssusb_group'" */
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reg_write(PERI_BUS_DCM_CTRL,
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(reg_read(PERI_BUS_DCM_CTRL) &
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~INFRACFG_AO_DCM_SSUSB_GROUP_REG0_MASK) |
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INFRACFG_AO_DCM_SSUSB_GROUP_REG0_OFF);
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}
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}
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#define MP0_CPUCFG_MP0_RGU_DCM_REG0_MASK ((0x1 << 0))
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#define MP0_CPUCFG_MP0_RGU_DCM_REG0_ON ((0x1 << 0))
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#define MP0_CPUCFG_MP0_RGU_DCM_REG0_OFF ((0x0 << 0))
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bool dcm_mp0_cpucfg_mp0_rgu_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(MP0_CPUCFG_MP0_RGU_DCM_CONFIG) &
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MP0_CPUCFG_MP0_RGU_DCM_REG0_MASK) ==
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(unsigned int) MP0_CPUCFG_MP0_RGU_DCM_REG0_ON);
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return ret;
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}
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void dcm_mp0_cpucfg_mp0_rgu_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'mp0_cpucfg_mp0_rgu_dcm'" */
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reg_write(MP0_CPUCFG_MP0_RGU_DCM_CONFIG,
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(reg_read(MP0_CPUCFG_MP0_RGU_DCM_CONFIG) &
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~MP0_CPUCFG_MP0_RGU_DCM_REG0_MASK) |
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MP0_CPUCFG_MP0_RGU_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'mp0_cpucfg_mp0_rgu_dcm'" */
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reg_write(MP0_CPUCFG_MP0_RGU_DCM_CONFIG,
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(reg_read(MP0_CPUCFG_MP0_RGU_DCM_CONFIG) &
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~MP0_CPUCFG_MP0_RGU_DCM_REG0_MASK) |
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MP0_CPUCFG_MP0_RGU_DCM_REG0_OFF);
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}
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}
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#define MCU_MISCCFG_ADB400_DCM_REG0_MASK ((0x1 << 0) | \
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(0x1 << 2) | \
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(0x1 << 6))
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#define MCU_MISCCFG_ADB400_DCM_REG0_ON ((0x1 << 0) | \
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(0x1 << 2) | \
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(0x1 << 6))
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#define MCU_MISCCFG_ADB400_DCM_REG0_OFF ((0x0 << 0) | \
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(0x0 << 2) | \
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(0x0 << 6))
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bool dcm_mcu_misccfg_adb400_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(CCI_ADB400_DCM_CONFIG) &
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MCU_MISCCFG_ADB400_DCM_REG0_MASK) ==
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(unsigned int) MCU_MISCCFG_ADB400_DCM_REG0_ON);
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return ret;
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}
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void dcm_mcu_misccfg_adb400_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'mcu_misccfg_adb400_dcm'" */
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reg_write(CCI_ADB400_DCM_CONFIG,
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(reg_read(CCI_ADB400_DCM_CONFIG) &
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~MCU_MISCCFG_ADB400_DCM_REG0_MASK) |
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MCU_MISCCFG_ADB400_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'mcu_misccfg_adb400_dcm'" */
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reg_write(CCI_ADB400_DCM_CONFIG,
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(reg_read(CCI_ADB400_DCM_CONFIG) &
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~MCU_MISCCFG_ADB400_DCM_REG0_MASK) |
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MCU_MISCCFG_ADB400_DCM_REG0_OFF);
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}
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}
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#define MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_MASK ((0x1 << 11))
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#define MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_ON ((0x1 << 11))
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#define MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_OFF ((0x0 << 11))
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bool dcm_mcu_misccfg_bus_arm_pll_divider_dcm_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(BUS_PLL_DIVIDER_CFG) &
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MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_MASK) ==
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(unsigned int) MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_ON);
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return ret;
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}
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void dcm_mcu_misccfg_bus_arm_pll_divider_dcm(int on)
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{
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if (on) {
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/* TINFO = "Turn ON 'mcu_misccfg_bus_arm_pll_divider_dcm'" */
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reg_write(BUS_PLL_DIVIDER_CFG,
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(reg_read(BUS_PLL_DIVIDER_CFG) &
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~MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_MASK) |
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MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_ON);
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} else {
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/* TINFO = "Turn OFF 'mcu_misccfg_bus_arm_pll_divider_dcm'" */
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reg_write(BUS_PLL_DIVIDER_CFG,
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(reg_read(BUS_PLL_DIVIDER_CFG) &
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~MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_MASK) |
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MCU_MISCCFG_BUS_ARM_PLL_DIVIDER_DCM_REG0_OFF);
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}
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}
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#define MCU_MISCCFG_BUS_CLOCK_DCM_REG0_MASK ((0x1 << 8))
|
|
#define MCU_MISCCFG_BUS_CLOCK_DCM_REG0_ON ((0x1 << 8))
|
|
#define MCU_MISCCFG_BUS_CLOCK_DCM_REG0_OFF ((0x0 << 8))
|
|
|
|
bool dcm_mcu_misccfg_bus_clock_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(CCI_CLK_CTRL) &
|
|
MCU_MISCCFG_BUS_CLOCK_DCM_REG0_MASK) ==
|
|
(unsigned int) MCU_MISCCFG_BUS_CLOCK_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcu_misccfg_bus_clock_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcu_misccfg_bus_clock_dcm'" */
|
|
reg_write(CCI_CLK_CTRL,
|
|
(reg_read(CCI_CLK_CTRL) &
|
|
~MCU_MISCCFG_BUS_CLOCK_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_BUS_CLOCK_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcu_misccfg_bus_clock_dcm'" */
|
|
reg_write(CCI_CLK_CTRL,
|
|
(reg_read(CCI_CLK_CTRL) &
|
|
~MCU_MISCCFG_BUS_CLOCK_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_BUS_CLOCK_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MCU_MISCCFG_BUS_FABRIC_DCM_REG0_MASK ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 2) | \
|
|
(0x1 << 3) | \
|
|
(0x1 << 4) | \
|
|
(0x1 << 5) | \
|
|
(0x1 << 8) | \
|
|
(0x1 << 9) | \
|
|
(0x1 << 10) | \
|
|
(0x1 << 11) | \
|
|
(0x1 << 12) | \
|
|
(0x1 << 18) | \
|
|
(0x1 << 21))
|
|
#define MCU_MISCCFG_BUS_FABRIC_DCM_REG0_ON ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 2) | \
|
|
(0x1 << 3) | \
|
|
(0x1 << 4) | \
|
|
(0x1 << 5) | \
|
|
(0x1 << 8) | \
|
|
(0x1 << 9) | \
|
|
(0x1 << 10) | \
|
|
(0x1 << 11) | \
|
|
(0x1 << 12) | \
|
|
(0x1 << 18) | \
|
|
(0x1 << 21))
|
|
#define MCU_MISCCFG_BUS_FABRIC_DCM_REG0_OFF ((0x0 << 0) | \
|
|
(0x0 << 1) | \
|
|
(0x0 << 2) | \
|
|
(0x0 << 3) | \
|
|
(0x0 << 4) | \
|
|
(0x0 << 5) | \
|
|
(0x0 << 8) | \
|
|
(0x0 << 9) | \
|
|
(0x0 << 10) | \
|
|
(0x0 << 11) | \
|
|
(0x0 << 12) | \
|
|
(0x0 << 18) | \
|
|
(0x0 << 21))
|
|
|
|
bool dcm_mcu_misccfg_bus_fabric_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(BUS_FABRIC_DCM_CTRL) &
|
|
MCU_MISCCFG_BUS_FABRIC_DCM_REG0_MASK) ==
|
|
(unsigned int) MCU_MISCCFG_BUS_FABRIC_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcu_misccfg_bus_fabric_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcu_misccfg_bus_fabric_dcm'" */
|
|
reg_write(BUS_FABRIC_DCM_CTRL,
|
|
(reg_read(BUS_FABRIC_DCM_CTRL) &
|
|
~MCU_MISCCFG_BUS_FABRIC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_BUS_FABRIC_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcu_misccfg_bus_fabric_dcm'" */
|
|
reg_write(BUS_FABRIC_DCM_CTRL,
|
|
(reg_read(BUS_FABRIC_DCM_CTRL) &
|
|
~MCU_MISCCFG_BUS_FABRIC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_BUS_FABRIC_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MCU_MISCCFG_GIC_SYNC_DCM_REG0_MASK ((0x1 << 0))
|
|
#define MCU_MISCCFG_GIC_SYNC_DCM_REG0_ON ((0x1 << 0))
|
|
#define MCU_MISCCFG_GIC_SYNC_DCM_REG0_OFF ((0x0 << 0))
|
|
|
|
bool dcm_mcu_misccfg_gic_sync_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MP_GIC_RGU_SYNC_DCM) &
|
|
MCU_MISCCFG_GIC_SYNC_DCM_REG0_MASK) ==
|
|
(unsigned int) MCU_MISCCFG_GIC_SYNC_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcu_misccfg_gic_sync_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcu_misccfg_gic_sync_dcm'" */
|
|
reg_write(MP_GIC_RGU_SYNC_DCM,
|
|
(reg_read(MP_GIC_RGU_SYNC_DCM) &
|
|
~MCU_MISCCFG_GIC_SYNC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_GIC_SYNC_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcu_misccfg_gic_sync_dcm'" */
|
|
reg_write(MP_GIC_RGU_SYNC_DCM,
|
|
(reg_read(MP_GIC_RGU_SYNC_DCM) &
|
|
~MCU_MISCCFG_GIC_SYNC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_GIC_SYNC_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MCU_MISCCFG_L2_SHARED_DCM_REG0_MASK ((0x1 << 0))
|
|
#define MCU_MISCCFG_L2_SHARED_DCM_REG0_ON ((0x1 << 0))
|
|
#define MCU_MISCCFG_L2_SHARED_DCM_REG0_OFF ((0x0 << 0))
|
|
|
|
bool dcm_mcu_misccfg_l2_shared_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(L2C_SRAM_CTRL) &
|
|
MCU_MISCCFG_L2_SHARED_DCM_REG0_MASK) ==
|
|
(unsigned int) MCU_MISCCFG_L2_SHARED_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcu_misccfg_l2_shared_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcu_misccfg_l2_shared_dcm'" */
|
|
reg_write(L2C_SRAM_CTRL,
|
|
(reg_read(L2C_SRAM_CTRL) &
|
|
~MCU_MISCCFG_L2_SHARED_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_L2_SHARED_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcu_misccfg_l2_shared_dcm'" */
|
|
reg_write(L2C_SRAM_CTRL,
|
|
(reg_read(L2C_SRAM_CTRL) &
|
|
~MCU_MISCCFG_L2_SHARED_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_L2_SHARED_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define MCU_MISCCFG_MCU_MISC_DCM_REG0_MASK ((0x1 << 0))
|
|
#define MCU_MISCCFG_MCU_MISC_DCM_REG0_ON ((0x1 << 0))
|
|
#define MCU_MISCCFG_MCU_MISC_DCM_REG0_OFF ((0x0 << 0))
|
|
|
|
bool dcm_mcu_misccfg_mcu_misc_dcm_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(MCU_MISC_DCM_CTRL) &
|
|
MCU_MISCCFG_MCU_MISC_DCM_REG0_MASK) ==
|
|
(unsigned int) MCU_MISCCFG_MCU_MISC_DCM_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_mcu_misccfg_mcu_misc_dcm(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'mcu_misccfg_mcu_misc_dcm'" */
|
|
reg_write(MCU_MISC_DCM_CTRL,
|
|
(reg_read(MCU_MISC_DCM_CTRL) &
|
|
~MCU_MISCCFG_MCU_MISC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_MCU_MISC_DCM_REG0_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'mcu_misccfg_mcu_misc_dcm'" */
|
|
reg_write(MCU_MISC_DCM_CTRL,
|
|
(reg_read(MCU_MISC_DCM_CTRL) &
|
|
~MCU_MISCCFG_MCU_MISC_DCM_REG0_MASK) |
|
|
MCU_MISCCFG_MCU_MISC_DCM_REG0_OFF);
|
|
}
|
|
}
|
|
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG0_MASK ((0x1 << 8) | \
|
|
(0x1 << 9) | \
|
|
(0x1 << 10) | \
|
|
(0x1 << 11) | \
|
|
(0x1 << 12) | \
|
|
(0x1 << 13) | \
|
|
(0x1 << 14) | \
|
|
(0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 19))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG1_MASK ((0x1 << 6) | \
|
|
(0x1 << 7) | \
|
|
(0x1 << 26))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG2_MASK ((0x1 << 26) | \
|
|
(0x1 << 27))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG0_ON ((0x0 << 8) | \
|
|
(0x0 << 9) | \
|
|
(0x0 << 10) | \
|
|
(0x0 << 11) | \
|
|
(0x0 << 12) | \
|
|
(0x0 << 13) | \
|
|
(0x0 << 14) | \
|
|
(0x0 << 15) | \
|
|
(0x0 << 16) | \
|
|
(0x0 << 17) | \
|
|
(0x0 << 19))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG1_ON ((0x0 << 6) | \
|
|
(0x0 << 7) | \
|
|
(0x0 << 26))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG2_ON ((0x0 << 26) | \
|
|
(0x0 << 27))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG0_OFF ((0x1 << 8) | \
|
|
(0x1 << 9) | \
|
|
(0x1 << 10) | \
|
|
(0x1 << 11) | \
|
|
(0x1 << 12) | \
|
|
(0x1 << 13) | \
|
|
(0x1 << 14) | \
|
|
(0x1 << 15) | \
|
|
(0x1 << 16) | \
|
|
(0x1 << 17) | \
|
|
(0x1 << 19))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG1_OFF ((0x1 << 6) | \
|
|
(0x1 << 7) | \
|
|
(0x0 << 26))
|
|
#define DRAMC_CH0_TOP0_DDRPHY_REG2_OFF ((0x1 << 26) | \
|
|
(0x1 << 27))
|
|
|
|
static void dramc_ch0_top0_rg_mem_dcm_idle_fsel_set(unsigned int val)
|
|
{
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL2,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
|
|
~(0x1f << 21)) |
|
|
(val & 0x1f) << 21);
|
|
}
|
|
|
|
bool dcm_dramc_ch0_top0_ddrphy_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
|
|
DRAMC_CH0_TOP0_DDRPHY_REG0_MASK) ==
|
|
(unsigned int) DRAMC_CH0_TOP0_DDRPHY_REG0_ON);
|
|
ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
|
|
DRAMC_CH0_TOP0_DDRPHY_REG1_MASK) ==
|
|
(unsigned int) DRAMC_CH0_TOP0_DDRPHY_REG1_ON);
|
|
ret &= ((reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
|
|
DRAMC_CH0_TOP0_DDRPHY_REG2_MASK) ==
|
|
(unsigned int) DRAMC_CH0_TOP0_DDRPHY_REG2_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_dramc_ch0_top0_ddrphy(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'dramc_ch0_top0_ddrphy'" */
|
|
dramc_ch0_top0_rg_mem_dcm_idle_fsel_set(0x8);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL0,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG0_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG0_ON);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL2,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG1_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG1_ON);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CTRL3,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG2_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG2_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'dramc_ch0_top0_ddrphy'" */
|
|
dramc_ch0_top0_rg_mem_dcm_idle_fsel_set(0x0);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL0,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL0) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG0_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG0_OFF);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CG_CTRL2,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CG_CTRL2) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG1_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG1_OFF);
|
|
reg_write(DRAMC_CH0_TOP0_MISC_CTRL3,
|
|
(reg_read(DRAMC_CH0_TOP0_MISC_CTRL3) &
|
|
~DRAMC_CH0_TOP0_DDRPHY_REG2_MASK) |
|
|
DRAMC_CH0_TOP0_DDRPHY_REG2_OFF);
|
|
}
|
|
}
|
|
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_MASK ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 2) | \
|
|
(0x1 << 26) | \
|
|
(0x1 << 30) | \
|
|
(0x1 << 31))
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_MASK ((0x1 << 31))
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_ON ((0x1 << 0) | \
|
|
(0x1 << 1) | \
|
|
(0x1 << 2) | \
|
|
(0x0 << 26) | \
|
|
(0x1 << 30) | \
|
|
(0x1 << 31))
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_ON ((0x1 << 31))
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_OFF ((0x0 << 0) | \
|
|
(0x0 << 1) | \
|
|
(0x0 << 2) | \
|
|
(0x1 << 26) | \
|
|
(0x0 << 30) | \
|
|
(0x0 << 31))
|
|
#define DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_OFF ((0x0 << 31))
|
|
|
|
bool dcm_dramc_ch0_top1_dcm_dramc_group_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_MASK) ==
|
|
(unsigned int) DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_ON);
|
|
ret &= ((reg_read(DRAMC_CH0_TOP1_CLKAR) &
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_MASK) ==
|
|
(unsigned int) DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_dramc_ch0_top1_dcm_dramc_group(int on)
|
|
{
|
|
if (on) {
|
|
/* TINFO = "Turn ON DCM 'dramc_ch0_top1_dcm_dramc_group'" */
|
|
reg_write(DRAMC_CH0_TOP1_DRAMC_PD_CTRL,
|
|
(reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
|
|
~DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_MASK) |
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_ON);
|
|
reg_write(DRAMC_CH0_TOP1_CLKAR,
|
|
(reg_read(DRAMC_CH0_TOP1_CLKAR) &
|
|
~DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_MASK) |
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_ON);
|
|
} else {
|
|
/* TINFO = "Turn OFF DCM 'dramc_ch0_top1_dcm_dramc_group'" */
|
|
reg_write(DRAMC_CH0_TOP1_DRAMC_PD_CTRL,
|
|
(reg_read(DRAMC_CH0_TOP1_DRAMC_PD_CTRL) &
|
|
~DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_MASK) |
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG0_OFF);
|
|
reg_write(DRAMC_CH0_TOP1_CLKAR,
|
|
(reg_read(DRAMC_CH0_TOP1_CLKAR) &
|
|
~DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_MASK) |
|
|
DRAMC_CH0_TOP1_DCM_DRAMC_GROUP_REG1_OFF);
|
|
}
|
|
}
|
|
|
|
#define CHN0_EMI_DCM_EMI_GROUP_REG0_MASK ((0xff << 24))
|
|
#define CHN0_EMI_DCM_EMI_GROUP_REG0_ON ((0x0 << 24))
|
|
#define CHN0_EMI_DCM_EMI_GROUP_REG0_OFF ((0xff << 24))
|
|
|
|
bool dcm_chn0_emi_dcm_emi_group_is_on(void)
|
|
{
|
|
bool ret = true;
|
|
|
|
ret &= ((reg_read(CHN0_EMI_CHN_EMI_CONB) &
|
|
CHN0_EMI_DCM_EMI_GROUP_REG0_MASK) ==
|
|
(unsigned int) CHN0_EMI_DCM_EMI_GROUP_REG0_ON);
|
|
|
|
return ret;
|
|
}
|
|
|
|
void dcm_chn0_emi_dcm_emi_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'chn0_emi_dcm_emi_group'" */
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reg_write(CHN0_EMI_CHN_EMI_CONB,
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(reg_read(CHN0_EMI_CHN_EMI_CONB) &
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~CHN0_EMI_DCM_EMI_GROUP_REG0_MASK) |
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CHN0_EMI_DCM_EMI_GROUP_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'chn0_emi_dcm_emi_group'" */
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reg_write(CHN0_EMI_CHN_EMI_CONB,
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(reg_read(CHN0_EMI_CHN_EMI_CONB) &
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~CHN0_EMI_DCM_EMI_GROUP_REG0_MASK) |
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CHN0_EMI_DCM_EMI_GROUP_REG0_OFF);
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}
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}
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#define DRAMC_CH1_TOP0_DDRPHY_REG0_MASK ((0x1 << 8) | \
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(0x1 << 9) | \
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(0x1 << 10) | \
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(0x1 << 11) | \
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(0x1 << 12) | \
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(0x1 << 13) | \
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(0x1 << 14) | \
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(0x1 << 15) | \
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(0x1 << 16) | \
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(0x1 << 17) | \
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(0x1 << 19))
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#define DRAMC_CH1_TOP0_DDRPHY_REG1_MASK ((0x1 << 6) | \
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(0x1 << 7) | \
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(0x1 << 26))
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#define DRAMC_CH1_TOP0_DDRPHY_REG2_MASK ((0x1 << 26) | \
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(0x1 << 27))
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#define DRAMC_CH1_TOP0_DDRPHY_REG0_ON ((0x0 << 8) | \
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(0x0 << 9) | \
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(0x0 << 10) | \
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(0x0 << 11) | \
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(0x0 << 12) | \
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(0x0 << 13) | \
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(0x0 << 14) | \
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(0x0 << 15) | \
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(0x0 << 16) | \
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(0x0 << 17) | \
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(0x0 << 19))
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#define DRAMC_CH1_TOP0_DDRPHY_REG1_ON ((0x0 << 6) | \
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(0x0 << 7) | \
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(0x0 << 26))
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#define DRAMC_CH1_TOP0_DDRPHY_REG2_ON ((0x0 << 26) | \
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(0x0 << 27))
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#define DRAMC_CH1_TOP0_DDRPHY_REG0_OFF ((0x1 << 8) | \
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(0x1 << 9) | \
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(0x1 << 10) | \
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(0x1 << 11) | \
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(0x1 << 12) | \
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(0x1 << 13) | \
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(0x1 << 14) | \
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(0x1 << 15) | \
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(0x1 << 16) | \
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(0x1 << 17) | \
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(0x1 << 19))
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#define DRAMC_CH1_TOP0_DDRPHY_REG1_OFF ((0x1 << 6) | \
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(0x1 << 7) | \
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(0x0 << 26))
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#define DRAMC_CH1_TOP0_DDRPHY_REG2_OFF ((0x1 << 26) | \
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(0x1 << 27))
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static void dramc_ch1_top0_rg_mem_dcm_idle_fsel_set(unsigned int val)
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{
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reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL2,
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(reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2) &
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~(0x1f << 21)) |
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(val & 0x1f) << 21);
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}
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bool dcm_dramc_ch1_top0_ddrphy_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0) &
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DRAMC_CH1_TOP0_DDRPHY_REG0_MASK) ==
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(unsigned int) DRAMC_CH1_TOP0_DDRPHY_REG0_ON);
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ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2) &
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DRAMC_CH1_TOP0_DDRPHY_REG1_MASK) ==
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(unsigned int) DRAMC_CH1_TOP0_DDRPHY_REG1_ON);
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ret &= ((reg_read(DRAMC_CH1_TOP0_MISC_CTRL3) &
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DRAMC_CH1_TOP0_DDRPHY_REG2_MASK) ==
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(unsigned int) DRAMC_CH1_TOP0_DDRPHY_REG2_ON);
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return ret;
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}
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void dcm_dramc_ch1_top0_ddrphy(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'dramc_ch1_top0_ddrphy'" */
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dramc_ch1_top0_rg_mem_dcm_idle_fsel_set(0x8);
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reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL0,
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(reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0) &
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~DRAMC_CH1_TOP0_DDRPHY_REG0_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG0_ON);
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reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL2,
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(reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2) &
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~DRAMC_CH1_TOP0_DDRPHY_REG1_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG1_ON);
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reg_write(DRAMC_CH1_TOP0_MISC_CTRL3,
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(reg_read(DRAMC_CH1_TOP0_MISC_CTRL3) &
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~DRAMC_CH1_TOP0_DDRPHY_REG2_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG2_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'dramc_ch1_top0_ddrphy'" */
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dramc_ch1_top0_rg_mem_dcm_idle_fsel_set(0x0);
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reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL0,
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(reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL0) &
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~DRAMC_CH1_TOP0_DDRPHY_REG0_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG0_OFF);
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reg_write(DRAMC_CH1_TOP0_MISC_CG_CTRL2,
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(reg_read(DRAMC_CH1_TOP0_MISC_CG_CTRL2) &
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~DRAMC_CH1_TOP0_DDRPHY_REG1_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG1_OFF);
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reg_write(DRAMC_CH1_TOP0_MISC_CTRL3,
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(reg_read(DRAMC_CH1_TOP0_MISC_CTRL3) &
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~DRAMC_CH1_TOP0_DDRPHY_REG2_MASK) |
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DRAMC_CH1_TOP0_DDRPHY_REG2_OFF);
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}
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}
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_MASK ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x1 << 26) | \
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(0x1 << 30) | \
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(0x1 << 31))
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_MASK ((0x1 << 31))
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_ON ((0x1 << 0) | \
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(0x1 << 1) | \
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(0x1 << 2) | \
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(0x0 << 26) | \
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(0x1 << 30) | \
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(0x1 << 31))
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_ON ((0x1 << 31))
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_OFF ((0x0 << 0) | \
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(0x0 << 1) | \
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(0x0 << 2) | \
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(0x1 << 26) | \
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(0x0 << 30) | \
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(0x0 << 31))
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#define DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_OFF ((0x0 << 31))
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bool dcm_dramc_ch1_top1_dcm_dramc_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL) &
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_MASK) ==
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(unsigned int) DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_ON);
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ret &= ((reg_read(DRAMC_CH1_TOP1_CLKAR) &
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_MASK) ==
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(unsigned int) DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_ON);
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return ret;
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}
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void dcm_dramc_ch1_top1_dcm_dramc_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'dramc_ch1_top1_dcm_dramc_group'" */
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reg_write(DRAMC_CH1_TOP1_DRAMC_PD_CTRL,
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(reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL) &
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~DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_MASK) |
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_ON);
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reg_write(DRAMC_CH1_TOP1_CLKAR,
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(reg_read(DRAMC_CH1_TOP1_CLKAR) &
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~DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_MASK) |
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'dramc_ch1_top1_dcm_dramc_group'" */
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reg_write(DRAMC_CH1_TOP1_DRAMC_PD_CTRL,
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(reg_read(DRAMC_CH1_TOP1_DRAMC_PD_CTRL) &
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~DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_MASK) |
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG0_OFF);
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reg_write(DRAMC_CH1_TOP1_CLKAR,
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(reg_read(DRAMC_CH1_TOP1_CLKAR) &
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~DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_MASK) |
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DRAMC_CH1_TOP1_DCM_DRAMC_GROUP_REG1_OFF);
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}
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}
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#define CHN1_EMI_DCM_EMI_GROUP_REG0_MASK ((0xff << 24))
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#define CHN1_EMI_DCM_EMI_GROUP_REG0_ON ((0x0 << 24))
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#define CHN1_EMI_DCM_EMI_GROUP_REG0_OFF ((0xff << 24))
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bool dcm_chn1_emi_dcm_emi_group_is_on(void)
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{
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bool ret = true;
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ret &= ((reg_read(CHN1_EMI_CHN_EMI_CONB) &
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CHN1_EMI_DCM_EMI_GROUP_REG0_MASK) ==
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(unsigned int) CHN1_EMI_DCM_EMI_GROUP_REG0_ON);
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return ret;
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}
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void dcm_chn1_emi_dcm_emi_group(int on)
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{
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if (on) {
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/* TINFO = "Turn ON DCM 'chn1_emi_dcm_emi_group'" */
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reg_write(CHN1_EMI_CHN_EMI_CONB,
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(reg_read(CHN1_EMI_CHN_EMI_CONB) &
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~CHN1_EMI_DCM_EMI_GROUP_REG0_MASK) |
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CHN1_EMI_DCM_EMI_GROUP_REG0_ON);
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} else {
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/* TINFO = "Turn OFF DCM 'chn1_emi_dcm_emi_group'" */
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reg_write(CHN1_EMI_CHN_EMI_CONB,
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(reg_read(CHN1_EMI_CHN_EMI_CONB) &
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~CHN1_EMI_DCM_EMI_GROUP_REG0_MASK) |
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CHN1_EMI_DCM_EMI_GROUP_REG0_OFF);
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}
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}
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