111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/printk.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <memory/mediatek/dramc.h>
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#include <linux/bug.h>
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#include <mt-plat/sync_write.h>
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#include "mtk_dramc_wa.h"
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#define APXGPT_OF_COMPTIBLE_NAME "mediatek,apxgpt"
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static struct mt_gpt_timers gpt_timers;
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static irqreturn_t dramc_apxgpt3_irq_handler(int irq, void *dev_id)
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{
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/* pr_info("%s\n", __func__); */
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/* 1. Stop and clear GPT */
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mt_reg_sync_writel(GPT3_STOP_CLEAR, GPT3_CON);
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/* 2. Clear pending irq */
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mt_reg_sync_writel(GPT3_IRQ_BIT, GPT_IRQ_ACK);
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/* 3. Configure GPT divider to 1 and using 32K clock source */
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mt_reg_sync_writel(GPT3_RTC_CLK, GPT3_CLK);
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/* 4. Calculate and Set compare value */
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mt_reg_sync_writel(32768*1000/1000, GPT3_CMP_L);
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/* 5. Set GTP3 SPE */
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mt_reg_sync_writel(GPT3_IRQ_SPE, GPT3_SPE);
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/* 6. Enabel IRQ En */
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mt_reg_sync_writel(GPT3_IRQ_BIT, GPT_IRQ_EN);
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return IRQ_HANDLED;
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}
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static int dramc_apxgpt3_init(void)
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{
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struct device_node *node;
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int ret = 0;
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const struct of_device_id apxgpt_of_match[] = {
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{ .compatible = APXGPT_OF_COMPTIBLE_NAME, },
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};
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node = of_find_compatible_node(NULL, NULL,
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apxgpt_of_match[0].compatible);
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if (!node) {
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pr_info("%s: node not found\n", __func__);
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return -1;
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}
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/* Setup IRQ numbers */
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gpt_timers.tmr_irq = irq_of_parse_and_map(node, 0);
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/* Setup IO addresses */
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gpt_timers.tmr_regs = of_iomap(node, 0);
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pr_info("%s: base=0x%lx, irq=%d\n", __func__,
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(unsigned long)gpt_timers.tmr_regs, gpt_timers.tmr_irq);
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/* 1. Stop and clear GPT */
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mt_reg_sync_writel(GPT3_STOP_CLEAR, GPT3_CON);
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/* 2. Clear pending irq */
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mt_reg_sync_writel(GPT3_IRQ_BIT, GPT_IRQ_ACK);
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/* 3. Configure GPT divider to 1 and using 32K clock source */
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mt_reg_sync_writel(GPT3_RTC_CLK, GPT3_CLK);
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/* 4. Calculate and Set compare value */
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mt_reg_sync_writel(32768*1000/1000, GPT3_CMP_L);
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/* 5. Set GPT3 SPE */
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mt_reg_sync_writel(GPT3_IRQ_SPE, GPT3_SPE);
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/* 6. Enabel IRQ En */
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mt_reg_sync_writel(GPT3_IRQ_BIT, GPT_IRQ_EN);
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ret = request_irq(gpt_timers.tmr_irq, dramc_apxgpt3_irq_handler,
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IRQF_TIMER | IRQF_IRQPOLL | IRQF_PERCPU,
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"dramc_apxgpt3", NULL);
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if (ret) {
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pr_info("%s: apxgpt3 request irq Failed ret =%d\n",
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__func__, ret);
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return ret;
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}
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/* pr_info("%s: enable apxgpt3 one-shot", __func__); */
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/* 7. Start GPT one-shot */
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/* mt_reg_sync_writel(GPT3_ONE_SHOT_EN, GPT3_CON); */
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return 0;
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}
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late_initcall(dramc_apxgpt3_init);
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MODULE_DESCRIPTION("MediaTek DRAMC WA Driver v0.1");
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