1608 lines
54 KiB
C
1608 lines
54 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MPU_PLATFORM_H__
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#define __MPU_PLATFORM_H__
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enum {
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MT6885_M4_AXI_MST_IRDMA,
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MT6885_M7_AXI_MST_SPI1,
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MT6885_M5_AXI_MST_WPE1_RDMA1,
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MT6885_M4_AXI_MST_DMA_RD,
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MT6885_M7_AXI_MST_SSPM,
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MT6885_M5_AXI_MST_FDVT_RB,
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MT6885_M2_AXI_MST_LSCI_1,
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MT6885_M2_AXI_MST_RSC_WDMA,
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MT6885_M4_AXI_MST_LOG_TOP_MCU,
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MT6885_M4_AXI_MST_DCXO,
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MT6885_M7_AXI_MST_CCU,
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MT6885_M5_AXI_MST_RSC_RDMA0,
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MT6885_M2_AXI_MST_WPE1_RDMA1,
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MT6885_M5_AXI_MST_DPE_RDMA,
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MT6885_M4_AXI_MST_CSH,
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MT6885_M7_AXI_MST_DMA_EXT,
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MT6885_M2_AXI_MST_OWE_WDMA,
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MT6885_M6_AXI_MST_MFG_M0,
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MT6885_M5_AXI_MST_HW_VDEC_PRED_RD_EXT,
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MT6885_M2_AXI_MST_WPE0_RDMA1,
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MT6885_M3_AXI_MST_MD_MM,
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MT6885_M7_AXI_MST_CQ_DMA,
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MT6885_M7_AXI_MST_SPI3,
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MT6885_M4_AXI_MST_IPSEC,
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MT6885_M2_AXI_MST_WPE1_WDMA,
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MT6885_M5_AXI_MST_JPGENC_BSDMA,
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MT6885_M2_AXI_MST_IPUI,
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MT6885_M2_AXI_MST_IMG3O,
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MT6885_M5_AXI_MST_DISP_RDMA1,
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MT6885_M5_AXI_MST_CCUO,
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MT6885_M7_AXI_MST_SPI5,
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MT6885_M2_AXI_MST_DISP_RDMA1,
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MT6885_M5_AXI_MST_VENC_REF_CHROMA,
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MT6885_M4_AXI_MST_MCUSYS_DFD,
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MT6885_M7_AXI_MST_DX_CC,
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MT6885_M2_AXI_MST_CCUO,
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MT6885_M4_AXI_MST_DBGSYS,
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MT6885_M7_AXI_MST_IPU,
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MT6885_M5_AXI_MST_SPARE2,
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MT6885_M2_AXI_MST_MM_IOMMU,
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MT6885_M5_AXI_MST_IPUI,
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MT6885_M0_AXI_MST_MP1,
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MT6885_M5_AXI_MST_FLKO,
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MT6885_M5_AXI_MST_IPU2I,
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MT6885_M2_AXI_MST_HW_VDEC_PRED_WR_EXT,
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MT6885_M2_AXI_MST_DISP_OVL0,
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MT6885_M5_AXI_MST_SPARE4,
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MT6885_M5_AXI_MST_LMVO,
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MT6885_M5_AXI_MST_AAO,
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MT6885_M5_AXI_MST_BPCI,
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MT6885_M2_AXI_MST_FLKO,
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MT6885_M2_AXI_MST_HW_VDEC_VLD_EXT,
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MT6885_M2_AXI_MST_MDP_WDMA0,
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MT6885_M7_AXI_MST_MFG_M1,
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MT6885_M2_AXI_MST_IPU2I,
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MT6885_M5_AXI_MST_HW_VDEC_AVC_MV_EXT,
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MT6885_M2_AXI_MST_LMVO,
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MT6885_M2_AXI_MST_IPUO,
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MT6885_M4_AXI_MST_HRQ_WR,
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MT6885_M2_AXI_MST_HW_VDEC_PPWRAP_EXT,
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MT6885_M2_AXI_MST_MDP_RDMA0,
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MT6885_M5_AXI_MST_SPARE6,
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MT6885_M2_AXI_MST_BPCI,
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MT6885_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
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MT6885_M5_AXI_MST_MFB_RDMA1,
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MT6885_M5_AXI_MST_WPE0_WDMA,
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MT6885_M2_AXI_MST_SPARE2,
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MT6885_M2_AXI_MST_DPE_WDMA,
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MT6885_M5_AXI_MST_PSO,
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MT6885_M5_AXI_MST_RRZO,
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MT6885_M2_AXI_MST_PDI,
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MT6885_M2_AXI_MST_DISP_OVL0_2L,
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MT6885_M4_AXI_MST_MMU,
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MT6885_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
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MT6885_M2_AXI_MST_RRZO,
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MT6885_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
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MT6885_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
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MT6885_M5_AXI_MST_DISP_FAKE,
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MT6885_M5_AXI_MST_AFO,
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MT6885_M2_AXI_MST_SPARE4,
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MT6885_M3_AXI_MST_MD_MMU,
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MT6885_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
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MT6885_M2_AXI_MST_VENC_REC,
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MT6885_M4_AXI_MST_TXBRP1,
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MT6885_M5_AXI_MST_SMXI,
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MT6885_M5_AXI_MST_IPUO,
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MT6885_M7_AXI_MST_SCP,
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MT6885_M5_AXI_MST_LSCI_0,
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MT6885_M5_AXI_MST_IPU2O,
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MT6885_M7_AXI_MST_CLDMA,
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MT6885_M5_AXI_MST_SOC2,
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MT6885_M5_AXI_MST_HW_VDEC_PP_EXT,
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MT6885_M2_AXI_MST_OWE_RDMA,
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MT6885_M2_AXI_MST_RSC_RDMA0,
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MT6885_M2_AXI_MST_SMXI,
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MT6885_M5_AXI_MST_RSSO_A,
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MT6885_M5_AXI_MST_WPE0_RDMA0,
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MT6885_M2_AXI_MST_SPARE6,
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MT6885_M2_AXI_MST_HW_VDEC_MC_EXT,
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MT6885_M5_AXI_MST_HW_VDEC_PRED_WR_EXT,
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MT6885_M5_AXI_MST_SPARE,
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MT6885_M5_AXI_MST_FDVT_RP,
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MT6885_M5_AXI_MST_IMGI,
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MT6885_M4_AXI_MST_BR_DMA,
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MT6885_M7_AXI_MST_UFS,
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MT6885_M7_AXI_MST_MSDC1,
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MT6885_M2_AXI_MST_SOC2,
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MT6885_M2_AXI_MST_IPU2O,
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MT6885_M4_AXI_MST_TRACE_TOP,
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MT6885_M5_AXI_MST_HW_VDEC_PPWRAP_EXT,
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MT6885_M5_AXI_MST_LSCI_2,
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MT6885_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
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MT6885_M2_AXI_MST_FDVT_RB,
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MT6885_M5_AXI_MST_RSC_WDMA,
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MT6885_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
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MT6885_M2_AXI_MST_IMGI,
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MT6885_M5_AXI_MST_RAWI_A,
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MT6885_M2_AXI_MST_DISP_OVL1_2L,
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MT6885_M1_AXI_MST_MP1,
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MT6885_M2_AXI_MST_PDO,
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MT6885_M4_AXI_MST_GDMA,
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MT6885_M7_AXI_MST_AUDIO,
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MT6885_M5_AXI_MST_OWE_WDMA,
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MT6885_M5_AXI_MST_VIPI,
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MT6885_M2_AXI_MST_MFB_WDMA,
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MT6885_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
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MT6885_M7_AXI_MST_THERM,
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MT6885_M7_AXI_MST_SPI0,
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MT6885_M5_AXI_MST_UFEO,
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MT6885_M5_AXI_MST_WPE1_RDMA0,
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MT6885_M2_AXI_MST_LSCI_0,
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MT6885_M4_AXI_MST_HRQ_WR1,
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MT6885_M2_AXI_MST_WPE1_RDMA0,
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MT6885_M2_AXI_MST_VIPI,
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MT6885_M4_AXI_MST_DMA_WR,
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MT6885_M3_AXI_MST_USIP_0_DNOCACHE,
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MT6885_M7_AXI_MST_PWM,
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MT6885_M2_AXI_MST_RSSO_A,
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MT6885_M2_AXI_MST_MFB_RDMA1,
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MT6885_M4_AXI_MST_MRSG1,
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MT6885_M5_AXI_MST_SMXO,
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MT6885_M2_AXI_MST_UFEO,
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MT6885_M3_AXI_MST_USIP_1_DCACHE,
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MT6885_M2_AXI_MST_WPE0_RDMA0,
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MT6885_M7_AXI_MST_SPI2,
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MT6885_M2_AXI_MST_LSCI_2,
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MT6885_M2_AXI_MST_SMXO,
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MT6885_M4_AXI_MST_PPPHA,
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MT6885_M5_AXI_MST_DISP_WDMA0,
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MT6885_M2_AXI_MST_DISP_FAKE,
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MT6885_M7_AXI_MST_SSUSB,
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MT6885_M5_AXI_MST_FDVT_WR,
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MT6885_M2_AXI_MST_RAWI_A,
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MT6885_M3_AXI_MST_USIP_0_DCACHE,
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MT6885_M5_AXI_MST_IMGO,
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MT6885_M5_AXI_MST_MDP_WROT0,
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MT6885_M2_AXI_MST_SPARE,
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MT6885_M2_AXI_MST_VENC_REF_CHROMA,
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MT6885_M2_AXI_MST_DISP_WDMA0,
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MT6885_M2_AXI_MST_JPGENC_BSDMA,
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MT6885_M5_AXI_MST_DISP_RDMA0,
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MT6885_M2_AXI_MST_AAO,
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MT6885_M4_AXI_MST_TXCAL,
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MT6885_M5_AXI_MST_MM_IOMMU,
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MT6885_M5_AXI_MST_LCEI,
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MT6885_M7_AXI_MST_GCE_M,
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MT6885_M7_AXI_MST_SPI4,
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MT6885_M5_AXI_MST_IPU3O,
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MT6885_M2_AXI_MST_DISP_RDMA0,
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MT6885_M2_AXI_MST_IMGO,
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MT6885_M2_AXI_MST_DPE_RDMA,
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MT6885_M2_AXI_MST_LCEI,
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MT6885_M4_AXI_MST_TPC,
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MT6885_M4_AXI_MST_DEBUG,
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MT6885_M2_AXI_MST_WPE0_WDMA,
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MT6885_M2_AXI_MST_IPU3O,
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MT6885_M5_AXI_MST_AFO_1,
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MT6885_M7_AXI_MST_SPM,
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MT6885_M0_AXI_MST_MP0,
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MT6885_M3_AXI_MST_USIP_1_I,
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MT6885_M5_AXI_MST_SOCO,
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MT6885_M2_AXI_MST_AFO,
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MT6885_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
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MT6885_M5_AXI_MST_SPARE3,
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MT6885_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
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MT6885_M5_AXI_MST_DPE_WDMA,
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MT6885_M4_AXI_MST_RXDFE_DMA,
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MT6885_M5_AXI_MST_IMG2O,
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MT6885_M2_AXI_MST_SOCO,
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MT6885_M5_AXI_MST_WPE1_WDMA,
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MT6885_M5_AXI_MST_JPGENC_RDMA,
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MT6885_M5_AXI_MST_SPARE5,
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MT6885_M5_AXI_MST_MFB_RDMA0,
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MT6885_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
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MT6885_M4_AXI_MST_DFE_DUMP,
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MT6885_M5_AXI_MST_VENC_REC,
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MT6885_M2_AXI_MST_PSO,
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MT6885_M4_AXI_MST_VTB,
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MT6885_M4_AXI_MST_HRQ_RD,
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MT6885_M3_AXI_MST_USIP_0_I,
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MT6885_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
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MT6885_M4_AXI_MST_CNWDMA,
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MT6885_M5_AXI_MST_DISP_OVL0_2L,
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MT6885_M2_AXI_MST_SPARE3,
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MT6885_M5_AXI_MST_PDI,
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MT6885_M2_AXI_MST_AFO_1,
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MT6885_M2_AXI_MST_FDVT_RP,
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MT6885_M4_AXI_MST_TXBRP0,
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MT6885_M5_AXI_MST_LCSO,
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MT6885_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
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MT6885_M5_AXI_MST_HW_VDEC_MC_EXT,
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MT6885_M5_AXI_MST_SOC1,
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MT6885_M5_AXI_MST_DISP_OVL0,
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MT6885_M2_AXI_MST_SPARE5,
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MT6885_M4_AXI_MST_TBO,
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MT6885_M2_AXI_MST_LCSO,
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MT6885_M2_AXI_MST_HW_VDEC_PRED_RD_EXT,
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MT6885_M2_AXI_MST_IMG2O,
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MT6885_M7_AXI_MST_MSDC0,
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MT6885_M5_AXI_MST_MFB_WDMA,
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MT6885_M5_AXI_MST_MDP_WDMA0,
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MT6885_M2_AXI_MST_SOC1,
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MT6885_M5_AXI_MST_CCUG,
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MT6885_M2_AXI_MST_JPGENC_RDMA,
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MT6885_M5_AXI_MST_LSCI_1,
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MT6885_M4_AXI_MST_QP,
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MT6885_M5_AXI_MST_MDP_RDMA0,
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MT6885_M5_AXI_MST_WPE0_RDMA1,
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MT6885_M1_AXI_MST_MP0,
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MT6885_M4_AXI_MST_HRQ_RD1,
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MT6885_M5_AXI_MST_UFGO,
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MT6885_M5_AXI_MST_OWE_RDMA,
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MT6885_M5_AXI_MST_HW_VDEC_VLD_EXT,
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MT6885_M2_AXI_MST_CCUG,
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MT6885_M2_AXI_MST_HW_VDEC_PP_EXT,
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MT6885_M2_AXI_MST_MDP_WROT0,
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MT6885_M5_AXI_MST_IMG3O,
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MT6885_M7_AXI_MST_MSDC2,
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MT6885_M7_AXI_MST_DEBUGTOP,
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MT6885_M5_AXI_MST_CCUI,
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MT6885_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
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MT6885_M5_AXI_MST_DISP_OVL1_2L,
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MT6885_M2_AXI_MST_UFGO,
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MT6885_M4_AXI_MST_LOG_TOP_DSP,
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MT6885_M3_AXI_MST_USIP_1_DNOCACHE,
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MT6885_M2_AXI_MST_FDVT_WR,
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MT6885_M2_AXI_MST_HW_VDEC_AVC_MV_EXT,
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MT6885_M5_AXI_MST_PDO,
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MT6885_M2_AXI_MST_CCUI,
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MT6885_M2_AXI_MST_MFB_RDMA0,
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MT6885_M4_AXI_MST_MRSG0,
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MT6885_M7_AXI_MST_CONNSYS,
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MST_INVALID,
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NR_MST
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};
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static const struct mst_tbl_entry mst_tbl[] = {
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
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.id_val = 0x0,
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.note = "Core nn system domain store exclusive",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
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.id_val = 0x8,
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.note = "Core nn barrier",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x10,
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.note = "Unused",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x12,
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.note = "SCU generated barrier",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFD,
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.id_val = 0x14,
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.note = "Unused",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
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.id_val = 0x18,
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.note = "Core nn non-re-orderable device write",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE1,
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.id_val = 0x20,
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.note = "Write to normal memory or re-orderable device memory",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1E01,
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.id_val = 0x400,
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.note = "MCSIB write to ensure clean",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
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.id_val = 0x0,
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.note = "Core nn exclusive read or non-reorderable device read",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
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.id_val = 0x8,
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.note = "Core nn barrier",
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.name = "MT6885_M0_AXI_MST_MP0"},
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{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x10,
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.note = "Unused",
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.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
|
|
.id_val = 0x12,
|
|
.note = "SCU generated barrier or DVM complete",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFD,
|
|
.id_val = 0x14,
|
|
.note = "Unused",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF9,
|
|
.id_val = 0x18,
|
|
.note = "Unused",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE7,
|
|
.id_val = 0x20,
|
|
.note = "ACP read",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE7,
|
|
.id_val = 0x22,
|
|
.note = "Unused",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE5,
|
|
.id_val = 0x24,
|
|
.note = "Unused",
|
|
.name = "MT6885_M0_AXI_MST_MP0"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FC1,
|
|
.id_val = 0x40,
|
|
.note = "Core nn read",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FE1,
|
|
.id_val = 0x1E1,
|
|
.note = "L2 Evictions",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F25,
|
|
.id_val = 0x5,
|
|
.note = "Normal non-cacheable",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x1,
|
|
.note = "SO",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x3,
|
|
.note = "DV",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x9,
|
|
.note = "Exclusive",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1E01,
|
|
.id_val = 0x401,
|
|
.note = "MCSIB write to ensure clean",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x1,
|
|
.note = "TLB NC",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x9,
|
|
.note = "Data NC/SO/Dev",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F3F,
|
|
.id_val = 0x11,
|
|
.note = "Instr NC",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F21,
|
|
.id_val = 0x21,
|
|
.note = "L2 Linefill",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FFF,
|
|
.id_val = 0x1D1,
|
|
.note = "DVM",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FE1,
|
|
.id_val = 0x161,
|
|
.note = "STB Make Unique",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FFF,
|
|
.id_val = 0x149,
|
|
.note = "CMO Clean Unique",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1FF9,
|
|
.id_val = 0x151,
|
|
.note = "Store EX CleanUnique",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M0_AXI_MST_MP1, .port = 0, .id_mask = 0x1F81,
|
|
.id_val = 0x181,
|
|
.note = "Invalidate CleanUnique",
|
|
.name = "MT6885_M0_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x0,
|
|
.note = "Core nn system domain store exclusive",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x8,
|
|
.note = "Core nn barrier",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x10,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x12,
|
|
.note = "SCU generated barrier",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFD,
|
|
.id_val = 0x14,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x18,
|
|
.note = "Core nn non-re-orderable device write",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FE1,
|
|
.id_val = 0x20,
|
|
.note = "Write to normal memory or re-orderable device memory",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1E01,
|
|
.id_val = 0x400,
|
|
.note = "MCSIB write to ensure clean",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x0,
|
|
.note = "Core nn exclusive read or non-reorderable device read",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x8,
|
|
.note = "Core nn barrier",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x10,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x12,
|
|
.note = "SCU generated barrier or DVM complete",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FFD,
|
|
.id_val = 0x14,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x18,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FE7,
|
|
.id_val = 0x20,
|
|
.note = "ACP read",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FE7,
|
|
.id_val = 0x22,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP0, .port = 1, .id_mask = 0x1FE5,
|
|
.id_val = 0x24,
|
|
.note = "Unused",
|
|
.name = "MT6885_M1_AXI_MST_MP0"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FC1,
|
|
.id_val = 0x40,
|
|
.note = "Core nn read",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FE1,
|
|
.id_val = 0x1E1,
|
|
.note = "L2 Evictions",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F25,
|
|
.id_val = 0x5,
|
|
.note = "Normal non-cacheable",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x1,
|
|
.note = "SO",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x3,
|
|
.note = "DV",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x9,
|
|
.note = "Exclusive",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1E01,
|
|
.id_val = 0x401,
|
|
.note = "MCSIB write to ensure clean",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x1,
|
|
.note = "TLB NC",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x9,
|
|
.note = "Data NC/SO/Dev",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F3F,
|
|
.id_val = 0x11,
|
|
.note = "Instr NC",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F21,
|
|
.id_val = 0x21,
|
|
.note = "L2 Linefill",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x1D1,
|
|
.note = "DVM",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FE1,
|
|
.id_val = 0x161,
|
|
.note = "STB Make Unique",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FFF,
|
|
.id_val = 0x149,
|
|
.note = "CMO Clean Unique",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1FF9,
|
|
.id_val = 0x151,
|
|
.note = "Store EX CleanUnique",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M1_AXI_MST_MP1, .port = 1, .id_mask = 0x1F81,
|
|
.id_val = 0x181,
|
|
.note = "Invalidate CleanUnique",
|
|
.name = "MT6885_M1_AXI_MST_MP1"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_OVL0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_OVL0"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_OVL0_2L, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_OVL0_2L"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_OVL1_2L, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_OVL1_2L"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0xC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_RDMA1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x10,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_RDMA1"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_WDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x14,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_WDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_MDP_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x18,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MDP_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_MDP_WROT0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MDP_WROT0"},
|
|
{.master = MT6885_M2_AXI_MST_MDP_WDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x20,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MDP_WDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_DISP_FAKE, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x24,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DISP_FAKE"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_MC_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x380,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_MC_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_PP_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x384,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_PP_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_VLD_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x388,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_VLD_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_AVC_MV_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x38C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_AVC_MV_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_PRED_RD_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x390,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_PRED_RD_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_PRED_WR_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x394,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_PRED_WR_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_HW_VDEC_PPWRAP_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x398,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_HW_VDEC_PPWRAP_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_IPUO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x280,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPUO"},
|
|
{.master = MT6885_M2_AXI_MST_IPU3O, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x284,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPU3O"},
|
|
{.master = MT6885_M2_AXI_MST_IPUI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x288,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPUI"},
|
|
{.master = MT6885_M2_AXI_MST_IPUO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x300,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPUO"},
|
|
{.master = MT6885_M2_AXI_MST_IPU2O, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x304,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPU2O"},
|
|
{.master = MT6885_M2_AXI_MST_IPU3O, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x308,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPU3O"},
|
|
{.master = MT6885_M2_AXI_MST_IPUI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x30C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPUI"},
|
|
{.master = MT6885_M2_AXI_MST_IPU2I, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x310,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IPU2I"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x80,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_REC, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x84,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_REC"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x88,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x8C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x90,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_JPGENC_RDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x94,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_JPGENC_RDMA"},
|
|
{.master = MT6885_M2_AXI_MST_JPGENC_BSDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x98,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_JPGENC_BSDMA"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x9C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0xA0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0xA4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT"},
|
|
{.master = MT6885_M2_AXI_MST_VENC_REF_CHROMA,
|
|
.port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0xA8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VENC_REF_CHROMA"},
|
|
{.master = MT6885_M2_AXI_MST_IMGI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x100,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IMGI"},
|
|
{.master = MT6885_M2_AXI_MST_IMG2O, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x104,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IMG2O"},
|
|
{.master = MT6885_M2_AXI_MST_IMG3O, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x108,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IMG3O"},
|
|
{.master = MT6885_M2_AXI_MST_VIPI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x10C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_VIPI"},
|
|
{.master = MT6885_M2_AXI_MST_LCEI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x110,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LCEI"},
|
|
{.master = MT6885_M2_AXI_MST_SMXI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x114,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SMXI"},
|
|
{.master = MT6885_M2_AXI_MST_SMXO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x118,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SMXO"},
|
|
{.master = MT6885_M2_AXI_MST_WPE0_RDMA1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x11C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE0_RDMA1"},
|
|
{.master = MT6885_M2_AXI_MST_WPE0_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x120,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE0_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_WPE0_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x124,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE0_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_FDVT_RP, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x128,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_FDVT_RP"},
|
|
{.master = MT6885_M2_AXI_MST_FDVT_WR, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x12C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_FDVT_WR"},
|
|
{.master = MT6885_M2_AXI_MST_FDVT_RB, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x130,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_FDVT_RB"},
|
|
{.master = MT6885_M2_AXI_MST_WPE1_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x134,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE1_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_WPE1_RDMA1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x138,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE1_RDMA1"},
|
|
{.master = MT6885_M2_AXI_MST_WPE1_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x13C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_WPE1_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_DPE_RDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x140,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DPE_RDMA"},
|
|
{.master = MT6885_M2_AXI_MST_DPE_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x144,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_DPE_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_MFB_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x148,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MFB_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_MFB_RDMA1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x14C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MFB_RDMA1"},
|
|
{.master = MT6885_M2_AXI_MST_MFB_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x150,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MFB_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_RSC_RDMA0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x154,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_RSC_RDMA0"},
|
|
{.master = MT6885_M2_AXI_MST_RSC_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x158,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_RSC_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_OWE_RDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x15C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_OWE_RDMA"},
|
|
{.master = MT6885_M2_AXI_MST_OWE_WDMA, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x160,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_OWE_WDMA"},
|
|
{.master = MT6885_M2_AXI_MST_IMGO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x180,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_IMGO"},
|
|
{.master = MT6885_M2_AXI_MST_RRZO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x184,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_RRZO"},
|
|
{.master = MT6885_M2_AXI_MST_AAO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x188,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_AAO"},
|
|
{.master = MT6885_M2_AXI_MST_AFO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x18C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_AFO"},
|
|
{.master = MT6885_M2_AXI_MST_LSCI_0, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x190,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LSCI_0"},
|
|
{.master = MT6885_M2_AXI_MST_LSCI_1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x194,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LSCI_1"},
|
|
{.master = MT6885_M2_AXI_MST_PDO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x198,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_PDO"},
|
|
{.master = MT6885_M2_AXI_MST_BPCI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x19C,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_BPCI"},
|
|
{.master = MT6885_M2_AXI_MST_LCSO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LCSO"},
|
|
{.master = MT6885_M2_AXI_MST_RSSO_A, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_RSSO_A"},
|
|
{.master = MT6885_M2_AXI_MST_UFEO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_UFEO"},
|
|
{.master = MT6885_M2_AXI_MST_SOCO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1AC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SOCO"},
|
|
{.master = MT6885_M2_AXI_MST_SOC1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SOC1"},
|
|
{.master = MT6885_M2_AXI_MST_SOC2, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SOC2"},
|
|
{.master = MT6885_M2_AXI_MST_CCUI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_CCUI"},
|
|
{.master = MT6885_M2_AXI_MST_CCUO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1BC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_CCUO"},
|
|
{.master = MT6885_M2_AXI_MST_RAWI_A, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_RAWI_A"},
|
|
{.master = MT6885_M2_AXI_MST_CCUG, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_CCUG"},
|
|
{.master = MT6885_M2_AXI_MST_PSO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_PSO"},
|
|
{.master = MT6885_M2_AXI_MST_AFO_1, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1CC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_AFO_1"},
|
|
{.master = MT6885_M2_AXI_MST_LSCI_2, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LSCI_2"},
|
|
{.master = MT6885_M2_AXI_MST_PDI, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_PDI"},
|
|
{.master = MT6885_M2_AXI_MST_FLKO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_FLKO"},
|
|
{.master = MT6885_M2_AXI_MST_LMVO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1DC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_LMVO"},
|
|
{.master = MT6885_M2_AXI_MST_UFGO, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_UFGO"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE2, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE2"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE3, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1EC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE3"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE4, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F0,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE4"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE5, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F4,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE5"},
|
|
{.master = MT6885_M2_AXI_MST_SPARE6, .port = 2, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F8,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_SPARE6"},
|
|
{.master = MT6885_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x3FC,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MM_IOMMU"},
|
|
{.master = MT6885_M2_AXI_MST_MM_IOMMU, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x3FD,
|
|
.note = "",
|
|
.name = "MT6885_M2_AXI_MST_MM_IOMMU"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_OVL0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_OVL0"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_OVL0_2L, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_OVL0_2L"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_OVL1_2L, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_OVL1_2L"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0xC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_RDMA1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x10,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_RDMA1"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_WDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x14,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_WDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_MDP_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x18,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MDP_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_MDP_WROT0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MDP_WROT0"},
|
|
{.master = MT6885_M5_AXI_MST_MDP_WDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x20,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MDP_WDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_DISP_FAKE, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x24,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DISP_FAKE"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_MC_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x380,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_MC_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_PP_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x384,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_PP_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_VLD_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x388,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_VLD_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_AVC_MV_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x38C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_AVC_MV_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_PRED_RD_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x390,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_PRED_RD_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_PRED_WR_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x394,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_PRED_WR_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_HW_VDEC_PPWRAP_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x398,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_HW_VDEC_PPWRAP_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_IPUO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x280,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPUO"},
|
|
{.master = MT6885_M5_AXI_MST_IPU3O, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x284,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPU3O"},
|
|
{.master = MT6885_M5_AXI_MST_IPUI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x288,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPUI"},
|
|
{.master = MT6885_M5_AXI_MST_IPUO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x300,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPUO"},
|
|
{.master = MT6885_M5_AXI_MST_IPU2O, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x304,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPU2O"},
|
|
{.master = MT6885_M5_AXI_MST_IPU3O, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x308,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPU3O"},
|
|
{.master = MT6885_M5_AXI_MST_IPUI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x30C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPUI"},
|
|
{.master = MT6885_M5_AXI_MST_IPU2I, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x310,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IPU2I"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x80,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_REC, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x84,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_REC"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x88,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x8C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x90,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_JPGENC_RDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x94,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_JPGENC_RDMA"},
|
|
{.master = MT6885_M5_AXI_MST_JPGENC_BSDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x98,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_JPGENC_BSDMA"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x9C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0xA0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0xA4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT"},
|
|
{.master = MT6885_M5_AXI_MST_VENC_REF_CHROMA,
|
|
.port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0xA8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VENC_REF_CHROMA"},
|
|
{.master = MT6885_M5_AXI_MST_IMGI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x100,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IMGI"},
|
|
{.master = MT6885_M5_AXI_MST_IMG2O, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x104,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IMG2O"},
|
|
{.master = MT6885_M5_AXI_MST_IMG3O, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x108,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IMG3O"},
|
|
{.master = MT6885_M5_AXI_MST_VIPI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x10C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_VIPI"},
|
|
{.master = MT6885_M5_AXI_MST_LCEI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x110,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LCEI"},
|
|
{.master = MT6885_M5_AXI_MST_SMXI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x114,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SMXI"},
|
|
{.master = MT6885_M5_AXI_MST_SMXO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x118,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SMXO"},
|
|
{.master = MT6885_M5_AXI_MST_WPE0_RDMA1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x11C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE0_RDMA1"},
|
|
{.master = MT6885_M5_AXI_MST_WPE0_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x120,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE0_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_WPE0_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x124,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE0_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_FDVT_RP, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x128,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_FDVT_RP"},
|
|
{.master = MT6885_M5_AXI_MST_FDVT_WR, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x12C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_FDVT_WR"},
|
|
{.master = MT6885_M5_AXI_MST_FDVT_RB, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x130,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_FDVT_RB"},
|
|
{.master = MT6885_M5_AXI_MST_WPE1_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x134,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE1_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_WPE1_RDMA1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x138,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE1_RDMA1"},
|
|
{.master = MT6885_M5_AXI_MST_WPE1_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x13C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_WPE1_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_DPE_RDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x140,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DPE_RDMA"},
|
|
{.master = MT6885_M5_AXI_MST_DPE_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x144,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_DPE_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_MFB_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x148,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MFB_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_MFB_RDMA1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x14C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MFB_RDMA1"},
|
|
{.master = MT6885_M5_AXI_MST_MFB_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x150,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MFB_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_RSC_RDMA0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x154,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_RSC_RDMA0"},
|
|
{.master = MT6885_M5_AXI_MST_RSC_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x158,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_RSC_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_OWE_RDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x15C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_OWE_RDMA"},
|
|
{.master = MT6885_M5_AXI_MST_OWE_WDMA, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x160,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_OWE_WDMA"},
|
|
{.master = MT6885_M5_AXI_MST_IMGO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x180,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_IMGO"},
|
|
{.master = MT6885_M5_AXI_MST_RRZO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x184,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_RRZO"},
|
|
{.master = MT6885_M5_AXI_MST_AAO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x188,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_AAO"},
|
|
{.master = MT6885_M5_AXI_MST_AFO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x18C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_AFO"},
|
|
{.master = MT6885_M5_AXI_MST_LSCI_0, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x190,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LSCI_0"},
|
|
{.master = MT6885_M5_AXI_MST_LSCI_1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x194,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LSCI_1"},
|
|
{.master = MT6885_M5_AXI_MST_PDO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x198,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_PDO"},
|
|
{.master = MT6885_M5_AXI_MST_BPCI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x19C,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_BPCI"},
|
|
{.master = MT6885_M5_AXI_MST_LCSO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LCSO"},
|
|
{.master = MT6885_M5_AXI_MST_RSSO_A, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_RSSO_A"},
|
|
{.master = MT6885_M5_AXI_MST_UFEO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1A8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_UFEO"},
|
|
{.master = MT6885_M5_AXI_MST_SOCO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1AC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SOCO"},
|
|
{.master = MT6885_M5_AXI_MST_SOC1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SOC1"},
|
|
{.master = MT6885_M5_AXI_MST_SOC2, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SOC2"},
|
|
{.master = MT6885_M5_AXI_MST_CCUI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1B8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_CCUI"},
|
|
{.master = MT6885_M5_AXI_MST_CCUO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1BC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_CCUO"},
|
|
{.master = MT6885_M5_AXI_MST_RAWI_A, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_RAWI_A"},
|
|
{.master = MT6885_M5_AXI_MST_CCUG, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_CCUG"},
|
|
{.master = MT6885_M5_AXI_MST_PSO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1C8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_PSO"},
|
|
{.master = MT6885_M5_AXI_MST_AFO_1, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1CC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_AFO_1"},
|
|
{.master = MT6885_M5_AXI_MST_LSCI_2, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LSCI_2"},
|
|
{.master = MT6885_M5_AXI_MST_PDI, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_PDI"},
|
|
{.master = MT6885_M5_AXI_MST_FLKO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1D8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_FLKO"},
|
|
{.master = MT6885_M5_AXI_MST_LMVO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1DC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_LMVO"},
|
|
{.master = MT6885_M5_AXI_MST_UFGO, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_UFGO"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE2, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1E8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE2"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE3, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1EC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE3"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE4, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F0,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE4"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE5, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F4,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE5"},
|
|
{.master = MT6885_M5_AXI_MST_SPARE6, .port = 5, .id_mask = 0x1FFC,
|
|
.id_val = 0x1F8,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_SPARE6"},
|
|
{.master = MT6885_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
|
|
.id_val = 0x3FC,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MM_IOMMU"},
|
|
{.master = MT6885_M5_AXI_MST_MM_IOMMU, .port = 5, .id_mask = 0x1FFF,
|
|
.id_val = 0x3FD,
|
|
.note = "",
|
|
.name = "MT6885_M5_AXI_MST_MM_IOMMU"},
|
|
{.master = MT6885_M6_AXI_MST_MFG_M0, .port = 6, .id_mask = 0x1FC0,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6885_M6_AXI_MST_MFG_M0"},
|
|
{.master = MT6885_M7_AXI_MST_SSUSB, .port = 7, .id_mask = 0x1FE7,
|
|
.id_val = 0x80,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SSUSB"},
|
|
{.master = MT6885_M7_AXI_MST_PWM, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x84,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_PWM"},
|
|
{.master = MT6885_M7_AXI_MST_MSDC1, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x8C,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MSDC1"},
|
|
{.master = MT6885_M7_AXI_MST_MSDC2, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x94,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MSDC2"},
|
|
{.master = MT6885_M7_AXI_MST_SPI0, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x9C,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI0"},
|
|
{.master = MT6885_M7_AXI_MST_DEBUGTOP, .port = 7, .id_mask = 0x1FDF,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_DEBUGTOP"},
|
|
{.master = MT6885_M7_AXI_MST_AUDIO, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x106,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_AUDIO"},
|
|
{.master = MT6885_M7_AXI_MST_IPU, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x206,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_IPU"},
|
|
{.master = MT6885_M7_AXI_MST_SPI1, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x306,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI1"},
|
|
{.master = MT6885_M7_AXI_MST_CCU, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x26,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_CCU"},
|
|
{.master = MT6885_M7_AXI_MST_SPM, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x126,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPM"},
|
|
{.master = MT6885_M7_AXI_MST_THERM, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x326,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_THERM"},
|
|
{.master = MT6885_M7_AXI_MST_UFS, .port = 7, .id_mask = 0x1CFF,
|
|
.id_val = 0x46,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_UFS"},
|
|
{.master = MT6885_M7_AXI_MST_DMA_EXT, .port = 7, .id_mask = 0x1EFF,
|
|
.id_val = 0x66,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_DMA_EXT"},
|
|
{.master = MT6885_M7_AXI_MST_PWM, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x186,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_PWM"},
|
|
{.master = MT6885_M7_AXI_MST_MSDC1, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x386,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MSDC1"},
|
|
{.master = MT6885_M7_AXI_MST_MSDC2, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x586,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MSDC2"},
|
|
{.master = MT6885_M7_AXI_MST_SPI0, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x786,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI0"},
|
|
{.master = MT6885_M7_AXI_MST_SPI2, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0xA6,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI2"},
|
|
{.master = MT6885_M7_AXI_MST_SPI3, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x1A6,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI3"},
|
|
{.master = MT6885_M7_AXI_MST_SPI4, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x2A6,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI4"},
|
|
{.master = MT6885_M7_AXI_MST_SPI5, .port = 7, .id_mask = 0x1FFF,
|
|
.id_val = 0x3A6,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SPI5"},
|
|
{.master = MT6885_M7_AXI_MST_MSDC0, .port = 7, .id_mask = 0x18FF,
|
|
.id_val = 0xC6,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MSDC0"},
|
|
{.master = MT6885_M7_AXI_MST_CONNSYS, .port = 7, .id_mask = 0x1FDF,
|
|
.id_val = 0xA,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_CONNSYS"},
|
|
{.master = MT6885_M7_AXI_MST_DX_CC, .port = 7, .id_mask = 0x1E1F,
|
|
.id_val = 0xE,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_DX_CC"},
|
|
{.master = MT6885_M7_AXI_MST_CQ_DMA, .port = 7, .id_mask = 0x1F9F,
|
|
.id_val = 0x12,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_CQ_DMA"},
|
|
{.master = MT6885_M7_AXI_MST_CLDMA, .port = 7, .id_mask = 0x1F9F,
|
|
.id_val = 0x16,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_CLDMA"},
|
|
{.master = MT6885_M7_AXI_MST_GCE_M, .port = 7, .id_mask = 0x1F9F,
|
|
.id_val = 0x1A,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_GCE_M"},
|
|
{.master = MT6885_M7_AXI_MST_SCP, .port = 7, .id_mask = 0x1F3F,
|
|
.id_val = 0x1E,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SCP"},
|
|
{.master = MT6885_M7_AXI_MST_SSPM, .port = 7, .id_mask = 0x1F3F,
|
|
.id_val = 0x3E,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_SSPM"},
|
|
{.master = MT6885_M7_AXI_MST_MFG_M1, .port = 7, .id_mask = 0x1F81,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6885_M7_AXI_MST_MFG_M1"},
|
|
{.master = MT6885_M3_AXI_MST_MD_MM, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_MD_MM"},
|
|
{.master = MT6885_M3_AXI_MST_MD_MMU, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_MD_MMU"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_0_I, .port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_0_I"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_0_DCACHE,
|
|
.port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_0_DCACHE"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_0_DNOCACHE,
|
|
.port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0xA,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_0_DNOCACHE"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_1_I, .port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0x12,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_1_I"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_1_DCACHE,
|
|
.port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0x16,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_1_DCACHE"},
|
|
{.master = MT6885_M3_AXI_MST_USIP_1_DNOCACHE,
|
|
.port = 3, .id_mask = 0x1E1F,
|
|
.id_val = 0x1A,
|
|
.note = "",
|
|
.name = "MT6885_M3_AXI_MST_USIP_1_DNOCACHE"},
|
|
{.master = MT6885_M4_AXI_MST_HRQ_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_HRQ_RD"},
|
|
{.master = MT6885_M4_AXI_MST_HRQ_RD1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1008,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_HRQ_RD1"},
|
|
{.master = MT6885_M4_AXI_MST_HRQ_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1002,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_HRQ_WR"},
|
|
{.master = MT6885_M4_AXI_MST_HRQ_WR1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x100A,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_HRQ_WR1"},
|
|
{.master = MT6885_M4_AXI_MST_VTB, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x100C,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_VTB"},
|
|
{.master = MT6885_M4_AXI_MST_TBO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1014,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TBO"},
|
|
{.master = MT6885_M4_AXI_MST_DEBUG, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1004,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DEBUG"},
|
|
{.master = MT6885_M4_AXI_MST_DFE_DUMP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x808,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DFE_DUMP"},
|
|
{.master = MT6885_M4_AXI_MST_BR_DMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x80A,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_BR_DMA"},
|
|
{.master = MT6885_M4_AXI_MST_IRDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x10,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_IRDMA"},
|
|
{.master = MT6885_M4_AXI_MST_TXBRP0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x50,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TXBRP0"},
|
|
{.master = MT6885_M4_AXI_MST_TXBRP1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x150,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TXBRP1"},
|
|
{.master = MT6885_M4_AXI_MST_TXCAL, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xD0,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TXCAL"},
|
|
{.master = MT6885_M4_AXI_MST_TPC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1D0,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TPC"},
|
|
{.master = MT6885_M4_AXI_MST_RXDFE_DMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x70,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_RXDFE_DMA"},
|
|
{.master = MT6885_M4_AXI_MST_MRSG0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xF0,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_MRSG0"},
|
|
{.master = MT6885_M4_AXI_MST_MRSG1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x170,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_MRSG1"},
|
|
{.master = MT6885_M4_AXI_MST_CNWDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x130,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_CNWDMA"},
|
|
{.master = MT6885_M4_AXI_MST_CSH, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xB0,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_CSH"},
|
|
{.master = MT6885_M4_AXI_MST_DCXO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x30,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DCXO"},
|
|
{.master = MT6885_M4_AXI_MST_DMA_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1804,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DMA_RD"},
|
|
{.master = MT6885_M4_AXI_MST_DMA_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1806,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DMA_WR"},
|
|
{.master = MT6885_M4_AXI_MST_MMU, .port = 4, .id_mask = 0x1FFF,
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.id_val = 0x1800,
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.note = "",
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.name = "MT6885_M4_AXI_MST_MMU"},
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{.master = MT6885_M4_AXI_MST_QP, .port = 4, .id_mask = 0x1FFF,
|
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.id_val = 0x1802,
|
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.note = "",
|
|
.name = "MT6885_M4_AXI_MST_QP"},
|
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{.master = MT6885_M4_AXI_MST_LOG_TOP_MCU, .port = 4, .id_mask = 0x1FFF,
|
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.id_val = 0x24,
|
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.note = "",
|
|
.name = "MT6885_M4_AXI_MST_LOG_TOP_MCU"},
|
|
{.master = MT6885_M4_AXI_MST_LOG_TOP_DSP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_LOG_TOP_DSP"},
|
|
{.master = MT6885_M4_AXI_MST_TRACE_TOP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x8,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_TRACE_TOP"},
|
|
{.master = MT6885_M4_AXI_MST_PPPHA, .port = 4, .id_mask = 0x1FDF,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_PPPHA"},
|
|
{.master = MT6885_M4_AXI_MST_IPSEC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xA,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_IPSEC"},
|
|
{.master = MT6885_M4_AXI_MST_GDMA, .port = 4, .id_mask = 0x1E3F,
|
|
.id_val = 0xE,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_GDMA"},
|
|
{.master = MT6885_M4_AXI_MST_DBGSYS, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xE,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_DBGSYS"},
|
|
{.master = MT6885_M4_AXI_MST_MCUSYS_DFD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6885_M4_AXI_MST_MCUSYS_DFD"},
|
|
};
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|
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#endif /* __MPU_PLATFORM_H__ */
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