550 lines
18 KiB
C
550 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _EMI_MODULE_H_
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#define _EMI_MODULE_H_
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struct mst_tbl_entry {
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u32 master;
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u32 port;
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u32 id_mask;
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u32 id_val;
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const char *note;
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const char *name;
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};
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enum {
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MT6739_M1_AXI_MST_DISP_RDMA0,
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MT6739_M4_AXI_MST_TBO,
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MT6739_M4_AXI_MST_HRQ_RD,
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MT6739_M3_AXI_MST_MD_MM,
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MT6739_M4_AXI_MST_CNWDMA,
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MT6739_M1_AXI_MST_DISP_OVL0,
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MT6739_M4_AXI_MST_TXBRP0,
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MT6739_M1_AXI_MST_MDP_WDMA0,
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MT6739_M1_AXI_MST_LSCI_0,
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MT6739_M2_AXI_MST_MSDC1,
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MT6739_M2_AXI_MST_NFI,
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MT6739_M2_AXI_MST_CQ_DMA,
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MT6739_M1_AXI_MST_MDP_RDMA0,
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MT6739_M2_AXI_MST_DMA_EXT,
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MT6739_M2_AXI_MST_GCE_M,
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MT6739_M1_AXI_MST_JPGENC_BSDMA,
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MT6739_M4_AXI_MST_RXDFE_DMA,
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MT6739_M2_AXI_MST_THERM,
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MT6739_M1_AXI_MST_BPCI_0,
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MT6739_M4_AXI_MST_IPSEC,
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MT6739_M4_AXI_MST_CSH,
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MT6739_M1_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT,
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MT6739_M4_AXI_MST_DCXO,
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MT6739_M1_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT,
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MT6739_M2_AXI_MST_USB20,
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MT6739_M3_AXI_MST_USIP_1_I,
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MT6739_M4_AXI_MST_DMA_RD,
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MT6739_M4_AXI_MST_DBGSYS,
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MT6739_M1_AXI_MST_CAM_SV0,
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MT6739_M1_AXI_MST_JPGENC_RDMA,
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MT6739_M3_AXI_MST_USIP_0_DNOCACHE,
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MT6739_M3_AXI_MST_USIP_0_I,
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MT6739_M2_AXI_MST_SPI1,
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MT6739_M4_AXI_MST_HRQ_RD1,
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MT6739_M4_AXI_MST_MMU,
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MT6739_M4_AXI_MST_DFE_DUMP,
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MT6739_M1_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT,
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MT6739_M1_AXI_MST_AAO,
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MT6739_M4_AXI_MST_MRSG1,
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MT6739_M4_AXI_MST_HRQ_WR,
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MT6739_M1_AXI_MST_DISP_FAKE,
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MT6739_M2_AXI_MST_MSDC0,
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MT6739_M2_AXI_MST_MCUPM,
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MT6739_M1_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT,
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MT6739_M1_AXI_MST_MM_IOMMU,
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MT6739_M4_AXI_MST_DEBUG,
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MT6739_M3_AXI_MST_MD_MMU,
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MT6739_M4_AXI_MST_TXBRP1,
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MT6739_M2_AXI_MST_MD,
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MT6739_M1_AXI_MST_RRZO,
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MT6739_M1_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT,
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MT6739_M1_AXI_MST_LSCI_1,
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MT6739_M4_AXI_MST_LOG_TOP_DSP,
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MT6739_M1_AXI_MST_IMG2O,
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MT6739_M2_AXI_MST_PWM,
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MT6739_M4_AXI_MST_PPPHA,
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MT6739_M4_AXI_MST_TPC,
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MT6739_M5_AXI_MST_MFG,
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MT6739_M4_AXI_MST_BR_DMA,
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MT6739_M4_AXI_MST_LOG_TOP_MCU,
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MT6739_M4_AXI_MST_TXCAL,
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MT6739_M3_AXI_MST_USIP_0_DCACHE,
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MT6739_M2_AXI_MST_DX_CC,
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MT6739_M1_AXI_MST_BPCI_1,
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MT6739_M1_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT,
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MT6739_M1_AXI_MST_IMGI,
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MT6739_M1_AXI_MST_ESFKO,
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MT6739_M4_AXI_MST_QP,
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MT6739_M4_AXI_MST_DMA_WR,
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MT6739_M3_AXI_MST_USIP_1_DCACHE,
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MT6739_M1_AXI_MST_MDP_WROT0,
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MT6739_M2_AXI_MST_SPM,
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MT6739_M4_AXI_MST_GDMA,
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MT6739_M4_AXI_MST_VTB,
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MT6739_M3_AXI_MST_USIP_1_DNOCACHE,
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MT6739_M0_AXI_MST_MP0,
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MT6739_M4_AXI_MST_TRACE_TOP,
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MT6739_M1_AXI_MST_DISP_WDMA0,
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MT6739_M1_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT,
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MT6739_M1_AXI_MST_VENC_REC,
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MT6739_M1_AXI_MST_IMGO,
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MT6739_M2_AXI_MST_DEBUGTOP,
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MT6739_M4_AXI_MST_HRQ_WR1,
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MT6739_M1_AXI_MST_VENC_REF_CHROMA,
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MT6739_M2_AXI_MST_SPI0,
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MT6739_M2_AXI_MST_CLDMA,
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MT6739_M2_AXI_MST_SPI2,
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MT6739_M4_AXI_MST_MRSG0,
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MT6739_M2_AXI_MST_CONNSYS,
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MT6739_M4_AXI_MST_IRDMA,
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MT6739_M2_AXI_MST_AUDIO,
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MST_INVALID,
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NR_MST
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};
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static const struct mst_tbl_entry mst_tbl[] = {
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0x0,
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.note = "Core nn system domain store exclusive",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0x4,
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.note = "Core nn barrier",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x8,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x9,
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.note = "SCU generated barrier",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFE,
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.id_val = 0xA,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0xC,
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.note = "Core nn non-re-orderable device write",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF0,
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.id_val = 0x10,
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.note = "Write to normal memory or re-orderable device memory",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0x0,
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.note = "Core nn exclusive read or non-reorderable device read",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0x4,
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.note = "Core nn barrier",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x8,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFF,
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.id_val = 0x9,
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.note = "SCU generated barrier or DVM complete",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFE,
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.id_val = 0xA,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FFC,
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.id_val = 0xC,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF3,
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.id_val = 0x10,
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.note = "ACP read",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF3,
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.id_val = 0x11,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FF2,
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.id_val = 0x12,
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.note = "Unused",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M0_AXI_MST_MP0, .port = 0, .id_mask = 0x1FE0,
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.id_val = 0x20,
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.note = "Core nn read",
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.name = "MT6739_M0_AXI_MST_MP0"},
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{.master = MT6739_M1_AXI_MST_DISP_OVL0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x0,
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.note = "",
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.name = "MT6739_M1_AXI_MST_DISP_OVL0"},
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{.master = MT6739_M1_AXI_MST_DISP_RDMA0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x4,
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.note = "",
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.name = "MT6739_M1_AXI_MST_DISP_RDMA0"},
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{.master = MT6739_M1_AXI_MST_DISP_WDMA0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x8,
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.note = "",
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.name = "MT6739_M1_AXI_MST_DISP_WDMA0"},
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{.master = MT6739_M1_AXI_MST_MDP_RDMA0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0xC,
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.note = "",
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.name = "MT6739_M1_AXI_MST_MDP_RDMA0"},
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{.master = MT6739_M1_AXI_MST_MDP_WDMA0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x10,
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.note = "",
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.name = "MT6739_M1_AXI_MST_MDP_WDMA0"},
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{.master = MT6739_M1_AXI_MST_MDP_WROT0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x14,
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.note = "",
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.name = "MT6739_M1_AXI_MST_MDP_WROT0"},
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{.master = MT6739_M1_AXI_MST_DISP_FAKE, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x18,
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.note = "",
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.name = "MT6739_M1_AXI_MST_DISP_FAKE"},
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{.master = MT6739_M1_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x80,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_RCPU_HW_VDEC_MC_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_REC, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x84,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_REC"},
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{.master = MT6739_M1_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x88,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_BSDMA_HW_VDEC_PP_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x8C,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_SV_COMV_HW_VDEC_PRED_WR_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x90,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_RD_COMV_HW_VDEC_PRED_RD_EXT"},
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{.master = MT6739_M1_AXI_MST_JPGENC_RDMA, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x94,
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.note = "",
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.name = "MT6739_M1_AXI_MST_JPGENC_RDMA"},
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{.master = MT6739_M1_AXI_MST_JPGENC_BSDMA, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x98,
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.note = "",
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.name = "MT6739_M1_AXI_MST_JPGENC_BSDMA"},
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{.master = MT6739_M1_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x9C,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_CUR_LUMA_HW_VDEC_VLD_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0xA0,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_CUR_CHROMA_HW_VDEC_PPWRAP_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0xA4,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_REF_LUMA_HW_VDEC_AVC_MV_EXT"},
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{.master = MT6739_M1_AXI_MST_VENC_REF_CHROMA, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0xA8,
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.note = "",
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.name = "MT6739_M1_AXI_MST_VENC_REF_CHROMA"},
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{.master = MT6739_M1_AXI_MST_IMGO, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x100,
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.note = "",
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.name = "MT6739_M1_AXI_MST_IMGO"},
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{.master = MT6739_M1_AXI_MST_RRZO, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x104,
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.note = "",
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.name = "MT6739_M1_AXI_MST_RRZO"},
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{.master = MT6739_M1_AXI_MST_LSCI_0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x108,
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.note = "",
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.name = "MT6739_M1_AXI_MST_LSCI_0"},
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{.master = MT6739_M1_AXI_MST_LSCI_1, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x10C,
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.note = "",
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.name = "MT6739_M1_AXI_MST_LSCI_1"},
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{.master = MT6739_M1_AXI_MST_BPCI_0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x110,
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.note = "",
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.name = "MT6739_M1_AXI_MST_BPCI_0"},
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{.master = MT6739_M1_AXI_MST_BPCI_1, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x114,
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.note = "",
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.name = "MT6739_M1_AXI_MST_BPCI_1"},
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{.master = MT6739_M1_AXI_MST_ESFKO, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x118,
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.note = "",
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.name = "MT6739_M1_AXI_MST_ESFKO"},
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{.master = MT6739_M1_AXI_MST_AAO, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x11C,
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.note = "",
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.name = "MT6739_M1_AXI_MST_AAO"},
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{.master = MT6739_M1_AXI_MST_CAM_SV0, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x120,
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.note = "",
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.name = "MT6739_M1_AXI_MST_CAM_SV0"},
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{.master = MT6739_M1_AXI_MST_IMGI, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x124,
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.note = "",
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.name = "MT6739_M1_AXI_MST_IMGI"},
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{.master = MT6739_M1_AXI_MST_IMG2O, .port = 1, .id_mask = 0x1FFC,
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.id_val = 0x128,
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.note = "",
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.name = "MT6739_M1_AXI_MST_IMG2O"},
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{.master = MT6739_M1_AXI_MST_MM_IOMMU, .port = 1, .id_mask = 0x1FFF,
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.id_val = 0x3FC,
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.note = "internal used",
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.name = "MT6739_M1_AXI_MST_MM_IOMMU"},
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{.master = MT6739_M1_AXI_MST_MM_IOMMU, .port = 1, .id_mask = 0x1FFF,
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.id_val = 0x3FD,
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.note = "internal used",
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.name = "MT6739_M1_AXI_MST_MM_IOMMU"},
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{.master = MT6739_M2_AXI_MST_DEBUGTOP, .port = 2, .id_mask = 0x1FF7,
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.id_val = 0x0,
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.note = "",
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.name = "MT6739_M2_AXI_MST_DEBUGTOP"},
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{.master = MT6739_M2_AXI_MST_MSDC0, .port = 2, .id_mask = 0x1FFF,
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.id_val = 0x1,
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.note = "",
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.name = "MT6739_M2_AXI_MST_MSDC0"},
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|
{.master = MT6739_M2_AXI_MST_PWM, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x9,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_PWM"},
|
|
{.master = MT6739_M2_AXI_MST_MSDC1, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x49,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_MSDC1"},
|
|
{.master = MT6739_M2_AXI_MST_AUDIO, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x89,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_AUDIO"},
|
|
{.master = MT6739_M2_AXI_MST_SPI0, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0xC9,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_SPI0"},
|
|
{.master = MT6739_M2_AXI_MST_NFI, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x11,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_NFI"},
|
|
{.master = MT6739_M2_AXI_MST_SPI2, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x51,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_SPI2"},
|
|
{.master = MT6739_M2_AXI_MST_SPI1, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x91,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_SPI1"},
|
|
{.master = MT6739_M2_AXI_MST_USB20, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0xD1,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_USB20"},
|
|
{.master = MT6739_M2_AXI_MST_MCUPM, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x19,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_MCUPM"},
|
|
{.master = MT6739_M2_AXI_MST_SPM, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x59,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_SPM"},
|
|
{.master = MT6739_M2_AXI_MST_MD, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x99,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_MD"},
|
|
{.master = MT6739_M2_AXI_MST_THERM, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0xD9,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_THERM"},
|
|
{.master = MT6739_M2_AXI_MST_DMA_EXT, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x21,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_DMA_EXT"},
|
|
{.master = MT6739_M2_AXI_MST_CONNSYS, .port = 2, .id_mask = 0x1FFF,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_CONNSYS"},
|
|
{.master = MT6739_M2_AXI_MST_DX_CC, .port = 2, .id_mask = 0x1F87,
|
|
.id_val = 0x3,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_DX_CC"},
|
|
{.master = MT6739_M2_AXI_MST_CQ_DMA, .port = 2, .id_mask = 0x1F87,
|
|
.id_val = 0x4,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_CQ_DMA"},
|
|
{.master = MT6739_M2_AXI_MST_CLDMA, .port = 2, .id_mask = 0x1FE7,
|
|
.id_val = 0x5,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_CLDMA"},
|
|
{.master = MT6739_M2_AXI_MST_GCE_M, .port = 2, .id_mask = 0x1FE7,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6739_M2_AXI_MST_GCE_M"},
|
|
{.master = MT6739_M3_AXI_MST_MD_MM, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_MD_MM"},
|
|
{.master = MT6739_M3_AXI_MST_MD_MMU, .port = 3, .id_mask = 0x1F83,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_MD_MMU"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_0_I, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x2,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_0_I"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_0_DCACHE, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x6,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_0_DCACHE"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_0_DNOCACHE, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0xA,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_0_DNOCACHE"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_1_I, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x12,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_1_I"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_1_DCACHE, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x16,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_1_DCACHE"},
|
|
{.master = MT6739_M3_AXI_MST_USIP_1_DNOCACHE, .port = 3, .id_mask = 0x1F1F,
|
|
.id_val = 0x1A,
|
|
.note = "",
|
|
.name = "MT6739_M3_AXI_MST_USIP_1_DNOCACHE"},
|
|
{.master = MT6739_M4_AXI_MST_HRQ_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_HRQ_RD"},
|
|
{.master = MT6739_M4_AXI_MST_HRQ_RD1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x804,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_HRQ_RD1"},
|
|
{.master = MT6739_M4_AXI_MST_HRQ_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x801,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_HRQ_WR"},
|
|
{.master = MT6739_M4_AXI_MST_HRQ_WR1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x805,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_HRQ_WR1"},
|
|
{.master = MT6739_M4_AXI_MST_VTB, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x806,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_VTB"},
|
|
{.master = MT6739_M4_AXI_MST_TBO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x80A,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TBO"},
|
|
{.master = MT6739_M4_AXI_MST_DEBUG, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x802,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DEBUG"},
|
|
{.master = MT6739_M4_AXI_MST_DFE_DUMP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x404,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DFE_DUMP"},
|
|
{.master = MT6739_M4_AXI_MST_BR_DMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x405,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_BR_DMA"},
|
|
{.master = MT6739_M4_AXI_MST_IRDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x8,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_IRDMA"},
|
|
{.master = MT6739_M4_AXI_MST_TXBRP0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x28,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TXBRP0"},
|
|
{.master = MT6739_M4_AXI_MST_TXBRP1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xA8,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TXBRP1"},
|
|
{.master = MT6739_M4_AXI_MST_TXCAL, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x68,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TXCAL"},
|
|
{.master = MT6739_M4_AXI_MST_TPC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xE8,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TPC"},
|
|
{.master = MT6739_M4_AXI_MST_RXDFE_DMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x38,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_RXDFE_DMA"},
|
|
{.master = MT6739_M4_AXI_MST_MRSG0, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x78,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_MRSG0"},
|
|
{.master = MT6739_M4_AXI_MST_MRSG1, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xB8,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_MRSG1"},
|
|
{.master = MT6739_M4_AXI_MST_CNWDMA, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x98,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_CNWDMA"},
|
|
{.master = MT6739_M4_AXI_MST_CSH, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x58,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_CSH"},
|
|
{.master = MT6739_M4_AXI_MST_DCXO, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x18,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DCXO"},
|
|
{.master = MT6739_M4_AXI_MST_DMA_RD, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xC02,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DMA_RD"},
|
|
{.master = MT6739_M4_AXI_MST_DMA_WR, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xC03,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DMA_WR"},
|
|
{.master = MT6739_M4_AXI_MST_MMU, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xC00,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_MMU"},
|
|
{.master = MT6739_M4_AXI_MST_QP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0xC01,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_QP"},
|
|
{.master = MT6739_M4_AXI_MST_LOG_TOP_MCU, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x12,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_LOG_TOP_MCU"},
|
|
{.master = MT6739_M4_AXI_MST_LOG_TOP_DSP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x3,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_LOG_TOP_DSP"},
|
|
{.master = MT6739_M4_AXI_MST_TRACE_TOP, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x4,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_TRACE_TOP"},
|
|
{.master = MT6739_M4_AXI_MST_PPPHA, .port = 4, .id_mask = 0x1FEF,
|
|
.id_val = 0x1,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_PPPHA"},
|
|
{.master = MT6739_M4_AXI_MST_IPSEC, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x5,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_IPSEC"},
|
|
{.master = MT6739_M4_AXI_MST_GDMA, .port = 4, .id_mask = 0x1F1F,
|
|
.id_val = 0x7,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_GDMA"},
|
|
{.master = MT6739_M4_AXI_MST_DBGSYS, .port = 4, .id_mask = 0x1FFF,
|
|
.id_val = 0x7,
|
|
.note = "",
|
|
.name = "MT6739_M4_AXI_MST_DBGSYS"},
|
|
{.master = MT6739_M5_AXI_MST_MFG, .port = 5, .id_mask = 0x1FC0,
|
|
.id_val = 0x0,
|
|
.note = "",
|
|
.name = "MT6739_M5_AXI_MST_MFG"},
|
|
};
|
|
|
|
#endif /* end of _EMI_MODULE_H_ */
|